STA50213TR [STMICROELECTRONICS]
IC,AUDIO AMPLIFIER,SINGLE,BCDMOS,SSOP,36PIN,PLASTIC;
| 型号： | STA50213TR |
| 厂家： | 
ST |
| 描述： | IC,AUDIO AMPLIFIER,SINGLE,BCDMOS,SSOP,36PIN,PLASTIC 放大器 CD 光电二极管 商用集成电路 |
| 文件： | 总9页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA502
40V 4A DOUBLE POWER HALF BRIDGE
1 FEATURES
Figure 1. Package
■ MULTIPOWER BCD TECHNOLOGY
■ MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION
PowerSO36
■ 200mΩ RdsON COMPLEMENTARY DMOS
OUTPUT STAGE
Table 1. Order Codes
■ CMOS COMPATIBLE LOGIC INPUTS
■ THERMAL PROTECTION
Part Number
Package
STA502
PowerSO36 (Slug Up)
■ THERMAL WARNING OUTPUT
■ UNDER VOLTAGE PROTECTION
The device is particularly designed to make the out-
put stage of a mono All-Digital High Efficiency
(DDX™) amplifier capable to deliver 60W @ THD =
2 DESCRIPTION
STA502 is a monolithic dual half bridge stage in Mul-
tipower BCD Technology.
10% at V 32V output power on 8
pins have threshold proportional to V pin voltage.
Ω
load. The input
cc
L
Figure 2. Block Diagram
+VCC
C55
VCC
VL
23
24
15
+3.3V
C30
1µF
CONFIG
1000µF
14
12
PWRDN
PWRDN
FAULT
25
GND
PROTECTIONS
R57
10K
R59
10K
27
26
VCCB
&
C31
1µF
LOGIC
GND
TRI-STATE
TH_WAR
13
C58
100nF
GND
GND
29
30
28
TH_WAR
VDD
VDD
VSS
VSS
21
22
33
34
REGULATORS
7
VCCA
C32
1µF
M17
M15
M16
M14
C58
100nF
C53
100nF
L113 22µH
VCCSIGN
8
9
35
OUTA
C60
100nF
C110
100nF
V
CCSIGN
36
31
20
19
OUTA
GNDA
C109
330pF
C107
100nF
6
4
R103
6
INA
INA
C108
470nF
C106
100nF
GND-Reg
GND-Clean
INB
VCCB
R104
20
R102
6
C33
1µF
3
2
C111
OUTB
OUTB
GNDB
INB
100nF
32
1
GNDSUB
L112 22µH
5
10
11
16
17
D02AU1447A
N.C. N.C.
N.C. N.C.
Rev. 2
1/9
November 2004
STA502
Table 2. Pin Description
N°
1
Pin
Description
GND-SUB
OUTB
Substrate ground
Output half bridge
Positive Supply
Negative Supply
Negative Supply
Positive Supply
Output half bridge
2 ; 3
4
V
CC
5
GND
GND
6
7
V
CC
8 ; 9
10 ; 11
12
OUTA
N.C.
V
CC
Positive Supply
Negative Supply
Negative Supply
Positive Supply
13
GND
GND
14
15
V
CC
16 ; 17
18
N.C.
NC
Not connected
19
GND-Clean Logical ground
20
GND-Reg
Vdd
Ground for regulator Vdd
21 ; 22
23
5V Regulator referred to ground
High logical state setting voltage
VL
24
GND
25
PWRDN
Stand-by pin
26
TRI-STATE Hi-Z pin
27
FAULT
TH-WAR
GND
Fault pin advisor
28
Thermal warning advisor
29
30
GND
31
INA
Input of half bridge
32
INB
Input of half bridge
33 ; 34
35 ; 36
V
5V Regulator referred to + V
Signal Positive supply
SS
CC
Vcc Sign
2/9
STA502
Table 3. FUNCTIONAL PIN STATUS
PIN NAME
FAULT
Logical value
IC -STATUS
0
1
0
1
0
1
0
1
Fault detected (Short circuit, or Thermal ..)
Normal Operation
FAULT *
TRI-STATE
TRI-STATE
PWRDN
PWRDN
THWAR
All powers in Hi-Z state
Normal operation
Low absorpion
Normal operation
Temperature of the IC =130°C
Normal operation
THWAR*
* : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
Figure 3. PIN CONNECTION
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
V
CCSign
GND-SUB
OUTB
OUTB
VCC
VCCSign
VSS
3
4
VSS
5
INB
GND
GND
VCC
6
INA
7
GND
8
GND
OUTA
OUTA
N.C
9
TH_WAR
FAULT
TRI-STATE
PWRDN
GND
10
11
12
13
14
15
16
17
18
N.C.
VCC
GND
GND
VCC
V
L
V
V
DD
DD
N.C.
GND-Reg
N.C.
GND-Clean
N.C.
D02AU1449
3/9
STA502
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
DC Supply Voltage (Pin 4,7,12,15)
Maximum Voltage on pins 23 to 32
Power Dissipation (T = 70°C)
Value
40
Unit
V
V
CC
V
5.5
V
max
P
50
W
tot
case
T
Operating Temperature Range
0 to 70
-40 to 150
°C
°C
op
T
, T
Storage and Junction Temperature
stg
j
Table 5. THERMAL DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
°C/W
°C
T
Thermal Resistance Junction to Case (thermal pad)
Thermal shut-down junction temperature
Thermal warning temperature
2.5
j-case
T
150
130
25
jSD
T
°C
warn
hSD
t
Thermal shut-down hysteresis
°C
Table 6. Electrical Characteristcs (VL = 3.3V; VCC = 30V; Tamb = 25°C unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
R
Power Pchannel/Nchannel
MOSFET RdsON
Id=1A;
200
270
mΩ
dsON
I
Power Pchannel/Nchannel
leakage Idss
V
=35V;
CC
50
µA
%
dss
g
g
Power Pchannel RdsON
Matching
Id=1A;
Id=1A;
95
95
N
P
Power Nchannel RdsON
Matching
%
Dt_s
Dt_d
Low current Dead Time (static)
see test circuit no.1; see fig. 14
10
20
50
ns
ns
High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω
Id=3.5A; see fig. 3
t
Turn-on delay time
Turn-off delay time
Rise time
Resistive load
100
100
25
ns
ns
ns
ns
V
d ON
t
Resistive load
d OFF
t
Resistive load; as fig.14
Resistive load; as fig. 4
r
t
f
Fall time
25
V
Supply voltage operating voltage
High level input voltage
10
36
CC
V
V /2
L
V
IN-High
+300mV
V
Low level input voltage
High level Input current
V /2
300mV
-
V
IN-Low
L
I
Pin voltage = V
1
µA
IN-H
L
4/9
STA502
Table 6. Electrical Characteristcs (continued)
Symbol
Parameter
Test conditions
Pin voltage = 0.3V
Min.
Typ.
1
Max.
Unit
µA
I
Low level input current
IN-L
IPWRDN-H High level PWRDN pin input
current
V = 3.3V
L
35
µA
V
Low logical state voltage VLow
(pin PWRDN, TRISTATE) (note 1)
V = 3.3V
0.8
V
V
Low
L
V
High logical state voltage VHigh
(pin PWRDN, TRISTATE) (note 1)
V = 3.3V
L
1.7
3
High
I
Supply current from Vcc in Power PWRDN = 0
Down
mA
VCC-
PWRDN
I
Output Current pins
FAULT -TH-WARN when
FAULT CONDITIONS
FAULT
Vpin = 3.3V
Tri-state=0;
1
mA
mA
mA
I
Supply current from Vcc in Tri-
state
22
50
VCC-hiz
I
Supply current from Vcc in
operation
(both channel switching)
Input pulse width = 50% Duty;
Switching Frequency = 384KHz;
No LC filters;
VCC
I
Isc (short circuit current limit)
Undervoltage protection threshold
Output minimum pulse width
4
6
7
8
A
V
out-sh
V
UV
pw-min
t
No Load
70
150
ns
Table 7.
VL
2.7
3.3
5
VLow min
0.7
VHigh max
1.5
Unit
V
0.8
1.7
V
0.85
1.85
V
Notes: 1. The following table explains the VLow, VHigh variation with VL
Table 8. Logic Truth (see fig. 5)
OUTPUT
MODE
TRI-STATE
INA
INB
Q1
Q2
Q3
Q4
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
Hi-Z
DUMP
ON
OFF
ON
NEGATIVE
POSITIVE
Not used
OFF
ON
OFF
OFF
ON
OFF
5/9
STA502
Figure 4. Test Circuit.
OUTY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
DTf
Duty cycle = 50%
INY
M58
M57
OUTY
R 8Ω
+
-
V67 =
vdc = Vcc/2
gnd
D02AU1448
Figure 5.
+VCC
Q1
OUTA
Q2
OUTB
INA
INB
Q3
Q4
GND
D02AU1450
Figure 6.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
M57
M64
M63
Q1
OUTA
Iout=4.5A
Q2
OUTB
Iout=4.5A
DTin(A)
DTout(B)
L68 22µ
DTin(B)
INB
Rload=8Ω
INA
L67 22µ
Q3
C69
470nF
C70
470nF
Q4
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
D03AU1517
6/9
STA502
Figure 7. Power SO36 (SLUG UP) Mechanical Data & Package Dimensions
mm
inch
TYP. MAX.
0.135
0.126
0.039
0.008
-0.0015
0.015
0.012
0.630
0.38
DIM.
MIN.
3.25
3.1
TYP. MAX. MIN.
3.43 0.128
OUTLINE AND
MECHANICAL DATA
A
A2
A4
A5
a1
b
3.2
1
0.122
0.031
0.8
0.2
0.030
0.22
0.23
15.8
9.4
-0.040 0.0011
0.38 0.008
0.32 0.009
c
D
16
0.622
0.37
D1
D2
E
9.8
1
0.039
0.57
13.9
10.9
14.5 0.547
11.1 0.429
2.9
E1
E2
E3
E4
e
0.437
0.114
0.244
1.259
0.026
0.435
0.003
0.625
0.043
0.043
10˚
5.8
2.9
6.2
3.2
0.228
0.114
0.65
e3
G
11.05
0
0.075
15.9
1.1
0
H
15.5
0.61
h
L
0.8
1.1
0.031
N
10˚
s
8 ˚
8˚
PowerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
7183931 D
7/9
STA502
Table 9. Revision History
Date
Revision
Description of Changes
May 2004
1
2
First Issue
Modificated the fig2; changed Ibias pin to VL pin.
November 2004
8/9
STA502
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
DDX is a trademark of Apogee tecnology inc.
© 2004 STMicroelectronics - All rights reserved
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9/9
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