STA516B13TR [STMICROELECTRONICS]
60 V 6 A quad power half bridge; 60 V 6的四核电源半桥
| 型号： | STA516B13TR |
| 厂家： | 
ST |
| 描述： | 60 V 6 A quad power half bridge |
| 文件： | 总13页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA516B
60 V 6 A quad power half bridge
Features
■ Minimum input output pulse width distortion
■ 200 mΩ R
complementary DMOS output
dsON
stage
■ CMOS compatible logic inputs
■ Thermal protection
Power SO36 slug up
■ Thermal warning output
■ Under voltage protection
Description
STA516B is a monolithic quad half bridge stage in
Multipower BCD Technology. The device can be
used as dual bridge or reconfigured, by
connecting CONFIG pin to Vdd pin, as single
bridge with double current capability, and as half
bridge (Binary mode) with half current capability.
The device is particularly designed to make the
output stage of a stereo all-digital high efficiency
(DDX™) amplifier capable to deliver 160 + 160 W
@ THD = 10 % at V 50 V output power on 8 Ω
cc
load and 320 W @ THD = 10 % at V 50V on 4 Ω
cc
load in single BTL configuration.
The input pins have threshold proportional to V
pin voltage.
L
Table 1.
Device summary
Part number
Package
Packaging
STA516B
Power SO36 slug up
Power SO36 slug up
Tube
STA516B13TR
Tape and reel
March 2007
Rev 2
1/13
www.st.com
1
Contents
STA516B
Contents
1
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mechanical and package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
STA516B
Introduction
1
Introduction
Figure 1.
Application circuit (dual BTL)
+VCC
VCC1A
15
17
16
C30
1µF
C55
1000µF
IN1A
29
M3
M2
M5
M4
IN1A
L18 22µH
C20
VL
23
24
+3.3V
OUT1A
CONFIG
100nF
OUT1A
GND1A
C52
330pF
PWRDN
PWRDN
FAULT
25
C99
100nF
14
12
R98
6
PROTECTIONS
R57
10K
R59
10K
27
26
&
C23
470nF
8Ω
LOGIC
VCC1B
R63 R100
C101
100nF
TRI-STATE
20
6
C58
100nF
C31
1µF
11
10
C21
100nF
TH_WAR
IN1B
28
30
OUT1B
OUT1B
GND1B
TH_WAR
L19 22µH
IN1B
VDD
VDD
VSS
VSS
21
22
33
34
13
7
REGULATORS
V
CC2A
C32
1µF
M17
M15
M16
M14
C58
100nF
C53
100nF
L113 22µH
VCCSIGN
8
9
35
OUT2A
C60
100nF
C110
100nF
VCCSIGN
36
31
20
19
OUT2A
GND2A
C109
330pF
C107
100nF
6
4
R103
6
IN2A
IN2B
IN2A
C108
470nF
8Ω
GND-Reg
V
CC2B
R104
20
R102
6
C106
100nF
GND-Clean
C33
1µF
3
2
C111
100nF
OUT2B
OUT2B
GND2B
IN2B
32
1
L112 22µH
GNDSUB
5
D00AU1148B
3/13
Pin lists
STA516B
2
Pin lists
Table 2.
Number
Pin function
Pin
Description
1
GND-SUB Substrate ground
2, 3
4
OUT2B
Vcc2B
GND2B
GND2A
Vcc2A
OUT2A
OUT1B
Vcc1B
GND1B
GND1A
Vcc1A
OUT1A
NC
Output half bridge 2B
Positive supply
5
Negative supply
Negative supply
Positive supply
6
7
8, 9
10, 11
12
Output half bridge 2A
Output half bridge 1B
Positive supply
13
Negative supply
Negative supply
Positive supply
14
15
16, 17
18
Output half bridge 1A
Not connected
19
GND-clean Logical ground
20
GND-Reg Ground for regulator Vdd
21, 22
23
Vdd
5 V regulator referred to ground
VL
High logical state setting voltage
Configuration pin
24
CONFIG
PWRDN
25
Stand-by pin
26
TRI-STATE Hi-Z pin
27
FAULT
TH-WAR
IN1A
Fault pin advisor
28
Thermal warning advisor
Input of half bridge 1A
Input of half bridge 1B
Input of half bridge 2A
Input of half bridge 2B
5 V regulator referred to +Vcc
Signal positive supply
29
30
IN1B
31
IN2A
32
IN2B
33, 34
35, 36
Vss
Vcc sign
4/13
STA516B
Pin lists
Table 3.
Pin name
Functional pin status
Logical value
Status
FAULT
0
1
0
1
0
1
0
1
0
Fault detected (short circuit or thermal for example)
Normal operation
FAULT (1)
TRI-STATE
TRI-STATE
PWRDN
PWRDN
THWAR
All powers in Hi-Z state
Normal operation
Low absorption
Normal operation
Temperature of the IC =130 oC
THWAR(1)
Normal operation
CONFIG
Normal operation
OUT1A=OUT1B; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
CONFIG(2)
1
1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
2. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
Figure 2.
Pin connection
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
V
CCSign
GND-SUB
OUT2B
OUT2B
VCC2B
VCCSign
VSS
3
4
VSS
5
IN2B
GND2B
GND2A
6
IN2A
7
IN1B
VCC2A
8
IN1A
OUT2A
OUT2A
OUT1B
OUT1B
9
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
10
11
12
13
14
15
16
17
18
V
CC1B
GND1B
GND1A
V
L
V
V
VCC1A
DD
DD
OUT1A
OUT1A
N.C.
GND-Reg
GND-Clean
D01AU1273
5/13
Electrical characteristics
STA516B
3
Electrical characteristics
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
DC supply voltage (Pins 4,7,12,15)
Maximum voltage on pins 23 to 32
Operating temperature range
60
V
Vmax
Top
5.5
V
0 to 70
°C
°C
Tstg, Tj
Storage and junction temperature
-40 to 150
Table 5.
Symbol
Thermal data
Parameter
Min.
Typ.
Max.
2.5
Unit
Tj-case
TjSD
Twarn
thSD
Thermal resistance junction to case (thermal pad)
Thermal shut-down junction temperature
Thermal warning temperature
1
°C/W
°C
150
130
25
°C
Thermal shut-down hysteresis
°C
Table 6.
Electrical characteristics
(VL= 3.3 V; Vcc = 50 V; Tamb = 25 °C unless otherwise specified)
Unit
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
mΩ
Power Pchannel/Nchannel MOSFET
RdsON
RdsON
Id=1A
200 240
100
µA
%
Idss
gN
Power Pchannel/Nchannel leakage Idss
Power Pchannel RdsON matching
Power Nchannel RdsON matching
Low current dead time (static)
Id=1A
95
95
%
gP
Id=1A
ns
ns
Dt_s
see Figure 4
10
20
50
L=22µH, C = 470nF
Rl = 8 Ω, Id=4.5A
see Figure 5
Dt_d
High current dead time (dynamic)
ns
ns
ns
td ON
Turn-on delay time
Turn-off delay time
Resistive load
Resistive load
100
100
td OFF
Resistive load
see Figure 4
tr
tf
Rise time
Fall time
25
ns
Resistive load
see Figure 4
25
52
V
V
VCC
Supply operating voltage
High level input voltage
Low level input voltage
High level Input current
Low level input current
10
VIN-High
VIN-Low
IIN-H
VL/2 +300mV
V
VL/2 -300mV
µA
µA
Pin voltage = VL
1
1
IIN-L
Pin voltage = 0.3 V
6/13
STA516B
Electrical characteristics
Table 6.
Symbol
Electrical characteristics (continued)
(VL= 3.3 V; Vcc = 50 V; Tamb = 25 °C unless otherwise specified)
Unit
µA
V
Parameter
Test conditions
Min.
Typ.
Max.
IPWRDN-H High level PWRDN pin input current
VL= 3.3 V
35
Low logical state voltage VL (pin
VLow
VL = 3.3 V
VL = 3.3 V
0.8
PWRDN, TRISTATE)(seeTable 7)
V
High logical state voltage VH (pin
VHigh
1.7
3
PWRDN, TRISTATE)(seeTable 7)
mA
IVCC-
Supply current from Vcc in power down PWRDN = 0
PWRDN
Output current pins
mA
IFAULT
FAULT -TH-WARN when
FAULT CONDITIONS
Vpin = 3.3 V
Tristate = 0
1
mA
mA
IVCC-hiz
Supply current from Vcc in Tristate
22
Input pulse width
= 50 % duty
Supply current from Vcc in operation
both channel switching)
IVCC
Switching frequency
= 384 Khz;
70
No LC filters
A
Over current protection threshold Isc
IOUT-SH
6
8
7
10
(short circuit current limit)1(1)
V
V
VUV
Under voltage protection threshold
Over voltage protection threshold
Output minimum pulse width
VOV
60
25
70
40
ns
tpw_min
No load
1. See specific application note number: AN1994.
Table 7.
VLow, VHigh variation with VL
VL
VLow min
VHigh max
Unit
2.7
3.3
5
0.7
0.8
1.5
1.7
V
V
V
0.85
1.85
Table 8.
Logic truth table (see Figure 2)
Tristate
INxA
INxB
Q1
Q2
Q3
Q4
OFF
Output mode
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
Hi-Z
ON
OFF
ON
DUMP
ON
NEGATIVE
POSITIVE
Not used
OFF
ON
OFF
OFF
ON
OFF
7/13
Power supply and control sequencing
STA516B
4
Power supply and control sequencing
To guarantee correct operation and reliability, a correct turn on/off sequence must be
followed. Figure 3 shows the correct power on sequence.
Figure 3.
Correct power-on sequence
Vcc
V
VL
Vcc > VL
t
t
PWRDN
IN
t
Vcc must turn on before V in order to prevent uncontrolled current flowing through an
L
internal protection diode connected between V (logic supply) and Vcc (high power supply).
L
Failure to do so could result in damage to the device.
PWRDN must be released after V is switched on. An input signal can then be sent to the
L
power stage.
8/13
STA516B
Test
5
Test
Figure 4.
Test circuit
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
DTf
Duty cycle = 50%
INxY
M58
M57
OUTxY
R 8Ω
+
-
V67 =
vdc = Vcc/2
gnd
D03AU1458
Figure 5.
Current dead time test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
M57
M64
M63
Q1
OUTxA
Iout=4.5A
Q2
Q4
DTin(A)
INxA
DTout(B)
DTin(B)
INxB
Rload=8Ω
OUTxB
L67 22µ
L68 22µ
Iout=4.5A
Q3
C69
470nF
C70
470nF
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
D00AU1162
9/13
Test
STA516B
Figure 6.
Typical single BTL configuration to obtain 320 W @ THD 10 %, RL = 4 W,
VCC = 50 V
(a)
V
L
+3.3V
23
18
N.C.
12µH
100nF
GND-Clean
GND-Reg
17
16
OUT1A
OUT1A
19
20
100nF
FILM
11
10
100nF
X7R
10K
100nF
X7R
680nF
FILM
100nF
OUT1B
OUT1B
OUT2A
OUT2A
22Ω
6.2
1/2W
VDD
VDD
1/2W
21
22
24
4Ω
6.2
1/2W
CONFIG
9
8
330pF
X7R
TH_WAR
PWRDN
FAULT
TH_WAR
OUT2B
OUT2B
28
25
100nF
FILM
3
2
nPWRDN
12µH
10K
V
CC1A
CC1B
27
26
+36V
15
TRI-STATE
IN1A
1µF
2200µF
63V
100nF
X7R
V
29
30
31
32
12
7
IN1B
IN1A
IN1B
VCC2A
IN2A
+36V
IN2B
1µF
X7R
VSS
VSS
VCC2B
33
34
4
14
13
GND1A
GND1B
100nF
X7R
VCCSIGN
35
100nF
X7R
VCCSIGN
GNDSUB
GND2A
GND2B
36
1
6
5
Add.
D04AU1545
Figure 7.
Typical quad half bridge configuration
+VCC
VCC1P
15
C21
2200µF
IN1A
29
M3
M2
M5
M4
R61
5K
IN1A
C31 820µF
L11 22µH
17
16
V
23
24
L
+3.3V
OUTPL
C71
100nF
CONFIG
PWRDN
FAULT
R41
20
C91
1µF
4Ω
OUTPL
PWRDN
25
C81
100nF
14
12
PGND1P
R51
6
R62
5K
C41
330pF
PROTECTIONS
R57
10K
R59
10K
27
26
&
LOGIC
VCC1N
TRI-STATE
C58
100nF
C51
1µF
C61
100nF
11
10
R63
5K
TH_WAR
IN1B
28
30
OUTNL
OUTNL
PGND1N
C32 820µF
L12 22µH
TH_WAR
C72
100nF
R42
20
IN1B
C92
1µF
4Ω
VDD
VDD
VSS
VSS
21
22
33
34
13
7
C82
100nF
R52
6
R64
5K
C42
330pF
REGULATORS
VCC2P
M17
M15
M16
M14
R65
5K
C58
100nF
C53
100nF
C33 820µF
L13 22µH
VCCSIGN
8
9
35
OUTPR
C60
100nF
C73
100nF
R43
20
V
CCSIGN
IN2A
C93
1µF
4Ω
36
31
20
19
OUTPR
C83
100nF
6
4
PGND2P
R53
6
R66
5K
IN2A
IN2B
C43
330pF
GND-Reg
VCC2N
GND-Clean
C52
1µF
C62
100nF
3
2
R67
5K
OUTNR
OUTNR
PGND2N
C34 820µF
L14 22µH
IN2B
32
1
C74
100nF
R44
20
GNDSUB
C94
1µF
4Ω
5
C84
100nF
R54
6
R68
5K
C44
330pF
D03AU1474
For more information, refer to the application note “ST50X and STA51X digital power
amplifiers”.
a. A PWM modulator as driver is required. This result was obtained using the STA30X+STA50X demo board.
10/13
STA516B
Mechanical and package data
6
Mechanical and package data
Figure 8.
Power SO36 (slug up) mechanical data and package dimension
mm
inch
TYP. MAX.
0.135
0.126
0.039
0.008
-0.0015
0.015
0.012
0.630
0.38
DIM.
MIN.
3.25
3.1
TYP. MAX. MIN.
3.43 0.128
OUTLINE AND
MECHANICAL DATA
A
A2
A4
A5
a1
b
3.2
1
0.122
0.031
0.8
0.2
0.030
0.22
0.23
15.8
9.4
-0.040 0.0011
0.38 0.008
0.32 0.009
c
D
16
0.622
0.37
D1
D2
E
9.8
1
0.039
0.57
13.9
10.9
14.5 0.547
11.1 0.429
2.9
E1
E2
E3
E4
e
0.437
0.114
0.244
1.259
0.026
0.435
0.003
0.625
0.043
0.043
10˚
5.8
2.9
6.2
3.2
0.228
0.114
0.65
e3
G
11.05
0
0.075
15.9
1.1
0
H
15.5
0.61
h
L
0.8
1.1
0.031
N
10˚
s
8 ˚
8˚
PowerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
7183931 D
11/13
Revision history
STA516B
7
Revision history
Table 9.
Date
Document revision history
Revision
Changes
01-Feb-2007
19-Mar-2007
1
2
Initial release
Update to reflect product maturity.
12/13
STA516B
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13/13
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