STD90N02L [STMICROELECTRONICS]
N-channel 24V - 0.0052ohm - 60A - DPAK - IPAK STripFET TM III Power MOSFET; N沟道24V - 0.0052ohm - 60A - DPAK - IPAK的STripFET TM III功率MOSFET
| 型号： | STD90N02L |
| 厂家： | 
ST |
| 描述： | N-channel 24V - 0.0052ohm - 60A - DPAK - IPAK STripFET TM III Power MOSFET |
| 文件： | 总17页 (文件大小：806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STD90N02L
STD90N02L-1
N-channel 24V - 0.0052Ω - 60A - DPAK - IPAK
STripFET™ III Power MOSFET
General features
Type
V
R
I
D
DSS
DS(on)
STD90N02L
24V
24V
<0.006Ω
<0.006Ω
60A
60A
STD90N02L-1
3
3
■ R
* Qg industry’s benchmark
DS(ON)
2
1
1
■ Conduction losses reduced
■ Switching losses reduced
■ Low threshold device
DPAK
IPAK
■ In compliance with the 2002/95/ec european
directive
Description
Internal schematic diagram
This series of products utilizes the latest
advanced design rules of ST’s proprietary
STripFET™ technology. This is suitable for the
most demanding DC-DC converter application
where high efficiency is to be achieved.
Applications
■ Switching application
Order codes
Part number
Marking
Package
Packaging
STD90N02L-1
STD90N02L
D90N02L
D90N02L
IPAK
Tube
DPAK
Tape & reel
May 2006
Rev 3
1/17
www.st.com
17
Contents
STD90N02L - STD90N02L-1
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
6
Test circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
STD90N02L - STD90N02L-1
Electrical ratings
1
Electrical ratings
Table 1.
Symbol
(1)
Absolute maximum ratings
Parameter
Value
Unit
Drain-source voltage rating
30
V
V
spike
V
Drain-source voltage (V = 0)
24
24
V
V
V
DS
GS
V
Drain-gate voltage (R = 20kΩ)
DGR
GS
V
Gate-source voltage
± 20
GS
(2)
Drain current (continuous) at T = 25°C
60
42
A
A
A
I
C
D
I
Drain current (continuous) at T = 100°C
D
C
(3)
Drain current (pulsed)
240
I
DM
P
Total dissipation at T = 25°C
70
W
TOT
C
Derating factor
0.47
W/°C
(4)
Single pulse avalanche energy
360
mJ
E
AS
T
Operating junction temperature
Storage temperature
j
-55 to 175
°C
T
stg
1. Guaranted when external Rg=4.7Ω and Tf<Tfmax
2. Value limited by wire bonding
3. Pulse width limited by safe operating area
4. Starting Tj =25°C, Id = 30A, VDD = 15V
Table 2.
Symbol
Thermal data
Parameter
Value
Unit
Rthj-case Thermal resistance junction-case Max
Rthj-amb Thermal resistance junction-amb Max
2.14
100
275
°C/W
°C/W
°C
T
Maximum lead temperature for soldering purpose
l
3/17
Electrical characteristics
STD90N02L - STD90N02L-1
2
Electrical characteristics
(Tcase =25°C unless otherwise specified)
Table 3.
Symbol
On /off states
Parameter
Test conditions
Min.
Typ.
Max. Unit
Drain-source breakdown
voltage
V
I = 25mA, V = 0
24
V
(BR)DSS
D
GS
V
= 20V,
1
µA
µA
Zero gate voltage drain
DS
DS
I
I
DSS
GSS
current (V = 0)
V
V
V
= 20V,Tc = 125°C
10
GS
Gate body leakage
= ±20V
±100
nA
V
GS
DS
current (V = 0)
DS
V
= V , I = 250µA
Gate threshold voltage
1
1.8
GS(th)
DS(on)
GS
D
V
V
= 10V, I = 30A
0.0052 0.006
0.007 0.011
Ω
Ω
GS
GS
D
Static drain-source on
resistance
R
= 5V, I = 15A
D
Table 4.
Symbol
Dynamic
Parameter
Test conditions
Min.
Typ.
Max. Unit
Forward
transconductance
(1)
V
V
=10V, I = 18A
27
S
g
DS
DS
D
fs
Input capacitance
Output capacitance
C
C
iss
2050
545
70
pF
pF
pF
=16V, f=1MHz, V =0
oss
GS
Reverse transfer
capacitance
C
rss
Q
V
V
=10V, I = 60A
g
Total gate charge
Gate-source charge
Gate-drain charge
17
7.7
3.5
22
3
nC
nC
nC
DD
D
Q
Q
=5V
gs
gd
GS
(see Figure 15)
f=1MHz Gate DC Bias =0
R
Gate input resistance test signal level =20mV
open drain
0.5
1.5
14
Ω
G
(2)
OSS
V
=10V, V =0V
GS
Output charge
nC
Q
DS
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
2. Qoss.= Coss * D Vin, Coss = Cgd + Cgd. (see Appendix A)
4/17
STD90N02L - STD90N02L-1
Electrical characteristics
Min. Typ. Max Unit
Table 5.
Symbol
Switching times
Parameter
Test conditions
=10V, I =30A,
t
Turn-on delay time
Rise time
12
200
18
ns
ns
ns
ns
d(on)
V
DD
D
t
r
R =4.7Ω, V =5V
G
GS
t
Turn-off delay time
Fall time
d(off)
(see Figure 17)
t
25
33
f
Table 6.
Symbol
Source drain diode
Parameter
Test conditions
Min. Typ. Max. Unit
I
Source-drain current
60
A
A
SD
I
Source-drain current (pulsed)
240
SDM
(1)
I
I
=30A, V =0
Forward on voltage
1.3
V
V
SD
GS
SD
t
=60A, di/dt = 100A/µs,
=15V, Tj=150°C
rr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
36
65
ns
nC
A
SD
V
Q
DD
rr
3.6
(see Figure 20)
I
RRM
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
5/17
Electrical characteristics
STD90N02L - STD90N02L-1
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5. Transconductance
Figure 6. Static drain-source on resistance
6/17
STD90N02L - STD90N02L-1
Electrical characteristics
Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations
Figure 9. Normalized gate threshold voltage Figure 10. Normalized on resistance vs
vs temperature
temperature
Figure 11. Source-drain diode forward
characteristics
Figure 12. Normalized B
vs temperature
VDSS
7/17
Electrical characteristics
STD90N02L - STD90N02L-1
Figure 13. Allowable I vs time in avalanche
AV
The previous curve gives the single pulse safe operating area for unclamped inductive
loads, under the following conditions:
P
E
=0.5*(1.3*B
*I
)
D(AVE)
AS(AR)
VDSS AV
=P
*t
D(AVE) AV
Where:
is the allowable current in avalanche
I
AV
P
is the average power dissipation in avalanche (single pulse)
D(AVE)
t
is the time in avalanche
AV
8/17
STD90N02L - STD90N02L-1
Appendix A
Figure 14. Synchronous buck converter
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the wotking
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
The low side (SW2) device requires:
Very low RDS(on) to reduce conduction losses
Small Qgls to reduce the gate charge losses
Small Coss to reduce losses due to output capacitance
Small Qrr to reduce losses on SW1 during its turn-on
The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to
avoid the cross conduction phenomenon.
The high side (SW1) device requires:
Small Rg and Lg to allow higher gate current peak and to limit the voltage feedback on the
gate
Small Qg to have a faster commutation and to reduce gate charge losses
Low RDS(on) to reduce the conduction losses
9/17
STD90N02L - STD90N02L-1
Low side switch (SW2)
Table 7.
Power losses
High side switch (SW1)
DS(on) • IL2 • δ
DS(on) • IL2 • (1 – δ)
R
P
R
conduction
IL
P
Zero voltage switching
Vin • (Qgsth(SW1) + Qgd(SW1)) • f • ---
switching
Ig
1Vin • Qrr(SW2) • f
recovery
Not applicable
Not applicable
P
diode
conduction
V
f(SW2) • IL • tdeadtime • f
gls(SW2) • Vgg • f
Q
P
P
Q
g(SW1) • Vgg • f
gate(Qg)
Qoss
Vin • Qoss(SW2) • f
Vin • Qoss(SW1) • f
------------------------------------------------
------------------------------------------------
2
2
Table 8.
Power losses parameters
Paramter
Meaning
d
Duty-cycle
Q
Q
Post threshold gate charge
gsth
gls
Third quadrant gate charge
On state losses
Pconduction
Pswitching
Pdiode
On-off transition losses
Conduction and reverse recovery diode losses
Gate driver losses
Pgate
P
Output capacitance losses
Qoss
10/17
STD90N02L - STD90N02L-1
Test circuits
3
Test circuits
Figure 15. Switching times test circuit for
resistive load
Figure 16. Gate charge test circuit
Figure 17. Test circuit for inductive load
switching and diode recovery times
Figure 18. Unclamped inductive load test
circuit
Figure 19. Unclamped inductive waveform
Figure 20. Switching time waveform
11/17
Package mechanical data
STD90N02L - STD90N02L-1
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at :www.st.com
12/17
STD90N02L - STD90N02L-1
Package mechanical data
TO-251 (IPAK) MECHANICAL DATA
mm
inch
DIM.
MIN.
2.2
TYP.
MAX.
2.4
MIN.
0.086
0.035
0.027
0.025
0.204
TYP.
MAX.
0.094
0.043
0.051
0.031
0.212
0.033
A
A1
A3
B
0.9
1.1
0.7
1.3
0.64
5.2
0.9
B2
B3
B5
B6
C
5.4
0.85
0.3
0.012
0.95
0.6
0.6
6.2
6.6
4.6
16.3
9.4
1.2
1
0.037
0.023
0.023
0.244
0.260
0.181
0.641
0.370
0.047
0.039
0.45
0.48
6
0.017
0.019
0.236
0.252
0.173
0.626
0.354
0.031
C2
D
E
6.4
4.4
15.9
9
G
H
L
L1
L2
0.8
0.8
0.031
H
L
D
L2
L1
0068771-E
13/17
Package mechanical data
STD90N02L - STD90N02L-1
DPAK MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
A1
A2
B
2.2
0.9
2.4
1.1
0.23
0.9
5.4
0.6
0.6
6.2
0.086
0.035
0.001
0.025
0.204
0.017
0.019
0.236
0.094
0.043
0.009
0.035
0.212
0.023
0.023
0.244
0.03
0.64
5.2
b4
C
0.45
0.48
6
C2
D
D1
E
5.1
0.200
6.4
6.6
0.252
0.260
E1
e
4.7
0.185
0.090
2.28
e1
H
4.4
9.35
1
4.6
0.173
0.368
0.039
0.181
0.397
10.1
L
(L1)
L2
L4
R
2.8
0.8
0.110
0.031
0.6
0°
1
0.023
0°
0.039
8°
0.2
0.008
V2
8°
0068772-F
14/17
STD90N02L - STD90N02L-1
Package mechanical data
5
Package mechanical data
DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
mm
MIN. MAX. MIN. MAX.
330 12.992
inch
DIM.
A
B
C
D
G
N
T
1.5
12.8
20.2
16.4
50
0.059
13.2 0.504 0.520
0.795
18.4 0.645 0.724
1.968
22.4
0.881
BASE QTY
BULK QTY
2500
TAPE MECHANICAL DATA
2500
mm
MIN. MAX. MIN. MAX.
6.8 0.267 0.275
10.4 10.6 0.409 0.417
12.1 0.476
inch
DIM.
A0
B0
B1
D
7
1.5
1.5
1.6 0.059 0.063
0.059
D1
E
1.65 1.85 0.065 0.073
7.4 7.6 0.291 0.299
2.55 2.75 0.100 0.108
F
K0
P0
P1
P2
R
3.9
7.9
1.9
40
4.1 0.153 0.161
8.1 0.311 0.319
2.1 0.075 0.082
1.574
W
15.7
16.3 0.618 0.641
15/17
Revision history
STD90N02L - STD90N02L-1
6
Revision history
Table 9.
Date
Revision history
Revision
Changes
29-Aug-2005
07-Apr-2006
03-May-2006
1
2
3
First release
New template
New value on Table 3, new curve (see Figure 13)
16/17
STD90N02L - STD90N02L-1
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED,
AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS,
NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
17/17
相关型号：
STD90N02L-1
N-channel 24V - 0.0052ohm - 60A - DPAK - IPAK STripFET TM III Power MOSFET
STMICROELECTR
STD90N4F3_08
N-channel 40 V, 5.4 mΩ, 80 A, DPAK, TO-220, IPAK, I2PAK STripFET™ Power MOSFET
STMICROELECTR
STD90N4F3_09
N-channel 40 V, 5.0 mΩ, 80 A, DPAK, TO-220, IPAK, I2PAK STripFET™ III Power MOSFET
STMICROELECTR
STD90NS3LLH7
N-channel 30 V, 2.8 mOhm typ., 80 A STripFET H7 Power MOSFET plus monolithic Schottky in a DPAK package
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明