STE2004DIE2 [STMICROELECTRONICS]
102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER; 102 ×65单芯片LCD控制器/驱动
| 型号： | STE2004DIE2 |
| 厂家： | 
ST |
| 描述： | 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER |
| 文件： | 总66页 (文件大小：1082K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STE2004
102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER
■ Low Power Consumption, suitable for battery
1 FEATURES
■ 102 x 65 bits Display Data RAM
■ Programmable MUX rate
■ Programmable Frame Rate
■ X,Y Programmable Carriage Return
operated systems
■ Logic Supply Voltage range from 1.7 to 3.6V
■ High Voltage Generator Supply Voltage range
from 1.75 to 4.5V
■ Display Supply Voltage range from 4.5 to 14.5V
■ Backward Compatibility with STE2001/2
■ Dual Partial Display Mode
■ Row by Row Scrolling
■ N-Line Inversion
2 DESCRIPTION
■ Automatic data RAM Blanking procedure
■ Selectable Input Interface:
The STE2004 is a low power CMOS LCD control-
ler driver. Designed to drive a 65 rows by 102 col-
umns graphic display, it provides all necessary
functions in a single chip, including on-chip LCD
supply and bias voltages generators, resulting in a
minimum of externals components and in a very
low power consumption.
STE2004 features six standard interfaces (3-lines
Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel,
8080 parallel & I2C) for ease of interfacing with the
host micro-controller
• I2C Bus Fast and Hs-mode (read and write)
• 68000 & 8080 Parallel Interfaces (read and write)
• 3-lines and 4-lines SPI Interface (read and write)
• 3-lines 9 bit Serial Interface (read and write)
■ Fully Integrated Oscillator requires no external
components
■ CMOS Compatible Inputs
■ Fully Integrated Configurable LCD bias voltage
generator with:
• Selectable multiplication factor (up to 5
X)
Table 1. Order Codes
• Effective sensing for High Precision Output
• Eight selectable temperature compensation
coefficients
Part Numbers
STE2004DIE1
STE2004DIE2
Type
Bumped Wafers
Bumped Dice on Waffle Pack
■ Designed for chip-on-glass (COG) applications.
Figure 1. Block Diagram
CO to C101
R0 to R64
OSC_IN
OSC_OUT
FR_IN
TIMING
GENERATOR
OSC
COLUMN
DRIVERS
ROW
DRIVERS
MASTER
SLAVE SYNC
CLOCK
FR_OUT
BIAS VOLTAGE
GENERATOR
DATA
LATCHES
SHIFT
REGISTER
VSENSE SLAVE
VLCD
HIGH VOLTAGE
GENERATOR
VLCDSENSE
65 x 102
RAM
SCROLL
LOGIC
RES
RESET
TEST_MODE
TEST_VREF
TEST
VSSAUX
VDD1,2
DISPLAY
CONTROL
LOGIC
DATA
REGISTER
INSTRUCTION
REGISTER
ICON_MODE
EXT
VSS
SEL1,2
SEL 0
SEL 1
SEL 2
3 & 4 Line SPI
Parallel 68K
I2C BUS
Parallel 8080
9 Bit SERIAL
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT
E/WR R/W- RD D/C
CS
DB0
to
LR0047
DB7
Rev. 4
1/66
July 2004
STE2004
Table 2. Pin Description
N°
Pad
Type
Function
R0 to R64
1-6
O
LCD Row Driver Output
109-141
C0 to C101
VSS
6-107
192-203
156-163
164-171
205-209
204
O
LCD Column Driver Output
Ground pads.
GND
VDD1
Supply IC Positive Power Supply
VDD2
Supply Internal Generator Supply Voltages.
VLCD
Supply Voltage Multiplier Output
VLCDSENSE
Supply Voltage Multiplier Regulation Input. VLCDOUT Sensing for Output Voltage Fine Tuning
Supply Voltage reference for SLAVE CHARGE PUMP
VSENSE_SLAVE
VSSAUX
145
190-177-
147
O
Ground Reference for Pins Configuration
VDD1AUX
142
O
I
VDD1 Reference for Pins Configuration
SEL1,2,3
152
153
154
Interface Mode Selection - CANNOT BE LEFT FLOATING
SEL3
SEL2
SEL1
Interface
2
GND / VSSAUX GND / VSSAUX GND / VSSAUX
I C
GND / VSSAUX GND / VSSAUX
VDD1
GND / VSSAUX
VDD1
SPI 4-Lines 8 bit
SPI 3-Lines 8 bit
GND / VSSAUX
GND / VSSAUX
VDD1
VDD1
VDD1
Serial 3-Lines 9 bit
Parallel 8080-series
Parallel 68000-series
GND / VSSAUX GND / VSSAUX
GND / VSSAUX VDD1
VDD1
EXT_SET
151
155
I
I
Extended Instruction Set Selection - CANNOT BE LEFT FLOATING
EXT PAD CONFIG
GND or VSSAUX
VDD1
INSTRUCTION SET SELECTED
BASIC
EXTENDED
ICON_MODE
Extended Instruction Set Selection - CANNOT BE LEFT FLOATING
ICON MODE PAD CONFIG
GND or VSSAUX
VDD1
ICON MODE STATUS
DISBLED
ENABLED
SDOUT
180
179
O
I
Serial & SPI Data Output - IF UNUSED MUST BE LEFT FLOATING
SDIN - Serial & SPI Interface Data Input - CANNOT BE LEFT FLOATING
SDIN - SDAIN
SDAIN - I2C Bus Data In - CANNOT BE LEFT FLOATING
I
SCLK - SCL
181
I
I
SCLK - Serial & SPI Interface Clock - CANNOT BE LEFT FLOATING
SCL - I2C bus Clock - CANNOT BE LEFT FLOATING
I2C Bus Data Out IF UNUSED MUST BE LEFT FLOATING
I2C Slave Address BIT 0 - CANNOT BE LEFT FLOATING
SDA_OUT
SA0
178
149
148
O
I
I2C Slave Address BIT 1- CANNOT BE LEFT FLOATING
SA1
I
DB0 to DB7
R/W - RD
182-189
175
I/O
I
Parallel Interface 8 Bit Data Bus - CANNOT BE LEFT FLOATING
R/W - 68000 Series Parallel Interface Read & Write Control Input
- CANNOT BE LEFT FLOATING
I
I
RD - 8080 Series Parallel Interface Read enable Clock Input
- CANNOT BE LEFT FLOATING
E / WR
176
E - 68000 Series Parallel Interface Read & Write Clock Input
- CANNOT BE LEFT FLOATING
2/66
STE2004
Table 2. Pin Description (continued)
N°
Pad
Type
Function
E / WR
176
I
WR - 8080 Series Parallel Interface - Write enable clock input
- CANNOT BE LEFT FLOATING
RES
D/C
CS
172
174
173
I
I
I
Reset Input. Active Low.
Interface Data/Command Selector- CANNOT BE LEFT FLOATING
Serial & Parallel Interfaces ENABLE. When Low the Incoming Data are Clocked In.
CANNOT BE LEFT FLOATING
TEST_MODE
TEST_VREF
OSCIN
191
146
144
I
O
I
Test Pad - 50 kohm internal Pull-down MUST BE CONNECTED TO VSS/VSSAUX
Test Pad - MUST BE LEFT FLOATING
Oscillator Input:
OSC_IN
High
Configuration
Internal Oscillator Enabled
Internal Oscillator Disabled
Internal Oscillator Disabled
Low
External Scillator
OSCOUT
FR_OUT
210
211
O
O
Internal/External Oscillator Out - IF UNUSED MUST BE LEFT FLOATING
Master Slave Frame Inversion Synchronization.
IF UNUSED MUST BE LEFT FLOATING
FR_IN
M/S
143
100
I
I
Master Slave Frame Inversion Synchronization.
CANNOT BE LEFT FLOATING
Master/Slave Configuration Bit:- CANNOT BE LEFT FLOATING
M/S PIN OSC_OUT FR_OUT
FR_IN
Charge Pump
High
Low
ENABLED
ENABLED
Enabled Disabled AuxVsense Disabled
Enabled Enabled Charge Pump in Slave Mode or Ext
Power
3/66
STE2004
Figure 2. Chip Mechanical Drawing
MARK_1
ROW
5
ROW28
ROW31
ROW
COL
0
0
FR_OUT
OSC_OUT
MARK_3
VLCD
STE2004
VLCDSENSE
VSS
TEST_MODE
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK - SCL
SDOUT
SDIN - SDAIN
SDAOUT
COL 50
COL 51
VSSAUX
E - WR
(0,0)
X
R/W - RD
D/C
Y
CS
RES
MARK_4
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
COL 101
ROW 32
ROW64/ICON
ROW63
ROW 37
ROW60
MARK_2
LR0048
4/66
STE2004
Figure 3. Improved ALTH & PLESKO Driving Method
V
LCD
V
V
2
3
∆V (t)
1
ROW 0
R0 (t)
∆V (t)
2
V
V
4
5
V
SS
V
LCD
V
V
2
3
ROW 1
R1 (t)
V
V
4
5
V
SS
V
LCD
V
V
2
3
COL 0
C0 (t)
V
V
4
5
V
SS
V
LCD
V
V
2
3
COL 1
C1 (t)
V
V
4
5
V
SS
SS
SS
V
LCD
- V
- V
V
3
V
LCD
- V
2
V - V
4 5
V (t)
state1
0V
0V
V
3
- V
SS
V - V
SS 5
V
V
- V
LCD
4
V
- V
- V
LCD
SS
- V
LCD
SS
V
3
SS
V
LCD
- V
2
V
4
- V
5
V (t)
state2
0V
0V
V
3
- V
SS
V
SS
- V
5
V
V
- V
LCD
4
- V
LCD
SS
.......
.......
0
..... 64
1
2
3
4
5
6
7
8
9
..... 64
0
1
2
3
4
5
6
7
8
9
FRAME n
FRAME n + 1
D00IN1154
∆V (t) = C1(t) - R0(t)
1
∆V (t) = C1(t) - R1(t)
2
5/66
STE2004
3 CIRCUIT DESCRIPTION
3.1 Supplies Voltages and Grounds
VDD2 is supply voltages to the internal voltage generator (see below). If the internal voltage generator is
not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the IC. VDD1 supply voltage
could be different form VDD2
.
2 VLCD
(n + 4)
V
≥ ------------------------ + 200mV
DD2
3.2 Internal Supply Voltage Generator
The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display
supply voltage generation. The multiplying factor can be programmed to be: Auto, X5, X4, X3, X2, using
the ’set CP Multiplication’ Command. If Auto is set, the multiplying factor is automatically selected to have
the lowest current consumption in every condition. This make possible to have an input voltage that chang-
es over time and a constant VLCD voltage. The output voltage (VLCD) is tightly controlled through the VL-
pad. For this voltage, eight different temperature coefficients (TC, rate of change with
CDSENSE
temperature) can be programmed using TC1 & TC0 or T2, T1 and T0 bits. This will ensure no contrast
degradation over the LCD operating range.
An external supply could be connected to VLCD to supply the LCD without using the internal generator. In
such event the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset con-
dition) and the Charge pump (CP[0;0]) set to 5x or Auto Mode.
3.3 Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock for the Dis-
play System. When used the OSC pad must be connected to VDD1 pad. An external oscillator could be
used and fed into the OSC pin.If an external oscillator is used, it must be always present when STE2004
is not in power down mode. An oscillator out is provided on the OSCOUT Pad to cascade two or more
drivers.
3.4 Master/Slave Mode
STE2004 support the Master Slave working Mode for Both Control Logic and Charge Pump. This function
allows to drive matrix such as 204x65 or 102x130 using two synchronized STE2004 and the internal
Charge Pump of both device.
If M/S is connected to VDD1, the driver is configured to work in Master Mode. When STE2004 is in Master
Mode the Vsense_Slave Pin is disabled and is possible to control the VLCD value using Vop Bits. The
Master Time Generator outputs on FR_OUT and on OSC_OUT the relevant timing references.
If M/S is connected to GND, the driver is configured to work in Slave Mode. When STE2004 is in Slave
Mode, the VLCD configuration set by Vop registers and the thermal compensation slope set by TC register
are neglected. The VLCD Value generated is equal to the Voltage value present on Vsense_Slave Pin so
the slave configuration can follow the master configuration. The only recognized configuration is Vop=0
that forces the Charge Pump to be in off state whatever is the value of Vsense_aux.
To Synchronize the Master & Slave timing circuits, the slave driver FR_IN pad must be connected to Mas-
ter Driver FR_OUT pad and Slave Driver OSC_IN pad must be connected to the master driver OSC_OUT
Pad (Fig. 4). This connection ensure a synchronization at both Frame level (R0 on the master is driven
together with the Slave R0 driver) and at Oscillator Level (same Frame frequency on the master and on
the slave). If the Synchronization at Frame level is not required, FR_IN pin must be connected toVDD1 or
to VDD1_aux (Fig. 5).
During Power Up Procesure, Master device must be forced to exit from power down before the slave de-
vice. To enter in PowerDown Mode, Slave Device must be forced in Power Down state before Master De-
vice.
6/66
STE2004
Figure 4. Master Slave Logic Connection with frame Synchronization
STE2004
STE2004
OSCOUT FROUT
VDD1AUX OSCIN FRIN
OSCOUT FROUT
FRIN OSCIN
LR0219
Figure 5. Master Slave Logic Connection without frame Synchronization
STE2004
STE2004
OSCIN
OSCOUT FROUT
VDD1AUX OSCIN FRIN
OSCOUT FROUT
LR0220
VDD1AUX
FRIN
3.5 Bias Levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated.
The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are
established to be (Fig. 6):
n + 3
n + 4
n + 2
n + 4
2
n + 4
1
n + 4
------------
------------
------------
------------
V
,
V
,
V
,
V
,
V ,V
LCD SS
LCD
LCD
LCD
LCD
Figure 6. Bias level Generator
VLCD
R
R
n + 3
n + 4
·VLCD
n + 2
n + 4
·VLCD
·VLCD
·VLCD
nR
R
2
n + 4
1
n + 4
R
VSS
D00IN1150
thus providing an 1/(n+4) ratio, with n calculated from:
n= m – 3
For m = 65, n = 5 and an 1/9 ratio is set.
For m = 49, n =4 and an 1/8 ratio is set.
The STE2004 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:
7/66
STE2004
Table 3.
BS2
0
BS1
0
BS0
0
n
7
6
5
4
3
2
1
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
The following table Bias Level for m = 65 and m = 49 are provided:
Table 4.
Symbol
V1
m = 65 (1/9)
m = 49 (1/8)
V
V
LCD
LCD
V2
8/9*V
7/9*V
7/8*V
6/8*V
2/8*V
1/8*V
LCD
LCD
LCD
LCD
LCD
LCD
V3
V4
2/9*V V
LCD
V5
1/9 *V
LCD
V6
V
V
SS
SS
3.6 LCD Voltage Generation
The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to
the following formula:
V
(T=To) = V
o = (Ai+V · B)
(i=0,1,2)
LCD
LCD
OP
with the following values:
Symbol
Ao
Value
2.95
Unit
V
Note
PRS = [0;0]
PRS = [0;1]
PRS = [1;0]
A1
6.83
V
A2
10.71
0.0303
27
V
B
V
To
°C
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits
are set to zero the internal voltage generator is switched off.
The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Mul-
tiplexing Rate. A general expression for this is:
1 + m
-----------------------------------
V
=
V
LCD
th
1
2
1 – --------
m
For MUX Rate m = 65 the ideal VLCD is:
than:
V
= 6.85 · V
th
LCD(to)
(6.85 V – A )
th
i
V
= ----------------------------------------
op
0.03
8/66
STE2004
3.7 Temperature Coefficients
As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's
the need to vary the LCD Voltage with temperature. STE2004 provides the possibility to change the VLCD
in a linear fashion against temperature with eight different Temperature Coefficient selectable through T2,
T1 and T0 bits. Only four of them are available through basic instruction set.
Table 5.
NAME
TC1
TC0
Value
Unit
-3
-3
TC0
0
0
1/ °C
-0.0· 10
TC2
TC3
TC6
0
1
1
1
0
1
1/°C
1/°C
1/°C
-0.7 · 10
-3
-1.05· 10
-3
-2.1 · 10
Table 6.
NAME
T2
T1
T0
Value
Unit
-3
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
0
0
0
1/ °C
-0.0· 10
-3
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
-0.35 · 10
-3
-0.7 · 10
-1.05· 10
-3
-3
-1.4 · 10
-3
-1.75· 10
-3
-2.1 · 10
-3
-2.3· 10
Figure 7.
LCD
V
B
2
A
1
A
0
A + B
1
A
00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh
O
V
PRS = [0;0]
PRS = [0;1]
PRS = [1;0]
Finally, the V
voltage at a given (T) temperature can be calculated as:
LCD
V
(T) = V
LCD
o · [1 + (T-To) · TC]
LCD
9/66
STE2004
3.8 Display Data RAM
The STE2004, provides an 102X65 bits Static RAM to store Display data. This is organized into 9 (Bank0
to Bank8) banks with 102 Bytes. One of these Banks can be used for Icons. RAM access is accomplished
in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X101 (Horizontal)
and Y0 to Y8 (Vertical).
When writing to RAM, four addressing mode are provided:
• Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the mem-
ory map. The X pointer is increased after each byte written. After the last column address (X=X-Car-
riage), Y address pointer is set to jump to the following bank and X restarts from X=0. (Fig. 8)
• Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory
map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage),
X address pointer is set to jump to next column and Y restarts from Y=0 (Fig. 9).
• Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the
memory map. The X pointer is increased after each byte written. After the last column address (X=X-
Carriage), Y address pointer is set to jump to the next bank and X restarts from X=0 (fig. 10).
• Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the mem-
ory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Car-
riage), the X pointer is set to jump to next column and Y restarts from Y=0 (fig. 11).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jump to the
cell with address (X;Y) = (0;0) (Fig. 12,13,14 & 15).
Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.16) or on the bottom (D0=1, Fig.
17).
The STE2004 provides also means to alter the normal output addressing. A mirroring of the Display along
the X axis is enabled setting to a logic one MY bit.This function doesn't affect the content of the memory
map. It is only related to the memory read process.
When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled.
When ICON MODE=0 the Icon Row is like an other graphic line and is mirrored and scrolled.
Three are the multiplex ratio available when the partial display mode is disabled (MUX 33, MUX 49 and
MUX 65). Only a subset of writable rows are output on Row drivers in MUX 33,49 & 65 Mode.
When Y-Carriage<MUX/8, if Mux 49 is selected only the first 49 memory rows are visualized; if Mux 33 is
selected only the first 33 memory rows are visualized. The unused output row & column drivers must be
left floating.
When Y-Carriage<=MUX/8 the icon Bank is located to BANK 8 in MUX 65 Mode, to BANK6 in MUX 49
Mode and to BANK 4 in MUX 33 Mode.
In Mux 33 & 49 Mode, when Y-Carriage>MUX/8 lines only 33, 49 lines are visualized.
It is possible to select which lines of DDRAM are connected on the output drivers using the scrolling func-
tion (Range: 0-Y-Carriage*8). When Y-Carriage>MUX/8 lines, the icon row is moved in DDRAM to the
first row of the Bank correspondant to Y-CARRIAGE Return value, being always connected on the same
output Driver.
When MY=0, the icon Row is output on R64 in mux 65 mode, on R56 in MUX 49 and on R48 in MUX33.
When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever is the MUX Rate.
10/66
STE2004
Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)1
0
1
2
3
98
99 100 101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LR0049
Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)1
0
1
2
3
98
99 100 101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LR0050
Figure 10. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)1
101 100 99
98
3
2
1
0
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LR0051
Figure 11. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)1
101 100 99
98
3
2
1
0
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LR0052
1. X Carriage=101; Y-Carriage = 8
11/66
STE2004
Figure 12. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=0)
X CARR
0
1
2
3
98
99 100 101
BANK
BANK
BANK
0
1
2
Y CARR
BANK 7
BANK 8
LR0053
Figure 13. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=0)
X CARR
0
1
2
3
98
99 100 101
BANK
BANK
BANK
0
1
2
Y CARR
BANK 7
BANK 8
LR0054
Figure 14. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=1)
X CARR
101 100 99
98
3
2
1
0
BANK
BANK
BANK
0
1
2
Y CARR
BANK 7
BANK 8
LR0055
Figure 15. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=1)
X CARR
101 100 99
98
3
2
1
0
BANK
BANK
BANK
0
1
2
Y CARR
BANK 7
BANK 8
LR0056
12/66
STE2004
Figure 16. Data RAM Byte organization with D0 = 0
MSB
0
1
2
3
98
99 100 101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
LSB
LR0057
Figure 17. Data RAM Byte organization with D0 = 1
LSB
0
1
2
3
98
99 100 101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
MSB
LR0058
13/66
STE2004
Figure 18. Memory Rows vs. Row Drivers Mapping ICON_MODE=1 and MUX 65
D
a
t
Y Address
ROW Output
Normal Reverse
direction direction
Line
D3 D2 D1 D0
Address
a
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R1
R2
R3
R4
R5
R6
R7
R63
R62
R61
R60
R59
R58
R57
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
Y-CARRIAGE
R8
R7
R6
R5
R4
R3
R2
R1
Page 7
Page 8
0
1
1
0
1
0
1
0
R0
R64
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
lr0268
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Reverse
Direction
96
98 97
95
4
6
5
0
101 100 99
3
2
1
14/66
STE2004
Figure 19. Memory Rows vs. Row Drivers Mapping ICON_MODE=0 and MUX 65
D
a
t
Y Address
ROW Output
Normal Reverse
Line
D3 D2 D1 D0
Address
a
direction direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
R0
R1
R2
R3
R4
R5
R6
R7
R64
R63
R62
R61
R60
R59
R58
R57
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
Y-CARRIAGE
R8
R7
R6
R5
R4
R3
R2
R1
Page 7
Page 8
0
1
1
0
1
0
1
0
R0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Reverse
Direction
lr0269
96
98 97
95
4
6
5
0
101 100 99
3
2
1
15/66
STE2004
Figure 20. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=6 and MUX 49
D
a
t
Y Address
ROW Output
Normal Reverse
direction direction
Line
D3 D2 D1 D0
Address
a
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R1
R2
R3
R4
R5
R6
R7
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
R8
R7
R6
R5
R4
R3
R2
R1
R0
R56
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Reverse
Direction
lr0270
96
98 97
95
4
6
5
0
101 100 99
3
2
1
16/66
STE2004
Figure 21. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage<=6 and MUX 49
D
a
t
Y Address
ROW Output
Normal Reverse
Line
D3 D2 D1 D0
Address
a
direction direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R1
R2
R3
R4
R5
R6
R7
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
R8
R7
R6
R5
R4
R3
R2
R1
R0
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
lr0271
Reverse
Direction
96
98 97
95
4
6
5
0
101 100 99
3
2
1
17/66
STE2004
Figure 22. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=7, Scrolling Pointer>07h and MUX 49
D
a
a
Y Address
ROW Output
Normal Reverse
direction direction
Line
t
D3 D2 D1 D0
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R1
R2
R3
R4
R5
R6
R7
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
R8
R7
R6
R5
R4
R3
R2
R1
R0
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
lr0275
C
O
L
C
O
L
Reverse
Direction
96
98 97
95
4
6
5
0
101 100 99
3
2
1
18/66
STE2004
Figure 23. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=7, Scrolling Pointer>07h and MUX 49
D
a
a
Y Address
ROW Output
Normal Reverse
direction direction
Line
t
D3 D2 D1 D0
Address
R0
R1
R2
R3
R4
R5
R6
R7
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
Scrolling Pointer
R8
R7
R6
R5
R4
R3
R2
R1
R0
R56
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
lr0276
C
O
L
C
O
L
Reverse
Direction
96
98 97
95
4
6
5
0
101 100 99
3
2
1
19/66
STE2004
Figure 24. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=8, Scrolling Pointer<10h and MUX 49
D
a
a
Y Address
ROW Output
Normal Reverse
direction direction
Line
t
D3 D2 D1 D0
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R1
R2
R3
R4
R5
R6
R7
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
Scrolling Pointer
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
R8
R7
R6
R5
R4
R3
R2
R1
R0
R56
Page 7
Page 8
0
1
1
0
1
0
1
0
Y-CARRIAGE
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
LR0273
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Reverse
Direction
96
98 97
95
4
6
5
0
101 100 99
3
2
1
20/66
STE2004
Figure 25. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=8, Scrolling Pointer<10h and MUX 49
D
a
a
ROW Output
Normal Reverse
direction direction
Y Address
Line
t
D3 D2 D1 D0
Address
R0
R1
R2
R3
R4
R5
R6
R7
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
Scrolling Pointer
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Page 2
Page 3
Page 4
Page 5
Page 6
R8
R7
R6
R5
R4
R3
R2
R1
R0
Page 7
Page 8
0
1
1
0
1
0
1
0
Y-CARRIAGE
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
LR0274
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Reverse
Direction
96
98 97
95
4
6
5
0
101 100 99
3
2
1
21/66
STE2004
Figure 26. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=4 and MUX33
D
a
a
Y Address
ROW Output
Normal Reverse
direction direction
Line
t
D3 D2 D1 D0
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R1
R2
R3
R4
R5
R6
R7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R15
R14
R13
R12
R11
R10
R9
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
R10
R11
R12
R13
R14
R15
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
Scrolling Pointer
Page 2
Page 3
Page 4
Page 5
Page 6
R8
R7
R6
R5
R4
R3
R2
R1
R0
R48
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Reverse
Direction
LR0272
96
98 97
95
4
6
5
0
101 100 99
3
2
1
22/66
STE2004
Figure 27. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage<=4 and MUX 33
D
a
a
Y Address
ROW Output
Normal Reverse
Line
t
D3 D2 D1 D0
Address
direction direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
R0
R1
R2
R3
R4
R5
R6
R7
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R15
R14
R13
R12
R11
R10
R9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
R8
R9
R10
R11
R12
R13
R14
R15
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
Scrolling Pointer
Page 2
Page 3
Page 4
Page 5
Page 6
R8
R7
R6
R5
R4
R3
R2
R1
R0
Y-CARRIAGE
Page 7
Page 8
0
1
1
0
1
0
1
0
X address
00H 01H 02H 03H 04H 05H 06H
5FH
60H
61H 62H 63H 64H 65H
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Normal
Direction
COL
Output
0
1
2
3
4
5
6
95 96 97 98 99 100 101
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
C
O
L
Reverse
Direction
LR0272
96
98 97
95
4
6
5
0
101 100 99
3
2
1
23/66
STE2004
Figure 28. Row Drivers vs. LCD Panel Interconnection in MUX65 Mode
ICON
MUX 65
COLUMN DRIVERS
R32
R
R
R
R
R
R
R
R
R
R
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
0
1
2
3
4
5
6
7
8
9
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
ROW DRIVERS
ROW DRIVERS
R49
R50 STE2004
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R30
R31
LR0109
Figure 29. Row Drivers vs. LCD Panel Interconnection in MUX49 Mode
ICON
MUX 49
COLUMN DRIVERS
R32
R
R
R
R
R
R
R
R
R
R
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
0
1
2
3
4
5
6
7
8
9
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
ROW DRIVERS
ROW DRIVERS
R45
R46
R47
R48
R49
R50 STE2004
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R30
R31
LR0108
24/66
STE2004
Figure 30. Row Drivers vs. LCD Panel Interconnection in MUX33 Mode
ICON
MUX 33
COLUMN DRIVERS
R32
R
R
R
R
R
R
R
R
R
R
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
0
1
2
3
4
5
6
7
8
9
R33
R34
R35
R36
R37
R38
R39
ROW DRIVERS
R40
ROW DRIVERS
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50 STE2004
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R30
R31
LR0107
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STE2004
4 BUS INTERFACES
To provide the widest flexibility and ease of use the STE2004 features Six different methods for interfacing
the host Controller. To select the desired interface the SEL1, SEL2 and SEL3 pads need to be connected
to a logic LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused inter-
faces must be connected to GND.
All interfaces are working while the STE2004 is in Power Down.
Table 7.
SEL3
SEL2
SEL1
Interface
Note
2
0
0
0
Read and Write; Fast and
High Speed Mode
I C
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
SPI 4 lines 8 bit
Read and Write
Read and Write
Read and Write
Read and Write
SPI 3 lines 8 bit
Serial 3 lines 9 bit
Parallel 8080-series
Parallel 68000-series Read and Write
4.1 I2C Interface
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock)
and High Speed Mode (3.4MHz).
This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for
data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a
positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, de-
fine the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High,
defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the High period of the clock signal. The data on the line may be changed during
the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of
data bytes transferred between the start and the stop conditions is not limited. The information is transmit-
ted byte-wide and each receiver acknowledges with the ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device that gets the
signals is called "receiver". The device that controls the message is called "master". The devices that are
controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock
pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also,
a master receiver must generate an acknowledge after the reception of each byte that has been clocked
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STE2004
out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the
acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver
must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the
master to generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the ac-
knowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass
(COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system
SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin
Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2004 will not be able
to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode
that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is nec-
essary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid
LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2004 is able to detect the special se-
quence "S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode with-
out detecting the master code.
Figure 31. Bit transfer and START,STOP conditions definition
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CHANGE OF
STOP
CONDITION
DATA ALLOWED
CONDITION
LR0069
2
Figure 32. Acknowledgment on the I C-bus
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
MSB
LSB
DATA OUTPUT
BY RECEIVER
LR0070
4.1.1 Communication Protocol
The STE2004 is an I2C slave. The access to the device is bi-directional since data write and status read
are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits (01111). The
two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or
to a logic 1.
To start the communication between the bus master and the slave LCD driver, the master must initiate a
START condition. Following this, the master sends an 8-bit byte, on the SDA bus line (Most significant bit
first). This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/W).
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus
transfer.
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STE2004
4.1.2 Writing Mode.
If the R/W bit is set to logic 0 the STE2004 is set to be a receiver. After the slaves acknowledge one or
more command word follows to define the status of the device.
A command word is composed by three bytes. The first is a control byte which defines the Co and D/C
values, the second and third are data bytes. The Co bit is the command MSB and defines if after this com-
mand will follow two data bytes and an other command word or if will follow a stream of data (Co = 1 Com-
mand word, Co = 0 Stream of data). The D/C bit defines whether the data byte is a command or RAM data
(D/C = 1 RAM Data, D/C = 0 Command).
If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the
following data byte will be stored in the data RAM at the location specified by the data pointer.
Every byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2004
Display RAM starting at the address specified by the data pointer. The data pointer is automatically up-
dated after every byte written and in the end points to the last RAM location written.
Every byte must be acknowledged by all addressed units.
4.1.3 Reading Mode.
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit
during the last write access, is set to a logic 0, the byte read is the status byte.
Figure 33. Communication Protocol
WRITE MODE
DRIVER ACK
DRIVER ACK
DRIVER ACK
DRIVER ACK
DRIVER ACK
S S
1 A A 0 A 1 DC Control Byte
S 0
1
1
1
A
DATA Byte
A 0 DC Control Byte
A
DATA Byte A P
1
0
R/W Co
Co
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
SLAVE ADDRESS
COMMAND WORD
READ MODE
DRIVER ACK
MASTER ACK
P
S S
1 A A 1 A
S S R
1 A A
0 W
H H H
E [1][0]
C D
o C
S 0
1
1
1
0
1
1
1
/
0
0
0
A
1
0
1
DRIVER
SLAVE ADDRESS
R/W
CONTROL BYTE
LR0008
4.2 SERIAL INTERFACES
STE2004 can feature three different serial synchronized interfaces with the host controller. It is possible to select
a 3-lines SPI, a 4-lines SPI or 3-line 9 bits Serial Interface.
4.2.1 4-lines SPI interface
STE2004 4-lines serial interface is a bidirectional link between the display driver and the application supervisor.
It consists of four lines: one/two for data signals (SDIN, SOUT), one for clock signals (SCLK), one for the pe-
ripheral enable (CS) and one for mode selection (SD/C).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral power
consumption is zero. While CS pin is high the serial interface is kept in reset.
The STE2004 is always a slave on the bus and receive the communication clock on the SCLK pin from the mas-
ter.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or a data (SD/C =1); SD/C line is read on
28/66
STE2004
the eighth SCLK clock pulse during every byte transfer.
If CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte
at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared.
If CS is low after the positive edge of RES, the serial interface is ready to receive data.
2
Throughout SDOUT can be read the driver I C slave address or the status byte. The Command sequence that
2
allows to read I C slave address or Status byte is reported in Fig. 34 & 35. SDOUT is in High impedance in
steady state and during data write.
It is possible to short circuit SDOUT and SDIN and read I2C address or status Byte without any additional lines.
Figure 34. 4-lines serial bus protocol - one byte transmission
CS
D/C
SCLK
SDIN
MSB
LSB
LR0071
Figure 35. 4-lines serial bus protocol - several byte transmission
CS
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
LR0072
Figure 36. 4-lines serial bus protocol - I2C Address or Status Byte Read
CS
SCLK
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
SDIN
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
High-Z
High-Z
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ID Number
SDOUT
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
STATUS BYTE
DATA Read
LR00076
Command Write
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STE2004
Figure 37. 4-lines SPI Reading Sequence
READING SEQUENCE
Write a "00000000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 8 pulses on SCLK and
Read the ID Number or the Status Byte On SDOUT1
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
.
LR0078
4.2.2 3-lines SPI Interface
The STE2004 3-lines serial Interface is a bidirectional link between the display driver and the application
supervisor.
It consists of three lines: one/two for data signals (SDIN,SDOUT), one for clock signals (SCLK) and one
for peripheral enable (CS).
If the R/W bit is set to logic 0 the STE2004 is set to be a receiver. One or more command word follows to
define the status of the device.
A command word is composed by two bytes. The first is a control byte which defines Co, D/C, R/W H[1;0]
and HE values, the second is a data byte (fig 39). The Co bit is the command MSB and defines if after this
command will follow one data byte and an other command word or if will follow a stream of Commands or
a Steam of DDRAM Data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether
the data byte is a command or DDRAM data (D/C = 1 RAM Data, D/C = 0 Command). The H[1;0] bits
define the instruction Set Page if HE bit =1. If HE bit is set to 0 H[1;0] values are neglected and it is possible
to update the instruction set page number using only the related instruction in the instruction Set.
If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the
following data byte will be stored in the data RAM at the location specified by the data pointer.
After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2004
Display Data RAM starting at the address specified by the data pointer. The data pointer is automatically
updated after every byte written and in the end points to the last RAM location written.
Throughout SDOUT can be read the driver I2C slave address or the status Byte. The Command sequence
that allows to read I2C slave address or the Status byte is reported in Fig. 39 & 40.
If the R bit is set to logic 0 and D/C=0, the I2C slave address is read; If the R bit is set to logic 1 and D/
C=0, the the I2C slave address is read
SDOUT is in High impedance in steady state and during data write.
It is possible to short circuit SDOUT and SDIN and read I2C address or status byte without any additional
line.
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STE2004
Figure 38. 3-lines serial interface protocol in Writing Mode
WRITE MODE
R
/
W
H H H
E [1][0]
C D
o C
1
Control Byte
DATA Byte
0
Control Byte
LAST
DATA Byte
0 0
CONTROL BYTE
Co
N> 0 BYTE
MSB........LSB
Co
COMMAND WORD
Control Byte
CONTROL BYTE
TRANSFERRED
ONLY COMMANDS
0 0
DATA Byte
DATA Byte
DATA Byte = Command
if D/C=0
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
DATA Byte = DDRAM Data if D/C=1
Control Byte
TRANSFERRED
ONLY DDRAM DATA
0 1
DATA Byte
DATA Byte
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
LR0002
Figure 39. 3-lines SPI interface protocol in Reading Mode
CS
SCLK
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
SDIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Co=1
D/C=0
R/W=1
"Command" "Read"
High-Z
High-Z
High-Z
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ID-Number
SDOUT
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
STATUS BYTE
DATA Read
LR0077
Command Write
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STE2004
Figure 40. 3-lines SPI Reading Sequence
READING SEQUENCE
Set Co bit =1, D/C Bit =0 R/W Bit =1
SDOUT Buffer become active (Low Impedence)
Source 8 pulses on SCLK and
1
Read the ID-Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
.
LR0079
4.2.3 3-lines 9 bits Serial Interface
The STE2004 3-lines serial Interface is a bidirectional link between the display driver and the application
supervisor.
It consists of three lines: one/two for data signals (SDIN, SDOUT), one for clock signals (SCLK) and one
for peripheral enable (CS).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral
power consumption is zero. While CS pin is high the serial interface is kept in reset.
The STE2004 is always a slave on the bus and receive the communication clock on the SCLK pin from
the master.
Information are exchanged word-wide. The word is composed by 9 bit. The first bit is named SD/C and
indicates whether the following byte is a command (SD/C =0) or Data Byte (SD/C =1). During data trans-
fer, the data line is sampled on the positive SCLK edge.
If CS stays low after the last bit of a command/data byte, the serial interface expects the SD/C Bit of the
next word at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the in-
ternal registers are cleared.
If CS is low after the positive edge of RES, the serial interface is ready to receive data.
2
Throughout SDOUT can be read only the driver I C slave address or the status byte. The Command sequence
2
that allows to read I C slave address or Status byte is reported in Fig. 43 & 44. SDOUT is in High impedance
in steady state and during data write.
It is possible to short circuit SDOUT and SDIN and read I C address or status byte without any additional line.
2
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STE2004
Figure 41. 3-lines serial bus protocol - one byte transmission
CS
SCLK
SDIN
SD/C
MSB
LSB
LR0073
Figure 42. 3-lines serial bus protocol - several byte transmission
CS
SCLK
SDIN
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D/C
DB7
DB6
LR0074
Figure 43. 3-lines serial interface protocol in Reading Mode
CS
SCLK
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
SDIN
SD/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
High-Z
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ID-Number
SDOUT
High-Z
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
STATUS BYTE
LR0075
DATA Read
Command Write
Figure 44. 3-lines Serial Reading Sequence
READING SEQUENCE
Write a "00000000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 9 pulses on SCLK and
Read the ID Number or the Status Byte On SDOUT1
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
.
LR0080
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STE2004
4.3 Parallel Interface
The STE2004 selectable parallel Interfaces are 68000-series and 8080-series. They are both an 8-bits bi-
directional link between the display driver and the application supervisor.
Throughout both parallel interfaces can be read the I2C driver slave address or the Status Byte.
4.3.1 68000-series parallel interface
If CS is low after the positive edge of RES, the 68000 parallel interface is ready to receive or transmit data.
While CS pin is high the 68000 Parallel interface is kept in reset.
4.3.2 Write Mode
If R/W line is set to 0 Data are latched on E falling edge.
4.3.3 Read Mode
When R/W line is set to 1, data are output on D0-D7 bus on E rising edge. Data Bus is set in high imped-
ance mode when E is set to logic 0.
Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus.
Figure 45. 68000-series Parallel interface protocol - one byte transmission
CS
R/W
D/C
E
D0
to
D7
LR0004
Figure 46. 68000-series Parallel interface bus protocol - Several bytes transmission
CS
R/W
D/C
E
D0
to
D7
LR0081
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STE2004
Figure 47. 68000-series Parallel interface protocol in Reading Mode
CS
D/C
R/W
E
D0
to
D7
LR0082
Figure 48. 68000-series Parallel interface protocol in Reading Mode (Several Bytes)
CS
D/C
R/W
E
D0
to
D7
Note 1) Data Bus is configured in high impedence mode after evry RD rising edge
2) Always the same data is output on D0-D7
LR0046
4.3.4 8080-series parallel interface
If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or transmit data.
While CS pin is high the 8080 Parallel interface is kept in reset.
Write Mode
Data are latched on WR rising edge.
Read Mode
Data are output on D0-D7 bus on RD rising edge. Data Bus is set in high impedance mode when RD is set to
logic 1.
Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus.
Figure 49. 8080-series parallel bus protocol - one byte transmission
CS
D/C
RD
WR
D0
to
D7
LR0083
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STE2004
Figure 50. 8080-series parallel bus protocol - several bytes transmission
CS
D/C
RD
WR
D0
to
D7
LR0084
Figure 51. 8080-series Parallel interface protocol in Reading Mode
CS
D/C
RD
WR
D0
to
D7
LR0085
Figure 52. 8080-series Parallel interface protocol in Reading Mode (Several Bytes)
CS
D/C
RD
WR
D0
to
D7
LR0045
Note 1) Data Bus is configured in high impedence mode after every RD rising edge
2) Always the same data is output on D0-D7
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STE2004
5 INSTRUCTION SET
Two different instructions formats are provided:
- With D/C set to LOW : commands are sent to the Control circuitry.
- With D/C set to HIGH : the Data RAM is addressed.
Two different instruction set are embedded: the STE2001-like instruction set and the extended instruction
set. To select the STE2001-like instruction set the EXT pad has to be connected to a logic LOW (connect
to GND). To select the he extended instruction the EXT pad has to be connected to a logic HIGH (connect
to VDD1).
The instructions have the syntax summarized in Table 1 (basic-set) and Table 2 (extended set)
5.1 Reset (RES)
At power-on, all internal registers are configured with the default value. The RAM content is not defined.
A Reset pulse on RES pad (active low) re-initialize the internal registers content (see Tables 3,4,5,&6).
Every on-going communication with the host controller is interrupted, applying a reset pulse. After the
power-on, the Software Reset instruction can be used to re-load the reset configuration into the internal
registers.
The Default configurations is:
- Horizontal addressing (V = 0)
- Frame Rate (FR[1:0]=”75Hz”)
- Power Down (PD = 1)
- Dual Partial Display Disabled (PE=0)
- VOP=0
- Normal instruction set (H[1:0] = 0)
- Normal display (MX = MY = 0)
- Display blank (E = D = 0)
- Address counter X[6: 0] = 0 and Y[4: 0] = 0
- Temperature coefficient (TC[1: 0] = 0)
- Bias system (BS[2: 0] = 0)
- Y-CARRIAGE=8
- X-CARRIAGE=101
- Multiplexing Ratio (M[1:0]=0 - MUX 65)
A MEMORY BLANK instruction can be executed to clear the DDRAM content.
5.2 Power Down (PD = 1)
When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator
are OFF (VLCDOUT output is discharged to VSS, and then is possible to disconnect VLCDOUT). The internal
Oscillator is in off state. An external clock can be provided. The RAM contents is not cleared.
5.3 Memory Blanking Procedure
This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly gener-
ated in memory when starting up the device. This instruction substitutes (102X8) single "write" instruc-
tions. It is possible to program "Memory Blanking Procedure" only under the following conditions:
- PD bit
= 0
No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock).
The start of Memory blanking procedure will be between one and two fclock cycles from the last active
edge (E fallig edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL
rising edge for the I2C interface).
5.4 Checker Board Procedure
This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended to developers,
who can now simply obtain complex module test configuration by means of a single instruction. It is pos-
sible to program "Checker Board Procedure" only under the following conditions:
- PD bit
= 0
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STE2004
No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock).
The start of Checker-board procedure will be between one and two fclock cycles from the last active edge
(E falling edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL
rising edge for the I2C interface).
5.5 Scrolling Function
The STE2004 can scroll the graphics display in units of raster-rows. The scrolling function is achieved
changing the correspondence between the rows of the logical memory map and the output row drivers.
The scroll function doesn't affect the data ram content. It is only related to the visualization process. The
information output on the drivers is related to the row reading sequence (the 1st row read is output on R0,
the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially in-
creased or decreased. After every scrolling command the offset between the memory address and the
memory scanning pointer is increased or decreased by one. The offset range changes in accordance with
MUX Rate. After 64th/65th scrolling commands in MUX 65 mode, or after the 48th/49th scrolling com-
mands in mux 49 mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the
memory address and the memory scanning pointer is again zero (Cyclic Scrolling).
A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the memory ad-
dress and the memory scanning pointer
If ICON MODE =1, the Icon Row is not scrolled. If ICON MODE=0 the last row is like a general purpose
row and it is scrolled as other lines.
If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top
down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled
from bottom-up.
Table 8.
MUX RATE
MUX 33
MUX 33
MUX 49
MUX 49
MUX 65
MUX 65
ICON MODE
DESCRIPTION
ICON Row Driver with MY=0
R48
1
0
1
0
1
0
ICON ROW NOT SCROOLED
33 LINE GRAPHIC MATRIX
ICON ROW NOT SCROOLED
49 LINE GRAPHIC MATRIX
ICON ROW NOT SCROOLED
65 LINE GRAPHIC MATRIX
R48
R56
R56
R64
R64
5.6 Dual Partial Display
If the PE Bit is set to a logic one the dual partial display mode is enabled.
Eight partial display modes are available. The offset of the two partial display zones is row by row pro-
grammable. The Icon row is accessed last in each partial display frame.
Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0], BS[2:0], CP[2:0].).
This allows switching from normal mode to partial display mode only with one instruction. The HV gener-
ator is automatically re configured using the parameters related to the enabled mode. The parameters of
the two sets of registers with the same function are located in the same position of the instruction set. The
registers related to the normal mode are accessible when normal mode (PE=0) is selected, the others are
accessible when the partial display mode is enabled (PE=1). To Setup PRS[1:0], Vop[6:0], BS[2:0],
CP[2:0] values the instruction flow proposed in Fig. 54 must be followed. To setup Partial Display Sectors
Start Address and Partial Display Mode no particular instruction flow has to be followed.
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Figure 53. Dual Partial Display Enabling Instruction Flow
ENABLE DUAL PARTIAL DISPLAY
SET 1st Sector Start Address
SET 2nd Sector Start Address
OPTIONAL1
SET PE=1
END OF ENABLING DUAL PARTIAL DISPLAY
Figure 54. Dual Partial Display Mode configuration or Duty Change
SETUP PARTIAL DISPLAY CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Partial Display Mode (PE=1)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]
for Partial Display Operation
SET Partial Display Configuration (PDC[2:0])
SET 1st Sector Start Address
SET 2nd Sector Start Address
OPTIONAL
SET Driver in Normal Mode (PE=0)
END OF PARTIAL DISPLAY CONFIG.
Table 9. Partial Display Configurations
PDC PDC PDC
SECTION 1
SECTION2
RESET STATE
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
8
8 + Icon Row
0 + Icon Row
8 + Icon Row
16 + Icon Row
0 + Icon Row
16 + Icon Row
8 + Icon Row
16 + Icon Row
8
0
000
16
8
16
16
39/66
STE2004
6 ID-NUMBER
The STE2004 allows to program a Driver Identification Number (ID-Number). This make possible to easily
manage on one platform more than one LCD module with different configuration parameters.
Four are the device ID-Numbers programmable: 00111100, 00111101, 0011110 & 0011111. All have in
common the first 6 bits (001111). The two least significant bit could be set connecting the SA0 and SA1
inputs to a VSS or VDD1.
The driver ID-number can be read through all communication interfaces. The way to read-out the ID-Num-
ber changes according the interface selected. The readout protocol for each interface is described in the
Bus interfaces paragraph.
Table 10. STE2001/2-like instruction Set
Instruction
D/C
R
/W
Description
B7 B6 B5
B4 B3 B2 B1
B0
H=0 or H=1
Read I2C Address or Status Byte
(with 3-Lines Serial & 4-lines SPI only)
Read Commnad
0
0
0
0
0
0
0
1
0
0
0
0
0
Function Set
Status Byte
0
0
0
1
MX MY PD
V
H[0] Power Down Management; Entry
Mode;
2
PD BSY
0
1
D
1
E
1
MX MY DO
ID1 ID0
(I C interface only)
ID Code
Write Data
H=0
0
1
1
0
0
0
1
D7 D6 D5
D4 D3 D2 D1
D0
Writes data to RAM
Memory Blank
Scroll
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
Starts Memory Blank Procedure
DIR Scrolls by one Row UP or DOWN
V
LCD Range Setting
PRS VLDC programming range selection
[0]
Display Control
Set CP Factor
0
0
0
0
0
0
0
0
0
0
0
1
1
0
D
0
E
Select Display Configuration
S2
S1
S0
Charge Pump Multiplication
factor
Set RAM Y
Set RAM X
H=1
0
0
0
0
0
1
1
0
0
Y3
X3
Y2
X2
Y1
X1
Y0 Set Horizontal (Y) RAM Address
X6
X5
X4
X0
Set Vertical (X) RAM Address
Checker Board
Duty
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
X
0
0
0
0
1
X
0
0
0
1
0
X
0
0
0
1
1
Starts Checker Board Procedure
Selects Duty factor
MUX
TC Select
Data Order
Bias Ratios
Reserved
1
TC1 TC0 Set Temperature Coefficient for VLDC
DO
0
0
BS2 BS1 BS0
Set desired Bias Ratios
Not to be used
X
X
X
Set V
OP6 OP5 OP4 OP3 OP2 OP1 OP0
V
OP
register Write instruction
OP
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STE2004
Table 11. Extended Instruction Set
Instruction
D/C R/W
Description
B7
B6 B5 B4 B3
B2
B1 B0
H Independent Instructions
Read I2C Address or Status Byte
(with 3-Lines Serial & 4-lines SPI only)
Read Command
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
MX MY PD H[1] H[0]
Page selector, Power Down
Management; Entry Mode
Status Byte
ID Code
0
0
1
1
1
0
PD BSY
0
1
D
1
E
1
MX MY DO
0
0
1
ID1 ID0
D1 D0
Write Data
D7
D6 D5 D4 D3
D2
Writes data to RAM
H=[0;0] RAM Commands
Memory Blank
Scroll
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
Starts Memory Blank Procedure
Scrolls by one Row UP or DOWN
DIR
VLCD Range Setting
PRS PRS VLDC programming range selection
[1]
[0]
Display Control
Set CP Factor
Set RAM Y
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
D
0
E
Select Display Configuration
Charge Pump Multiplication factor
Set Horizontal (Y) RAM Address
Set Vertical (X) RAM Address
S2
Y2
X2
S1
Y1
X1
S0
Y0
X0
1
0
0
Y3
X3
Set RAM X
X6
X5
X4
H=[0;1]
Checker Board
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
R
0
0
0
1
1
Starts Checker Board Procedure
Vertical Addressing Mode
V
TC Select
Data Order
Bias Ratios
Read Mode,
1
TC1 TC0 Set Temperature Coefficient for VLDC
DO
0
0
MSB Position
BS2 BS1 BS0
Set desired Bias Ratios
0
0
0
Set V
OP6 OP5 OP4 OP3 OP2 OP1 OP0
VOP register Write instruction
OP
H=[1;0]
Driver Control
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
Software RESET
Partial Enable
Display Control
PE
FR1 FR0
M[1] M[0]
Frame rate Control
Mux Ratio
Partial Mode
PDC PDC PDC
Partial Display Config
2
1
0
1st Sector Start Address
2nd Sector Start Address
0
0
0
0
0
1
1
PD PD PD PD PD PD
Y5
Y4
Y3
Y2
Y1
Y0
PD PD PD PD PD PD PD
Y6
Y5
Y4
Y3
Y2
Y1
Y0
H=[1;1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
Scrolling Pointer Reset
Not Used
0
0
0
0
1
0
0
0
0
0
0
1
1
X
X
X
Not Used
T2
T1
T0 Set Temperature Coefficient for VLDC
NW3 NW2 NW1 NW0
YC-3 YC-2 YC-1 YC-0
N-Line Inversion
Y-CARRIAGE RETURN
X CARRIAGE RETURN
XC-6 XC-5 XC-4 XC-3 XC-2 XC-1 XC-0
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STE2004
Table 12. Explanations of Table 3 & 4 symbols
RESET
STATE
BIT
0
1
DIR
H[0]
PD
V
Scroll by one down
Select page 0
Scroll by one up
Select page 1
0
1
0
0
0
0
0
0
0
Device fully working
Device in power down
Vertical addressing
Horizontal addressing
Normal X axis addressing
Image is displayed not vertically mirrored
MSB on TOP
MX
MY
DO
PE
MUX
R
X axis address is mirrored.
Image is displayed vertically mirrored
MSB on BOTTOM
Partial Display disabled
MUx 65 Mode
Partial Display enabled
MUX 33 Mode
Read ID-Number / I2C Address
Read Status Byte
Table 13. PAGE SELECTION
H[1]
H[0]
DESCRIPTION
RESET STATE
0
0
1
1
0
1
0
1
Page 0
Page 1
Page 2
Page 3
Page 0
Table 14. DISPLAY MODE
D
0
0
1
1
E
0
1
0
1
DESCRIPTION
RESET STATE
display blank
all display segments on
normal mode
E=0
D=0
inverse video mode
Table 15. FRAME RATE CONTROL
FR[1]
FR[0]
DESCRIPTION
65Hz
RESET STATE
0
0
1
1
0
1
0
1
70Hz
75Hz
75Hz
80Hz
Table 16. VLCD RANGE SELECTION
PRS[1]
PRS[0]
DESCRIPTION
2.94
RESET STATE
0
0
1
1
0
1
0
1
6.78
10.62
10.62
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STE2004
Table 17. MULTIPLEXING RATIO
M[1]
M[0]
DESCRIPTION
RESET STATE
0
0
1
1
0
1
0
1
49
65
33
01
Not Allowed
Table 18. TEMPERATURE COEFFICIENT
T2
0
T1
0
T0
0
DESCRIPTION
RESET STATE
VLCD temperature Coefficient 0
VLCD temperature Coefficient 1
VLCD temperature Coefficient 2
VLCD temperature Coefficient 3
VLCD temperature Coefficient 4
VLCD temperature Coefficient 5
VLCD temperature Coefficient 6
VLCD temperature Coefficient 7
0
0
1
0
1
0
0
1
1
000
1
0
0
1
0
1
1
1
0
1
1
1
Table 19.
TC1
TC0
DESCRIPTION
RESET STATE
0
0
0
1
0
1
1
1
VLCD temperature Coefficient 0
VLCD temperature Coefficient 2
VLCD temperature Coefficient 3
VLCD temperature Coefficient 6
00
Table 20. CHARGE PUMP MULTIPLICATION FACTOR
CP2
CP1
CP0
DESCRIPTION
Multiplication Factor X2
Multiplication Factor X3
Multiplication Factor X4
Multiplication Factor X5
NOT USED
RESET STATE
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
000
NOT USED
NOT USED
AUTOMATIC
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Table 21. BIAS RATIO
BS2
0
BS1
0
BS0
0
DESCRIPTION
RESET STATE
Bias Ratio equal to 7
Bias Ratio equal to 6
Bias Ratio equal to 5
Bias Ratio equal to 4
Bias Ratio equal to 3
Bias Ratio equal to 2
Bias Ratio equal to 1
Bias Ratio equal to 0
0
0
1
0
1
0
0
1
1
000
1
0
0
1
0
1
1
1
0
1
1
1
Table 22. Y CARRIAGE RETURN REGISTER
Y-C[3] Y-C[2] Y-C[1] Y-C[0]
DESCRIPTION
RESET STATE
0
0
0
0
0
.
0
0
0
0
1
.
0
0
1
1
0
.
0
1
0
1
0
.
Y-CARRIAGE =0
Y-CARRIAGE =1
Y-CARRIAGE =2
Y-CARRIAGE =3
Y-CARRIAGE =4
1000
0
0
1
1
1
0
1
1
0
0
1
0
Y-CARRIAGE =6
Y-CARRIAGE =7
Y-CARRIAGE =8
Table 23. PARTIAL DISPLAY CONFIGURATION
PD2 PD1 PD0
SECTION 1
SECTION2
8 + Icon Row
0 + Icon Row
8 + Icon Row
16 + Icon Row
0 + Icon Row
16 + Icon Row
8 + Icon Row
16 + Icon Row
RESET STATE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
8
8
0
000
16
8
16
16
Table 24. N-LINE INVERSION
NW3
NW2
NW1
NW0
DESCRIPTION
RESET STATE
0
0
0
0
0-Line Inversion
(Frame Inversion)
2-Line Inversion
3-Line Inversion
4-Line Inversion
:
0
0
0
:
0
0
0
:
0
1
1
:
1
0
1
:
0000
1
1
1
1
1
1
0
1
15-Line Inversion
16-Line Inversion
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STE2004
Figure 55. I2C Interface Interconnection in Master/ Slave Mode
STE2004
STE2004
RES
SCL
SDAOUT SDAIN
RES
SCL
SDAOUT SDAIN
LR0214
NOTE:
MASTER and SLAVE I2C AADDRESS
MUST BE DIFFERENT
RES
SCL
SDA
Figure 56. I3-lines SPI & 3-lines Serial Interfaces Interconnection in Master Slave Mode
STE2004
STE2004
RES
CS SCLK
SDIN SDOUT
RES
CS
SCLK SDIN
SDOUT
LR0215
RES MASTER SCLK
CS
SD
SLAVE
CS
Figure 57. 4-lines SPI Interface Interconnection in Master Slave Mode
STE2004
STE2004
RES
D/C
CS
SCLK
SDIN SDOUT
RES
CS
D/C
SCLK
SDIN
SDOUT
LR0216
RES
D/C
MASTER
CS
SCLK
SD
SLAVE
CS
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STE2004
Figure 58. 8080-series & 68000-series Interface Interconnection in Master Slave Mode
STE2004
STE2004
CS
D/C RW-RD
E-WR
D7-D0
RES
D/C
RW-RD
D7-D0
E-WR
RES
CS
LR0217
8 LINES
8 LINES
RES MASTER D/C
CS
RW-RD E-WR D7-D0
SLAVE
CS
Figure 59. Host Processor Interconnection with I2C Interface
VSS
TEST_MODE
µP
VSSAUX
STE2004
D0
D1
D2
D3
D4
D5
D6
D7
SCLK -SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON
ANALOG VDD
DIGITAL VDD
VDD1 / VSSAUX
VSSAUX
SEL1
SEL2
SEL3
EXT_SET
M/S
VDD1 / VSSAUX
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0110
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STE2004
Figure 60. Host Processor Interconnection with 4-line SPI Interface
VSS
TEST_MODE
µP
VSSAUX
D0
STE2004
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
SEL1
SEL2
VDD1
VSSAUX
SEL3
EXT_SET
M/S
VDD1 / VSSAUX
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0111
Figure 61. Host Processor Interconnection with 3-line SPI Interface
VSS
TEST_MODE
µP
VSSAUX
D0
STE2004
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
SEL1
SEL2
VSSAUX
VDD1
SEL3
VSSAUX
EXT_SET
VDD1 / VSSAUX
M/S
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0112
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STE2004
Figure 62. Host Processor Interconnection with 3-line Serial Interface
VSS
TEST_MODE
µP
VSSAUX
STE2004
D0
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
SEL1
SEL2
VDD1
VDD1
SEL3
VSSAUX
EXT_SET
M/S
VDD1 / VSSAUX
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0113
Figure 63. Host Processor Interconnection with 8080-series Parallel Interface
VSS
TEST_MODE
µP
VSSAUX
STE2004
D0
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
VSSAUX
SEL1
SEL2
VSSAUX
SEL3
VDD1
EXT_SET
M/S
VDD1 / VSSAUX
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0114
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STE2004
Figure 64. Host Processor Interconnection with 6800
VSS
TEST_MODE
µP
VSSAUX
STE2004
D0
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
ANALOG VDD
VDD1
ICON
DIGITAL VDD
VDD1 / VSSAUX
SEL1
SEL2
VDD1
VSSAUX
SEL3
VDD1
EXT_SET
M/S
VDD1 / VSSAUX
VDD1
SA0
SA1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0115
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STE2004
Figure 65. Application Schematic using the Internal LCD Voltage Generator and two separate supplies
I/O
VDD2
VDD2
VDD1
32
102
33
VDD1
1µF
1µF
VSS
VSS
65 x 102
DISPLAY
1µF
VLCDSENSE
VLCD
Figure 66. Application Schematic using the Internal LCD Voltage Generator and a single supply
I/O
VDD
VDD2
VDD1
32
102
33
1µF
65 x 102
DISPLAY
VSS
VSS
1µF
VLCDSENSE
VLCD
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STE2004
Figure 67. Power-ON timing diagram
T
vdd
Tw(res)
Tlogic(res)
VDD2
VDD1
RES
CS
SCLK
SDIN
D/C
E
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
Hi-Z
SCL- SDAIN
SDOUT -
SDA OUT
OSCIN, FR_IN
(HOST)
OSC OUT, FR_OUT
(DRIVER)
POWER ON
INTERNAL
RESET
RESET
Acceptance
Time
BOOSTER
OFF
LR0208
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STE2004
Figure 68. Power-OFF timing diagram
TVDD
VDD2
VDD1
RES
CLK-SCL
SDIN-SDAIN
D/C
E
CS
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
Hi-Z
SDOUT
SDA-OUT
OSCIN
(HOST)
OSC OUT
FR_OUT
(DRIVER)
FR_IN
RESET
TABLE
LOADED
LR0207
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STE2004
Figure 69. Initialization with built-in Booster
SETUP NORMAL DISPLAY MODE CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Normal Display Mode (PE=0)
SET Operative Voltage for Normal Display Operation
( Vop[6:0] - PRS[1;0])
SET Bias Raio for Normal Display Operation
(BS[2:0])
SET Temperature Compensation for
Normal Display Operation (T[2:0] or TC[1:0])
SET Multiplexing Rate
M[1:0)
SET Charge Pump for
Normal Display Operation (CP[1:0])
Switch "ON" Booster and Display Control Logic
(PD=0)
END OF NORMAL DISPLAY MODE CONFIG.
LR0218
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STE2004
Figure 70. DATA RAM to display Mapping
DISPLAY DATA RAM
bank
0
GLASS
TOP VIEW
bank
1
DISPLAY DATA RAM = "1"
DISPLAY DATA RAM = "0"
bank
2
LCD
bank
3
bank
7
bank
8
ICOR ROW
D00IN1155
Table 25. Test Pin Configuration
Test Pin
Pin Configuration
OPEN
TEST_VREF
TEST_MODE
GND
54/66
STE2004
Table 26. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
V
V
V
Supply Voltage Range
Supply Voltage Range
LCD Supply Voltage Range
Supply Current
- 0.5 to + 5
- 0.5 to + 7
- 0.5 to + 15
- 50 to +50
DD1
DD2
LCD
V
V
I
SS
mA
V
V
Input Voltage (all input pads)
DC Input Current
-0.5 to V
+ 0.5
DD1
i
in
I
- 10 to + 10
mA
mA
mW
mW
°C
I
DC Output Current
- 10 to + 10
300
out
P
Total Power Dissipation (T = 85°C)
tot
j
P
o
Power Dissipation per Output
Operating Junction Temperature
Storage Temperature
30
T
-40 to + 85
- 65 to 150
j
T
°C
stg
Table 27. Electrical Characteristics
DC OPERATION
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Supply Voltages
V
Supply Voltage
Note 9
1.7
3.6
V
V
V
DD1
V
DD2
V
V
Supply Voltage
LCD Voltage Internally
generated
1.75
4.5
DD2
LCD
LCD Supply Voltage
LCD Supply Voltage
Supply Current
LCD Voltage Supplied externally
Internally generated; note 1
4.5
4.5
15
14.5
14.5
30
V
V
I(V
)
)
V
= 2.8V; V = 10V;
LCD
20
µA
DD1
DD1
f
= 0;T
= 25°C;
sclk
amb
Parallel Port; note 3,8.
Supply Current Write Mode
V
= 2.8V; V = 10V;
100
120
µA
DD2
LCD
f
= 1Mhz;T
= 25°C;
sclk
amb
OSC_IN=GND; Note8.
I(V
Voltage Generator Supply
Current
with V = 0 and PRS = [0:0]
1
µA
µA
DD2
OP
with external V
LCD
LCD
V
= 2.8V; V
= 10V;
60
80
3
100
DD2
f
=0; T
= 25°C; no display
sclk
amb
load; 5x charge pump; note
2,3,6,
I(V
I(V
)
Total Supply Current
V
= 2.8V; V
= 10V; 5x
= 0;
130
µA
DD1,2
DD2
LCD
sclk
charge pump; f
T
amb
= 25°C; no display load;
note 2, 3, 6
Power down Mode with internal
or External VLCD. Note 4
10
23
µA
µA
)
External LCD Supply Voltage
Current
V
=2.8V; V
LCD
=10V;no
= 0;
LDCIN
DD
display load; f
sclk
T
amb
= 25°C; note 3.
Logic Outputs
V
High logic Level Output Voltage IOH=-500µA
Low logic Level Output Voltage IOL=+500µA
0.8VDD1
VSS
VDD1
V
V
0H
OL
V
0.2VDD1
55/66
STE2004
Table 23 Electrical Characteristics (continued)
DC OPERATION (continued)
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Logic Inputs
V
Logic LOW voltage level
Logic HIGH Voltage Level
Input Current
VSS
0.7
0.3
V
V
IL
IH
in
V
DD1
V
VDD2
V
DD1
I
V
= V
or V
DD1
-1
1
µA
in
SS1
Logic Inputs/Outputs
V
Logic LOW voltage level
V
0.3
V
V
IL
SS
V
DD1
V
Logic HIGH Voltage Level
0.7
V
+
IH
DD1
V
DD1
0.5
Column and Row Driver
R
ROW Output Resistance
Column Output resistance
Column Bias voltage accuracy
Row Bias voltage accuracy
3K
5K
5K
kohm
kohm
mV
row
R
V
10K
+50
+50
col
No load
-50
-50
col
V
mV
row
LCD Supply Voltage
V
LCD Supply Voltage accuracy;
Internally generated
V
= 2.8V; V = 10V;
LCD
-1.8
+1.8
%
LCD
DD
fsclk=0; T =25 C; no display
amb
load;note 2, 3, 6 & 7, VOP=69h,
PRS=2Hex
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
Temperature coefficient
-0.0·
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
-3
10
-0.35 ·
-3
10
-0.7 ·
-3
10
-1.05·
-3
10
-1.4 ·
-3
10
-1.75·
-3
10
-2.1 ·
-3
10
-2.3·
-3
10
Notes: 1. The maximum possible V
2. Internal clock
voltage that can be generated is dependent on voltage, temperature and (display) load.
LCD
3. When f
= 0 there is no interface clock.
sclk
4. Power-down mode. During power-down all static currents are switched-off.
5. If external V , the display load current is not transmitted to I
LCD
DD
6. Tolerance depends on the temperature; (typically zero at T
ature range limit.
= 27°C), maximum tolerance values are measured at the temper-
amb
7. For TC0 to TC7
8. Data Byte Writing Mode
9. VDD1<=VDD2
56/66
STE2004
Table 23 Electrical Characteristics (continued)
AC OPERATION
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
INTERNAL OSCILLATOR
F
Internal Oscillator frequency
V
= 2.8V;
DD
63
20
72
81
kHz
OSC
Tamb = -20 to +70 °C
F
External Oscillator frequency
Frame frequency
100
kHz
Hz
µs
EXT
F
fosc or fext = 72 kHz; note 1
75
FRAME
T
RES LOW pulse width
Reset Pulse Rejection
Internal Logic Reset Time
5
w(RES)
1
5
µs
T
µs
LOGIC
(RES)
T
VDD1 vs. VDD2 Delay
0
µs
VDD
Figure 71. RESET timing diagram
Tw(res)
Tlogic(res)
VDD2
VDD1
RES
INPUTS
I/O
(HOST)
I/O
(DRIVER)
Hi-Z
Hi-Z
INTERFACE
OUTPUT
OSCIN
FR_IN
(HOST)
OSC OUT
FR_OUT
(DRIVER)
RESET
TABLE
LOADED
LR0209
57/66
STE2004
Table 23 Electrical Characteristics (continued)
AC OPERATION (continued)
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
2
I C BUS INTERFACE (See note 4, 7)
F
SCL Clock Frequency
Fast Mode
DC
DC
400
3.4
kHz
SCL
High Speed Mode; Cb=100pF
(max);note 6;VDD1=2
MHz
High Speed Mode; Cb=400pF
(max);note 6; VDD1=2
DC
1.7
MHz
Fast Mode; note 6; VDD1=1.7V
Note 2,3, Cb = 100pF
400
KHz
ns
T
T
Set-up time (repeated) START
Condition
160
160
SU;STA
Hold Time (repeated) START
Condition
Note 2,3, Cb = 100pF
ns
HD;STA
T
Low Period of SCLH Clock
HIGH Period of SCLH Clock
Data set-up Time
Note 2,3, Cb = 100pF
Note 2,3, Cb = 100pF
Note 2,3, Cb = 100pF
Note 2,3, Cb = 100pF
Note 2,3, Cb = 100pF
160
160
60
ns
ns
ns
ns
ns
ns
LOW
T
HIGH
T
T
SU;DAT
HD;DAT
Data Hold Time
10
T
Rise Time of SCLH Signal
10
r;CL
T
r;CL1
Rise Time of SCLH Signal after Note 2,3, Cb = 100pF
a repeated START condition
10
and aftyer an Acknowledge bit
T
Fall time of SCLH signal
Rise time of SCLH signal
Fall time of SDAH signal
Rise Time of SDAH signal
Fall Time of SDAH signal
Note 2,3, Cb = 100pF
Note 2,3, Cb = 100pF
Note 2,3, Cb = 100pF
Note 2,3, Cb = 400pF
Note 2,3, Cb = 400pF
10
10
ns
ns
ns
ns
ns
ns
pF
f;CL
T
r;DA
T
10
80
f;DA
T
r;DA
20
T
20
160
f;DA
T
Setup Time for STOP condition Note 2,3, Cb = 100pF
160
100
SU;STO
Cb
Capacitive Load for SDAH and
SCLH
400
400
Cb
Capacitive Load for SDAH
pF
+SDA line and SCLH +SCL Line
2
Figure 72. I C-bus timings
Sr
Sr P
t
t
rDA
fDA
SDAH
SCLH
t
HD;DAT
t
HD;STA
t
SU;DAT
t
SU;STA
t
fCL
t
t
t
rCL1
rCL
rCL1
(1)
(1)
t
t
t
t
LOW HIGH
HIGH LOW
LR0093
= MCS current source pull-up
= Rp resistor pull-up
58/66
STE2004
Table 23 Electrical Characteristics (continued)
AC OPERATION (continued)
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
PARALLEL INTERFACE
T
T
System Cycle Time
V
= 1.7V; Read & Write
DD1
125
20
75
40
55
60
60
60
60
10
10
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CYC
CLW
CHW
Control Low Pulse Width (WR)
Control High Pulse Width (WR)
Control Low Pulse Width (RD)
Control High Pulse Width (RD)
Enable High Pulse Width (Write)
Enable Low Pulse Width (Write)
Enable High Pulse Width (Read)
Enable Low Pulse Width (Read)
Address Set-up Time
T
T
CLR
CHR
T
T
EWHW
T
T
EWLW
EWHR
T
EWLR
T
SU(A)
T
Address Hold Time
H(A)
T
Data Set-Up Time
SU1
T
Data Hold Time
H1
T
Read Access Time
40
30
SU2
T
Output Disable Time
0
H2
Figure 73. 68000-series Parallel interface timing
D/C
R/W
t
SU(A)
tH(A)
CS
E
t
CYC
t
EWHR, tEWHW
t
EWLR, tEWLW
t
SU1
t
H1
D0 to D7
(Write)
t
SU2
tH2
D0 to D7
(Read)
Figure 74. 8080-series parallel Interface timing
D/C
t
SU(A)
tH (A)
CS
t
CYC
t
CLR , tCLW
WR, RD
t
CHR , tCHW
t
SU1
t
H1
D0 to D7
(Write)
t
SU2
tH2
D0 to D7
(Read)
59/66
STE2004
Table 23 Electrical Characteristics (continued)
AC OPERATION (continued)
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SERIAL INTERFACE
F
T
T
T
T
T
T
T
T
T
T
T
T
T
Clock Frequency
V
V
= 1.7V;
8
MHz
SCLK
CYC
PWH1
PWL1
S2
DD1
DD1
Clock Cycle SCLK
SCLK pulse width HIGH
SCLK Pulse width LOW
CS setup time
125
60
60
40
50
50
30
30
30
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 1.7V
CS hold time
H2
CS minimum high time
SD/C setup time
PWH2
S3
SD/C hold time
H3
SDIN setup time
S4
SDIN hold time
H4
SDOUT Access Time
SDOUT Disable Time vs. SCLK
SDOUT Disable Time vs. CS
30
S5
0
0
20
20
H5
H6
Figure 75. Serial interface Timing
t
t
t
PWH2
S2
H2
CS
t
t
H3
S3
D/C
t
CYC
t
t
WH1
PWL1
t
S2
SCLK
SDIN
SOUT
t
t
H4
S4
t
H6
t
t
H5
S5
LR0096
fosc
Notes: 1. Fframe = ---------
960
2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V and V with
IL
IH
an input voltage swing of V to V
SS
DD
3. Cb is the capacitive load for each bus line.
4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
5. C
is the filtering CApacitor on VLCD
VLCD
6. Trise and Tfall (30%-70%) -10ns
2
7. I C bus AC Characteristics are tested by correlation
60/66
STE2004
Table 28. Pad Coordinates
Table 28. Pad Coordinates (continued)
NAME
R5
PAD
1
X (µm)
-2925.0
-2875.0
-2825.0
-2775.0
-2725.0
-2675.0
-2625.0
-2575.0
-2525.0
-2475.0
-2425.0
-2375.0
-2325.0
-2275.0
-2225.0
-2175.0
-2125.0
-2075.0
-2025.0
-1975.0
-1925.0
-1875.0
-1825.0
-1775.0
-1725.0
-1675.0
-1625.0
-1575.0
-1525.0
-1475.0
-1425.0
Y(µm)
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
NAME
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
PAD
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
X (µm)
-1375.0
-1325.0
-1275.0
-1225.0
-1175.0
-1125.0
-1075.0
-1025.0
-975.0
-925.0
-875.0
-825.0
-775.0
-725.0
-675.0
-625.0
-575.0
-525.0
-475.0
-425.0
-375.0
-325.0
-275.0
-225.0
-175.0
-125.0
125.0
Y(µm)
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
R4
2
R3
3
R2
4
R1
5
R0
6
C0
7
C1
8
C2
9
C3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
175.0
225.0
275.0
325.0
61/66
STE2004
Table 28. Pad Coordinates (continued)
Table 28. Pad Coordinates (continued)
NAME
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
PAD
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
X (µm)
375.0
Y(µm)
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
NAME
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C98
C99
C100
C101
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
PAD
94
X (µm)
1925.0
1975.0
2025.0
2075.0
2125.0
2175.0
2225.0
2275.0
2325.0
2375.0
2425.0
2475.0
2525.0
2575.0
2625.0
2675.0
2725.0
2775.0
2825.0
2875.0
2925.0
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
Y(µm)
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-596.5
-525.0
-475.0
-425.0
-375.0
-325.0
-275.0
-225.0
-175.0
-125.0
-75.0
425.0
95
475.0
96
525.0
97
575.0
98
625.0
99
675.0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
725.0
775.0
825.0
875.0
925.0
975.0
1025.0
1075.0
1125.0
1175.0
1225.0
1275.0
1325.0
1375.0
1425.0
1475.0
1525.0
1575.0
1625.0
1675.0
1725.0
1775.0
1825.0
1875.0
62/66
STE2004
Table 28. Pad Coordinates (continued)
Table 28. Pad Coordinates (continued)
NAME
R48
PAD
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
X (µm)
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
3086.5
2925.0
2875.0
2825.0
2775.0
2725.0
2475.0
2425.0
2375.0
2325.0
1975.0
1925.0
1875.0
1825.0
1775.0
1725.0
1675.0
1625.0
1575.0
1525.0
Y(µm)
-25.0
25.0
NAME
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
RES
PAD
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
X (µm)
1475.0
1425.0
1375.0
1325.0
1275.0
1225.0
1175.0
1125.0
1075.0
1025.0
975.0
Y(µm)
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
R49
R50
75.0
R51
125.0
175.0
225.0
275.0
325.0
375.0
425.0
475.0
525.0
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
R52
R53
R54
R55
R56
R57
R58
R59
925.0
R60
875.0
R61
825.0
R62
775.0
R63
725.0
R64-ICON
VDD1_AUX
FR_IN
OSC_IN
VSENSE_SLAVE
TEST_VREF
VSSAUX
SA1
375.0
CS
275.0
D/C
175.0
R/W - RD
E - WR
VSSAUX
SDAOUT
SDIN-SDAIN
SDOUT
SCLK-SCL
D7
75.0
-25.0
-75.0
-175.0
-225.0
-275.0
-375.0
-425.0
-475.0
-525.0
-575.0
-625.0
SA0
M/S
EXT_SET
SEL3
SEL2
SEL1
ICON
D6
D5
D4
D3
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Table 28. Pad Coordinates (continued)
Table 28. Pad Coordinates (continued)
NAME
D2
PAD
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
X (µm)
-675.0
Y(µm)
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
596.5
525.0
R26
NAME
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
217
PAD
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
-3086.5
X (µm)
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
-3086.5
475.0
Y(µm)
425.0
375.0
325.0
275.0
225.0
175.0
125.0
75.0
D1
-725.0
D0
-775.0
VSSAUX
TEST_MODE
VSS
-825.0
-1225.0
-1275.0
-1325.0
-1375.0
-1425.0
-1475.0
-1525.0
-1575.0
-1625.0
-1675.0
-1725.0
-1775.0
-1825.0
-2075.0
-2125.0
-2175.0
-2225.0
-2275.0
-2325.0
-2475.0
-2525.0
-2775.0
-2825.0
-2875.0
-2925.0
-3086.5
VSS
VSS
VSS
VSS
25.0
VSS
-25.0
VSS
-75.0
VSS
-125.0
-175.0
-225.0
-275.0
-325.0
-375.0
-425.0
-475.0
-525.0
VSS
VSS
VSS
VSS
VLCDSENSE
VLCD
VLCD
VLCD
VLCD
VLCD
OSC_OUT
FR_OUT
R31
R8
R7
R6
Table 29. Alignment marks coordinates
MARKS
mark1
mark2
mark3
mark4
X
Y
-3089.5
3089.5
-2400.0
538.1
-599.5
-599.5
599.5
599.5
R30
R29
R28
R27
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Figure 76. Alignment marks dimensions
Table 30. Bumps
Bump
Dimensions
Number
Bumps Size
Pad Size
30
µ
m X 98
µm X 17.5
43 m X 107µm
µ
Pad Pitch
50
µ
µ
m
m
39 µm
Spacing between
Bumps
20
94 µm
Table 31. Die Mechanical Dimensions
Die Size (X x Y)
6.42mm x 1.46mm
Wafers Thickness
500µm
Table 32. Revision History
Date
Revision
Description of Changes
May 2004
3
Moved the value of FSCLK parameter from Min. to Max. on the page 60/
66.
July 2004
4
Inserted Table 24 -N-Line Inversion in the page 44/66
65/66
STE2004
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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