STLC5465B [STMICROELECTRONICS]
MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED; 多HDLCWITH的N× 64开关矩阵相关的
| 型号： | STLC5465B |
| 厂家： | 
ST |
| 描述： | MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED |
| 文件： | 总101页 (文件大小：737K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STLC5465B
MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED
.
32 TxHDLCs WITH BROADCASTING CAPA-
BILITY AND/OR CSMA/CR FUNCTION WITH
AUTOMATIC RESTART IN CASE OF TX
FRAMEABORT
DESCRIPTION
TheSTLC5465Bis a Subscriberline interfacecard
controller for Central Office, Central Exchange,
NT2 and PBX capableof handling:
- 16 U Interfacesor
- 2 Megabitsline interface cards or
- 16 SLICs (Plain Old TelephoneService) or
- Mixed analogue and digital Interfaces (SLICs or
U Interfaces)or
.
.
.
.
32 RxHDLCs INCLUDING ADDRESS REC-
OGNITION
16 COMMAND/INDICATE CHANNELS (4 OR
6-BIT PRIMITIVE)
- 16 S Interfaces
- Switching Network with centralized processing
16 MONITOR CHANNELS PROCESSED IN
ACCORDANCE WITH GCI OR V*
256 x 256 SWITCHING MATRIX WITHOUT
BLOCKING AND WITH TIME SLOT SE-
QUENCE INTEGRITY AND LOOPBACK PER
BIDIRECTIONAL CONNECTION
.
DMA CONTROLLER FOR 32 Tx CHANNELS
AND 32 Rx CHANNELS
.
HDLCs AND DMA CONTROLLER ARE CAPA-
BLE OF HANDLING A MIX OF LAPD, LAPB,
SS7,CASANDPROPRIETARYSIGNALLINGS
.
.
EXTERNAL SHARED MEMORY ACCESS BE-
TWEEN DMA CONTROLLER AND MICRO-
PROCESSOR
SINGLE MEMORY SHARED BETWEEN
n x MULTI-HDLCs AND SINGLE MICRO-
PROCESSOR ALLOWS TO HANDLE n x 32
CHANNELS
PQFP160
(Plastic Quad Flat Pack)
.
.
BUSARBITRATION
INTERFACE FOR VARIOUS 8,16 OR 32 BIT
MICROPROCESSORS
ORDERING NUMBER : STLC5465B
.
RAM CONTROLLER ALLOWS TO INTER-
FACE UP TO :
-16 MEGABYTES OF DYNAMIC RAM OR
-1 MEGABYTE OF STATIC RAM
.
INTERRUPT CONTROLLER TO STORE
AUTOMATICALLY EVENTS IN SHARED
MEMORY
.
.
PQFP160PACKAGE
BOUNDARY SCAN FOR TEST FACILITY
November 1999
1/101
STLC5465B
TABLE OF CONTENTS
Page
I - PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I.1 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
I.2 - Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I.3 - Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I.3.1 - Input Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I.3.2 - Output Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I.3.3 - Input/OutputPin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
II - BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
III - FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
III.1 - The Switching Matrix N x 64 KBits/S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
III.1.1 - Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
III.1.2 - Architecture of the Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
III.1.3 - ConnectionFunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
III.1.4 - Loop Back Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
III.1.5 - Delay through the Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
III.1.5.1- Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
III.1.5.2 - SequenceIntegrity Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
III.1.6 - ConnectionMemory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
III.1.6.1- Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
III.1.6.2 - Access to Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
III.1.6.3 - Access to Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
III.1.6.4 - Switching at 32 Kbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
III.1.6.5 - Switching at 16 kbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
III.2 - HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
III.2.1- FunctionDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
III.2.1.1 - Format of the HDLC Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
III.2.1.2 - Composition of an HDLC Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
III.2.1.3 - Description and Functionsof the HDLC Bytes . . . . . . . . . . . . . . . . . . . . . . 26
III.2.2 - CSMA/CR Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
III.2.3 - Time Slot Assigner Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
III.2.4 - Data Storage Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
III.2.4.1 - Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
III.2.4.2 - Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
III.2.4.3 - Frame Relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
III.2.5 - Transparent Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
III.2.6 - Command of the HDLC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
III.2.6.1 - Reception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
III.2.6.2 - Transmission Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
III.3 - C/I and Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
III.3.1 - FunctionDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
III.3.2 - GCI and V* Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
III.3.3 - Structureof the Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/101
STLC5465B
Page
TABLE OF CONTENTS (continued)
III - FUNCTIONAL DESCRIPTION (continued)
III.3.4 - CI and Monitor Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
III.3.5 - CI and Monitor Transmission/Reception Command . . . . . . . . . . . . . . . . . . . . 30
III.4 - Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
III.4.1 - Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
III.4.2 - Exchangewith the shared memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
III.4.2.1 - Write FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
III.4.2.2 - Read Fetch Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
III.4.3 - Definition of the Interfacefor the different microprocessors . . . . . . . . . . . . . . . . . 35
III.5 - Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
III.5.1 - Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
III.5.2 - Choice of memory versus microprocessor and capacityrequired . . . . . . . . . . . . . 38
III.5.3 - Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
III.5.4 - SRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
III.5.5 - DRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
III.5.4.2 - 512K x n SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
III.5.5.2 - 1M x n DRAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
III.5.5.3 - 4M x n DRAM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
III.6 - Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
III.7 - Clock Selection and Time Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 41
III.7.1 - Clock Distribution Selection and Supervision . . . . . . . . . . . . . . . . . . . . . . . . 41
III.7.2 - VCXOFrequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
III.8 - InterruptController . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
III.8.1 - Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
III.8.2 - OperatingInterrupts (INT0 Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
III.8.3 - Time Base Interrupts (INT1 Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
III.8.4 - EmergencyInterrupts (WDO Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
III.8.5 - Interrupt Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
III.9 - Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
III.10 - Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
III.11 - Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IV - DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IV.1 - AbsoluteMaximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IV.2 - Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IV.3 - RecommendedDC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IV.4 - TTL Input DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IV.5 - CMOS Output DC ElectricalCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . 44
IV.6 - Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
V - CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
V.1 - SynchronizationSignals delivered by the system . . . . . . . . . . . . . . . . . . . . . . . 45
V.2 - TDM Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
V.3 - GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
V.4 - V* Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/101
STLC5465B
TABLE OF CONTENTS (continued)
Page
V1 - MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
VI.1 - Dynamic Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
VI.2 - Static Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
VII - MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
VII.1 - ST9 Family MOD0=1, MOD1=0, MOD2=0 . . . . . . . . . . . . . . . . . . . . . . . . . . 53
VII.2 - ST10/C16x mult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = 1 . . . . . . . . . . . . . . . . . . 55
VII.3 - ST10/C16x demult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = 1 . . . . . . . . . . . . . . . . . 57
VII.4 - 80C188 MOD0=1, MOD1=1, MOD2=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
VII.5 - 80C186 MOD0=1, MOD1=1, MOD2=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
VII.6 - 68000 MOD0=0, MOD1=0, MOD2=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
VII.7 - 68020 MOD0=0, MOD1=0, MOD2=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
VII.8 - Token Ring Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VII.9 - MasterClock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VIII - INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
VIII.1 - Identificationand Dynamic Command Register - IDCR (00)H . . . . . . . . . . . . . . . . 68
VIII.2 - GeneralConfiguration - GCR (02)H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
VIII.3 - Input Multiplex Configuration Register 0 - IMCR0 (04)H . . . . . . . . . . . . . . . . . . 70
VIII.4 - Input Multiplex Configuration Register 1 - IMCR1 (06)H . . . . . . . . . . . . . . . . . . 70
VIII.5 - Output Multiplex ConfigurationRegister 0 - OMCR0 (08)H . . . . . . . . . . . . . . . . . 71
VIII.6 - Output Multiplex ConfigurationRegister 1 - OMCR1 (0A)H . . . . . . . . . . . . . . . . . 71
VIII.7 - Switching Matrix ConfigurationRegister - SMCR (0C)H . . . . . . . . . . . . . . . . . . 71
VIII.8 - Connection Memory Data Register- CMDR (0E)H . . . . . . . . . . . . . . . . . . . . . 74
VIII.9 - Connection Memory Address Register - CMAR (10)H . . . . . . . . . . . . . . . . . . . 77
VIII.10 - SequenceFault Counter Register - SFCR (12)H . . . . . . . . . . . . . . . . . . . . . 79
VIII.11 - TimeSlot Assigner Address Register - TAAR (14)H . . . . . . . . . . . . . . . . . . . . 79
VIII.12 - TimeSlot Assigner Data Register - TADR (16)H . . . . . . . . . . . . . . . . . . . . . 80
VIII.13 - HDLCTransmit Command Register - HTCR (18)H . . . . . . . . . . . . . . . . . . . . 81
VIII.14 - HDLCReceive Command Register - HRCR (1A)H . . . . . . . . . . . . . . . . . . . . 82
VIII.15 - AddressField Recognition Address Register - AFRAR (1C)H . . . . . . . . . . . . . . . 84
VIII.16 - AddressField Recognition Data Register - AFRDR (1E)H . . . . . . . . . . . . . . . . . 84
VIII.17 - Fill Character Register - FCR (20)H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
VIII.18 - GCI Channels Definition Register 0 - GCIR0 (22)H . . . . . . . . . . . . . . . . . . . . 84
VIII.19 - GCI Channels Definition Register 1 - GCIR1 (24)H . . . . . . . . . . . . . . . . . . . . 85
VIII.20 - GCI Channels Definition Register 2 - GCIR2 (26)H . . . . . . . . . . . . . . . . . . . . 85
VIII.21 - GCI Channels Definition Register 3 - GCIR3 (28)H . . . . . . . . . . . . . . . . . . . . 85
VIII.22 - Transmit Command / IndicateRegister - TCIR (2A)H . . . . . . . . . . . . . . . . . . . 86
Transmit Command/Indicate Register (after reading) . . . . . . . . . . . . . . . . . . . 86
VIII.23 - Transmit Monitor Address Register - TMAR (2C)H . . . . . . . . . . . . . . . . . . . . 87
Transmit Monitor Address Register (after reading) . . . . . . . . . . . . . . . . . . . . . 87
VIII.24 - Transmit Monitor Data Register - TMDR (2E)H . . . . . . . . . . . . . . . . . . . . . . 88
VIII.25 - Transmit Monitor Interrupt Register - TMIR (30)H . . . . . . . . . . . . . . . . . . . . . 88
VIII.26 - Memory Interface ConfigurationRegister - MICR (32)H . . . . . . . . . . . . . . . . . . 88
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4/101
STLC5465B
Page
TABLE OF CONTENTS (continued)
VIII - INTERNAL REGISTERS (continued)
VIII.27 - InitiateBlock Address Register - IBAR (34)H . . . . . . . . . . . . . . . . . . . . . . . 90
VIII.28 - Interrupt Queue Size Register - IQSR (36)H . . . . . . . . . . . . . . . . . . . . . . . . 90
VIII.29 - Interrupt Register - IR (38)H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
VIII.30 - Interrupt Mask Register - IMR (3A)H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
VIII.31 - Timer Register - TIMR (3C)H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
VIII.32 - Test Register - TR (3E)H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
IX - EXTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IX.1 - Initialization Block in External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IX.2 - Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
IX.2.1 - Bits written by the Microprocessor only . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
IX.2.2 - Bits written by the Rx DMAC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
IX.2.3 - Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
IX.3 - Transmit Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
IX.3.1 - Bits written by the Microprocessor only . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
IX.3.2 - Bits written by the DMAC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
IX.3.3 - Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
IX.4 - Receive & Transmit HDLC Frame Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 96
IX.5 - Receive Command / Indicate Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0 . . . . . . . . . . . . . . . . . . . 97
IX.5.2 - Receive Command / IndicateInterrupt when TSV = 1 . . . . . . . . . . . . . . . . . . . 98
IX.6 - Receive Monitor Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
IX.6.1 - Receive Monitor Interrupt when TSV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 98
IX.6.2 - Receive Monitor Interrupt when TSV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 99
X - PQFP160 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5/101
STLC5465B
LIST OF FIGURES
Page
I - PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
II - BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 1 : GeneralBlock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
III - FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2 : Switching Matrix Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3 : Unidirectionaland Bidirectional Connections . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4 : LoopBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 : VariableDelay through the matrix with ITDM = 1 . . . . . . . . . . . . . . . . . . . . 18
Figure 6 : VariableDelay through the matrix with ITDM = 0 . . . . . . . . . . . . . . . . . . . . 19
Figure 7 : ConstantDelay through the matrix with SI = 1 . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8: DownstreamSwitching at 32kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9: UpstreamSwitching at 32kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10: Upstream and Downstream Switching at 16kb/s . . . . . . . . . . . . . . . . . . . . 24
Figure 11 : HDLC and DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12 : Structure of the Receive Circular Queue . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13 : Structure of the Transmit Circular Queue . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14 : D, C/I and Monitor Channel Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15: GCI channel to/from ISDN Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16: From GCI Channels to ISDN Channels . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17: From ISDN channelsto GCI Channels . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17.1: Write FIFO and Fetch Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18 : Multi-HDLC connected to µP with multiplexed buses . . . . . . . . . . . . . . . . . 36
Figure 19 : Multi-HDLC connected to µP with non-multiplexed buses . . . . . . . . . . . . . . . 36
Figure 20 : Microprocessor Interface for INTEL 80C188 . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21 : Microprocessor Interface for INTEL 80C186 . . . . . . . . . . . . . . . . . . . . . . 36
Figure 22 : Microprocessor Interface for MOTOROLA 68000 . . . . . . . . . . . . . . . . . . . 37
Figure 23 : Microprocessor Interface for MOTOROLA 68020 . . . . . . . . . . . . . . . . . . . 37
Figure 24 : Microprocessor Interface for ST9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 25 : n x 128K x 16 SRAM Memory Organization . . . . . . . . . . . . . . . . . . . . . . 39
Figure 26 : 512K x 8 SRAM Circuit Memory Organization . . . . . . . . . . . . . . . . . . . . . 39
Figure 27 : 256K x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 28 : 1M x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 29 : 4M x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 30 : Chain of n Multi-HDLC Components . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 31 : MHDLC Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 32 : VCXO Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 33 : The Three Circular Interrupt Memories . . . . . . . . . . . . . . . . . . . . . . . . . 43
IV - DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
V - CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 34 : Clocks received and delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . . 45
Figure 35 : SynchronizationSignals received by the Multi-HDLC . . . . . . . . . . . . . . . . . 46
Figure 36 : GCI Synchro Signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . . 47
Figure 37 : V* Synchronization Signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . 48
6/101
STLC5465B
Page
LIST OF FIGURES (continued)
VI - MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 38 : Dynamic Memory Read Signals from the Multi-HDLC . . . . . . . . . . . . . . . . . 49
Figure 39 : Dynamic Memory Write Signals from the Multi-HDLC . . . . . . . . . . . . . . . . . 50
Figure 40 : Static Memory Read Signals from the Multi-HDLC . . . . . . . . . . . . . . . . . . . 51
Figure 41 : Static Memory Write Signals from the Multi-HDLC . . . . . . . . . . . . . . . . . . . 52
Figure 42 : ST9 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
VII - MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 43 : ST9 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 44 : ST10 (C16x) Read Cycle; Multiplexed A/D . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 45 : ST10 (C16x) Write Cycle; Multiplexed A/D . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 46 : ST10 (C16x) Read Cycle; Demultiplexed A/D . . . . . . . . . . . . . . . . . . . . . 57
Figure 47 : ST10 (C16x) Write Cycle; Demultiplexed A/D . . . . . . . . . . . . . . . . . . . . . 58
Figure 48 : 80C188 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 49 : 80C188 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 50 : 80C186 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 51 : 80C186 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 52 : 68000 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 53 : 68000 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 54 : 68020 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 55 : 68020 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 56 : Token Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 57 : Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7/101
STLC5465B
I - PIN INFORMATION
I.1 - Pin Connections
1
2
NRESET
XTAL1
XTAL2
WDO
NCE7
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
NRAS3/NCE6
3
NCE5
4
NRAS2/NCE4
5
CB
NCAS1/NCE3
6
EC
NRAS1/NCE2
7
VCXO IN
VCXO OUT
DCLK
CLOCKA
CLOCKB
FRAMEA
FRAMEB
VDD
NCAS0/NCE1
8
NRAS0/NCE0
9
NOE
NWE
TRO
TRI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
VDD
VSS
D15
FS
D14
FSCG
FSCV
PSS
D13
D12
D11
DIN0
D10
DIN1
D9
DIN2
D8
DIN3
D7
98
DIN4
D6
97
DIN5
D5
96
DIN6
D4
95
DIN7
D3
94
DIN8
D2
93
VDD
D1
92
VSS
D0
91
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
NDIS
VSS
90
VDD
89
A23/ADM18
A22/ADM17
A21/ADM16
A20/ADM15
A19
88
87
86
85
84
A18
83
A17
82
NTRST
A16
81
8/101
STLC5465B
I - PIN INFORMATION (continued)
I.2 - Pin Description
Pin N°
Symbol
Type
Function
POWER PINS (all the power and ground pins must be connected)
14
15
VDD1
VSS1
VDD2
VSS2
VDD3
VSS3
VDD4
VSS4
VDD5
VSS5
VDD6
VSS6
VDD7
VSS7
VDD8
VSS8
VDD9
VSS9
VDD10
VSS10
VDD11
VSS11
Power
Ground DC ground
Power DC supply
Ground DC ground
Power DC supply
Ground DC ground
Power DC supply
Ground DC ground
Power DC supply
Ground DC ground
Power DC supply
Ground DC ground
Power DC supply
Ground DC ground
Power DC supply
Ground DC ground
Power DC supply
Ground DC ground
Power DC supply
Ground DC ground
Power DC supply
Ground DC ground (Total 22)
DC supply
29
30
45
46
61
62
73
74
89
90
107
108
121
122
133
134
145
146
158
159
CLOCKS
2
XTAL1
XTAL2
I
Crystal 1. A clock pulse at fMin. = 32000kHz can be applied to this input (or one pin
of two crystal pins) with : -50.10-6 f < +50.10-6.
<
∆
3
7
O
I3
Crystal 2. If the internal crystal oscillator is used, the second crystal pin is applied
to this output.
VCXO IN
VCXO input signal. This signal is compared to clock A(or B) selected inside the
Multi-HDLC.
8
VCXO OUT
CLOCKA
CLOCKB
FRAMEA
FRAMEB
DCLK
O4
I3
VCXO error signal. This pin delivers the result of the comparison.
Input Clock A (4096kHz or 8192kHz)
Input Clock B (4096kHz or 8192kHz)
Clock A at 8kHz
10
11
12
13
9
I3
I3
I3
Clock B at 8kHz
O8
Data Clock issued from Input Clock A (or B). This clock is delivered by the circuit
at 4096kHz (or2048kHz). DOUT0/7 aretransmittedon the risingedge of thissignal.
DIN0/7 are sampled on the falling edge of this signal.
17
18
16
19
FSCG
FSCV*
FS
O8
O8
I3
Frame synchronization for GCI at 8kHz. This clock is issuedfrom FRAME A (or B).
Frame synchronization for V Star at 8kHz
Frame synchronization.This signal synchronizes DIN0/7 and DOUT0/7.
PSS
O8
Programmable synchronization Signal. The PS bit of connection memory is read
in real time.
Type : I1 = Input TTL ;
O4 = Output CMOS 4mA ;
I2 = I1 + Pull-up ;
O4T = O4 + Tristate ;
I3 = I1 + Hysteresis ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate;
I4 = I3 + Pull-up ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = OutputCMOS 8mA, Tristate
I1 and I3 must be connected to VDD and VSS if not used
9/101
STLC5465B
I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Pin N°
Symbol
Type
Function
TIME DIVISION MULTIPLEXES (TDM)
20
21
22
23
24
25
26
27
28
31
32
33
34
35
36
37
38
39
DIN0
DIN1
I1
I1
TDM0 Data Input 0
TDM1 Data Input 1
TDM2 Data Input 2
TDM3 Data Input 3
TDM4 Data Input 4
TDM5 Data Input 5
TDM6 Data Input 6
TDM7 Data Input 7
TDM8 Data Input 8
TDM0 Data Output 0
TDM1 Data Output 1
TDM2 Data Output 2
TDM3 Data Output 3
TDM4 Data Output 4
TDM5 Data Output 5
TDM6 Data Output 6
TDM7 Data Output 7
DIN2
I1
DIN3
I1
DIN4
I1
DIN5
I1
DIN6
I1
DIN7
I1
DIN8
I1
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
NDIS
O8DT
O8DT
O8DT
O8DT
O8DT
O8DT
O8DT
O8DT
I1
DOUT 0/7 Not Disable. When this pin is at 0V, the Data Output 0/7 are at high
impedance. Wired at VDD if not used.
5
6
CB
EC
O8D
I1
Contention Bus for CSMA/CR
Echo
BOUDARY SCAN
40
41
42
43
44
NTRST
I4
I2
Reset for boundary scan
TMS
TDI
Mode Selection for boundary scan
Input Data for boundary scan
Output Data for boundary scan
Clock for boundary scan
I2
TDO
TCK
O4
I2
MICROPROCESSOR INTERFACE
58
59
60
MOD0
MOD1
MOD2
I1
I1
I1
1
1
0
1
1
1
0
0
1
0
0
0
1
0
0
1
0
1
0
1
1
80C188 80C186 68000 68020 ST9
Circuit Reset
ST10m ST10Nm
1
NRESET
NCS0
NCS1
INT0
I3
I3
47
48
49
50
Chip Select 0 : internal registers are selected
I3
Chip Select 1 : external memory is selected
O4
O4
Interrupt generated by HDLC, RxC/I or RxMON. Active high.
Interrupt1.This pin goes to 5V when the selected clock A (or B) has disappeared ;
INT1
250 s after reset this pin goes to 5V also if clock A is not present.
µ
4
WDO
O4
Watch Dog Output.This pin goes to 5V during1ms when the microprocessor has not
reset the Watch Dog during the programmable time.
Type : I1 = Input TTL ;
O4 = Output CMOS 4mA ;
I2 = I1 + Pull-up ;
O4T = O4 + Tristate ;
I3 = I1 + Hysteresis ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate;
I4 = I3 + Pull-up ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = OutputCMOS 8mA, Tristate
10/101
STLC5465B
I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Pin N°
Symbol
Type
Function
MICROPROCESSOR INTERFACE (continued)
51
52
53
SIZE0/NLDS
I3
I3
Transfer Size0 (68020)/Lower Data Strobe (68000)
Transfer Size1 (68020)/Bus High Enable (Intel) / Upper Data Strobe (68000)
SIZE1/NBHE/NUDS
NDSACK0/NDTACK O8T Data Strobe, Acknowledge and Size0 (68020)/Data Transfer Acknowledge
(68000)
54
NDSACK1/READY
O8T Data Strobe, Acknowledge and Size0 (68020)/Data Transfer Acknowledge
(Intel)
55
56
57
63
64
65
66
67
68
69
70
71
72
75
76
77
78
79
80
81
82
83
84
85
86
87
88
91
92
93
94
95
96
97
98
99
NAS/ALE
R/W / NWR
NDS/NRD
A0/AD0
A1/AD1
A2/AD2
A3/AD3
A4/AD4
A5/AD5
A6/AD6
A7/AD7
A8/AD8
A9/AD9
A10/AD10
A11/AD11
A12/AD12
A13/AD13
A14/AD14
A15/AD15
A16
I3
Address Strobe(Motorola) / Addresss Latch Enable(Intel)
Read/Write (Motorola / Write(Intel)
I3
I3
Data Strobe (Motorola 68020); at Vdd for 68000/Read Data (Intel)
Address bit 0 (Motorola 68020); at Vdd for 68000 / Address/Data bit 0 (Intel)
Address bit 1 (Motorola) / Address/Data bit 1 (Intel)
Address bit 2 (Motorola) / Address/Data bit 2 (Intel)
Address bit 3 (Motorola) / Address/Data bit 3 (Intel)
Address bit 4 (Motorola) / Address/Data bit 4 (Intel)
Address bit 5 (Motorola) / Address/Data bit 5 (Intel)
Address bit 6 (Motorola) / Address/Data bit 6 (Intel)
Address bit 7 (Motorola) / Address/Data bit 7 (Intel)
Address bit 8 (Motorola) / Address/Data bit 8 (Intel)
Address bit 9 (Motorola) / Address/Data bit 9 (Intel)
Address bit 10 (Motorola) / Address/Data bit 10 (Intel)
Address bit 11 (Motorola) / Address/Data bit 11 (Intel)
Address bit 12 (Motorola) / Address/Data bit 12 (Intel)
Address bit 13 (Motorola) / Address/Data bit 13 (Intel)
Address bit14 (Motorola) / Address/Data bit 14 (Intel)
Address bit15 (Motorola) / Address/Data bit 15 (Intel)
Address bit16 (Motorola) / Address bit 16 (Intel)
Address bit17 (Motorola) / Address bit 17 (Intel)
Address bit18 (Motorola) / Address bit 18 (Intel)
Address bit19 (Motorola) / Address bit 19 (Intel)
Address bit 20 from µP (input) / Address bit 15 for SRAM (output)
Address bit 21 from µP (input) / Address bit 16 for SRAM (output)
Address bit 22 from µP (input) / Address bit 17 for SRAM (output)
Address bit 23 from µP (input) / Address bit 18 for SRAM (output)
Data bit 0 for µP if not multiplexed (see Note 1).
Data bit 1 for µP if not multiplexed
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I1
A17
I1
A18
I1
A19
I1
A20/ADM15
A21/ADM16
A22/ADM17
A23/ADM18
DO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D1
D2
Data bit 2 for µP if not multiplexed
D3
Data bit 3 for µP if not multiplexed
D4
Data bit 4 for µP if not multiplexed
D5
Data bit 5 for P if not multiplexed
µ
D6
Data bit 6 for µP if not multiplexed
Data bit 7 for µP if not multiplexed
D7
D8
Data bit 8 for P if not multiplexed
µ
Type : I1 = Input TTL ;
O4 = Output CMOS 4mA ;
I2 = I1 + Pull-up ;
O4T = O4 + Tristate ;
I3 = I1 + Hysteresis ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate;
I4 = I3 + Pull-up ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = OutputCMOS 8mA, Tristate
11/101
STLC5465B
I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Pin N°
Symbol
Type
Function
MICROPROCESSOR INTERFACE (continued)
100
101
102
103
104
105
106
D9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data bit 9 for µP if not multiplexed
Data bit 10 for µP if not multiplexed
D10
D11
D12
D13
D14
D15
Data bit 11 for P if not multiplexed
µ
Data bit 12 for µP if not multiplexed
Data bit 13 for µP if not multiplexed
Data bit 14 for P if not multiplexed
µ
Data bit 15 for µP if not multiplexed
MEMORY INTERFACE
109
110
111
112
113
114
115
116
117
118
119
120
123
124
125
126
127
128
129
130
131
132
135
136
137
138
139
TRI
TRO
I3
Token Ring Input (for use Multi-HDLCs in cascade)
Token Ring Output (for use Multi-HDLCs in cascade)
Write Enable for memory circuits
O4
NWE
O4T
O4T
O4T
O4T
O4T
O4T
O4T
O4T
O4T
O4T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
NOE
Control Output Enable for memory circuits
Row Address Strobe Bank 0 / Chip Enable 0 for SRAM
Column Address Strobe Bank 0 / Chip Enable1 for SRAM
Row Address Strobe Bank 1 / Chip Enable 2 for SRAM
Column Address Strobe Bank 1 / Chip Enable 3 for SRAM
Row Address Strobe Bank 2 / Chip Enable 4 for SRAM
Chip Enable 5 for SRAM
NRAS0/NCE0
NCAS0/NCE1
NRAS1/NCE2
NCAS1/NCE3
NRAS2/NCE4
NCE5
NRAS3/NCE6
NCE7
Row Address Strobe Bank 3 / Chip Enable 6 for SRAM
Chip Enable 7 for SRAM
ADM0
Address bit 0 for SRAM and DRAM
ADM1
Address bit 1 for SRAM and DRAM
ADM2
Address bit 2 for SRAM and DRAM
ADM3
Address bit 3 for SRAM and DRAM
ADM4
Address bit 4 for SRAM and DRAM
ADM5
Address bit 5 for SRAM and DRAM
ADM6
Address bit 6 for SRAM and DRAM
ADM7
Address bit 7 for SRAM and DRAM
ADM8
Address bit 8 for SRAM and DRAM
ADM9
Address bit 9 for SRAM and DRAM
ADM10
ADM11
ADM12
ADM13
ADM14
Address bit 10 for SRAM and DRAM
Address bit 11 for SRAM only
Address bit 12 for SRAM only
Address bit 13 for SRAM only
Address bit 14 for SRAM only
Type : I1 = Input TTL ;
O4 = Output CMOS 4mA ;
I2 = I1 + Pull-up ;
O4T = O4 + Tristate ;
I3 = I1 + Hysteresis ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate;
I4 = I3 + Pull-up ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = OutputCMOS 8mA, Tristate
12/101
STLC5465B
I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Pin N°
Symbol
Type
Function
MEMORY INTERFACE (continued)
140
141
142
143
144
147
148
149
150
151
152
153
154
155
156
157
160
DM0
DM1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I2
Memory Data bit 0
Memory Data bit 1
Memory Data bit 2
Memory Data bit 3
Memory Data bit 4
Memory Data bit 5
Memory Data bit 6
Memory Data bit 7
Memory Data bit 8
Memory Data bit 9
Memory Data bit 10
Memory Data bit 11
Memory Data bit 12
Memory Data bit 13
Memory Data bit 14
Memory Data bit 15
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DM9
DM10
DM11
DM12
DM13
DM14
DM15
NTEST
Test Control. When this pin is at 0V each output is high impedance except XTAL2 Pin.
Type : I1 = Input TTL ;
O4 = Output CMOS 4mA ;
I2 = I1 + Pull-up ;
O4T = O4 + Tristate ;
I3 = I1 + Hysteresis ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate;
I4 = I3 + Pull-up ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = OutputCMOS 8mA, Tristate
Note : D0/15 input/output pins must be connected to one single external pull up resistor if not used.
I.3 - Pin Definition
I.3.1 - Input Pin Definition
I1
I2
I3
I4
: Input 1 TTL
: Input 2 TTL+ pull-up
: Input 3 TTL+ hysteresis
: Input 4 TTL + hysteresis +pull-up
I.3.2 - Output Pin Definition
O4 : Output CMOS 4mA
O4T : Output CMOS 4mA, Tristate
O8 : Output CMOS 8mA
O8T : Output CMOS 8mA,Tristate
O8D : Output CMOS 8mA,Open Drain
O8DT : Output CMOS 8mA,Open Drain or Tristate (Programmable pin)
Moreover, each output is high impedance when the NTEST Pin is at 0 volt except XTAL2 Pin which is a
CMOS output.
I.3.3 - Input/Output Pin Definition
I/O : InputTTL/ Output CMOS 8mA.
N.B. XTAL1 : this input is CMOS.
XTAL2 : NTEST pin at 0 has no effecton this pin.
13/101
STLC5465B
II - BLOCK DIAGRAM
The top level functionalitiesof Multi-HDLC appear on the general block diagram.
Figure 1 : GeneralBlock Diagram
B
C L O C K
F R A M E
C L O C K
F R A M
B
A
A E
U T 7 D O
U T 6 D O
U T 5 D O
D O U T 4
D O U T 3
U T 2 D O
U T 1 D O
U T 0 D O
N D I S
D I N 0
D I N 1
D I N 2
D I N 3
D I N 4
D I N 5
There are :
- The switching matrix,
- The time slot assigner,
- The 16 Command/Indicateand Monitor Channel
receivers belonging to two General Component
Interfaces(GCI),
- The 32 HDLC transmitters with associated DMA
controllers,
- The 32 HDLC receivers with associated DMA
controllers,
- The 16 Command/Indicateand Monitor Channel
transmitters belonging to two General Compo-
nent Interfaces(GCI),
- The memory interface,
- The microprocessor interface,
- The bus arbitration,
- The clock selection and time synchronization
function,
- The interrupt controller,
- The watchdog,
- The boundaryscan.
14/101
STLC5465B
III - FUNCTIONAL DESCRIPTION
III.1 - The SwitchingMatrix N x 64 KBits/S
III.1.1 - Function Description
An external pin (NDIS) asserts a high impedance
on all the TDM outputs of the matrix when active
(during the initialization of the board for example).
The matrix performs a non-blocking switch of 256
time slots from 8 Input Time Division Multiplex
(TDM) at 2 Mbit/s to 8 output Time Division Multi-
plex. A TDM is composedof 32 Time Slots (TS) at
64 kbit/s. The matrix is designed to switch a 64
kbit/s channel (Variable delay mode) or an hyper-
channel of data (Sequence integrity mode). So, it
will both provide minimum throughput switching
delayfor voiceapplicationsandtime slotsequence
integrity for data applications on a per channel
basis.
The requirements of the Sequence Integrity(n*64
kbit/s) mode are the following:
Allthe time slotsof a giveninput framemust be put
out during a same output frame.
The time slots of an hyperchannel (concatenation
of TS in the same TDM) are not crossed together
at output in different frames.
In variable delay mode, the time slot is put out as
soon as possible. (The delay is two or three time
slots minimum between input and output).
III.1.2 - Architecture of the Matrix
The matrix is essentially composed of buffer data
memories and a connection memory.
Thereceivedserial datais first convertedtoparallel
by aserialto parallelconverterandstoredconsecu-
tively in a 256 position Buffer Data Memory (see
Figure 2 on Page 16).
To satisfy the Sequence Integrity (n*64 kbit/s) re-
quirements, the data memory is built with an even
memory, an odd memory and an output memory.
Two consecutive frames are storedalternatively in
the odd and evenmemory.During the timean input
frame is stored, the one previously stored is trans-
ferred into the output memory according to the
connectionmemoryswitchingorders.Aframelater,
the outputmemoryis readand datais convertedto
serial and transferred to the output TDM.
III.1.3 - Connection Function
Two types of connections are offered:
- unidirectional connection and
- bidirectional connection.
An unidirectionalconnectionmakesonly theswitch
of an inputtimeslotthroughan outputonewhereas
a bidirectionalconnectionestablishesthelinkin the
other direction too. So a double connectioncan be
achieved by a single command (see Figure 3 on
Page 17).
For test facilities, any time slot of an Output TDM
(OTDM) can be internally looped back into the
same Input TDM number(ITDM) at the same time
slot number.
A Pseudo Random Sequence Generator and a
Pseudo Random Sequence Analyzer are imple-
mented in the matrix. They allow the generationa
sequence on a channel or on a hyperchannel, to
analyse it and verify its integrity after several
switching in the matrix or some passing of the
sequenceacross different boards.
The Frame Signal (FS) synchronises ITDM and
OTDM but a programmabledelay or advance can
beintroducedseparatelyon eachITDMand OTDM
(a half bit time, a bit time or two bit times).
An additional pin (PSS) permits the generation of
a programmable signal composed of 256 bits per
frame at a bit rate of 2048 kbit/s.
III.1.4 - Loop Back Function
Any time slot of an Output TDM can be internally
looped back on the time slot which has the same
TDM number and the same TS number
(OTDMi, TSj) ----> (ITDMi, TSj).
In the case of a bidirectional connection, only the
one specified by the microprocessor is concerned
by the loop back (see Figure 4 on Page 17).
15/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 2 : Switching Matrix Data Path
PRSG : Pseudo Random Sequence Generator
PRSA : Pseudo Random Sequence Analyzer
OTSV : Output Time Slot Validated
INS : Insert
DIN 0/7
CM : Connection Memory (from CMARRegister)
BIT SYNCHRO
ME
: Message Enable
IMTD : IncreasedMin ThroughtputDelay
SGV : SequenceGenerator Validated
DIN
From SMCR Register
0/7
D7
DIN’ 7
Tx
HDLC
Rx
GCI
SAV :
SequenceAnalyzer Validated
D4/5
HDLCM
1
PRSG
SGV
1
LOOP
1
PSEUDO RANDOM
SEQUENCE
GENERATOR
211 - 1
CM
(whenRead)
Internal
Bus
S / P
Rec. O.152
CONNECTION
MEMORY
D
1
DATA
MEMORIES
A
CMDR
IMTD
D
D
Sequence Integrity,
LOOP, PRSA, PRSG,
INS, OTSV
64kb/s and
n x 64kb/s
D
Data
Register
Sequence
Integrity
A
1
CM
CMAR
Address
Register
INS
1
PRSA
SAV
PRSG
PSEUDORANDOM
SEQUENCE
ANALYZER
211 - 1
ME
1
SFCR
Rec. O.152
Sequence Fault
Counter Register
P / S
D4/5
Tx
Rx
GCI
HDLC
D7
GCIR
1
D0/7
BIT SYNCHRO
From Connection Memory
OTSV (per channel)
From OMCR Register
OMV (per multiplex)
OR
From N DIS PIN
(for all multiplexes)
DOUT 0/7
16/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 3 : Unidirectional and Bidirectional Connections
OTSy, OTDMq
ITSx,ITDMp
DATA
MEMORY
n x 64kb/s
DOWN STREAM
DOWN STREAM
Unidirectional Connection
OTSy, OTDMq
ITSx,ITDMp
DATA
MEMORY
n x 64kb/s
DOWN STREAM
DOWN STREAM
ITSy, ITDMq
UP STREAM
OTSx, OTDMp
UP STREAM
DATA
MEMORY
n x 64kb/s
p, q = 0 to 7
x, y = 0 to 31
Bidirectional Connection
Figure 4 : LoopBack
OTSV
OTSy, OTDMq
ITSx,ITDMp
DATA
MEMORY
n x 64kb/s
DOWN STREAM
DOWN STREAM
OTSx, OTDMp
UP STREAM
DATA
MEMORY
n x 64kb/s
ITSy, ITDMq
UP STREAM
Loop
p, q = 0 to 7
x, y = 0 to 31
Loopback per channel relevant if bidirectional connection has been done.
III.1.5 - Delay through the Matrix
III.1.5.1 - VariableDelay Mode
b) IfITSx< OTSy< ITSx+n thenthevariabledelay
is :
OTSy - ITSx + 32 Time slots
c) OTSy < ITSxthen the variable delay is :
32 - (ITSx- OTSy)Time slots.
In the variable delay mode, the delay through the
matrixdependson therelativepositionsof theinput
and output time slots in the frame.
So, some limits are fixed :
- the maximum delay is a frame+ 2 time slots,
- the minimum delay is programmable.
N.B. Rule b) and rule c) are identical.
For n = 1 and n = 2, see Figure 5 on Page 18.
Three time slots if IMTD = 1, in this case n = 2 in
the formula hereafter or two time slots if
IMTD = 0, in this case n = 1 in the sameformula
(see Paragraph ”Switching Matrix Configuration
Reg SMCR(0C)H” on Page 64).
III.1.5.2 - Sequence Integrity Mode
In the sequenceintegrity mode (SI = 1, bit located
in theConnectionMemory), theinputtime slotsare
put out 2frameslater(fig. 6 - page19). In thiscase,
the delay is defined by a single expression :
All the possibilities can be ranked in three cases :
a) If OTSy > ITSx + n then the variable delay is :
OTSy - ITSx Time slots
Constant Delay = (32 - ITSx) + 32 + OTSy
So, the delay in sequence integrity mode varies
from 33 to 95 time slots.
17/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 5 : Variable Delay through the matrixwith ITDM = 1
1) Case : If OTSy > ITSx + 2, then Variable Delay is : OTS y - ITSx TimeSlots
Frame n
Frame n + 1
ITS0
ITSx ITSx+1 ITSx+2
ITS31 ITS0
ITS31
Input
Frame
y > x + 2
OTS0
OTS31
Output
Frame
OTSy
Variable De lay
(OTSy - ITSx)
2) Case : If ITSx OTSy ITSx + 2, then Variable Delay is : OTSy - ITSx + 32 TimeSlots
≤
≤
Frame n
Frame n + 1
ITS0
ITSx ITSx+1 ITSx+2
ITS31 ITS0
ITSx
ITS31
Input
Frame
x
y
x + 2
≤
≤
OTS0
OTS31
Output
Frame
OTSy
OTSy
32 TimeSlots
Variable De lay : OTSy - ITSx + 32 TimeSlots
3) Case : If OTSy < ITSx, then Variable De lay is : 32 - (ITSx - OTSy) TimeSlots
Frame n
Frame n + 1
ITSx
ITS0
ITSx
ITS31 ITS0
ITS31
Input
Frame
y < x
OTS0
OTS31
Output
Frame
OTSy
OTSy
Variable Delay : 32 - (ITSx - OTSy) TimeSlots
32 TimeSlots
18/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 6: Variable Delay through the matrix with ITDM = 0
1) Case : If OTSy > ITSx + 1, then Variable Delay is : OTSy - ITSx TimeSlots
Frame n
Frame n + 1
ITS0
ITSx ITSx+1 ITSx+2
ITS31 ITS0
ITS31
Input
Frame
y > x + 1
OTS0
OTS31
Output
Frame
OTSy
Variable Delay
(OTSy - ITSx)
2) Case : If ITSx ≤ OTSy ≤ ITSx + 1, then Variable Delay is : OTSy - ITSx + 32 TimeSlots
Frame n
Frame n + 1
ITS0
ITSx ITSx+1 ITSx+2
ITS31 ITS0
ITSx
ITS31
Input
Frame
x ≤ y ≤ x + 1
OTS0
OTS31
Output
Frame
OTSy
OTSy
32 TimeSlots
Variable Delay : OTSy - ITSx + 32 TimeSlots
3) Case : If OTSy < ITSx, then Variable Delay is : 32 - (ITSx - OTSy) TimeSlots
Frame n
Frame n + 1
ITS0
ITSx
ITS31 ITS0
ITSx
ITS31
Input
Frame
y < x
OTSy
OTS0
OTS31
Output
Frame
OTSy
Variable Delay : 32 - (ITSx - OTSy) TimeSlots
32 TimeSlots
19/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 7 : Constant Delay through the matrix with SI = 1
Cons tant Delay = (32 -ITSx) + 32 + OTSy
ITS
:
:
Input TimeSlot
0
0
x
y
31
31
≤
≤
≤
≤
OTS
Output TimeSlot
Frame n
Frame n + 1
Frame n + 2
ITS0
ITS31 ITS0
ITS31 ITS0
ITS31
Min. Constant Delay = 33TS
32 TimeSlots
OTS0
+ 0
OTS31
1
+
= 33
TimeSlots
OTS31
Max. Constant Delay = 95 TimeSlots
+ 32
32 - 0
+ 31
= 95
TimeSlots
+ 32
+ OTSy
= Constant
Delay
(32 - ITSx)
20/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.1.6 - Connection Memory
III.1.6.1 - Description
- Connection Memory Data Register (CMDR) and
- Connection Memory Address Register (CMAR).
The connection memory is composedof 256 loca-
tions addressed by the number of OTDM and TS
(8x32).
III.1.6.3 - Access to Data Memory
To extract the contents of the data memory it is
possible to read the data memory from microproc-
essor with the help of the two registers :
- Connection Memory Data Register (CMDR) and
- Connection Memory Address Register (CMAR).
Each location permits :
- to connect each input time slotto one outputtime
slot (If two or more output time slots are con-
nected to the same input time slot number, there
is broadcasting).
- toselectthe variabledelaymodeorthesequence
integrity mode for any time slot.
III.1.6.4 - Switchingat 32 Kbit/s
- to loop back an output time slot. In this case the
contentsof an inputtime slot(ITSx,ITDMp)is the
same as the output time slot (OTSx,OTDMp).
- to output the contents of the corresponding con-
nection memory instead of the data which has
been stored in data memory.
Four TDMs can be programmed individually to
carry 64 channelsat 32 Kbit/s (only if these TDMs
are at 2 Mbit/s).
Two bits (SW0/1) located in SMCR define the type
of channels of two couples of TDMs.
- to output the sequence of the pseudo random
sequence generator on an output time slot: a
pseudo random sequencecan be insertedin one
or severaltime slots (hyperchannel) of the same
Output TDM ; this insertion must be enabled by
the microprocessor in the configuration register
of the matrix.
- to definethe sourceof a sequenceby the pseudo
random sequence analyzer: a pseudo random
sequence can be extracted from one or several
time slots (hyperchannel)of thesame InputTDM
and routedto the analyzer;this extraction can be
enabled by the microprocessor in the configura-
tion register of the matrix (SMCR).
SW0 defines TDM0 and TDM4 (GCI0) and SW1
defines TDM1 and TDM5 (GCI1). If TDM0 or/and
TDM1 carry 64 channels at 32 Kbit/s then TDM2
or/and TDM3 are not available externally they are
used internally to perform the function.
Downstreamswitching at 32 kb/s on page 22.
Upstreamswitching at 32 kb/son page23.
III.1.6.5 - Switchingat 16 kbit/s
TheTDM4andTDM5can beGCImultipexes.Each
GCI multipexcomprises8GCI channels.Each GCI
channelcomprises oneD channelat 16 Kbit/s.See
GCI channel definition GCI Synchro signal deliv-
ered by the Multi-HDLC on page 30.
- to assert a high impedance level on an output
time slot (disconnection).
- to delivera programmable256-bitsequencedur-
ing 125microsecondson theProgrammablesyn-
chronizationSignal pin (PSS).
Itis possibletoswitchthe contentsof16 Dchannels
from the 16 GCI channelsto 4 timeslotsof the 256
output timeslots.
III.1.6.2 - Access to Connection Memory
In the other direction the contents of an selected
timeslot is automaticallyswitched to 4 D channels
at 16 Kbit/s.
Supposingthat the Switching Matrix Configuration
Register (SMCR) has been already written by the
microprocessor, it is possible to access to the con-
nectionmemoryfrom microprocessorwith the help
of two registers :
See Connection Memory Data Register CMDR
(0E)H on page 74
21/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 8: DownstreamSwitching at 32kb/s
3.9µs
a
b
Free
c
Free
d
Free
d
e
DIN0
a
b
c
c
e
din2
dout2
dout4
a
d
d
b
MON
D C/I
Internal
command
c
b
a
If SW0=1
DOUT4
(GCI 0)
A E
C/I
D
B1
B2
MON
D
C/I
DIN0
dout 4
din 0
DOUT 4
4 bit shifting
(GCI 0)
DOUT2
dout 2
din 2
DIN2 not used
SW0=1
Internal
commands
Switching
at 32kb/ s
DIN 1
dout 5
din 1
din 3
DOUT5
(GCI 1)
4 bit shifting
dout 3
DIN3 not used
DOUT3
SW1=1
MULTI HDLC STLC 546 5
22/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 9: Upstream Switching at 32kb/s
µ
Timeslot (3.9 s)
d
d
c
b
a
DIN4
(GCI 0)
B1
B2
MON
D C/I
b
c
a
x
y
z
DOUT6
B2 GCI 1
B1 GCI 0
d
B2 GCI 0
B1 GCI 1
x
B2 GCI1
y
DIN6 =
shifted
DOUT6
a
c
b
B2 GCI1
B1 GCI 0
Free
B2 GCI 0
B1 GCI1
a
b
d
Free
c
Free
Free
e
DOUT0
GCI 0
DOUT 0
DIN4
Internal loopback
and
4 bit shifting (2+2)
by software
From
DOUT6
DOUT6
Switching at 32 kb/s
DOUT1
DIN6
DIN5
GCI1
MULTI HDLC
STLC 5465
23/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 10: Upstreamand DownstreamSwitching at 16kb/s
TDM side
GCI side
D11
D12
C1
C2
C3
C4
D11
D12
D21
D22
D31
D32
D41
D42
TS 16n+3
TSy
A
E
D21
D22
C1
C2
C3
C4
A
TSy of any TDM can
programmablewith y
be
comprised between
0 and 31
TS 16n+7
.
E
D31
D32
C1
C2
TS 16n+11
C3
C4
A
E
D41
D42
C1
C2
C3
C4
A
TS 16n+15
E
n: GCIchannel
number, 0 to 1
24/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.2 - HDLC Controller
III.2.1.2 - Composition of an HDLC Frame
III.2.1 - Function Description
Opening Flag
The internal HDLC controller can run up to 32
channels in a conventional HDLC mode or in a
transparent (non-HDLC) mode (configurable per
channel).
Eachchannel bitrate is programmablefrom 4kbit/s
to 64kbit/s. All the configurationsare also possible
from 32 channels (from 4 to 64 kbit/s) to one
channelat 2 Mbit/s.
Address Field (first byte)
Address Field (second byte)
Command Field (first byte)
Command Field (second byte)
Data (first byte)
Data (optional)
Inreception,theHDLCtime slotscan directlycome
from the input TDM DIN8 (direct HDLC Input) or
from any other TDM input after switching towards
the output 7 of the matrix (configurable per time
slot).
In transmission, the HDLC frames are sent on the
output DOUT6 and on the output CB (with or with-
out contention mechanism), or are switched to-
wards the other TDM output via the input 7 of the
matrix (see Figure 11).
Data (last byte)
FCS (first byte)
FCS (second byte)
Closing Flag
- Opening Flag
- One or two bytes for address recognition(recep-
tion) and insertion (transmission)
- Data bytes with bit stuffing
- Frame Check Sequence: CRC with polynomial
III.2.1.1 - Format of the HDLC Frame
Theformatofan HDLCframeisthesameinreceive
and transmit direction and shown here after.
G(x) = x16 +x12+x5+1
- Closing Flag.
Figure 11 : HDLC and DMAController Block Diagram
DOUT 6
Direct HDLC Output
From Output 7
of the Matrix
From Output 6
of the Matrix
DIN 8
Direct HDLC Input
Conte ntion
Bus
To Input 7 of the Matrix
TIME SLOT ASSIGNER
32 Rx HDLC
32 CSMA-CR
32 Tx HDLC
Echo
32 ADDRESS
RECOGNITION
32 Rx FIFO’s
32 Rx DMAC
32 Tx FIFO’s
32 Rx DMAC
P
RAM
INTERFACE
µ
INTERFACE
25/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.2.1.3 - Description and Functions of the
HDLC Bytes
- FLAG
The binary sequence 01111110marksthe begin-
ning and the end of the HDLC Frame.
Note : In reception,three possibleflag configura-
tions are allowed and correctly detected :
- two normal consecutive flags :
Field Recognition Mask register is associated to
each AddressField Recognitionregister; soeach
received address bit can be masked or not indi-
vidually.
TheprogrammableAddressFieldRecognitionreg-
ister is located in the Address Field Recognition
MemoryandtheprogrammableAddressFieldRec-
ognition Mask register is located in the Address
Field RecognitionMask Memory.
...0111111001111110...
Upon an address match, the address and the
data followingarewrittentothedatabuffers;upon
an address mismatch, the frame is ignored. So,
it authorizes the filtering of the messages. If no
comparison is specified, each frame is received
whatever its address field.
In Transmission, the whole of the transmit frame
is locatedin sharedmemory;thecontrollersends
the frame including the destination or broadcast
addresses.
- two consecutiveflags with a ”0” common :
...011111101111110...
- a global common flag : ...01111110...
this flag is the closing flag for the current frame
and the opening flag for the next frame
- ABORT
The binary sequence 1111111 marks an Abort
command.
Inreception,sevenconsecutive1’s,insidea mes-
sage, are detected as an abort command and
generates an interrupt to the host.
In transmit direction, an abort is sent upon com-
mand of the micro-processor. No ending flag is
expected after the abort command.
- BIT STUFFING AND UNSTUFFING
This operation is done to avoid the confusion of
a data byte with a flag.
In transmission, if five consecutive 1’s appear in
theserial streambeingtransmitted,a zeroisauto-
maticallyinserted (bit stuffing)after he fifth ”1”.
In reception, if five consecutive ”1” followed by a
zero are received, the ”0” is assumed to have
been inserted and is automatically deleted (bit
unstuffing).
III.2.2 - CSMA/CR Capability
An HDLC channel can come in and go out by any
TDM input on the matrix. For time constraints,
direct HDLC Access is achievedby the input TDM
(DIN 8) and the outputTDM (DOUT6).
In transmission, a time slotof a TDM canbe shared
between different sources in Multi-point to point
configuration(differentsubscriber’sboardsforexam-
ple).ThearbitrationsystemistheCSMA/CR(Carrier
SenseMultiple accesswithContention Resolution).
The contention is resolved by a bus connected to
the CB pin (Contention Bus). This bus is a 2Mbit/s
wire line common to all the potentialsources.
If a Multi-HDLC has obtainedthe accessto the bus,
thedatato transmitis sentsimultaneouslyon theCB
lineandtheoutputTDM. Theresult ofthe contention
isreadbackontheEcholine.Ifacollisionisdetected,
the transmission is stoppedimmediately. A conten-
tionon a bitbasisis soachieved. Each message to
be sentwith CSMA/CRhas a priorityclass(PRI= 8,
10) indicated by the Transmit Descriptor and some
rules are implementedto arbitratethe access to the
line. The CSMA/CR Algorithm is given. When a re-
questto send a message occurs, the transmitter
determines if the shared channel is free. The Multi-
HDLClistenstotheEcholine.IfCormoreconsecutive
”1” are detected (C depending on the message’s
priority), the Multi-HDLC beginsto send its message.
Eachbitsent issampledbackandcomparedwith the
originalvaluetosend.If a bitisdifferent,thetransmis-
sionis instantaneouslystopped(beforethe endofthis
bittime)andwill restartassoonastheMulti-HDLC will
detectthatthechannel is freewithoutinterruptingthe
microprocessor.
- FRAME CHECK SEQUENCE
TheFrameCheckSequenceiscalculatedaccording
to therecommendationQ921oftheCCITT.
- ADDRESS RECOGNITION
In the frame, one or two bytes are transmitted to
indicate the destinationof the message.
Two types of addresses are possible :
- a specific destinationaddress
- a broadcast address.
In reception, the controller compares the receive
addresses to internal registers, which contain its
own address. 4 bits in the receive command
register (HRCR) inform the receiver of which
registers, it has to take into account for the com-
parison. The receiver can compare one or two
address bytes of the message to the specific
board address and/or the broadcastaddress.
For the specific destination address only, the
receiver can compare or not each bit of the two
receive address bytes to the programmable Ad-
dress Field Recognition register. An Address
After a successful transmission of a message, a
26/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
programmablepenaltyPEN(1or2) is appliedto the
transmitter (see Paragraph HDLC Transmit Com-
mandRegisteron Page 81). It guaranteesthat the
same transmitterwill not takethe bus anothertime
before a transmitterwhich has to send a message
of same priority.
This structure allows to :
- Store receive frames of variable and unknown
length
- Read transmit frames stored in external memory
by the host
- Easily perform the frame relay function.
In case of a collision, the frame which has been
aborted is automaticallyretransmitted by the DMA
controller without warning the microprocessor of
this collision. The frame can be located in several
buffers in external memory. The collision can be
detectedfrom the second bit of the opening frame
to the last but one bit of the closing frame.
III.2.4.1 - Reception
At the initialization of the application, the host has
to prepare an Initialization Block memory, which
containsthe first receive buffer descriptor address
for each channel, and the receivecircular queues.
At the opening of a receive channel, the DMA
controller reads the address of the first buffer de-
scriptor correspondingto thischannel in the initiali-
zation Block. Then, the data transfer can occur
without intervention of the processor (see Figure
12 on Page 28).
A new HDLCframe always begins in a new buffer.
A long frame can be split between several buffers
if the buffersize is not sufficient.All the information
concerning the frame and its location in the
circular queue is included in the Receive Buffer
Descriptor :
III.2.3 - Time Slot Assigner Memory
Each HDLC channel is bidirectional and configu-
rate by the Time Slot Assigner(TSA).
TheTSAis amemoryof 32 words(oneper physical
TimeSlot) where all ofthe 32 inputand outputtime
slots of the HDLC controllers can be associated
to logical HDLC channels. Super channels are
created by assigning the same logical channel
number to several physical time slots.
The following features are configurate for each
HDLC time slot :
- The Receive Buffer Address (RBA),
- The size of the receive buffer (SOB),
- Thenumberof byteswritteninto thebuffer(NBR),
- The Next Receive Descriptor Address (NRDA),
- The status concerningthe receive frame,
- The control of the queue.
- Time slot used or not
- One logical channel number
- Its source : (DIN 8 or the output 7 of the matrix)
- Its bit rate and concerned bits (4kbit/s to
64kbit/s). 4kbit/s correspond to one bit transmit-
ted each two frames. This bit must be presentin
two consecutive frames in reception, and re-
peated twice in transmission.
III.2.4.2 - Transmission
In transmission, the data is managed by a similar
structure as in reception (see Figure 13 on
Page 28).
- Its destination:
- direct output on DOUT6
- direct output on DOUT6 and on the Contention
Bus(CB)
- on another OTDM via input 7 of the matrix and
on the ContentionBus (CB)
By the same way, a framecan be split up between
consecutivetransmit buffers.
The main information contained in the Transmit
Descriptor are :
- transmit buffer address (TBA),
- numberof bytesto transmit(NBT)concerningthe
buffer,
- next transmit descriptoraddress (NTDA),
- status of the frame after transmission,
- control bit of the queue,
III.2.4 - Data Storage Structure
Data associated with each Rx andTx HDLC chan-
nelis storedin externalmemory;Thedatatransfers
between the HDLC controllers and memory are
ensuredby 32 DMAC(DirectMemory AccessCon-
troller) in receptionand 32 DMAC in transmission.
- CSMA/CR priority (8 or 10).
The storage structure chosen in both directions is
composed of one circular queue of buffers per
channel. In such a queue, each data buffer is
pointedto bya Descriptorlocatedinexternalmem-
ory too. The main information contained in the
Descriptor is the address of the Data Buffer, its
length and the address of the next Descriptor; so
the descriptors can be linked together.
III.2.4.3 - Frame Relay
The principle of the frame relay is to transmit a
frame which has been received without treatment.
A new heading is just added. This will be easily
achieved, taking into accountthat the queue struc-
ture allows the transmission of a frame split be-
tween several buffers.
27/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 12 : Structureof the Receive Circular Queue
Initialization Block
up to 32 channels
RECEIVE
DMA
CONTROLLER
0
1
RDA
RDA
31 RDA
Receive
Descriptor 2
Initial Receive
Descriptor
NRDA
RBA
NRDA
RBA
Receive
Buffer 1
Receive
Buffer 2
Receive
Descriptor n
Receive
Descriptor 3
NRDA
RBA
NRDA
RBA
Receive
Buffer n
Receive
Buffer 3
One receive circular queue by channel
Figure 13 : Structureof the Transmit Circular Queue
Initialization Block
up to 32 channels
TRANSMIT
DMA
CONTROLLER
0
1
TDA
TDA
31 TDA
Transmit
Descriptor 2
Initial Transmit
Descriptor
NTDA
TBA
NTDA
TBA
Transmit
Buffer 1
Transmit
Buffer 2
Transmit
Descriptor n
Transmit
Descriptor 3
NTDA
TBA
NTDA
TBA
Transmit
Buffer n
Transmit
Buffer 3
One transmit circularqueue by channel
28/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.2.5 - Transparent Modes
the addressesthatthe Rx controllerhasto takeinto
account.
In transparent mode: ”fill character” register se-
lected or not.
Inthe transparentmode, the Multi-HDLC transmits
data in a completely transparent manner without
performing any bit manipulation or Flag insertion.
The transparentmode is per byte function.
III.2.6.2 - TransmissionControl
Two transparent modes are offered :
The configurationof the controlleroperatingmode
is : HDLC mode or Transparentmode.
- First mode : for the receive channels, the
Multi-HDLC continuously writes received bytes
into the external memory as specified in the cur-
rentreceivedescriptorwithouttakingintoaccount
the Fill Character Register.
- Secondmode: theFill CharacterRegister specifies
the”fill character”which must be takeninto account.
Inreception,the”fill character”willnotbetransferred
totheexternalmemory.Thedetectionof”Fillcharac-
ter”marks the end of a messageand generatesan
interruptifBINT=1(seeTransmitDescriptoronPage
95). When the”Fill character”is not detecteda new
messageis receiving.
The control of the controller : START, HALT, CON-
TINUE,ABORT.
- START: Ona startcommand,theTxDMAcontrol-
ler reads the address of the first descriptor in the
initializationblockmemoryandtriesto transmitthe
first frame if End Of Queueis not at ”1”.
- HALT : The transmitter finishes to send the cur-
rentframeand stops.Thechannel can be restart-
ed on a CONTINUE command.
- CONTINUE: if the CONTINUEcommand occurs
after HALT command, the HDLC Transmitter re-
starts by transmitting the next buffer associated
to the next descriptor.
As for the HDLC mode the correspondence
between the physical time slot and the logical
channel is fully defined in the Time Slot Assigner
memory (Time slot used or not used, logical chan-
nel number,source, destination).
If the CONTINUE command occurs after an
ABORT command which has occurred during a
frame, the HDLC transmitterrestarts by transmit-
tingthe framewhich has beeneffectivelyaborted
by the microprocessor.
III.2.6 - Command of the HDLC Channels
- ABORT: On an abortcommand, the transmission
of the current frame is instantaneouslystopped,
an ABORT sequence”1111111” is sent, followed
by IDLE or FLAG bytes. The channel can be
restarted on a START or CONTINUEcommand.
The microprocessor is able to control each HDLC
receive and transmit channel. Some of the com-
mands are specific to the transmission or the re-
ception but others are identical.
Transmission of FLAG (01111110) or IDLE
(111111111)between frames can be selected.
CRC can be generated or not. If the CRC is not
generated by the HDLC Controller, it must be lo-
cated in the shared memory.
III.2.6.1 - Reception Control
The configuration of the controller operating mode
is: HDLC mode or Transparentmode.
The control of the controller: START, HALT, CON-
TINUE,ABORT.
- START : On a start command, the RxDMA con-
troller reads the address of the first descriptor in
the initialization block memory and is ready to
receive a frame.
- HALT: For overloading reasons, the microproc-
essor can decide to halt the reception. The DMA
controllerfinishes transferof the currentframe to
external memory and stops. The channel can be
restarted on CONTINUE command.
- CONTINUE : The reception restarts in the next
descriptor.
In transparentmode: ”fill character”register can be
selectedor not.
III.3 - C/I and Monitor
III.3.1 - Function Description
TheMulti-HDLC is ableto operateboth GCI andV*
links. The TDM DIN/DOUT 4 and 5 are internally
connected to the CI and Monitor receivers/trans-
mitters.Sincethecontrollershandleupto 16CIand
16 Monitor channels simultaneously, the Multi-
HDLC can manage up to 16 level 1 circuits.
- ABORT: On an abort command, the reception is
instantaneously stopped. The channel can be
restarted on a START or CONTINUE command.
The Multi-HDLCcan be used to supportthe CI and
monitor channels based on the following proto-
cols :
Receptionof FLAG(01111110) or IDLE (11111111)
between Frames.
- ISDN V* protocol
- ISDN GCI protocol
Address recognition. The microprocessor defines
- Analog GCI protocol.
29/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.3.2 - GCI and V* Protocol
A TDM can carry 8 GCI channels or V* channels. The monitor and S/C bytes always stand at the same
position in the TDM in both cases.
Channel 0
Channel 31
TS29 TS30
B2 MON
Channel 1 to Channel 30
TS0
B1
TS1
B2
TS2
TS3
S/C
TS28
B1
TS31
S/C
MON
The GCI or V* channels are composed of 4 bytes
and have both the same general structure.
III.3.3 - Structure of the Treatment
GCI/V* TDM’s are connected to DIN 4 and DIN 5.
The D channels are switched through the matrix
towards the output 7 and the HDLC receiver. The
Monitor and S/C bytes are multiplexed and sent to
the CI and Monitor receivers (see Figure 14 on
Page 31).
B1
B2
MON
S/C
B1, B2 : Bytes of data. Those bytes are not
affectedby the monitorand CI protocols.
MON : Monitor channel for operation and
maintenanceinformation.
In transmission, the S/C and Monitor bytes are
recombined by multiplexing the information pro-
videdbythe Monitor,C/I andtheHDLCTransmitter.
Likeinreception,the D channelis switchedthrough
the matrix.
S/C
: Signallingand control information.
Only Monitor handshakes and S/C bytes are dif-
ferent in the three protocols :
ISDN V* S/C byte
D
C/I 4 bits
C/I 4 bits
T
A
A
E
E
E
III.3.4 - CI and Monitor Channel Configuration
ISDN GCI S/C byte
D
Monitor channel data is located in a time slot ; the
CI and monitorhandshakebits arein the next time
slot.
Analog GCI S/C byte
Each channel can be defined independently. A
table with all the possible configurations is pre-
sented hereafter (Table 13).
C/I 6 bits
CI : The Command/Indicate channel is used for
activation/deactivation of lines and control
functions.
D : These 2 bits carry the 16 kbit/s ISDN basic
access D channel.
Table 13 : C/I and MON Channel Configuration
CI For analog subscriber (6 bits)
C/I validated or not
CI For ISDN subscriber (4 bits)
Monitor V*
Monitor validated
or not
In GCI protocol, A and E are the handshake bits
and are used to control the transfer of information
on monitor channels.The E bit indicates the trans-
fer of each new byte in one direction and the A bit
acknowledges this byte transfer in the reverse di-
rection.
Monitor GCI
Note : A mix of V* and GCI monitoring can be performed for two
distinct channels in the same application.
III.3.5 - CI and Monitor Transmission/Reception
Command
InV*protocol,thereisn’t anyhandshakemode.The
transmitter has only to mark the validity of the
Monitor byte by positioningthe E bit (Tis not used
and is forced to ”1”).
The reception of C/I and Monitor messages are
managed by two interrupt queues.
In transmission, a transmit command register is
implemented for each C/I and monitor channel (16
C/I transmit command registers and 16 Monitor
transmit command registers). Those registers are
accessible in read and write modes by the micro-
processor.
For more information about the GCI and V*, refer
to the General Interface Circuit Specification (is-
sue1.0, march 1989) and the France Telecom
Specification about ISDN Basic Access second
generation(November 1990).
30/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 14 : D, C/I and Monitor Channel Path
DIN 5
DIN 4
DOUT 4 DOUT 5
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
GCI1
GCI0
GCI0
GCI1
SWITCHING
MATRIX
D Channels
from Tx HDLC
D Channels
to Rx HDLC
GCI CHANNEL DEFINITION
16 Rx
C/I
16 Rx
MON
16 Tx
C/I
16 Tx
MON
INTERRUPT
CONTROLLER
Internal Bus
III.3.6 - Scramblerand Descrambler
- in reception: 16 GCI channels (B1+B2+MON+
D+C/I),
- in transmission: 16 ISDN channels (B1+B2+B*).
It is possibleto switch the contentsof B1, B2 and
D channelsfrom16 GCIchannelsinany16 “ISDN
channels”, TDM side.
The contents of B1 and/or B2 can be scrambled
ornot.If scrambledthenumberof the32timeslots
(TDM side) are different mandatory.
Receiving thecontentsof MonitorandCommand
/ Indicatechannels from 16 GCI channels.Primi-
tives and messages are stored automatically in
the externalshared memory.
Transmitting “six bit word” (A, E, S1, S2, S3, S4)
to any 16 “ISDN channels”TDM side or not. See
SBV bit of General Configuration Register GCR
(02)H on page 68.
Downstream. From ISDN channels to GCI chan-
nels on page 34.
TheTDM4andTDM5canbe GCImultipexes.Each
GCI multipexcomprises 8GCIchannels.EachGCI
channelcomprises two B channels at 64 Kbit/s.
In receptionit is possibleto switchand to scramble
the contents of 32 B channels of GCI channels to
32 timeslots of the 256 output timeslots. In trans-
mission these 32 timeslots are assigned to 32 B
channels.
In the other direction the contentsof an selected B
channels is automatically switched and descram-
bled to one B channel of 16 GCI channel.
See Connection Memory Data Register CMDR
(0E)H on page 74 (SCR bit).
Connection between “ISDN channels” and GCI
channels.
Three timeslots are assigned to one“ISDN chan-
nels”. Each “ISDN channels” comprises three
channels:B1+B2+B*with B*=D1,D2, A, E, S1, S2,
S3, S4. GCI channel to/from ISDN channel on
page 32.
- in reception:ISDN channel (B1+B2+B*)
- in transmission: GCI channel (B1+B2+MON+
D+C/I)
It is possibleto switch the contentsof B1, B2 and
D channels from 16 “ISDN channels”, TDM side
Upstream. From GCI channels to ISDN channels
on page 33.
31/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
in 16 GCI channels.
See SBV bit of General Configuration Register
GCR (02)H on page 68.
Alarm Indication Signal.
This detection concerns 16 hyperchannels. One
hyperchannel comprises 16 bits (B1 and B2 only).
TheAlarmIndicationsfor the16 hyperchannelsare
stored automatically in the external shared mem-
ory.See AISDbitof SwitchingMatrixConfiguration
Reg SMCR (0C)H on page 71.
The contents of B1 and/or B2 can be descram-
bled or not. If descrambled the 32 B1/B2 belong
to GCI channels mandatory.
Receiving six bit word (A, E, S1, S2, S3, S4) from
any 16 “ISDN channels”, TDM side. The 16 “six
bit word” are stored automaticallyin the external
shared memory.
Transmitting the contents of Monitor and Com-
mand / Indicate channels to 16 GCI channels.
Figure 15: GCI channel to/from ISDN Channel
GCI side
TDM side
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
SCRAMBLER /
DESCRAMBLER
TS4n
TS3m
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
SCRAMBLER /
DESCRAMBLER
TS4n+1
TS3m+1
D
D
A
M1
M2
M3
M4
M5
M6
M7
M8
E
TS3m+2
S1
S2
S3
S4
TS4n+2
TS4n+3
D
D
PCM at 2 Mb/s
m: ISDN channel
number, 0 to 9
C1
C2
C3
C4
A
If TDMat 4 Mb/s
odd timeslot
or eventimeslot
can be selected
E
n: GCI channel
number, 0 to 7
Six bit word
Primitive
Monitor controllers
Command Indicate controllers
RX
TX
TX
RX
C/I interrupt
Queue located in
shared memory
MON interrupt
Queue located in
shared memory
Microprocessor
32/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 16: From GCI Channelsto ISDN Channels
Extension TX
C/I controllers
up to 16 for
A, E, S1 to S4
SCRAMBLER
up to 32
SBV
for the 16
controllers
SCR
by timeslot
TDM 0, 2
if PCM
at 4 Mb/s
1
GCI side
DIN4/5
B1, B2
SWITCHING
MATRIX
D, A, E S1 to S4
RX C/I
RX MON
controllers
up to 16 for
primitives
controllers
up to 16
Interruptcontroller
C/I interrupt Queue,
MON interruptQueue,
located in shared memory
Microprocessor
33/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 17: From ISDN channelsto GCI Channels
DESCRAMBLER
up to 32
SCR
by timeslot
B1, B2
TDM 0, 2
if PCM
at 4 Mb/ s
GCI side
DOUT4/5
B1, B2
D
SWITCHING
MATRIX
A, E, S1 to S4
C/I
A, E, MON
B1, B2
(16 bits)
AIS
Detection
up to 16
Extension RX
C/I controller
up to 16
TX C/I
TX MON
controller
up to 16
primitives
controller
up to 16
primitives
ISDN channels
ISDN channels
Interrupt controller
C/I interrupt Queue
Microprocessor
located in shared memory
III.4 - MicroprocessorInterface
III.4.1 - Description
select the internal registers and CS1 the external
memory.
TheMulti-HDLC circuitcanbe controlledbyseveral
types of microprocessors(ST9, Intel/Motorola8 or
16 data bits interfaces) such as :
- ST9 family
- INTEL 80C188 8 bits
- INTEL 80C186 16 bits
- MOTOROLA 68000 16 bits
- MOTOROLA 68020 16/32 bits
- ST10 family
During the initialization of the Multi-HDLC circuit,
themicroprocessorinterfaceis informedof thetype
ofmicroprocessorthat is connectedby polarisation
of three external pins MOD 0/2).
Table 14 : MicroprocessorInterface Selection
MOD2 MOD1 MOD0
Microprocessor
Pin
0
Pin
1
Pin
1
80C188
80C186
1
1
1
1
0
0
68000
0
0
0
68020
0
0
1
ST9
1
0
1
ST10 A/D multiplexed
ST10 A/D not multiplexed
Reserved
1
1
0
0
1
0
TwochipSelect(CS0/1)pinsare provided.CS0will
34/101
STLC5465B
III.4.2 - Exchange with the shared memory
III.4.2.2 - Read Fetch Memory
AFetch Buffer located in the microprocessor inter-
face allows to reduce the shared memory access
cycle for the microprocessor.
Itisusedwhatevermicroprocessorselectedthanks
to MOD0/2 pins.
When the microprocessor delivers the address
word named An to readdata named [An] out ofthe
shared memory in fact it reads data [An] from one
of four Read Fetch Memories.
Thenumber of wait cycle for the microprocessoris
strongly reduced and can reach zero when An,
addressworddeliveredby themicroprocessor,and
data[An] is alreadyin the ReadFetchMemory and
validated.
This Fetch Buffer consists of one Write FIFO and
four Read Fetch Memories.
III.4.2.1 - Write FIFO
The source of [An] is truly the shared memory
whateverAn.
When the microprocessor delivers the address
word named An to write data named [An] in the
shared memory in fact it writes data [An] and
addressword An in theWriteFIFO(Deep 4 words).
If An is in Fetch Memory, [An] is removed in Fetch
Memory.
III.4.3 - Definition of the Interface for the differ-
ent microprocessors
Thesignalsconnectedtothe microprocessorinter-
face are presented on the following figures for the
different microprocessor.
The number of wait cycles for the microprocessor
is strongly reduced.
Figure 17.1: Write FIFO and Fetch Memories.
Shared memory
To shared memory
From shared memory
Write FIFO
An, [An]
Read Fetch
Memory
Four
Fetch Memories
An+1, [An+1]
An+2, [An+2]
An+3, [An+3]
microprocessor
interface
An, [An]
From microprocessor
To microprocessor
Microprocessor
35/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 18 : Multi-HDLC connectedto µP with multiplexed buses
MULTI-HDLC
Multiplex
Address/Data Bus
Address Bus
Data Bus
P
µ
ST9/10
STATIC or
DYNAMIC RAM
(organized
Internal Bus
P
RAM
INTERFACE
INTEL
MOTOROLA
8/16 BITS
µ
INTERFACE
by 16 bits)
BUS ARBITRATION
Figure 19 : Multi-HDLC connected to µP with non-multiplexed buses
MULTI-HDLC
Address Bus
Address Bus
Data Bus
STATIC or
DYNAMIC RAM
(organized
µP ST10
INTEL
MOTOROLA
8/16 BITS
Internal Bus
RAM
INTERFACE
µP
INTERFACE
by 16 bits)
Data Bus
BUS ARBITRATION
Figure 20 : MicroprocessorInterface for INTEL 80C188
INT0/1
WDO
NRESET
CS0/1
ARDY
INTEL
80C188
P
µ
NWR
INTERFACE
NRD
ALE
A8/19
AD0/7
Figure 21 : MicroprocessorInterface for INTEL 80C186
INT0/1
WDO
NRESET
CS0/1
NBHE
ARDY
INTEL
80C186
P
µ
NWR
INTERFACE
NRD
ALE
A16/19
AD0/15
36/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 22 : MicroprocessorInterface for MOTOROLA68000
INT0/1
WDO
MHDLC
NRESET
CS0/1
NDTACK
R/NW
NUDS
NLDS
NAS
MOTOROLA
68000
P
µ
INTERFACE
A1/23
AD8/15
AD0/7
CS0/1, Ax/23
R/NW
Figure 23 : MicroprocessorInterface for MOTOROLA68020
INT0/1
WDO
MHDLC
NRESET
CS0/1
NDSACK0/1
SIZE0/1
R/NW
NDS
MOTOROLA
68020
P
µ
INTERFACE
NAS
A0/23
AD8/15
AD0/7
CS0/1, Ax/23
R/NW
Figure 24 : MicroprocessorInterface for ST9
INT0/1
WDO
MHDLC
NRESET
CS0/1
WAIT
R/NW
NDS
µP
ST9
INTERFACE
NAS
A8/15
AD0/7
37/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.5 - Memory Interface
III.5.1 - Function Description
Example1 : iftheapplicationrequires16bitmProc-
essorand 1 MegawordSharedmemorysize, three
capabilitiesare offered:
- 4 DRAM Circuits (256Kx16) or
- 4 DRAM Circuits (1Mx4) or
The memory interface allows the connection of
Static or Dynamic RAM. The memory space ad-
dressablein thetwo configurationsisnot thesame.
Inthe caseof dynamicmemory(DRAM),the mem-
ory interface will address up to 16 Megabytes. In
caseof staticmemory(SRAM)only1 Megabytewill
be addressed. The memory location is always or-
ganized in 16 bits.
- 1 DRAM Circuit (1Mx16).
Example2 : if the applicationrequires8 bit mProc-
essor and 1 MegabyteShared memory size, three
capabilitiesare offered:
- 2 DRAM Circuits (256Kx16) or
- 8 SRAM Circuits (128Kx8)or
- 2 SRAM Circuits (512kx8).
The memory is shared between the Multi-HDLC
andthe microprocessor.Theaccess tothe memory
is arbitrated by an internal function of the circuit:
the bus arbitration.
Example 3 : for small applications it is possible to
connect 2 SRAM Circuits (128Kx8) to obtain 256
Kilobytes shared memory.
III.5.2 - Choice of memory versus microproc-
essor and capacity required
III.5.3 - MemoryCycle
For SRAM and DRAM, the different cycles are
programmable. See Memory Interface Configura-
tion Regist. MICR (32)H on Page 88.
The memory interface depends on the memory
chips which are connected. As the memory chips
will be chosen versus the microprocessor and the
wanted memory space, the following table pre-
sents the different configurations DRAM and
Each cycle is equal to : p x 1/f
with f the frequencyof signal applied to the Crystal
1 input and p selected by the user. See page 9.
µ
SRAM selection versus P.
Table 22 : DRAM and SDRAM Selection versus µP
Microprocessor and
shared memory
Shared memory size required by the application
8 bits
Number of
Megabytes
0.5
1
2
1
4
2
8
4
16
8
µProcessor
16/32 bits
µProcessor
Number of
Megawords
0.25
0.5
DRAM Circuits proposed
Capacity
Organization
256Kx16
1Mx4
4 Megabits
1(256Kx16) 2(256Kx16) 4(256Kx16)
4(1Mx4)
8(1Mx4)
16(1Mx4)
4(1Mx16)
4(4Mx4)
16 Megabits
1Mx16
1(1Mx16)
2(1Mx16)
4Mx4
8(4Mx4)
64 Megabits
4Mx16
1(4Mx16)
2(4Mx16)
SRAM Circuits proposed
Capacity
1 Megabits
4 Megabits
Organization
128Kx8
Not possible
4(128Kx8)
8(128Kx8)
2(512kx8)
512kx8
38/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.5.4 - SRAM interface
The Address bits delivered by the Multi-HDLC for
512K x n SRAM circuits are :
ADM0/14 and ADM15/18 (19 bits) corresponding
The SRAM space achieves 1 Mbyte max. It is
always organized in 16 bits. The structure of the
memory plane is shown in the following figures.
Because of the different chips usable, 19 address
wires and 8 NCE (Chip Enable) are necessary to
addressthe 1 Mbyte. The NCE selects the Most or
LeastSignificantByte versus the valueof A0 deliv-
ered by the µP and the location of chip in the
memory space.
µ
with A1/19 delivered by the P.
Figure 26 :512K x 8 SRAM Circuit Memory
Organization
ADM0/18, NWE, NOE
512K x 16
are connected to eachcircuit
512K x 8 circuit
1
0
NCE1
NCE0
DM8/15
DM0/7
III.5.4.1 - 128K x 16 (up to 512K x 16) SRAM
This memory can be obtained with two 128K x 8
SRAM circuits (up to eight circuits)
III.5.5 - DRAM Interface
In DRAM, the memory space can achieveup to 16
megabytes organized by 16 bits. Eleven address
wires, four NRAS and two NCAS are needed to
select any byte in the memory. One NRAS signal
selects1 bankof 4 andthe NCASsignalsselectthe
bytes concerned by the transfer (1 or 2 selecting a
byte or a word). The DRAM memory interface is
then defined. The ”RAS only” refresh cycles will
refresh all memory locations. The refresh is pro-
grammable. The frequency of the refresh is fixed
by the memory requirements.
Signals
NCE7
NCE6
NCE5
NCE4
NCE3
NCE2
NCE1
NCE0
A19
1
A18
1
A0 or equiv.
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
1
0
1
0
0
0
0
III.5.5.1 - 256Kx n DRAM Signals
The Address bits delivered by the Multi-HDLC for
128K x 8 SRAM circuits are :
ADM0/14 and ADM15/16 (17 bits) corresponding
with A1/17 delivered by the µP.
Signals
NRAS3
NRAS2
NRAS1
NRAS0
NCAS1
NCAS0
A20
1
A19
1
A0
6800
1
0
0
0
1
0
Figure 25 :n x 128K x 16 SRAM Memory
1
0
UDS
LDS
Organization
The Address bits delivered by the Multi-HDLC for
256K x n DRAM circuits are :
ADM0/8(2 x 9 = 18 bits) correspondingwithA1/18
delivered by the µP.
ADM0/16, NWE, NOE
128K x 16
are connecte dto eachcircuit
128K x 8 circuit
7
6
NCE7
NCE6
Figure 27 : 256K x 16 DRAM Circuit Organization
5
3
1
4
2
0
NCE5
NCE3
NCE1
NCE4
NCE2
NCE0
CAS1
7
CAS0
6
256K x 16
RAS3
5
3
1
4
2
0
RAS2
RAS1
RAS0
DM8/15
DM0/7
III.5.4.2 - 512K x n SRAM
Signals
NCE1
A0 or equiv.
DM8/15
DM0/7
1
0
NCE0
ADM0/8, NWE, NOE a re connected to ea ch circuit.
39/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.5.5.2 - 1M x n DRAM Signals
Figure 29 : 4M x 16 DRAM Circuit Organization
Signals
NRAS3
NRAS2
NRAS1
NRAS0
NCAS1
NCAS0
A22
1
A20
1
A0
6800
NCAS1
NCAS0
4M x 16
1
0
3
2
NRAS1
NRAS0
0
1
0
0
1
0
1
0
UDS
LDS
DM8/15
DM0/7
ADM0/10, NWE, NOE are connected to each circuit
The Address bits delivered by the Multi-HDLC for
1M x n DRAM circuits are :
ADM0/9(2 x10 =18bits)correspondingwithA1/20
delivered by the µP.
III.6 - Bus Arbitration
The Bus arbitration function arbitrates the access
to the bus between different entities of the circuit.
Those entities which can call for the bus are the
following :
Figure 28 : 1M x 16 DRAM Circuit Organization
NCAS1
NCAS0
- The receive DMAcontroller,
- The microprocessor,
- The transmit DMA controller,
1Mx 16
- The Interrupt controller,
- The memory interface for refreshing the DRAM.
7
6
NRAS3
This list gives the memory access priorities per
default.
If the treatmentof morethan 32 HDLC channelsis
required by the application, it is possible to chain
severalMulti-HDLC components.Thatis donewith
two external pins (TRI, TRO) and a token ring
system.
The TRI, TRO signals are managed by the bus
arbitration function too. When a chip has finished
its tasks, it sends a pulse of 30 ns to the next chip.
5
3
1
4
2
0
NRAS2
NRAS1
NRAS0
DM8/15
DM0/7
Figure 30 : Chain of n Multi-HDLC Components
ADM0/9, NWE, NOE are connected to each circuit
III.5.5.3 - 4M x n DRAM Signals
TRI
MHDLC 0
Signals
NRAS1
NRAS0
NCAS1
NCAS0
A23
1
A0 or equiv.
P
µ
RAM
TRO
TRI
MHDLC 1
TRO
0
1
0
TRI
The Address bits delivered by the Multi-HDLC for
4M x n DRAM circuits are :
MHDLC n
ADM0/10 (2 x 11 = 22 bits) corresponding with
TRO
P Bus
µ
RAMBus
µ
A1/22 delivered by the P.
40/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.7 - Clock Selectionand Time Synchronization
III.7.1 - Clock Distribution Selection and
Supervision
clock distribution can be controlled by the micro-
processor thanks to SELB, bit of GeneralConfigu-
ration Register.
Dependingon the applications,three different sig-
nals of synchronization (GCI, V* or Sy) can be
provided to the component. The clock A/B fre-
quency can be a 4096 or 8192kHz clock. The
componentis informed of the synchronization and
clocks that are connectedby software.Thetimings
of the different synchronizationare given page 45.
Two clock distributions are available: Clock at
4.096 MHz or 8.192 MHz and a synchronization
signal at 8 KHz. The componenthas to select one
of these two distributions and to checkits integrity.
See Fig. 31 MHDLC clock generation.
Two other clock distributions are allowed: Clock at
3072 MHz or 6144 MHz and a synchronization
signal at 8 KHz. See GeneralConfigurationRegis-
ter GCR (02)H on page 61 DCLK, FSC GCI and
FSC V* are output on three external pins of the
Multi-HDLC. DCLK is the clock selected between
Clock A and Clock B. FSC, GCI and FSC V* are
functions of the selected distribution and respect
the GCI and V* frame synchronization specifica-
tions.
III.7.2 - VCXOFrequency Synchronization
An external VCXO can be used to provide a clock
to thetransmission components.This clock is con-
trolled by the main clock distribution (Clock A or
Clock B at 4096kHz). As the clock of the transmis-
sion componentis 15360or 16384kHz,a configur-
able function is necessary.
Thesupervisionof theclockdistributionconsists of
verifying its availability. The detection of the clock
absence is done in a less than 250 microseconds.
In case the clock is absent, an interrupt is gener-
ated with a 4 kHz recurrence. Then the clock
distribution is switched automatically up to detec-
tion of couple A or couple B. When a couple is
detected the change of clock occurs on a falling
edgeof thenew selecteddistribution.Moreoverthe
The VCXO frequency is divided by P (30 or 32) to
provide a common sub-multiple (512kHz) of the
reference frequency CLOCKA or CLOCKB
(4096kHz). The comparison of these two signals
gives an error signal which commands the VCXO.
Two external pinsare needed to performthis func-
tion : VCXO-IN and VCXO-OUT(see Figure 32 on
Page 42).
Figure 31 : MHDLCClock Generation
REF. CLOCK RESET
INT1
Clock Lack
Detection
FRAME A
CLOCK A
from 250 s
µ
FSCV*
CLOCK
Frame
CLOCK SELECTION
At RESET
FRAME A and CLOCK A
are selected
FSCGCI
ADAPTATION
Clock
FRAME B
CLOCK B
DCLK
Select A or B
(SELB)
Clock
Supervision
Deactivation
(CSD)
HCL
SYN1
SYN0
To the internal
MHDLC
A or B
Selected
(BSEL)
GENERAL CONFIGURATION REGISTER (GCR)
41/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 32 : VCXO FrequencySynchronization
VCXO
f = 15360kHz
or 16384kHz
LOW PASS
FILTER
7
/p
/8
VCXO IN
OUX
8
VCXO OUT
iff = 15360kHz, p = 30
iff = 16384kHz, p = 32
Ref =
MHDLC
EVM
4096kHz
III.8 - InterruptController
III.8.1 - Description
This register informs the microprocessor of the
interrupt source. The microprocessor will have in-
formationabout the interruptsource by readingthe
correspondinginterruptqueue (see Paragraph”In-
terrupt Register IR (38)H” on Page 91).
Three external pins are used to managethe inter-
ruptsgenerated by the Multi-HDLC. The interrupts
have three main sources :
- The operatinginterrupts generated by the HDLC
receivers/transmitters, the CI receivers and the
monitor transmitters/receivers. INT0 Pin is re-
served for this use.
On an overflowof the circular interrupt queuesand
an overrun or underrun of the different FIFO, the
INT0 Pin is activatedand the originof the interrupt
is stored in the InterruptRegister.
- The interrupt generatedby an abnormal working of
theclockdistribution.INT1Pinisreservedforthisuse.
- The non-activity of the microprocessor (Watch-
dog). WDO Pin is reserved for this use.
A 16 bits register is associatedwith the Tx Monitor
interrupt. It informs the microprocessor of which
transmitterhas generated the interrupt (see Para-
graph ”Transmit Monitor Interrupt Register TMIR
(30)H” on Page 88).
III.8.2 - Operating Interrupts (INT0 Pin)
Thereare five mainsourcesof operatinginterrupts
in the Multi-HDLC circuit :
- The HDLC receiver,
- The HDLC transmitter,
- The CI receiver,
III.8.3 - Time Base Interrupts (INT1 Pin)
The Time base interrupt is generated when an
absence or an abnormalworking of clock distribu-
tion is detected. The INT1 Pin is activated.
- The Monitor receiver,
- The Monitor transmitter.
III.8.4 - EmergencyInterrupts (WDO Pin)
The WDO signal is activated by an overflow of the
watchdog register.
When an interrupt is generated by one of these
functions, the interrupt controller :
- Collects all the information about the reasons of
this interrupt,
III.8.5 - Interrupt Queues
There are three different interrupt queues :
- Tx and Rx HDLC interrupt queue,
- Rx C/I interrupt queue,
- Stores them in externalmemory,
- Informs the microprocessor by positioning the
INT0 pin in the high level.
Threeinterruptqueuesare builtinexternalmemory
to store the information about the interrupts :
- Asingle queue for the HDLCreceiversand trans-
mitters,
- Rx Monitor interrupt queue.
Their length can be defined by software.
For debuggingfunction,each interrupt word of the
CI interruptqueue and monitorinterrupt queuecan
be followedbya timestampedword.It iscomposed
of a counterwhich runs in the range of 250µs. The
counter is the same as the watchdog counter.
Consequently,thewatchdogfunctionisn’tavailable
at the same time.
- One for the CI receivers,
- One for the monitor receivers.
The microprocessor takes the interrupts into ac-
count by reading the Interrupt Register (IR) of the
interrupt controller.
42/101
STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
Figure 33 : The Three Circular InterruptMemories
IBA
IBA+ 256
IBA + 256
+ HDLC
Queue Size
+ MON
IBA + 256
+ HDLC
Queue Size
INITIALIZATION
BLOCK
HDLC (Tx and Rx)
MON (Rx)
C/I (Rx)
INTERRUPT QUEUE
INTERRUP TQUEUE
INTERRUP TQUEUE
Queue Size
IBA+ 254
III.9 - Watchdog
III.10 - Reset
This function is used to control the activity of the
application. It is composed of a counter which
counts down from an initial value loaded in the
Timer register by the microprocessor.
There are two possibilities to reset the circuit :
- by software,
- by hardware.
Each programmable register receives its default
value. After that, the default value of each data
registeris storedin the associatedmemory except
for Time slot Assigner memory.
If the microprocessor doesn’t reset this counter
before it is totally decremented, the external Pin
WDOis activated; this signal can be used to reset
the microprocessor and all the application.
Theinitial time value of the counteris programma-
ble from 0 to 15s in increments of 0.25ms.
III.11 - Boundary Scan
At the reset of the component,the counteris auto-
matically initialized by the value corresponding to
512ms which are indicated in the Timer register.
The microprocessor must put WDR (IDCR Regis-
ter) to”1” to reset this counter and to confirm that
the application started correctly.
The Multi-HDLC is equipped with an IEEE Stand-
ard TestAccessPort(IEEEStd1149.1).Thebound-
ary scan techniqueinvolves the inclusion of a shift
register stage adjacent to each component pin so
that signals at component boundariescan be con-
trolled and observed using scan testing principle.
Its intention is to enable the test of on board inter-
connectionsand ASIC production tests.
Inthe reversecase, the WDOsignal could be used
to reset the board a secondtime.
The FS signal (8kHz) divided by two or the XTAL1
signal(typically 32768kHz)dividedby 8192can be
selected to increment the counter. At reset the
watchdog is incremented by the XTAL1 signal.
The external interface of the Boundary Scan is
composedof thesignals TDI,TDO, TCK, TMSand
TRST as defined in the IEEE Standard.
43/101
STLC5465B
The values indicated in the tables from pag. 44 to pag. 67 are referred to VDD = 5V if not otherwise
specificated.
IV - DC SPECIFICATIONS
IV.1 - Absolute Maximum Ratings
Symbol
Parameter
Value
-0.5, 6.5
Unit
V
VDD
5V Power Supply Voltage
Input or Output Voltage
Storage Temperature
-0.5, VDD + 0.5
-55, +125
V
Tstg
°C
IV.2 - Power Dissipation
Symbol
Parameter
Power Dissipation
Test Conditions
VDD = 5V
VDD = 3.3V
Min.
Typ.
Max.
Unit
P
300
100
400
130
mW
mW
IV.3 - Recommended DC Operating Conditions
Symbol
Parameter
5V Power Supply Voltage
3.3V Power Supply Voltage
Operating Temperature
Test Conditions
Min.
4.75
3
Typ.
Max.
5.25
3.6
Unit
V
VDD
V
Toper
-40
+85
°C
Note 1 : All the following specifications are valid only within these recommended operating conditions.
IV.4 - TTL Input DC Electrical Characteristics
Symbol
VIL
Parameter
Low Level Input Voltage
High Level Input Voltage
Low Level Input Current
High Level Input
Test Conditions
VDD = 5V; VDD = 3.3V
VDD = 5V; VDD = 3.3V
VI = 0V
Min.
Typ.
Max.
Unit
V
0.8
VIH
2.0
V
IIL
1
A
µ
IIH
VI = VDD
-1
µA
Vhyst
Schmitt Trigger hysteresis
VDD = 5V
VDD = 3.3V
0.4
0.3
0.7
0.5
1
0.8
V
V
VT+
VT-
Positive Trigger Voltage
Negative Trigger Voltage
VDD = 5V
2
2.4
2
V
V
VDD = 3.3V
1.4
VDD = 5V
VDD = 3.3V
0.6
0.6
0.8
0.9
V
V
CIN
COUT
CI/O
Input Capacitance (see Note 2)
Output Capacitance
f = 1MHz @ 0V
2
4
8
4
pF
Bidirextional I/O Capacitance
4
Note 2 : Excluding package
IV.5 - CMOS Output DC Electrical Characteristics
Symbol
VOL
Parameter
Low Level Output Voltage
High Level Output Voltage
Test Conditions
Min.
Typ.
Max.
Unit
V
IOL = X mA (see Note 3)
0.4
VOH
IOH = -X mA (see Note 3) VDD-0.4
V
Note 3 : X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
X = 4 or 8mA.
IV.6 - Protection
Symbol
Parameter
Electrostatic Protection
Test Conditions
Min.
Typ.
Max.
Unit
VESD
C = 100pF, R = 1.5kΩ
2000
V
44/101
STLC5465B
V - CLOCK TIMING
V.1 - Synchronization Signals delivered by the system
For one of three different input synchronizations which is programmed, FSCG and FSCV* signals
delivered by the Multi-HDLC are in accordance with the figure hereafter.
Figure 34 : Clocks received and delivered by the Multi-HDLC
CLOCK B
t1
t2
t5h
4
t5l
CLOCK A
3
5
6
7
0
1
1) Sy Mode
Frame A (or B)
t3
t4
t3
t4
t3
t4 CGI
2) GCI Mode
Frame A (or B)
3) V*Mode
Frame A (or B)
DIN 0/8, ECHO
DOUT 0/7, CB
if FS = F S CG
Bit3
Bit4
Bit5
Bit6
Bit7
Bit0
Bit1
Time Slot 31
Time Slot 0
TDM0/7
de livere d
FSCG
by the circuit
delivered
FSCV*
t6
The four Multiplex Configuration Registers a re at zero (no delay).
by the circuit
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Clock Period if 4096kHz (3072)
Clock Period if 8192kHz (6144)
239 (320)
120 (158)
244 (325)
122 (162)
249 (330)
125 (165)
ns
ns
t2
t3
Delay between Clock A and Clock B
- 60
10
0
+60
ns
ns
ns
Set up time Frame A (or B)/CLOCK A (or B)
Hold time Frame A (or B)/CLOCK A (or B)
t1-10
t4
t4GCI
10
10
t1-10
125000 - (t1 - 10)
t5
t6
Clock ratio t5h/t5l
Duration of FSCG
75
100
488
125
%
ns
45/101
STLC5465B
V - CLOCK TIMING (continued)
V.2 - TDM Synchronization
Figure 35 : SynchronizationSignals received by the Multi-HDLC
CLOCK A (or B)
t1
t2
delivered by
DCLK
the Multi-HDLC
t3
t4
delivered by
FS
the Multi-HDLC
t5
t6
DOUT0/7, CB
Bit 7, Time Slot 31
Bit 0, Time Slot 0
t7
t7
DIN0/8
t9
t8
ECHO
The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes).
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
DCLK Clock Period if 4096kHz (3072)
DCLK Clock Period if 2048kHz (1536)
Id CLOCKA 244 (325)
Id CLOCKA
or B
ns
ns
or B
488 (651)
t2
Delay between CLOCK A or B and DCLK (30pF)
VDD = 5V
5
20
30
32
ns
ns
VDD = 3.3V
t3
t4
t5
t6
Set-up Time FS/DCLK
Hold Time FS/DCLK
Duration FS
20
20
t1-20
ns
ns
ns
ns
244 (325)
125000-244
DCLK to Data 50pF
DCLK to Data 100pF
50
100
t7
t7
t8
t9
Set-up Time Data/DCLK
20
20
ns
ns
ns
ns
Hold Time Data/DCLK
Set-up Echo/DCLK (rising edge)
Hold Time Echo/DCLK (rising edge)
155
205
46/101
STLC5465B
V - CLOCK TIMING (continued)
V.3 - GCI Interface
Figure 36 : GCI Synchro Signal delivered by the Multi-HDLC
125 s
µ
received by
FS
the Multi-HDLC
CH0
CH1
CH7
DIN4/5
DOUT4/5
GCI Channel
B1
B2
MON
D
C/I AE
t1
DCLK delivered by
the Multi-HDLC
t3
t6
t3
delivered by
the Multi-HDLC
FSCG
DOUT0/7, CB
if FSCG is connected to FS
Bit 0, Time Slot 0
t7
t7
DIN0/8
The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes).
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
DCLK Clock Period if 4096kHz (3072)
DCLK Clock Period if 2048kHz (1536)
Id CLOCK A
or B
244 (325)
488 (651)
Id CLOCK A
or B
ns
ns
t3
t5
t6
DCLK to FSCG
Duration FS
20
ns
ns
244
125000-244
DCLK to Data 50pF
DCLK to Data 100pF
50
100
ns
ns
t7
t7
Set-up Time Data/DCLK
Hold Time Data/DCLK
20
20
ns
ns
47/101
STLC5465B
V - CLOCK TIMING (continued)
V.4 - V* Interface
Figure 37 : V* SynchronizationSignal delivered by the Multi-HDLC
125 s
µ
FS received by
the Multi-HDLC
CH0
CH1
CH7
DIN4/5
DOUT4/5
GCI Channel
B1
B2
MON
D
C/I AT
t1
delivered by
DCLK
the Multi-HDLC
t3
t3
delivered by
FSCV*
the Multi-HDLC
DOUT0/7, CB
ifFSCG is connecte d to FS
Bit 3, Time Slot 31
t7
t7
DIN0/8
The four Multiplex Configuration Registe rs are at zero (no delay between FS and Multiplexes).
Symbol
Parameter
Min.
Typ.
Max.
Unit
ns
t1
t3
t5
t6
Clock Period 4096kHz
DCLK to FSCV*
244
20
ns
Duration FSCV*
244
ns
Clock to Data 50pF
Clock to Data 100pF
50
100
ns
nS
t7
t7
Set-up Time Data/DCLK
Hold Time Data/DCLK
20
20
ns
ns
48/101
STLC5465B
V1 - MEMORY TIMING
VI.1 - Dynamic Memories
Figure 38 : Dynamic Memory Read Signals from the Multi-HDLC
NDS from
(or equivalent)
P
µ
T
Total Read Cycle
a
1/f
a
a
a
a
MASTERCLOCK
applied to XTAL1 Pin
a
Tu
HZ
HZ
NRAS0/3
Tv
Tw
Tz
NCAS0/1
NWE
Tv/2
ADM0/10
NOE
Tw + Tz/2
Ts
Th
from
DM0/15
DRAMCircuit
HZ
HZ
Each signal from the MHDLC is high
impedance outside this time if MBL = 0
See
Note :
MBLDefinition
Symbol
Parameter
Min.
Typ.
Max.
Unit
T
a
Delay between Data Strobe from the mP and beginning of cycle
2/f
Delay between Masterclock and Edge of each signal delivered by the
MHDLC (30pF)
V DD = 5V
V DD = 3.3V
20
30
ns
ns
40
2/f
2/f
Tw
Tz
Ts
Th
Delay between NCAS Falling Edge and NCAS rising Edge
Delay between NCAS Rising Edge and end of cycle
Set-up Time Data /NCAS Rising Edge
1/f
1/f
20
0
ns
ns
ns
ns
Hold Time Data/NCAS Rising Edge
49/101
STLC5465B
VI - MEMORY TIMING (continued)
Figure 39 : Dynamic Memory Write Signals from the Multi-HDLC
NDS from µP
(or equivalent)
T
Total Write Cycle
a
1/f
a
a
a
a
MASTERCLOCK
applied to XTAL1 P in
a
Tu
HZ
HZ
NRAS0/3
NCAS0/1
NWE
Tv
Tw
Tz
Tv/2
ADM0/10
Td
DM0/15
NOE
HZ
HZ
Each signal from the MHDLC is high
Note : See
impedance outside this time ifMBL= 0
MBLDefinition
Symbol
f
Parameter
Min.
32
Typ.
Max.
33
Unit
MHz
ns
f : Masterclock Frequency
Tu
Delay between beginning of cycle and NRAS Falling Edge
Delay between NRAS Falling Edge and NCAS Falling Edge
Delay between NCAS Falling Edge and NWE Rising Edge
Delay between NWE Rising Edge and end of cycle
Delay between NRAS Falling Edge and address change
Data Valid after beginning of cycle (30 pF)
1/f
2/f
Tv
1/f
2/f
ns
Tw
Tz
1/f
2/f
ns
1/f
2/f
ns
Tv/2
Td
1/2f
1/f
1/f
ns
1/f
ns
Note : Total Cycle : Tu + Tv + Tw + Tz
50/101
STLC5465B
VI - MEMORY TIMING (continued)
VI.2 - Static Memories
Figure 40 : Static Memory Read Signals from the Multi-HDLC
NDS from µP
(or equivalent)
T
Total Read Cycle
1/f
a
a
MASTERCLOCK
applied to XTAL1 Pin
a
a
HZ
HZ
HZ
ADM0/18
NCE0/7
NWE
Twz
NOE
HZ
Ts Th
from
DM0/15
SRAM Circuit
Each signal delivered by the MHDLC
is high impedance outside this time
See
Note :
MBLDefinition
Symbol
Parameter
Min.
Typ.
Max.
Unit
T
Delay between Data Strobe delivered by the mP and beginning of
cycle
2/f
1/f
a
f: Masterclock frequency
Total read cycle: Twz + 1/f
Delay between Masterclock and Edge of each signal delivered by the
MHDLC (30pF)
V DD = 5V
V DD = 3.3V
20
30
ns
ns
40
4/f
Twz
Ts
NOE width
1/f
20
0
ns
ns
ns
Set-up Time Data /NOE Rising Edge
Hold Time Data /NOE Rising Edge
Th
51/101
STLC5465B
VI - MEMORY TIMING (continued)
Figure 41 : Static Memory Write Signals from the Multi-HDLC
NDS from µP
(or equivalent)
T
Total Write Cycle
1/f
a
a
a
MASTERCLOCK
applied to XTAL1 Pin
a
a
ADM0/18
NCE0/7
HZ
HZ
Tuv
NWE
NOE
DM0/15
HZ
HZ
Each signal delivered by the MHDLC
is high impedance outside this time
Note : See
MBL Definition
Symbol
Parameter
Min.
Typ.
Max.
Unit
T
Delay between Data Strobe delivered by the µP and beginning of
cycle
2/f
1/f
a
f : Masterclock frequency
Delay between Masterclock and Edge of each signal delivered by the
MHDLC (30pF)
V DD = 5V
V DD = 3.3V
20
40
ns
ns
30
Tuv
NCE width
1/f
4/f
ns
Note : TotalWrite Cycle : Tuv + 1/f
52/101
STLC5465B
VII - MICROPROCESSOR TIMING
VII.1 - ST9 Family MOD0=1, MOD1=0, MOD2=0
Figure 42 : ST9 Read Cycle
NCS0/1
t1
t2
t3
READY
t4
NAS/ALE
NDS/NRD
t12
t11
t7
t8
t5
t6
D0/7
t10
A0/7
AD0/7
t9
R/W / NWR
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
Delay when immediate access
0
ns
ns
98
t2
t3
Hold Time Chip Select /Data Strobe
14
0
ns
Delay Ready / NAS (if t1 > t3), (30pF)
Delay when immediate access
ns
ns
98
t4
t5
Width NAS
20
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
Set-up Time Address / NAS
Hold Time Address / NAS
Data Valid after Ready
t6
9
t7
0
15
15
t8
Data Valid after Data Strobe (30pF)
Set-up Time R/W /NAS
Hold Time R/W / Data Strobe
Width NDS when immediate access
Delay NDS / NCS
0
t9
15
15
50
5
t10
t11
t12
53/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
Figure 43 : ST9 Write Cycle
NCS0/1
t1
t2
t3
READY
t4
NAS/ALE
NDS/NRD
t12
t11
t7
t8
t5
t6
A0/7
AD0/7
D0/7
t9
t10
R/W / NWR
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
Delay when immediate access
0
ns
NS
98
t2
t3
Hold Time Chip Select / Data Strobe
14
0
ns
Delay Ready / NAS (if t1 > t3), (30pF)
Delay when immediate access
ns
NS
98
t4
t5
Width NAS
20
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
Set-up Time Address / NAS
Hold Time Address / NAS
Set-up Time Data / Data Strobe
Hold Time Data / Data Strobe
Set-up Time R/W / NAS
Hold Time R/W / Data Strobe
Width NDS when immediate access
Delay NDS / NCS
t6
9
t7
-15
15
15
15
50
5
t8
t9
t10
t11
t12
54/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
VII.2 - ST10/C16xmult. A/D, MOD0 = 1, MOD1= 0, MOD2 = 1
Figure 44 : ST10 (C16x) Read Cycle; Multiplexed A/D
NCS0/1
t2
NDSACK 0
DTAC K
/
/
t1
NREADY
t3
t4
NAS
/
ALE
t12
NDS/
NRD
t7
t8
D0/15
R/W /
NWR
t10
t9
/ AD0/15
A0/15
A16/23 NBHE
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Not Ready/NRD (if NCS0/1 = 0), (30pF)
Delay when immediate access
0
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t2
t3
Hold Time Chip Select / NRD
10
0
ns
Delay Not Ready / NRD rising edge
Delay when immediate access
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t4
t5
t6
Width ALE
20
5
ns
ns
Set-up Time Address / ALE
Hold Time Address /ALE
V DD = 5V
V DD = 3.3V
5
10
ns
ns
t7
t8
Data valid after ready
0
0
15
ns
ns
ns
ns
ns
Data bus at high impedance after NRD (30pF)
Set-up Time NBHE, Address A 16/23/ALE
Hold Time NBHE / NRD
15
t9
5
t10
t12
10
0
Delay NRD / NCS
55/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
Figure 45 : ST10 (C16x) Write Cycle; Multiplexed A/D
NCS0/1
t2
NDSACK0/
NDTAC K /
NREADY
t1
t3
t4
NAS
/
ALE
t12
ND S/
NRD
t5
t9
t6
t8
A0/15
D0/15
AD0/15
t7
R/W /
NWR
t10
NBHE
A16/23
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Not Ready/ALE (if NCS0/1 = 0), (30pF)
Delay when immediate access
0
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t2
t3
Hold Time Chip Select / NWR
10
0
ns
Delay Not Ready / NRD rising edge
Delay when immediate access
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t4
t5
t6
Width ALE
20
5
ns
ns
Set-up Time Address / ALE
Hold Time Address /ALE
V DD = 5V
V DD = 3.3V
5
10
ns
ns
t7
t8
Set up time Data/NWR
-15
0
ns
ns
ns
ns
ns
Set up time NBHE-Address A 16/23/ALE
Set-up Time NBHE, Address A 16/23/ALE
Hold Time NBHE / NWR
t9
5
t10
t12
10
0
Delay NWR / NCS
56/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
VII.3 - ST10/C16xdemult. A/D, MOD0 = 0, MOD1 = 1, MOD0 = 1
Figure 46 : ST10 (C16x) Read Cycle; Demultiplexed A/D
NCS0/1
t2
NDSACK 0
DTAC K
/
/
t1
NREADY
t3
t4
NAS
/
ALE
t12
NDS/
NRD
t7
t8
D0/15
R/W /
NWR
t10
t9
/ AD0/15
A0/15
A16/23 NBHE
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Not Ready/NRD (if NCS0/1 = 0), (30pF)
Delay when immediate access
0
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t2
t3
Hold Time Chip Select / NRD
10
0
ns
Delay Not Ready / NRD rising edge
Delay when immediate access
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t4
t7
Width ALE
20
0
ns
ns
ns
ns
ns
ns
Data valid after NOTREADY falling efge (30pF)
Data bus at high impedance after NRD (30pF)
Set-up Time NBHE, Address AD0/15, A16/ALE
15
15
t8
0
t9
5
t10
t12
Hold Time NBHE / Address ADO/15, A16/23/NRD
Delay NRD / NCS
10
0
57/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
Figure 47 : ST10 (C16x) Write Cycle; Demultiplexed A/D
NCS0/1
t2
NDSACK0/
DTACK /
t1
NREADY
t3
t4
NAS
/
ALE
t12
NDS/
NRD
t8
D0/15
t7
R/W /
NWR
t10
t9
AD0/15
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Not Ready/NWR (if NCS0/1 = 0), (30pF)
Delay when immediate access
0
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t2
t3
Hold Time Chip Select / NRD
10
0
ns
Delay Not Ready / NWR rising edge
Delay when immediate access
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t4
t7
Width ALE
20
-15
15
5
ns
ns
ns
ns
ns
ns
Set up time Data/NWR
Hold time Data/NWR
t8
t9
Set-up Time NBHE, Address AD0/15, A16/23/ALE
Hold Time NBHE, Address AD0/15, A16/23 NWR
Delay NWR / NCS
t10
t12
10
0
58/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
VII.4 - 80C188 MOD0=1, MOD1=1, MOD2=0
Figure 48 : 80C188 Read Cycle
NCS0/1
t1
t2
READY
t3
t4
NAS/ALE
NDS/NRD
t12
t7
t8
t5
t6
A0/7
D0/7
AD0/7
R/W / NWR
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
Delay when immediate access
0
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t2
t3
Hold Time Chip Select / NRD
10
0
ns
Delay Ready / ALE (if t1 > t3), (30pF)
Delay when immediate access
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t4
t5
t6
Width ALE
20
5
ns
ns
Set-up Time Address / ALE
Hold Time Address / ALE
V DD = 5V
V DD = 3.3V
5
10
ns
ns
t7
t8
Data Valid after Ready
Data Valid after NRD (30pF)
Delay NDS / NCS
0
0
0
15
ns
ns
ns
t12
59/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
Figure 49 : 80C188 Write Cycle
NCS0/1
t1
t2
READY
t3
t4
NAS/ALE
NDS/NRD
t12
t8
t5
t6
A0/7
AD0/7
D0/7
t7
R/W / NWR
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
Delay when immediate access
0
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t2
t3
Hold Time Chip Select / NWR
10
0
ns
Delay Ready / ALE (if t1 > t3), (30pF)
Delay when immediate access
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t4
t5
t6
Width ALE
20
5
ns
ns
Set-up Time Address / ALE
Hold Time Address / ALE
V DD = 5V
V DD = 3.3V
5
10
ns
ns
t7
t8
Set-up Time Data / NWR
Hold Time Data / NWR
Delay NWR / NCS
-15
15
0
ns
ns
ns
t12
60/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
VII.5 - 80C186 MOD0=1, MOD1=1, MOD2=1
Figure 50 : 80C186 Read Cycle
NCS0/1
t1
t2
READY
t3
t4
NAS/ALE
NDS/NRD
t12
t7
t8
t5
t6
A0/15
D0/15
AD0/15
R/W / NWR
t9
t10
t11
NBHE
A16/19
NBHE A16/19
NBHE
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
Delay when immediate access
0
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t2
t3
Hold Time Chip Select / NRD
10
0
ns
Delay Ready / ALE (if t1 > t3), (30pF)
Delay when immediate access
VDD = 5V
V DD = 3.3V
98
108
ns
ns
t4
t5
t6
Width ALE
20
5
ns
ns
Set-up Time Address / ALE
Hold Time Address / ALE
VDD = 5V
VDD = 3.3V
5
10
ns
ns
t7
t8
Data Valid after Ready
0
0
15
15
ns
ns
ns
ns
ns
ns
Data Valid after NRD (30pF)
Set-up Time NBHE-Address A16/19 / ALE
Hold Time Address A1619 / NRD
Hold Time NBHE- / NRD
t9
5
t10
t11
t12
10
10
0
Delay NRD / NCS
61/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
Figure 51 : 80C186 Write Cycle
NCS0/1
t1
t2
READY
t3
t4
NAS/ALE
NDS/NRD
t12
t8
t5
t6
A0/15
AD0/15
D0/15
t7
R/W / NWR
t9
t10
t11
NBHE
A16/19
NBHE A16/19
NBHE
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
Delay when immediate access
0
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t2
t3
Hold Time Chip Select / NWR
10
0
ns
Delay Ready / ALE (if t1 > t3), (30pF)
Delay when immediate access
ns
ns
ns
VDD = 5V
V DD = 3.3V
98
108
t4
t5
t6
Width ALE
20
5
ns
ns
Set-up Time Address / ALE
Hold Time Address / ALE
V DD = 5V
V DD = 3.3V
5
10
ns
ns
t7
t8
Set-up Time Data / NWR
-15
15
5
ns
ns
ns
ns
ns
ns
Hold Time Data / NWR
t9
Set-up Time NBHE-Address A16/19 / ALE
Hold Time Address 16/19 / ALE
Hold Time NBHE- / NWR
Delay NWR / NCS
t10
t11
t12
10
10
0
62/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
VII.6 - 68000 MOD0=0, MOD1=0, MOD2=1
Figure 52 : 68000 Read Cycle
NCS0/1
t1
t2
t4
t3
NDTACK
NAS/ALE
SIZE0/NLDS
SIZE1/NUDS
t6
t8
t5
A1/23
R/W / NWR
A1/23
t7
D0/15
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay NDTACK / NCS0/1 (if t3 > t1), (30pF)
Delay when immediate access
V DD = 5V
V DD = 3.3V
0
0
98
108
ns
ns
t2
t3
Hold Time Chip Select / NLDS-NUDS
0
ns
Delay NDTACK / NLDS-NUDS Falling Edge (if t1> t3), (30pF)
Delay when immediate access
VDD = 5V
VDD = 3.3V
0
0
98
108
ns
ns
t4
Delay NDTACK / NLDS-NUDS Rising Edge
VDD = 5V
VDD = 3.3V
0
0
20
30
ns
ns
t5
t6
t7
t8
Set-up Time Address and R/W / last NLDS-NUDS or NCS
Hold Time Address and R/W / NLDS-NUDS
0
0
0
0
ns
ns
ns
ns
Data Valid after NDTACK Falling Edge (30pF)
15
15
Data High Impedance after NLDS-NUDS Rising Edge (30pF)
63/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
Figure 53 : 68000 Write Cycle
NCS0/1
t1
t2
t4
t3
NDTACK
NAS/ALE
SIZE0/NLDS
SIZE1/NUDS
t6
t5
A1/23
R/W / NWR
A1/23
t9
t10
D0/15
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay NDTACK / NCS0/1 (if t3 > t1), (30pF)
Delay when immediate access
V DD = 5V
V DD = 3.3V
0
0
98
108
ns
ns
t2
t3
Hold Time Chip Select / NLDS-NUDS
0
ns
Delay NDTACK / NLDS-NUDS Falling Edge (if t1> t3), (30pF)
Delay when immediate access
V DD = 5V
V DD = 3.3V
0
0
98
108
ns
ns
t4
Delay NDTACK / NLDS-NUDS Rising Edge
V DD = 5V
V DD = 3.3V
20
30
ns
ns
t5
t6
Set-up Time Address and R/W / last NLDS-NUDS or NCS
Hold Time Address / NLDS-NUDS
0
0
ns
ns
ns
ns
t9
Set-up Time Data / NLDS-NUDS
15
7
t10
Hold Time Data / NLDS-NUDS
64/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
VII.7 - 68020 MOD0=0, MOD1=0, MOD2=0
Figure 54 : 68020 Read Cycle
NCS0/1
t2
t1
NDSACK0/
NDTACK
NDSACK1/
t4
t3
READY
NAS/
ALE
NDS /NRD
SIZE0/
NLDS
SIZE1/ NUDS
t6
t5
A 0/23
R/W /
NWR
t7
t8
D0/15
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay NDTACK / NCS0/1 (if t3 > t1), (30pF)
Delay when immediate access
V DD = 5V
V DD = 3.3V
0
0
98
108
ns
ns
t2
t3
Hold Time Chip Select / NDS rising edge
0
ns
Delay NDSACK1 / NDS Falling Edge (if t1> t3), (30pF)
Delay when immediate access
V DD = 5V
V DD = 3.3V
0
0
98
108
ns
ns
t4
Delay NDSACK1 / NDS Rising Edge
V DD = 5V
V DD = 3.3V
20
30
ns
ns
t5
t6
t7
t8
Set-up Time Address and R/W/last NDS or NCS
Hold Time Address / NDS
0
0
0
0
ns
ns
ns
ns
Data valid before NDSACK1 falling edge (30pF)
Data High Impedance after NDS (30pF)
15
15
65/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
Figure 55 : 68020 Write Cycle
NCS0/1
t2
t1
NDSACK0/
NDTACK
t4
NDSACK1/
t3
READY
NAS/
ALE
NDS /NRD
SIZE0/
NLDS
SIZE1/ NUDS
t6
t5
A 0/23
R/W /NWR
t9
t10
D0/15
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Delay NDTACK / NCS0/1 (if t3 > t1), (30pF)
Delay when immediate access
V DD = 5V
V DD = 3.3V
0
0
98
108
ns
ns
t2
t3
Hold Time Chip Select / NDS rising edge
0
ns
Delay NDSACK1 / NDS Falling Edge (if t1> t3), (30pF)
Delay when immediate access
V DD = 5V
V DD = 3.3V
0
0
98
108
ns
ns
t4
Delay NDSACK 1/ NDS Rising Edge
V DD = 5V
V DD = 3.3V
20
30
ns
ns
t5
t6
Set-up Time Address and R/W/last NDS or NCS
Hold Time Address / NDS
0
0
0
7
ns
ns
ns
ns
t9
Set-up Time Data / NDS
t10
Hold Time Data / NDS
66/101
STLC5465B
VII - MICROPROCESSOR TIMING (continued)
VII.8 - Token Ring Timing
Figure 56 : Token Ring
1/f
MASTER CLOCK
(applied to XTAL1 Pin)
a
a
TRO
TRI
tS
tH
Symbol
Parameter
Min.
Typ.
Max.
Unit
f
f : Masterclock frequency
32.768
MHz
a
Delay between Masterclock Rising Edge and Edges of TRO Pulse
delivered by the MHDLC (10pF)
VDD = 5V
25
30
ns
ns
V DD = 3.3V
tS
Set-up Time TRI/Masterclock Masterclock Falling Edge
Hold Time TRI/Masterclock Falling Edge
5
5
ns
ns
tH
0
VII.9 - Master Clock Timing
Figure 57 : Master Clock
1/f
tH
MASTER CLOCK
(applied to XTAL1 Pin)
tL
Symbol
Parameter
Min.
30
Typ.
32.768
30.5
Max.
33
Unit
MHz
ns
f
Masterclock Frequency
Masterclock Period
Masterclock High
1/f
tH
tL
30.3
12
33.3
ns
Masterclock Low
12
ns
Crystal parameters:
a) frequency
To reduce the drive level, the Crystal parameters
can be:
f (typically 32768.00 kHz)
fundamental
parallel
a) frequency
b) Mode
f (typically 32768.00kHz)
fundamental
parallel
b) Mode
c) Resonance
d) Load Capacity
c) Resonance
d) Load Capacity
Cl= 30pF
Cl = 20pF
in accordance with 2 capacitors (47 pF each of
them) the first capacitor is soldered nearest pin 2
(XTAL1) and nearest the ground, the second ca-
pacitor is soldered nearest pin 3 (XTAL2) and
nearestthe ground.
in accordance with 2 capacitors (33 pF each of
them)
e) Serialresistor
40 Ohms max
N.B It is not necessary to add an external bias
resistor between XTAL1 pin and XTAL2 pin. This
resistor is inside the circuit.
e) Serial resistor
40 Ohms max
67/101
STLC5465B
VIII - INTERNAL REGISTERS
‘Not used’ bits (Nu) are accessible by the microprocessor but the use of these bits by software is not
recommended.
‘Reserved’ bits are not implemented in the circuit. However, it is not recommendedto use this address.
VIII.1 - Identification and Dynamic Command Register - IDCR (00)H
bit15
C15
bit8
C8
bit7
C7
bit 0
C0
C14 C13 C12 C11 C10
C9
C6
C5
C4
C3
C2
C1
When this register is read by the microprocessor, the circuit code C0/15 is returned. Reset has no effect
on this register.
C0/3 indicates the version.
C4/7 indicates the revision.
C8/11 indicates the foundry.
C12/15 indicates the type.
Example : this code is (0010)Hfor the first sample.
When this register is written by the microprocessor then :
bit15
Nu
bit8
Nu
bit7
Nu
bit 0
TL
Nu
Nu
Nu
Nu
Nu
Nu
Nu
Nu
Nu
Nu
RSS WDR
TL
: TOKEN LAUNCH
When TLis set to1 by the microprocessor,the token pulse is launchedfrom the TRO pin (Token
Ring Output pin). This pulse is provided to the TRI pin (Token Ring Input pin) of the next circuit
in the applicationswhere several Multi-HDLCs are connectedto the same shared memory.
WDR : WATCHDOG RESET.
When the bit 1 (WDR)of this registeris set to 1 by the microprocessor, the watchdog counter is
reset.
RSS : RESET SOFTWARE
When the bit 2 (RSS)of this registeris set to 1 by the microprocessor, the circuit is reset (Same
action as reset pin).
After writing this register, the values of these three bits return to the default value.
VIII.2 - General Configuration - GCR (02)H
bit15
bit8
bit7
bit 0
SBV MBL AFAB SCL BSEL SELB CSD HCL SYN1 SYN0 D7 EVM TSV TRD PMA WDD
After reset (0000)H
WDD : Watch Dog Disable
WDD = 1, the Watch Dog is masked : WDO pin stays at ”0”.
WDD = 0, the Watch Dog generatesan ”1” on WDO pin if the microprocessorhas not reset the
Watch Dog during the durationprogrammed in Timer Register.
PMA : Priority Memory Access
PMA = 1, if the token ring has been launched it is captured and kept in order to authorize
memory accesses.
PMA= 0, memoryis accessibleonly if the token is present; after one memory access the token
is re-launched from TRO pin of the current circuit to TRI pin of the next circuit.
TRD : Token Ring Disable
TRD = 1, if the token has been launched, the token ring is stopped and destroyed ; memory
accesses are not possible. The token will not appearon TRO pin.
TRD= 0, the tokenring isauthorized; whenthetokenwill be launched,it will appearon TRO pin.
68/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
TSV : Time Stamping Validated
TSV= 1, the time stampingcounterbecomesa freebinarycounterand countsdown from 65535
to 0 in step of 250ms (Total = 16384ms).So if an event occurswhen the counterindicates Aand
if the next event occurs when the counterindicates B then : t = (A-B)x 250ms is the time which
haspassedbetweenthetwoeventswhichhavebeenstoredinmemorybytheInterruptController
(for Rx C/I and Rx MON CHANNEL only).
TSV = 0, the counter becomes a decimal counter.The Timer Register and this decimal counter
constitute a Watch Dog or a Timer.
EVM : EXTERNAL VCXO MODE
EVM=1,VCXO SynchronizationCounter is divided by 32.
EVM=0,VCXO SynchronizationCounter is divided by 30.
D7
: HDLC connected to MATRIX
D7 = 1, the transmit HDLC is connected to matrix input 7, the DIN7 signal is ignored.
D7 = 0, the DIN7 signal is taken into account by the matrix, the transmitHDLC is ignoredby the
matrix.
SYN0/1: SYNCHRONIZATION
SYN0/1 : these two bits define the signal applied on FRAMEA/B inputs. For more details, see
”Synchronizationsignals delivered by the system. V.1.
SYN1 SYN0
Signal applied on FRAMEA/B inputs
0
0
1
1
0
1
0
1
SYIinterface
GCI Interface (the signal defines the first bit of the frame)
Vstar Interface (the signal defines thrid bit of the frame)
Not used
HCL : HIGH BIT CLOCK
This bit defines the signal applied on CLOCKA/Binputs.
HCL = 1, bit clock signal is at 8192kHz
HCL= 0, bit clock signal is at 4096kHz
CSD : Clock Supervision Deactivation
CSD = 1, the lack of selectedclock is not seen by the microprocessor; INT1 is masked.
CSD = 0, when the selected clock disappears the INT1 pin goes to 5V, 250ms after this
disappearance.
SELB : SELECT B
SELB = 1, FRAME B and CLOCK B must be selected.
SELB = 0, FRAME A and CLOCKA must be selected.
BSEL : B SELECTED (this bit is read only)
BSEL = 1, FRAME B and CLOCK B are selected.
BSEL = 0, FRAME Aand CLOCK Aare selected.
SCL
: Single Clock
This bit defines the signal delivered by DCLK output pin.
SCL = 1, Data Clock is at 2048kHz.
SCL = 0, Data Clock is at 4096kHz.
AFAB : AdvancedFrame A/B Signal
AFAB = 1, the advanceof Frame A Signal and Frame B Signal is 0.5 bit time versus the signal
frameA (or B) drawn in Figure 34.
AFAB = 0, Frame A Signal and Frame B Signal are in accordancewith the clock timing
(see : Synchronizationsignals delivered by the Figure 45).
69/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
MBL : Memory Bus Low impedance
MBL = 1, the shared memory bus is at low impedance between two memory cycles.
The memory bus includes Controlbits, Data bits, Addressbits. One Multi-HDLC is connectedto
the shared memory.
MBL = 0, the shared memory bus is at high impedance between two memory cycles.
Several Muti-HDLCs can be connected to the shared memory. One pull up resistor is
recommendedon each wire.
SBV : Six Bit Validation (A, E, S1/S4 bits). Global validation for 16 channels (Upstream and
downstream).
SBV = 1, in reception, the six bit word (A, E, S1/S4) located in the same timeslot as D channel
can be receivedfrom any input timeslot;when thiswordis receivedidenticaltwiceconsecutively,
it is stored in the external shared memory and an interrupt is generated if not masked (like the
reception of primitive from C/I channel). See “RECEIVE Command/Indicate INTERRUPT” on
page 97.
Sixteen independent detectionsare performed if the contents of any input timeslot is switched
in the timeslot 4n+3 of two GCI multiplexes (corresponding to DOUT4 and DOUT5) with (0 £ n
£ 7). Only the contents of D channel will be transmitted from input timeslot to GCI multiplexes.
From ISDN channels to GCI channels on page 34.
Intransmission a sixbit word(A,E, S1/S4)canbe transmittedcontinuouslytoany outputtimeslot
via the TCIR. See “Transmit Command/Indicate Register TCIR (2A)H” on page 76. This word
(A, E, S1/S4)is set instead of primitive (C1, C2, C3, C4) and A, E bitsreceived from the timeslot
4n+3 of two GCI multiplexes and the new contents of this timeslot 4n+3 must be switched on
the selected output timeslot.
SBV=0, the 16 six bit detectionsare not validated.
VIII.3 - Input Multiplex Configuration Register 0 - IMCR0 (04)H
bit15
bit8
bit7
bit 0
LP3 DEL3 ST(3)1 ST(3)0 LP2 DEL2 ST(2)1 ST(2)0 LP1 DEL1 ST(1)1 ST(1)0 LP0 DEL0 ST(0)1 ST(0)0
After reset (0000)H
See definition in next Paragraph.
VIII.4 - Input Multiplex Configuration Register 1 - IMCR1 (06)H
bit15
bit8
bit7
bit 0
LP7 DEL7 ST(7)1 ST(7)0 LP6 DEL6 ST(6)1 ST(6)0 LP5 DEL5 ST(5)1 ST(5)0 LP4 DEL4 ST(4)1 ST(4)0
After reset (0000)H
ST(i)0 : STEP0 for each Input Multiplex i(0 ≤ i ≤ 7), delayed or not.
ST(i)1 : STEP1 for each Input Multiplex i(0 ≤ i ≤ 7), delayed or not.
DEL(i); : DELAYED Multiplex i(0 ≤ i ≤ 7).
DEL (i) ST (i) 1 ST (i) 0
STEP for each Input Multiplex 0/7 delayed or not
X
0
0
Each received bit is sampled at 3/4 bit-time without delay.
First bit of the frame is defined by Frame synchronization Signal.
1
1
1
0
0
0
0
1
1
0
1
1
1
0
1
1
0
1
Each received bit is sampled with 1/2 bit-time delay.
Each received bit is sampled with 1 bit-time delay.
Each received bit is sampled with 2 bit-time delay.
Each received bit is sampled with 1/2 bit-time advance.
Each received bit is sampled with 1 bit-time advance
Each received bit is sampled with 2 bit-time advance.
When IMTD = 0 (bit of SMCR),DEL = 1 is not taken into account by the circuit.
1/2 bit time 244ns if TDM at 2048 kHz,
1/2 bit time 122ns if TDM at 4096 kHz.
70/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
LP (i) : LOOPBACK0/7
LPi= 1,Output Multiplex i is put insteadof InputMultiplexi (0 ≤ i ≤ 7). LOOPBACKis transparent
or not in accordancewith OMVi (bit of Output Multiplex Configuration Register).
LPi = 0, Normal case, Input Multiplex i(0 ≤ i ≤ 7) is taken into account.
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.5 - Output Multiplex Configuration Register 0 - OMCR0 (08)H
bit15
bit8
bit7
bit 0
OMV3 DEL3 ST(3)1 ST(3)0 OMV2 DEL2 ST(2)1 ST(2)0 OMV1 DEL1 ST(1)1 ST(1)0 OMV0 DEL0 ST(0)1 ST(0)0
After reset (0000)H
See definition in next Paragraph.
VIII.6 - Output Multiplex Configuration Register 1 - OMCR1 (0A)H
bit15
bit8
bit7
bit 0
OMV7 DEL7 ST(7)1 ST(7)0 OMV6 DEL6 ST(6)1 ST(6)0 OMV5 DEL5 ST(5)1 ST(5)0 OMV4 DEL4 ST(4)1 ST(4)0
After reset (0000)H
ST(i)0 : STEP0 for each Output Multiplex i(0 ≤ i ≤ 7), delayed or not.
ST(i)1 : STEP1 for each Output Multiplex i(0 ≤ i ≤ 7), delayed or not.
≤ ≤
i 7).
DEL(i); : DELAYED Multiplex i(0
DEL (i) ST (i) 1 ST (i) 0
STEP for each Output Multiplex 0/7 delayed or not
X
0
0
Each bit is transmitted on the rising edge of the double clock without delay.
Bit 0 is defined by Frame synchronization Signal.
1
1
1
0
0
0
0
1
1
0
1
1
1
0
1
1
0
1
Each bit is transmitted with 1/2 bit-time delay.
Each bit is transmitted with 1 bit-time delay.
Each bit is transmitted with 2 bit-time delay.
Each bit is transmitted with 1/2 bit-time advance.
Each bit is transmitted with 1 bit-time advance
Each bit is transmitted with 2 bit-time advance.
When IMTD = 0 (bit of SMCR),DEL = 0 is not taken into account by the circuit.
1/2 bit time 244ns if TDM at 2048 kHz,
1/2 bit time 122ns if TDM at 4096 kHz.
OMV (i): Output Multiplex Validated 0/7
OMVi =1, condition to have DOUTi pin active (0
≤ ≤
i
7).
OMVi =0, DOUTi pin is High Impedance continuously(0 ≤ i ≤ 7).
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.7 - Switching Matrix Configuration Register - SMCR (0C)H
bit15
bit8
bit7
bit 0
SW1 SW0
M1
M0 DR64 DR44 DR24 DR04 AISD ME SGC SAV SGV TS1 TS0 IMTD
After reset (0000)H
IMTD : Increased Minimum Throughput Delay
When SI = 0 (bit of CMDR, variable delay mode) :
IMTD=1,theminimumdelaythroughthe matrixmemoryis threetimeslotswhateverthe selected
TDM output.
IMTD= 0, the minimumdelaythrough the matrixmemoryis twotime slotswhatevertheselected
TDM output.
When IMTD = 0, the input TDMs cannot be delayed versus the frame synchronization (Use
of IMCR is limited) and the output TDMs cannot be advanced versus the frame
synchronization.(Useof OMCR is limited).
71/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
TS0
: Tristate 0
TS0 = 1, the DOUT0/3 and DOUT6/7 pins are tristate : ”0” is at low impedance, ”1” is at low
impedance and the third state is high impedance.
TS0= 0, the DOUT0/3 and DOUT6/7 pins are open drain : ”0” is at low impedance, ”1” is at high
impedance.
TS1
: Tristate 1
TS1 = 1, the DOUT4/5 pins are tristate : ”0” is at low impedance, ”1” is at low impedance and
the third state is high impedance.
TS1 = 0, the DOUT4/5 pins are open drain : ”0” is at low impedance, ”1” is at high impedance.
SGV : Pseudo Random Sequence Generator Validated
SGV = 1,PRS Generatoris validated.ThePseudo Random Sequenceis transmitted during the
related time slot(s).
SGV = 0, PRS Generator is reset.”0” are transmittedduring the related time slot.
SAV
: Pseudo Random Sequence analyzer Validated
SAV = 1, PRS analyzer is validated.
SAV = 0, PRS analyzer is reset.
SGC : Pseudo Random Sequence Generator Corrupted
When SGC bit goes from 0 to 1, one bit of sequencetransmitted is corrupted.
When the corrupted bit has been transmitted, SGC bit goes from 1 to 0 automatically.
ME
: MESSAGE ENABLE
ME = 1 The contents of ConnectionMemory is output on DOUT0/7 continuously.
ME = 0 The contents of ConnectionMemory acts as an address for the Data Memory.
AISD : Alarm Indication Signal Detection.
AISD = 1, the Alarm IndicationSignal detection is validated.
Sixteen independentdetections are performed for sixteen hyperchannels.The contents of any
input hyperchannel (B1, B2, D) switched (in transparent mode or not) on GCI channels is
analysedindependently.
For each GCI channel, the 16bits of B1 and B2 are checked together; when all “one” has been
detected during 30 milliseconds, a status is stored in the Command/ Indicate interrupt queue
and an interruptis generatedif not masked(like thereceptionof primitive from GCI multiplexes).
See “RECEIVE Command/IndicateINTERRUPT” on page 97.
AISD=0, the Alarm Indication Signal detectionfor 16 hyperchannelsis not validated.
DR04 : Data Rate of TDM0 is at 4Mb/s. Case:M1=M0=0
DR04= 1, the signal received from DIN0 pin and the signal delivered by Dout0 pin are at 4Mb/s.
DIN1 pin and DOUT1 pin are ignored.
The Time Division Multiplex 0 is constituted by 64 timeslots numbered from 0 to 63.
DR04 = 0, the signals receivedfrom DIN0/1 pins and the signals delivered by Dout0/1 pins are
at 2Mb/s.
DR24 : Data Rate of TDM2 is at 4Mb/s.Case:M1=M0=0
R24 = 1, the signal received from DIN2 pin and the signal delivered by Dout2 pin are at 4Mb/s.
DIN3 pin and DOUT3 pin are ignored.
The Time Division Multiplex 2 is constituted by 64 timeslots numbered from 0 to 63.
DR24 = 0, the signals receivedfrom DIN2/3 pins and the signals delivered by Dout2/3 pins are
at 2Mb/s.
DR44 : Data Rate of TDM4 is at 4Mb/s.Case:M1=M0=0
DR44= 1, the signal received from DIN4 pin and the signal delivered by Dout4 pin are at 4Mb/s.
DIN5 pin and DOUT5 pin are ignored.
TDM4/5 cannot be GCI multiplexes.
The Time Division Multiplex 4 is constituted by 64 timeslots numbered from 0 to 63.
DR44 = 0, the signals receivedfrom DIN4/5 pins and the signals delivered by Dout4/5 pins are
at 2Mb/s.
72/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
DR64 : Data Rate of TDM6 is at 4Mb/s.Case:M1=M0=0
DR64= 1, the signal received from DIN6 pin and the signal delivered by Dout6 pin are at 4Mb/s.
DIN7 pin and DOUT7 pin are ignored.
The Switching Matrix cannot be used to switch the channels to/from the HDLC controllers but
theRX HDLCcontrollercanbe connectedtoDIN8and the TXHDLCcontrollercan be connected
to CB pin.
The Time Division Multiplex 6 is constituted by 64 timeslots numbered from 0 to 63.
DR64 = 0, the signals receivedfrom DIN6/7 pins and the signals delivered by Dout6/7 pins are
at 2M b/s.
M1/0 : Data Rate of TDM0/8;
thesetwobitsindicatethe datarateof heightTimeDivisionMultiplexesTDM0/7 relativetoDIN0/7
and DOUT0/7. The table below shows the different data rates with the clock frequency defined
by HCL bit (General ConfigurationRegister).
M1
M0
Data Rate of TDM0/7 in Kbit/s
CLOCKA/B signal frequency
HCL = 0
4096KHz
3072KHz
HCL = 1
8192KHz
6144KHz
0
0
1
1
0
1
0
1
2048 (or 4096 in accordance with DR0x4)
1536 (or 3072 in accordance with DR0x4)
Reserved
Reserved
SW
: Switching at 32 Kbit/s for the TDM0 (DIN0/DOUT0)
SW0=1
DIN0 can receive 64 channelsat 32 Kbit/s if Data Rate of TDM0is at 2048 Kbit/s.
DOUT0 can deliver 64 channels at 32 Kbit/s.
DIN2/DOUT2 are not available.
DIN2 is used to receive internally TDM0 (DIN0) 4 bit-times shifted
DOUT2 is used to multiplex internally TDM2 and TDM4. Downstream switching at 32 kb/s on
page 22.
SW1 : SW1: Switching at 32 Kbit/s for the TDM1 (DIN1/DOUT1)
SW1=1
DIN1 can receive 64 channels at 32 Kbit/s if Data Rate of TDM1is at 2048 Kbit/s.DOUT0 can
deliver 64 channels at 32 Kbit/s.
DIN3/DOUT3 are not available.
DIN3 is used to receive internally TDM1(DIN1) and to shift it (4 bit-times)DOUT3 is used to
multiplex internally TDM3 and TDM5. Downstreamswitching at 32 kb/s on page22.
SW1=0
DIN0 receive 32 (or 24) channels at 64 Kbit/s or 64 (or 48) channels at 64 Kbit/s dependingon
DR04 bit.
73/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
VIII.8 - Connection Memory Data Register - CMDR (0E)H
CONTROL REGISTER (CTLR)
SOURCE REGISTER (SRCR)
bit15
bit8
SI
bit7
bit 0
IM0 ITS 4 ITS 3 ITS 2 ITS 1 ITS 0
SCR PS PRSA
S1
S0 OTSV LOOP
IM2 IM1
After reset (0000)H
This 16 bit register is constitutedby two registers :
SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR)
SOURCE REGISTER (SRCR) has two use modes dependingon CM (bit of CMAR).
CM = 1, access to connection memory (read or write)
- PRSG = 0, ITS 0/4 and IM0/2 bits are defined hereafter :
ITS 0/4 : Input time slot 0/4 define ITSx with : 0 ≤ x ≤ 31;
IM0/2 : Input TimeDivision Multiplex 0/2 define ITDMp with : 0 ≤ p ≤ 7.
- PRSG = 1, the Pseudo Random SequenceGeneratoris validated,SRCR is not significant.
CM = 0, access to data memory (read only). SRC is the data register of the data memory.
CONTROL REGISTER (CTLR) defines each Output Time Slot OTSy of each Output Time Division Multi-
plex OTDMq :
SI
: SEQUENCE INTEGRITY
SI = 1, the delay is always : (31 - ITSx) + 32 + OTSy.
SI = 0, the delay is minimum to pass through the data memory.
LOOP : LOOPBACK per channel relevant if a bidirectionalconnection has been established.
LOOP = 1, OTSy, OTDMq is taken into accountinstead of ITSy, ITDMq.
OTSV = 1, transparentMode LOOPBACK.
OTSV = 0, not Transparent Mode LOOPBACK.
OTSV : OUTPUT TIME SLOT VALIDATED
OTSV = 1, OTSy OTDMq is enabled.
OTSV = 0, OTSy OTDMq is High Impedance.
≤
≤ ≤ ≤
31;OTDMq : OutputTime Division Multiplex with0 q 7).
(OTSy : Output Time slot with 0
y
S1/S0 : SOURCE 1/0
S1
S0
Source for each timeslot of DOUT0/7
0
0
Data Memory (Normal case)
0
1
1
1
0
1
Connection Memory
D channels from/to GCI multiplexes (See note and table hereafter)
Pseudo Random Sequence Generator delivers Hyperchannel at n x 64Kb/s is possible.
Note:
Connection
When the source of D channelsis selected(GCI channelsdefined by ITS 1/0) andwhen
the destination is selected (Outputtimeslot defined by OTS 0/4; output TDM defined by
OM 0/2) the upstream connection is set up; the downstream connection (reverse
direction TDM to GCI) is set up automatically if ITS 2 bit is at 1. So BID, bit of CMAR
must be written at”0”.
Release
Remember: write S1=1, S0=0 and ITS2 bit = 0 to release the downstreamconnection;
the upstream connectionis releasedwhen the source changes.
74/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
TABLE:SWITCHING AT 16Kb/s WHEN ITS3 = 0
S1 S0 ITS 3 ITS 2 ITS 1 ITS 0
Upstream
Downstream
Source: D channels of one of 16
GCI channels
Destination: two bits of one TDM
Source: two bits of one TDM
Destination: D channels of one of 16
GCI channels
Thecontents of D channels of GCI
0 /3 of multiplex DIN4 aretransferred
into the output timeslot of one TDM
defined by thedestination register
(CMAR).
The contents of the input timeslot
(same number as the number of the
output timeslot) is transferred in D
channel of GCI 0/3 of multiplex
DOUT4
0
0
1
1
0
1
0
1
D channel of GCI 0 in bit 1/2
D channel of GCI 1 in bit 3/4
D channel of GCI 2 in bit 5/6
D channel of GCI 3 in bit 7/8
bit 1/2 in D channel of GCI 0
bit 3/4 in D channel of GCI 1
bit 5/6 in D channel of GCI 2
bit 7/8 in D channel of GCI 3
The contents of D channels of GCI
4/7 of multiplex DIN4 are transferred
into the output timeslot of one TDM
defined by the destination register
(CMAR).
The contents of the input timeslot
(same number as the number of the
output timeslot) is transferred in D
channel of GCI 4/7 of multiplex
DOUT4.
D channel of GCI 4 in bit 1/2
D channel of GCI 5 in bit 3/4
D channel of GCI 6 in bit 5/6
D channel of GCI 7 in bit 7/8
bit 1/2 in D channel of GCI 4
bit 3/4 in D channel of GCI 5
bit 5/6 in D channel of GCI 6
bit 7/8 in D channel of GCI 7
1
0
0
1
The contents of D channels of GCI 0
/3 of multiplex DIN5 are transferred
into the output timeslot of one TDM
defined by the destination register
(CMAR).
The contents of the input timeslot
(same number as the number of the
output timeslot) is transferred in D
channel of GCI 0/3 of multiplex
DOUT5.
D channel of GCI 0 in bit 1/2
D channel of GCI 1 in bit 3/4
D channel of GCI 2 in bit 5/6
D channel of GCI 3 in bit 7/8
bit 1/2 in D channel of GCI 0
bit 3/4 in D channel of GCI 1
bit 5/6 in D channel of GCI 2
bit 7/8 in D channel of GCI 3
The contents of D channels of GCI
4/7 of multiplex DIN5 are transferred
into the output timeslot of one TDM
defined by the destination register
(CMAR).
The contents of the input timeslot
(same number as the number of the
output timeslot) is transferred in D
channel of GCI 4/7 of multiplex
DOUT5.
D channel of GCI 4 in bit 1/2
D channel of GCI 5 in bit 3/4
D channel of GCI 6 in bit 5/6
D channel of GCI 7 in bit 7/8
bit 1/2 in D channel of GCI 4
bit 3/4 in D channel of GCI 5
bit 5/6 in D channel of GCI6
bit 7/8 in D channel of GCI 7
75/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
TABLE:SWITCHING AT 16KB/S when ITS3 =1
S1 S0 ITS 3 ITS 2 ITS 1 ITS 0
Upstream
Source: D channels of one of 16
GCI channels
Destination: two bits of one TDM
Downstream
Source: two bits of one TDM
Destination: D channels of one of 16
GCI channels
Thecontents of D channels of GCI
0 /3 of multiplex DIN4 aretransferred
into the output timeslot of one TDM
defined by thedestination register
(CMAR).
The contents of the input timeslot
(same number as the number of the
output timeslot) is transferred in D
channel of GCI 0/3 of multiplex
DOUT4
0
0
1
1
0
1
0
1
D channel of GCI 0 in bit 7/8
D channel of GCI 1 in bit 5/6
D channel of GCI 2 in bit 3/4
D channel of GCI 3 in bit 1/2
bit 7/8 in D channel of GCI 0
bit 5/6 in D channel of GCI 1
bit 3/4 in D channel of GCI 2
bit 1/2 in D channel of GCI 3
The contents of D channels of GCI
4/7 of multiplex DIN4 are transferred
into the output timeslot of one TDM
defined by the destination register
(CMAR).
The contents of the input timeslot
(same number as the number of the
output timeslot) is transferred in D
channel of GCI 4/7 of multiplex
DOUT4.
D channel of GCI 4 in bit 7/8
D channel of GCI 5 in bit 5/6
D channel of GCI 6 in bit 3/4
D channel of GCI 7 in bit 1/2
bit 7/8 in D channel of GCI 4
bit 5/6 in D channel of GCI 5
bit 3/4 in D channel of GCI 6
bit 1/2 in D channel of GCI 7
1
0
1
1
The contents of D channels of GCI 0
/3 of multiplex DIN5 are transferred
into the output timeslot of one TDM
defined by the destination register
(CMAR).
The contents of the input timeslot
(same number as the number of the
output timeslot) is transferred in D
channel of GCI 0/3 of multiplex
DOUT5.
D channel of GCI 0 in bit 7/8
D channel of GCI 1 in bit 5/6
D channel of GCI 2 in bit 3/4
D channel of GCI 3 in bit 1/2
bit 7/8 in D channel of GCI 0
bit 5/6 in D channel of GCI 1
bit 3/4 in D channel of GCI 2
bit 1/2 in D channel of GCI 3
The contents of D channels of GCI
4/7 of multiplex DIN5 are transferred
into the output timeslot of one TDM
defined by the destination register
(CMAR).
The contents of the input timeslot
(same number as the number of the
output timeslot) is transferred in D
channel of GCI 4/7 of multiplex
DOUT5.
D channel of GCI 4 in bit 7/8
D channel of GCI 5 in bit 5/6
D channel of GCI 6 in bit 3/4
D channel of GCI 7 in bit 1/2
bit 7/8 in D channel of GCI 4
bit 5/6 in D channel of GCI 5
bit 3/4 in D channel of GCI 6
bit 1/2 in D channel of GCI 7
PRSA : Pseudo Random Sequence analyzer
If PRSA= 1, PRS analyzer is enabled during OTSy OTDMq and receives data :
INS = 0, data comes from Data Memory.
INS = 1 AND PRSG=1, Data comes from PRS Generator(Test Mode).
If PRSA= 0, PRS analyzer is disabledduring OTSy OTDMq.
: Programmable Synchronization
PS
If PS= 1, ProgrammableSynchronizationSignal Pin is at”1” duringthe bittime definedby OTSy
and OTDMq.
For OTSy and OTDMq with y = q = 0, PSS pin is at ”1” during the first bit of the frame defined
by the Frame synchronization Signal (FS).
If PS = 0, PSS Pin is at ”0” during the bit time defined by OTSy and OTDMq.
SCR : Scrambler/ Descrambler
SCR=1, the scrambler or the descrambler are enabled. Both of them are located after the
switching matrix.
76/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
SCR : The scrambler is enabled when the output timeslot defined by the destinationregister (DSTR)
(cont’d) is an output timeslot belonging to any TDM exceptthe two GCI multiplexes; the contentsof this
output timeslot will be scrambled in accordancewith the IUT-T V.29 Rec.
Thedescrambleris enabledwhen the outputtimeslot defined bythe destinationregister(DSTR)
is an output timeslot belonging to the two GCI multiplexes except any TDM; the contentsof this
output timeslot is descrambled in accordancewith the IUT-T V.29 Rec.
Only 32 timeslotsof 256 can be scrambled or/and descrambled:
GCI side, only B1 and B2 can be selected in each GCI channel (16 GCI channelsare available:
8 per GCI multiplex).
*TDMside,itisforbiddentoselectagiventimeslotmorethanoncewhenseveralTDMsareselected.
SCR=0,thescramblerorthedescrambleraredisabled;thecontentsofoutputtimeslotsarenotmodified.
VIII.9 - Connection Memory Address Register - CMAR (10)H
ACCESS MODE REGISTER (AMR)
DESTINATION REGISTER (DSTR)
bit15
Nu
bit8
bit7
bit 0
Nu
TC CACL CAC BID
CM READ OM2 OM1 OM0 OTS4 OTS3 OTS2 OTS1 OTS0
After reset (0800)H
This16 bitregisterisconstitutedbytworegisters: DESTINATIONREGISTER(DSTR)and ACCESSMODE
REGISTER (AMR) respectively 8 bits and 6 bits.
DESTINATION REGISTER (DSTR)
When DSTR Registeris written by the microprocessor, a memoryaccess is launched.DSTR has two use
modes dependingon CM (bit of CMAR).
CM = 1, access to connection memory (read or write) ;
OTS 0/4 : Output time slot 0/4 define OTSy with : 0 ≤ y ≤ 31,
≤
≤
7.
OM0/2 : Output Time Division Multiplex 0/2 define OTDMq with : 0
q
See table hereafter when DR04, DR24, DR44 and/or DR64 are at “1”; the bits of SMCRdefine the TDMs
at 4 Mbit/s.
The IM2/1 bits of Source Register (SRCR of CMDR) indicate the DIN pin number and the OM2/1 bits of
Destination Register (DSTR of CMAR) indicate the Dout pin number.
IM2 (bit7)
IM1 (bit6)
DIN pin
DIN0
OM2 (bit7)
OM1(bit6)
DOUT pin
DOUT0
DOUT2
DOUT4
DOUT6
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
DIN2
DIN4
DIN6
The ITS4/0 and IM0 bits of Source Register (SRCR of CMDR) indicate the input timeslot number. (IM0 bit
is the Least Significant Bit; it indicates either even timeslot or odd timeslot.
ITS4
(bit4)
ITS3
(bit3)
ITS2
(bit2)
ITS1
(bit1)
ITS0
(bit0)
IMO
(bit5)
Input timeslot number
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
=
=
1
1
1
1
1
1
63
77/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
The OTS4/0 and OM0 bits of DestinationRegister (DSTR of CMAR) indicate the output timeslot number.
(OM0 bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot
OTS4
(bit4)
OTS3
(bit3)
OTS2
(bit2)
OTS1
(bit1)
OTS0
(bit0)
OMO
(bit5)
Output timeslot number
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
=
=
1
1
1
1
1
1
63
Nota Bene:
- CLOCK A/B is at 4 or at 8 MHz in accordancewith HCL bit of General ConfigurationRegister GCR (02).
HCL=1, bit clock frequency is at 8 192 KHz.
For a TDM at 4 Mbit/s or 2Mbit/s, each received bit is sampledat 3/4 bit-time.
HCL=0, bit clock frequency is at 4 096 KHz
For a TDM at 4 Mbit/s, each received bit is sampled at half bit-time.
For a TDM at 2 Mbit/s, each received bit is sampled at 3/4 bit-time.
The definition of IMCRO/1, OMCRO/1 are kept with bit time = 244 ns
Remarks:
- OM0, bit5 of DSTRindicates either even TDM or odd TDM if TDM at 2 Mb/s.
- OM0, bit5 of DSTRindicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s.
- IM0, bit5 of SRCR indicates either even TDM or odd TDM if TDM at 2 Mb/s.
- IM0, bit5 of SRCR indicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s.
- CAC = CACL= 0, DSTR is the AddressRegister of the Connection Memory;
- CAC or CACL= 1, DSTR is usedto indicatethe current addressfor the Connection Memory; its contents
is assignedto the outputs.
CM = 0, access to data memory (read only) ;
- DSTR is the Address Register of the Data Memory; its contentsis assignedto the inputs.
ACCESS MODE REGISTER
(AMR)
READ : READ MEMORY
READ = 1, Read ConnectionMemory (or Data Memory in accordancewith CM).
READ = 0, Write Connection Memory.
: CONNECTION MEMORY
CM = 1, Write or Read ConnectionMemory in accordancewith READ.
CM = 0, Read only Data Memory (READ = 0 has no effect).
: BIDIRECTIONAL CONNECTION
CM
BID
BID = 1; Two connectionsare set up:
ITSxITDMp ------> OTSy OTDMq (LOOP of CMDR Register is taken into account) and
ITSyITDMq ------> OTSx OTDMp (LOOP of CMDR Register is not taken into account).
BID = 0; One connection is set up:
ITSxITDMp ------> OTSy OTDMq only.
CAC : CYCLICALACCESS
CAC = 1 (BID is ignored)
if Write Connection Memory, an automatic data write from Connection Memory Data Register
(CMDR) up to 256 locations of ConnectionMemory occurs. The first address is indicated by the
register DSTR, the last is (FF)H.
if Read Connection Memory, an automatic transfer of data from the location indicated by the
register (DSTR) into Connection Memory Data Register (CMDR) after reading by the
microprocessor occurs. The last location is (FF)H.
CAC = 0, Write and Read Connection Memory in the normal way.
78/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
CACL : CYCLICALACCESS LIMITED
CACL = 1 (BID is ignored)
If Write Connection Memory, an automatic data write from Connection Memory Data Register
(CMDR) up to 32 locations of ConnectionMemory occurs.The firstlocation is indicated by OTS
0/4bits of the register(DSTR) related to OTDMq as defined by OM0/2 occurs. The lastlocation
is q +1 F(H).
If Read Connection Memory, an automatic transfer of data from Connection Memory into
Connection Memory Data Register (CMDR) after reading this last by the microprocessor
occurs.The first location is indicated by OTS 0/4 bits of the register (DSTR) related to OTDMq
as defined by OM0/2. The last location is q +1 F(H).
CACL = 0, Writeand Read Connection Memory in the normal way.
: Transparent Connection
TC
TC = 1, (BID is ignored), if READ = 0 :
CAC = 0 and CACL = 0. TheDSTR bits are taken into accountinsteadof SRCRbits. SRCRbits
are ignored (Destination and Source are identical). The contents of Input time slot i - Input
multiplex j is switched into Output time slot i - Output multiplex j.
CAC = 0 and CACL = 1. Up to 32 ”Transparent Connections”are set up.
CAC = 1 and CACL = 0. Up to 256 ”Transparent Connections”are set up.
TC = 0, Write and Read Connection Memory are in accordancewith BID.
VIII.10 - SequenceFault Counter Register - SFCR (12)H
bit15
F15
bit8
F8
bit7
F7
bit 0
F0
F14
F13
F12
F11
F10
F9
F6
F5
F4
F3
F2
F1
After reset (0000)H
When this register is read by the microprocessor, this register is reset(0000)H.
F0/15 : FAULT0/15
Number of faults detected by the Pseudo Random Sequenceanalyzer if the analyzerhas been
validated and has recovered the receive sequence.
When the Fault Counter Register reaches (00FF)H it stays at its maximum value.
NB. As the SFCR is reset after reading, a 8-bitmicroprocessor must read the LSB that will represent the
numberof faults between 0 and 255. To avoid overflow escape notice, it is necessaryto startcounting
at FF00h,by writing this value inSFCR before launchingPRSA.If thereare more than FFh errors, the
SFCO interrupt bit(see interrupt register IR -38Haddress)will signal that the fault count register has
reachedthe value FFFFh (because of the number of faults exceeded 255).
VIII.11- Time Slot Assigner Address Register - TAAR (14)H
bit15
bit8
HDI
bit7
r
bit 0
d
TS4 TS3 TS2 TS1 TS0 READ
Nu
e
s
e
r
v
e
After reset (0100)H
READ : READ MEMORY
READ = 1, Read Time slot Assigner Memory.
READ = 0, WriteTime slot Assigner Memory.
TS0/4 : TIME SLOTS0/4
These five bits define one of 32 time slots in which a channel is set-up or not.
79/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
HDI
: HDLC INIT
HDI = 1, TSA Memory, Tx HDLC, Tx DMA, Rx HDLC, Rx DMA and GCI controllers are reset
within 250ms. An automate writes data from Time slot Assigner Data Register (TADR) (except
CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner
Memory after HDLC INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4
bits of Time slot Assigner Address Register.
HDI = 0, Normal state.
N.B.
After software reset (bit 2 of IDCR Register) or pin reset the automateabove-mentioned is
working. The automateis stoppedwhen the microprocessor writes TAAR Register withHDI =0.
VIII.12 - Time Slot Assigner Data Register - TADR (16)H
bit15
V11
bit8
V4
bit7
V3
bit 0
V10
V9
V8
V7
V6
V5
V2
V1
CH4 CH3 CH2 CH1 CH0
After reset (0000)H
CH0/4 : CHANNEL0/4
These five bits define one of 32 channels associated to TIME SLOT defined by the previous
Register (TAAR).
V1/8 : VALIDATION
The logical channel CHx is constituted by each subchannel1 to 8 and validated by V1/8 bit at
1 respectively.
V1 to V8 at 0: the subchannelsare ignored
V1 at 1: the first bit of thecurrent time slot is taken into account in receptionthe first bit received
and in transmission the first bit transmitted.
V8 at 1: the last bit of the current time slot is taken into account in receptionthe last bit received
and in transmission the last bit transmitted in transmission.
V9
: VALIDATION SUBCHANNEL
V 9 = 1, each V1/8 bit is taken into account once every 250ms.
In transmit direction, data is transmittedconsecutively during the time slot of the current frame
and during the same time slot of the next frame.Id est.: the same data is transmitted in two
consecutiveframes.
In receive direction, HDLC controller fetches data during the time slot of the current frame and
ignores data during the same time slot of the next frame.
V 9 = 0, each V1/8 bit is taken into account once every 125ms.
V10
: DIRECT MHDLC ACCESS
If V10 = 1, the Rx HDLC Controllerreceives data issued from DIN8 input during the current time
slot (bits validated by V1/8) and DOUT6 output transmits data issued from the Tx HDLC
Controller.
If V10 = 0, the Rx HDLC Controller receives data issued from the matrix output 7 during the
current time slot ; DOUT6 output delivers data issued from the matrixoutput 6 during the same
current time slot.
N.B : If D7 = 1, (see ”General Configuration Register GCR (02)H”) the Tx HDLC controller is
connected to matrix input 7 continuously so the HDLC frames can be sent to any DOUT (i.e.
DOUT0 to DOUT7).
V11
: VALIDATION of CB pin
This bit is not taken into account if CSMA= 1 (HDLC Transmit Command Register).
if CSMA= 0 :
V11 = 1, Contention Bus pin is validated and Echo pin (which is an input) is not taken into
account.
V11 = 0, ContentionBus pin is high impedance during the current time slot (This pin is an open
drain output).
80/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
VIII.13 - HDLC Transmit Command Register - HTCR (18)H
bit15
bit8
bit7
bit 0
CH4 CH3 CH2 CH1 CH0 READ
Nu
CF PEN CSMA NCRC
After reset (0000)H
F
P1
P0
C1
C0
READ : READ COMMAND MEMORY
READ = 1, READ COMMAND MEMORY.
READ = 0, WRITE COMMAND MEMORY.
CH0/4 : These five bits define one of 32 channels.
C1/C0 : COMMAND BITS
C1 C0
Commands Bits
0
0
ABORT ; if this command occurs during the current frame, HDLC Controller transmits seven ”1”
immediately, afterwards HDLC Controller transmits ”1” or flag inaccordance with F bit, generates
an interrupt and waits new command such as START orn CONTINUE.
If this command occurs after transmitting a frame, HDLC Controller generates an interrupt and
waits a new command such as START or CONTINUE.
0
1
1
1
0
1
START ; Tx DMA Controller is now going to transfer first frame from buffer related to initial
descriptor. The initial descriptor address is provided by the Initiate Block located in external
memory.
CONTINUE ; Tx DMA Controller is now going to transfer next frame from buffer related to next
descriptor. The next descriptor address is provided by the previous descriptor from which the
related frame had been already transmitted.
HALT ; after transmitting frame, HDLC Controller transmits ”1” or flag in accordance with F bit,
generates an interrupt and is waiting new command such as START or CONTINUE.
P0/1 : PROTOCOLBITS
P1 P0
Transmission Mode
0
0
1
1
0
1
0
1
HDLC
Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.
Transparent Mode 2 (perbyte) ; the fillcharacter definedin FCR Register is nottaken intoaccount.
Reserved
F
: Flag
F = 1; flagsare transmittedbetweenclosing flagof currentframeand openingflagof nextframe.
F = 0 ; ”1” are transmitted between closing flag of currentframe and openingflag of next frame.
NCRC : CRC NOT TRANSMITTED
NCRC = 1, the CRC is not transmitted at the end of the frame.
NCR C =0, the CRC is transmitted at the end of the frame.
CSMA : Carrier Sense Multiple Access with ContentionResolution
CSMA= 1, CB output and the Echo Bit are taken into account during this channel transmission
by the Tx HDLC.
CSMA = 0, CB output and the Echo Bit are defined by V11 (see ” Time slot Assigner Data
Register TADR (16)H”).
81/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
PEN : CSMAPENALTY significant if CSMA= 1
PEN = 1, the penaltyvalue is 1 ; a transmitterwhich has transmitted a framecorrectly will count
(PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8
or 10 given by the buffer descriptor related to the frame.
PEN = 0, the penaltyvalue is 2 ; a transmitterwhich has transmitted a framecorrectly will count
(PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8
or 10 given by the transmit descriptor related to the frame).
CF
: Common flag
CF = 1, theclosing flag of previous frame and openingflag of nextframe are identical if the next
frame is ready to be transmitted.
CF = 0, the closing flag of previous frame and opening flag of next frame are distinct.
VIII.14 - HDLC Receive Command Register - HRCR (1A)H
bit15
bit8
bit7
bit 0
C0
CH4 CH3 CH2 CH1 CH0 READ AR21 AR20 AR11 AR10 CRC FM
After reset (0000)H
P1
P0
C1
READ : READ COMMAND MEMORY
READ = 1, READ COMMAND MEMORY.
READ = 0, WRITE COMMAND MEMORY.
CH0/4 : These five bits define one of 32 channels.
C1/C0 : COMMAND
C1 C0
Commands Bits
0
0
ABORT ; if this command occurs during receiving a current frame, HDLC Controller stops the
reception, generates an interrupt and waits new command such as START orn CONTINUE.
If this command occurs after receiving a frame, HDLC Controller generates an interrupt and waits
a new command such as START or CONTINUE.
0
1
1
1
0
1
START ; Rx DMA Controller is now going to transfer first frame into buffer related to the initial
descriptor. The initial descriptor address is provided by the Initiate Block located in external
memory.
CONTINUE ; Rx DMA Controller is now going to transfer next frame into buffer related to next
descriptor. The next descriptor address is provided by the previous descriptor from which the
related frame had been already received.
HALT ; after receiving frame, HDLC Controller stops the reception, generates an interrupt and
waits a new command such as START or CONTINUE.
P0/1 : PROTOCOLBITS
P1 P0
Transmission Mode
0
0
1
1
0
1
0
1
HDLC
Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.
Transparent Mode 2 (perbyte) ; the fillcharacter definedin FCR Register is nottaken intoaccount.
Reserved
FM
: Flag Monitoring.
This bit is a status bit read by the microprocessor.
FM=1: HDLC Controller is receiving a frame or HDLC Controller has just received one flag.
FM is put to 0 by the microprocessor.
CRC : CRC stored in external memory
CRC = 1, the CRC is stored at the end of the frame in external memory.
CRC = 0, the CRC is not stored into external memory.
82/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
AR10 : Address Recognition10
AR10 = 1, First byte after opening flag of received frame is compared to AF0/7 bits of AFRDR.
If the first byte received and AF0/7 bits are not identicalthe frame is ignored.
AR10= 0, First byteafter openingflag of receivedframeis not comparedtoAF0/7bitsof AFRDR
Register.
AR11 : Address Recognition 11
AR11 = 1, First byte after opening flag of received frame is compared to all ”1”s.If the first byte
received is not all ”1”s the frame is ignored.
AR11 = 0, First byte after opening flag of received frame is not compared to all ”1”s.
AR20 : Address Recognition 20
AR20= 1, Secondbyte afteropeningflag of receivedframeis comparedto AF8/15bitsofAFRDR
Register. If the second byte received and AF8/15 bits are not identical the frame is ignored.
AR20 = 0, Second byte after opening flag of received frame is not compared to AF8/15 bits of
AFRDR Register.
AR21 : Address Recognition 21
AR21 = 1, Second byte after opening flag of received frame is compared to all ”1”s. If the
Second byte received is not all ”1”s the frame is ignored.
AR21 = 0, Secondbyte after opening flag of received frame is not compared to all ”1”s.
Second Byte
First Byte
Conditions to Receive a Frame
AR21 AR20 AR11 AR10
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Each frame is received without condition.
Only value of the first received byte must be equal to that of AF0/7 bits.
Only value of the first received byte must be equal to all ”1”s.
The value of the first received byte must be equal either to that of AF0/7 or
to all ”1”s.
0
0
1
1
0
0
0
1
Only value of the second received byte must be equal to that of AF8/15 bits.
The value of the first received byte must be equal to that of AF0/7 bits and
the value of the second received byte must be equal to that of AF8/15 bits.
0
0
1
1
1
1
0
1
The value of first received byte is must be equal to all ”1”s and the value of
second received byte must be equal to that of AF8/15 bits.
The value of the first received byte must be equal either to that of AF0/7 or
to all ”1”s and the value of the second received byte must be equal to that
of AF8/15 bits.
1
1
0
0
0
0
0
1
Only the value of the second received byte must be equal to all ”1”s.
The value of the first received byte must be equal to that of AF0/7 bits and
the value of the second received byte must be equal to all ”1”s.
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
The value of thefirst receivedbyte must be equal to all ”1”s and the valueof
the second received byte must be equal to ”1” also.
The value of the first received byte must be equal either to that of AF0/7 or
to ”1” and the value of the second received byte must be equal to all ”1”s.
The value of the second received byte must be equal either to that of AF8/15
or to all ”1”s.
The value of the first received byte must be equal to that of AF0/7 bits and
the value of the second received byte must be equal either to that of AF8/15
or to all ”1”s.
1
1
1
1
1
1
0
1
The value of the first received byte must be equal to ”1” and the value of the
second received byte must be equal either to that of AF8/15 or to all ”1”s.
The value of the first received byte must be equal either to that of AF0/7 or
to ”1” and the value of the second received byte must be equal either to that
of AF8/15 or to all ”1”s.
83/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
VIII.15 - Address Field Recognition Address Register - AFRAR (1C)H
bit15
bit8
Nu
bit7
r
bit 0
d
CH4 CH3 CH2 CH1 CHO READ AMM
e
s
e
r
v
e
After reset (0000)H
The write operation is lauched when AFRAR is written by the microprocessor.
AMM : Access to Mask Memory.
AMM=1, Access to Address Field RecognitionMask Memory.
AMM=0, Access to Address Field RecognitionMemory.
READ : READ ADDRESS FIELD RECOGNITION MEMORY
READ=1, READ AFR MEMORY.
READ=0, WRITE AFR MEMORY.
CH0/4 : These five bits define one of 32 channels in reception
VIII.16 - Address Field Recognition Data Register - AFRDR (1E)H
bit15
bit8
bit7
bit 0
AF0/
AF15/ AF14/ AF13/ AF12/ AF11/ AF10/ AF9/
AF8/
AF7/
AF6/
AF5/
AF4/
AF3/
AF2/
AF1/
AFM15 AFM14 AFM13 AFM12 AFM11 AFM10 AFM9 AFM8 AFM7 AFM6 AFM5 AFM4 AFM3 AFM2 AFM1 AFMO
After reset (0001)H
AF0/15 : ADDRESS FIELD BITS
AF0/7 ; Firstbyte received; AF8/15: Second byte received.
These two bytes are stored into Address Field RecognitionMemory when AFRAR is written by
the microprocessor.
AFM0/
15:
ADDRESS FIELD BIT MASK0/15 if AMM=1 (AMM bit of AFRAR)
AMF0/7. WhenAR10=1 (See HRCR) each bit of the first receivedbyte iscompared respectively
to AFx bit if AFMx=0. In case of mismatching, the received frame is ignored. If AFMx=1, no
comparison between AFx and the correspondingreceived bit.
AMF8/15. When AR20=1 (See HRCR) each bit of the second received byte is compared
respectively to AFy bit if AFMy=0. In case of mismatching, the received frame is ignored. If
AFMy=1, no comparison between AFy and the correspondingreceived bit.
Thesetwobytesare storedinto AddressFieldRecognitionMaskMemorywhen AFRARis written
by the microprocessor (AMM=1).
VIII.17 - Fill Character Register - FCR (20)H
bit15
bit8
d
bit7
bit 0
r
e
s
e
r
v
e
FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0
After reset (0000)H
FC0/7 : FILL CHARACTER (eight bits)
InTransparentModeM1, twomessagesareseparatedby FILLCHARACTERS andthedetection
of one FILL CHARACTER marks the end of a message.
VIII.18 - GCI Channels Definition Register 0 - GCIR0 (22)H
The definitions of x and y indices are the same for GCIR0, GCIR1, GCIR2, GCIR3 :
≤
≤
- 0
x
7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5
- y = 0, TDM4 is selected
- y = 1, TDM5 is selected.
84/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
bit15
bit8
bit7
bit 0
ANA11 VCI11 V*11 VM11 ANA10 VCI10 V*10 VM10 ANA01 VCI01 V*01 VM01 ANA00 VCI00 V*00 VM00
TDM5 TDM4 TDM5 TDM4
GCI CHANNEL 1
GCI CHANNEL 0
After reset (0000)H
VMxy : VALIDATION of MONITOR CHANNELx, MULTIPLEXy :
When this bit is at 1, monitor channel xy is validated.
When this bit is at 0, monitor channel xy is not validated.
Online toreset (ifnecessary)one MONchannelwhichhad been selectedpreviouslyVMxymust
be put at 0 during125ms before reselectingthis channel.Deselecting one MONchannel during
125ms resets this MON channel.
V*xy : VALIDATION of V Starx, MULTIPLEX y
When this bit is at 1, V Star protocol is validated if VMxy=1.
When this bit is at 0, GCI Monitor protocol is validated if VMxy=1.
VCxy : VALIDATION of Command/IndicateCHANNEL x, MULTIPLEXy
When this bit is at 1, Command/Indicatechannelxy is validated.
When this bit is at 0, Command/Indicatechannelxy is not validated.
It is necessaryto let VCxy at ”0” during 125ms to initiate the Command/Indicate channel.
ANAxy : ANALOGAPPLICATION
When this bit is at 1, Primitive has 6 bits if C/Ixy is validated.
When this bit is at 0, Primitive has 4 bits if C/Ixy is validated.
VIII.19 - GCI Channels Definition Register 1 - GCIR1 (24)H
bit15
ANA31 VCI31 V*31 VM31 ANA30 VCI30 V*30 VM30 ANA21 VCI21 V*21 VM21 ANA20 VCI20 V*20 VM20
TDM5 TDM4 TDM5 TDM4
bit8
bit7
bit 0
GCI CHANNEL 3
GCI CHANNEL 2
After reset (0000)H
For definition see GCI Channels Definition Register above.
VIII.20 - GCI Channels Definition Register 2 - GCIR2 (26)H
bit15
ANA51 VCI51 V*51 VM51 ANA50 VCI50 V*50 VM30 ANA41 VCI41 V*41 VM41 ANA40 VCI40 V*40 VM40
TDM5 TDM4 TDM5 TDM4
bit8
bit7
bit 0
GCI CHANNEL 5
GCI CHANNEL 4
After reset (0000)H
For definition see GCI Channels Definition Register above.
VIII.21 - GCI Channels Definition Register 3 - GCIR3 (28)H
bit15
ANA71 VCI71 V*71 VM71 ANA70 VCI70 V*70 VM70 ANA61 VCI61 V*61 VM61 ANA60 VCI60 V*60 VM60
TDM5 TDM4 TDM5 TDM4
bit8
bit7
bit 0
GCI CHANNEL 7
GCI CHANNEL 6
After reset (0000)H
For definition see GCI Channels Definition Register above.
85/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
VIII.22 - Transmit Command / Indicate Register - TCIR (2A)H
bit15
D
bit8
0
bit7
Nu
bit 0
G0
CA2 CA1 CA0 READ
0
Nu
C6A C5/E C4/S1 C3/S2 C2/S3 C1/S4
After reset (00FF)H
When this register is written by the microprocessor, these different bits mean :
READ : READ C/I MEMORY
READ = 1, READ C/I MEMORY.
READ = 0, WRITE C/I MEMORY.
CA0/2 : TRANSMIT COMMAND/INDICATE MEMORYADDRESS
CA 0/2 : These bits define one of eight Command/IndicateChannels.
G0
: This bit defines one of two GCI MULTIPLEXy.
G0 = 0, GCI0 (DIN4/DOUT4) is selected.
G0 = 1, GCI1 (DIN5/DOUT5) is selected.
D
: Destination; this bit definesthe destination of bits 0 to 5.
D=0: the primitive C6 to C1 is transmitted directly into one of 16 GCI channels defined by G0
and CA 0/2.
D=1: the 6 bit word A, E, S1, S2, S3, S4 is put instead of the six bits received latest during the
timeslot 4n+3 (GCI channel defined by G0 and CA0/2) and these 6 bit word is transmitted into
any selected output timeslot after switching.
bit15
bit8
Nu
bit7
Nu
bit 0
C1
D=0
G0
G0
CA2 CA1 CA0 READ
CA2 CA1 CA0 READ
Nu
Nu
Nu
Nu
C6
A
C5
E
C4
S1
C3
S2
C2
S3
D=0
Nu
Nu
S4
C6/1 : New Primitive to be transmitted to the selected GCI channel (DOUT4 or DOUT5). Case of D=0.
C6 is transmitted first if ANA=1.
C4 is transmitted first if ANA=0.
A, E, S1 to S4: New 6 bit word to be transmitted into any output timeslot. Case of D=1.
The New Primitive (or the 6 bit word) is taken into account by the transmitter after writing bits 8 to 15 (if
8bit microprocessor).
Transmit Command/Indicate Register
(after reading)
bit15
bit8
Nu
Nu
bit7
bit 0
C1
D=0
D=1
G0
G0
CA2 CA1 CA0 READ
CA2 CA1 CA0 READ
Nu
Nu
PT1 PT0
PT1 PT0
C6
A
C5
E
C4
S1
C3
S2
C2
S3
S4
When this register is read by the microprocessor, these different bits mean :
READ : READ C/I MEMORY
READ = 1, READ C/I MEMORY.
READ = 0, WRITE C/I MEMORY.
CA0/2 : TRANSMIT C/I ADDRESS
CA 0/2 : These bits define one of eight Command/IndicateChannels.
G0
D
: This bit defines one of two GCI multiplexes.
G0 = 0, DIN4/DOUT4 are selected.
G0 = 1, DIN5/DOUT5 are selected.
: Destination. This bit defines the destinationof bits 0 to 5
D=0: the destination is one of 16 GCI channels defined by G0and CA 0/2.
D=1:the destinationis any TDM (after switching).
C6/1 : Last Primitive transmitted. Case of D=1
86/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
A, E, S1 to S4: 6 bit word transmitted. Case of D=1.
PT0/1 : Status bits
P1
0
0
P0
0
1
Primitive Status
Primitive (or 6 bit word) has not been transmitted yet.
Primitive (or 6 bit word) has been transmitted once.
Primitive (or 6 bit word) has been transmitted twice.
Primitive (or 6 bit word) has been transmitted three times or more.
1
1
0
1
VIII.23 - Transmit Monitor Address Register - TMAR (2C)H
bit15
0
bit8
Nu
bit7
Nu
bit 0
G0
MA2 MA1 MA0 READ
Nu
Nu
TIV
FABT
L
NOB
0
Nu
After reset (000F)H
When this register is written by the microprocessor, these different bits mean :
READ : READ MON MEMORY
READ=1, READ MON MEMORY.
READ=0, WRITE MON MEMORY.
MA 0/2 : TRANSMIT MONITOR ADDRESS
MA 0/2 :These bits define one of eight Monitor Channel if validated.
G0
: This bit defines one of two GCI multiplexes.
G0 = 0, TDM4 is selected.
G0 = 1, TDM5 is selected.
NOB : NUMBER OF BYTE to be transmitted
NOB = 1, One byte to transmit.
NOB = 0, Two bytes to transmit.
L
: Last byte
L = 1, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is the last.
L = 0, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is not the
last.
FABT : FABT = 1, the current message is aborted by the transmitter.
TIV
: Timer interrupt is Validated
TIV = 1, Time Out alarm generates an interrupt when the timer has expired.
TIV = 0, Time Out alarm is masked.
If 8 bit microprocessor the Data (TMDR Register) is taken into accountby the transmitterafter writing bits
8 to 15 of this register.
Transmit Monitor Address Register (after reading)
bit15
0
bit8
Nu
bit7
Nu
bit 0
G0
MA2 MA1 MA0 READ
Nu
Nu
TO
ABT
L
NOBT EXE IDLE
When this register is read by the microprocessor, these different bits mean :
READ, MA0/2, G0 have same definition as already described for the write register cycle.
IDLE : When this bit is at ”1”, IDLE (all 1’s) is transmitted during the channel validation.
EXE : EXECUTED
When this status bit is at ”1”, the command written previously by the microprocessor has been
executed and a new word can be stored in the Transmit Monitor Data Register (TMDR) by the
microprocessor.
When this bit is at ”0”, the command written previously by the microprocessor has not yet been
executed.
87/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
NOBT : NUMBER OF BYTE which has been transmitted.
NOBT = 1, the first byte is transmitting.
NOB T = 0, the second byte is transmitting, the first byte has been transmitted.
: Last byte ; this L bit is the L bit which has been written by the microprocessor.
L
ABT
: ABORT
ABT=1, the remote receiver has aborted the current message.
: Time Out one millisecond
TO
TO = 1, the remote receiver has not acknowledged the byte which has been transmitted one
millisecond ago.
VIII.24 - Transmit Monitor Data Register - TMDR (2E)H
bit15
bit8
bit7
bit 0
M18 M17 M16 M15 M14 M13 M12 M11 M08 M07 M06 M05 M04 M03 M02 M01
After reset(FFFF)H
M08/01: First Monitor Byte to transmit. M08 bit is transmittedfirst.
M18/11: Second Monitor Byte to transmit if NOB = 0 (bit of TMAR). M18 bit is transmitted first.
VIII.25 - Transmit Monitor Interrupt Register - TMIR (30)H
bit15
TDM5
bit8
bit7
TDM4
bit 0
MI71 MI61 MI51 MI41 MI31 MI21 MI11 MI01 MI70 MI60 MI50 MI40 MI30 MI20 MI10 MI00
After reset (0000)H
When the microprocessor read this register, this registeris reset(0000)H.
MIxy : Transmit Monitor Channel x Interrupt, Multiplex y with :
0 ≤ x ≤ 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5
y = 0, GCI CHANNEL belongs to the multiplex TDM4 and y = 1 to TDM5.
MIxy = 1 when :
- a word has been transmitted and pre-acknowledged by the Transmit Monitor Channel xy (In
this case the Transmit Monitor Data Register (TMDR) is available to transmit a new word) or
- the message has been aborted by the remote receive Monitor Channel or
- the Timer has reachedone millisecond (in accordancewith TIVbit ofTMAR)by IM3bit ofIMR.
When MIxy goes to ”1”, the Interrupt MTX bit of IR is generated.InterruptMTX can be masked.
VIII.26 - Memory Interface Configuration Register - MICR (32)H
bit15
P41
bit8
bit7
Z
bit 0
REF
P40
P31
P30
P21
P20
P11
P10
W
V
U
T
S
R
After reset (E4F0)H
REF : MEMORY REFRESH
REF = 1, DRAM REFRESH is validated,
REF = 0, DRAM REFRESH is not validated.
R,S,T : These three bits define the external RAM circuit organization(1word=2bytes)
The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 pin).
T
0
0
0
0
1
1
S
0
0
1
1
0
0
R
0
1
0
1
0
1
If refresh
128K x 8 SRAM circuit (up to 512K words)
512K x 8 SRAM circuit (up to 512K words)
256K x 16 DRAM circuit (up to 1M word)
512 cycles / 8ms
1024 cycles / 16ms
2048 cycles / 32ms
1M x 4 (or 16) bits DRAM circuit (up to 4M words)
4M x 4 (or 16) bits DRAM circuit (up to 8M words)
101 to 111 not used (this writting is forbidden)
The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 Pin).
88/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
U,V,W,Z : These four bits define the differentsignals delivered by the MHDLC.
First Case :
the external RAM circuit is DRAM (T = 1 or S = 1)
- U defines the time Tu comprised between beginningof cycle and falling edge of NRAS :
U = 1, Tu = 60ns - U = 0, Tu= 30ns
- V definesthe time Tv comprised between falling edge of NRAS and falling edge of NCAS:
V = 1, Tv = 60ns - V = 0, Tv = 30ns
- W definesthe time Tw comprised betweenfalling edge of NCAS and rising edge of NCAS :
W = 1, Tw = 60ns - W = 0, Tw = 30ns
- Z defines the time Tz comprised between rising edge of NCAS and end of cycle :
Z = 1, Tz = 60ns - Z = 0, Tz = 30ns
The total cycle is Tu + Tv + Tw + Tz.
The different output signals are high impedance during 15ns before the end of each cycle.
Second Case :
the external RAM circuit is SRAM (T = 0 or S = 0)
- U and V definea part of write cycle for SRAM : the time Tuv comprised betweenfalling edge
and rising edge of NCE. Thetotal of write cycle is : 15ns+Tuv + 15ns.
V
0
0
1
1
U
0
1
0
1
Tuv
30ns
60ns
90ns
120ns
- W and Z definea partof readcycle for SRAM: the timeTwz comprised betweenfallingedge
of NOE and rising edge of NOE. The total of read cycle is : Twz +30ns
Z
0
0
1
1
W
0
Twz
30ns
60ns
90ns
120ns
1
0
1
N.B.The differentoutput signals are high impedance during 15ns before theend of each cycle. On the outside of each (DRAM
or SRAM) cycle all the outputs are high impedance or not in accordance with MBL bit (see ”MBL : Memory Bus Low
impedance”).
Memory
bit15
bit8
bit7
Z
bit 0
REF
P4E1 P4E0 P3E1 P3E0 P2E1 P2E0 P1E1 P1E0
W
V
U
T
S
R
After reset (E4F0)H
P1 E0/1 : PRIORITY 1 for entity defined by E0/1
P2 E0/1 : PRIORITY 2 for entity defined by E0/1
P3 E0/1 : PRIORITY 3 for entity defined by E0/1
P4 E0/1 : PRIORITY 4 for entity defined by E0/1
Entity definition :
E1
0
E0
0
Entity
Rx DMA Controller
Microprocessor
0
1
1
0
Tx DMA Controller
Interrupt Controller
1
1
89/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
PRIORITY 5 is the last priority for DRAM Refresh if validated. DRAM Refresh obtains PRIORITY 0 (the
first priority) automatically when the first half cycle is spent without access to memory.
After reset (E400)H, the Rx DMAController has the PRIORITY1
the Microprocessor has the PRIORITY 2
the Tx DMAController has the PRIORITY 3
the Interrupt Controller has the PRIORITY 4
the DRAM Refresh has the PRIORITY5
VIII.27 - Initiate Block Address Register - IBAR (34)H
bit15
A23
bit8
bit7
bit 0
A8
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
After reset (0000)H
A8/23 : Addressbits. These 16 bits are the segment address bits of the Initiate Block(A8 to A23 for the
external memory in the MHDLC address space).The offset is zero (A0 to A7 =”0”).
The Initiate Block Address (IBA) is :
23
8
7
0
0
0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
0
0 0 0 0 0
The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.)
The least significant bit defines one of two bytes when the microprocessor selects one byte.
Example: MHDLC device address inside µP mapping = 100000H
Initiate Block address inside µP mapping = 110000H
IBARvalue = (110000- 100000)/256= 100H
VIII.28 - Interrupt Queue Size Register - IQSR (36)H
bit15
bit8
0d
bit7
bit 0
TBFS
0
0
0
0
0v
0
HS2 HS1 HS0 MS2 MS1 MS0 CS1 CS0
After reset (0000)H
CS0/1 : Command/IndicateInterrupt Queue Size
These two bits define the size of Command/IndicateInterruptQueue in external memory.
The location is IBA + 256 + HDLC Queue size + MonitorChannel Queue Size (see The Initiate
Block Address(IBA)).
MS0/2 : Monitor Channel Interrupt Queue Size
These three bits define the size of Monitor Channel Interrupt Queue in external memory.
The location is IBA + 256 + HDLC Queue size.
HS0/2 : HDLC Interrupt Queue Size
These threebitsdefinethesize ofHDLC statusInterruptQueueinexternalmemoryforeachchannel.
The locationis IBA+256(see The Initiate Block Address (IBA))
HDLC
Queue Size
MON
Queue Size
C/I
HS2 HS1 HS0
MS2 MS1 MS0
CS1 CS0
Queue Size
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
128 words
256 words
384 words
512 words
640 words
768 words
896 words
1024 words
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
128 words
256 words
384 words
512 words
640 words
768 words
896 words
1024 words
0
0
1
1
0
1
0
1
64 words
128 words
192 words
256 words
90/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
TBFS : Time Base running with Frame Synchronisationsignal
TBFS=1, the Time Base defined by the Timer Register (see page 92) is running on the rising
edge of Frame Synchronisationsignal.
TBFS=0, the Time Base defined by the Timer Register is running on the rising edge of MCLK
signal.
VIII.29 - Interrupt Register - IR (38)H
bit15
bit8
Tx
bit7
Tx
bit 0
Nu Nu SFCO PRSR TIM INT
INT
Rx
Rx
ICOV MTX MRX C/IRX HDLC
FOV FWAR FOV FWAR FOV FWAR
After reset (0000)H
This register is read only.
When this register is read by the microprocessor, this register is reset(0000)H.
If not masked, each bit at ”1” generates ”1” on INT0 pin.
HDLC
C/IRX
MRX
MTX
: HDLC INTERRUPT
HDLC = 1, Tx HDLC or Rx HDLC has generated an interrupt The status is in the HDLC
queue.
: Command/IndicateRx Interrupt
C/IRX = 1, Rx Commande/Indicatehas generated an interrupt. The status is in the HDLC
queue.
: Rx MONITOR CHANNEL INTERRUPT
MRX = 1, one Rx MONITOR CHANNEL has generated an interrupt.Thestatus is in the Rx
Monitor Channel queue.
: Tx MONITOR CHANNEL INTERRUPT
MTX = 1, one or several Tx MONITOR CHANNELS have generatedan interrupt. Transmit
MonitorInterruptRegister (TMIR) indicates the Tx MonitorChannels which have generated
this interrupt.
ICOV
: INTERRUPT CIRCULAR OVERLOAD
ICOV = 1, One of three circular interrupt memories is completed.
RxFWAR : Rx DMACONTROLLER FIFO WARNING
RxFWAR = 1, Rx DMACONTROLLER has generatedan interrupt, its fifo is 3/4 completed.
: Rx DMACONTROLLER FIFO OVERLOAD
RxFOV
RxFOV= 1,Rx DMACONTROLLERhas generatedan interrupt,it cannottransferdata from
Rx HDLC to external memory, its fifo is completed.
TxFWAR : Tx DMACONTROLLER FIFO WARNING
TxFWAR = 1, Tx DMACONTROLLER has generated an interrupt, its fifo is 3/4 completed.
: Tx DMACONTROLLER FIFO OVERLOAD
TxFOV
TxFOV = 1, Tx DMACONTROLLERhas generatedan interrupt,it cannot transferdata from
Tx HDLC to external memory, its fifo is completed.
INTFWAR : INTERRUPT CONTROLLER FIFO WARNING
INTFWAR = 1, INTERRUPT CONTROLLER has generated an interrupt, its fifo is 3/4
completed.
INTFOV
: INTERRUPT CONTROLLER FIFO OVERLOAD
INTFOV = 1, INTERRUPT CONTROLLER has generated an interrupt, it cannot transfer
status from DMA and GCI controllersto external memory, its internal fifo is completed.
TIM
: TIMER
TIM = 1, the programmable timer has generated an interrupt.
91/101
STLC5465B
VIII - INTERNAL REGISTERS (continued)
PRSR
: Pseudo Random SequenceRecovered
PRSR= 1,thePseudo RandomSequencetransmittedby thegeneratorhas beenrecovered
by the analyzer.
SFCO
: SequenceFault Counter Overload
SFCO = 1, the Fault Counter has reached the value (00FF)H.
VIII.30 - Interrupt Mask Register - IMR (3A)H
bit15
bit8
IM8
bit7
IM7
bit 0
IM0
Nu
Nu
IM13 IM12 IM11 IM10 IM9
IM6
IM5
IM4
IM3
IM2
IM1
After reset(FFFF)H
IM13/0 : INTERRUPT MASK 0/7
When IM0 = 1, HDLC bit is masked.
When IM1 =1, C/IRX bit is masked.
When IM2 = 1, MRX bit is masked.
When IM3 = 1, MTX bit is masked.
When IM4 = 1, ICOV bit is masked
When IM5 = 1, RxFWAR bit is masked.
When IM6 = 1, RxFOV bit is masked.
When IM7 = 1, TxFWAR bit is masked.
When IM8 = 1, TxFOV bit is masked.
When IM9 = 1, INTFWAR bit is masked.
When IM10 = 1, INTFOV bit is masked.
When IM11 = 1, TIM bit is masked.
When IM12 = 1, PRSR bit is masked.
When IM13 = 1, SFCO bit is masked.
VIII.31 - Timer Register - TIMR (3C)H
bit15
S3
bit12
bit0
bit1
bit 0
S2
S1
S0 MS9 MS8 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 MM1 MM0
0 to 15s
0 to 999ms
0 to
3x0.25ms
After reset (0800)H id 512ms
This programmableregister indicates the time at the end of whichthe WatchDog deliverslogic ”1” on the
pin WDO (which is an output) but only if the microprocessordoes not reset the counterassigned (with the
help of WDR bit of IDCR Identification and Dynamic Command Register) during the time defined by the
Timer Register.
The Timer Register and its counter can be used as a time base by the microprocessor. An interrupt (TIM)
is generatedat eachperiod defined by the Timer Register if the microprocessordoes not reset the counter
with the helpof WDR (bit of IDCR).
The Watch Dog or the Timer is incremented by the Frame Synchronisation clock (TBFS=1) or by a
submultiple of MCLK signal (TBFS=0; TBFS, bit of InterruptQueue Size Register).
When TSV=1{Time Stamping Validated (GCR)} this programmable register is not used.
VIII.32 - Test Register - TR (3E)H
bit15
bit8
bit7
bit 0
92/101
STLC5465B
IX - EXTERNAL REGISTERS
These registers are located in shared memory. Initiate Block Address Register (IBAR) gives the Initiate
Block Address (IBA) in shared memory (see RegisterIBAR(34)Hon Page 90).
‘Not used’ bits (Nu) are accessible by the microprocessor but the use of these bits by software is not
recommended.
IX.1 - InitializationBlock in External Memory
Descriptor Address
Channel
Address
IBA+00
IBA+02
IBA+04
IBA+06
IBA+08
IBA+10
IBA+12
IBA+14
bit15
bit8
bit7
bit0
Not used
Transmit Descriptor Address (TDA Low)
Not used RDA High
Receive Descriptor Address (RDA Low)
Not used TDA High
Transmit Descriptor Address (TDA Low)
Not used RDA High
Receive Descriptor Address (RDA Low)
TDA High
T
R
T
CH 0
CH1
R
CH 2
to
CH30
IBA+16
to
IBA+246
IBA+248
IBA+250
IBA+252
IBA+254
Not used
Transmit Descriptor Address (TDA Low)
Not used RDA High
Receive Descriptor Address (RDA Low)
TDA High
T
CH 31
R
When Direct Memory Access Controller receives Start from oneof 64 channels,it readsinitialization block
immediately to know the first addressof the first descriptor for this channel.
Bit 0 of Transmit Descriptor Address (TDA Low) and bit 0 of Receive Descriptor Address (RDALow), are
at ZERO mandatory. This Least Significant Bit is not used by DMA Controller, The shared memory is
always a 16 bit memory for the DMAController.
N.B. If several descriptors are used to transmit one frame then before transmitting frame, DMA Controller
stores the address of the first Transmit Descriptor Address into this Initialization Block.
93/101
STLC5465B
IX - EXTERNAL REGISTERS (continued)
IX.2 - Receive Descriptor
This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory
size only.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
RDA+00
RDA+02
RDA+04
RDA+06
RDA+08
RDA+10
IBC
EOQ
Size Of the Buffer (SOB)
RBA High (8 bits)
Not used
Receive Buffer Address Low (16 bits)
Not used
NRDA High (8 bits)
Next Receive Descriptor Address Low (16 bits)
OVF FCRC Number of Bytes Received (NBR)
FR
ABT
The 5 first words located in shared memory to RDA+00 from RDA+08 are written by the microprocessor
and read by the DMAC only. The 6th word located in shared memory in RDA+10 is written by the DMAC
only during the frame reception and read by the microprocessor.
SOB : Size Of the Buffer associated to descriptor up to 2048 words (1 word = 2 bytes).
If SOB = 0, DMAC goes to next descriptor.
RBA : Receive Buffer Address. LSB of RBALow is at Zero mandatory.
RDA : Receive Descriptor Address.
NRDA : Next Receive Descriptor Address. LSB of NRDALow is at Zero mandatory.
NBR : Number of Bytes Received (up to 4096).
IX.2.1 - Bits written by the Microprocessor only
IBC
: Interruptif the buffer has been completed.
IBC=1, the DMAC generates an interrupt if the buffer has been completed.
EOQ : End Of Queue.
EOQ=1, the DMACstops immediately its receptiongeneratesan interrupt(HDLC = 1 in IR) and
waits a command from the HRCR (HDLC Receive Command Register).
EOQ=0, the DMAC continues.
IX.2.2 - Bits written by the Rx DMAC only
FR
1
ABT
OVF
FCRC
Definition
0
0
0
0
0
0
0
1
0
The frame has been received without error. The end of frame is in this buffer.
The frame has been received with false CRC.
1
0
If NBR is different to 0, the buffer related to this descriptor is completed.The end
of frame is not in this buffer.
0
0
0
1
0
0
0
0
If NBR is equal to 0, the Rx DMAC is receiving a frame.
ABORT. The received frame has been aborted by the remote transmitter or the
local microprocessor.
0
0
1
1
1
0
0
1
OVERFLOW of FIFO. The received frame has been aborted.
The received frame had not an integer of bytes.
IX.2.3 - Receive Buffer
Each receive buffer is defined by its receive descriptor.
The maximum size of the bufferis 2048 words (1 word=2 bytes)
15
8
7
0
RBA
SECOND BYTE LOCATION
FIRST BYTE LOCATION
THIRD BYTE LOCATION
LAST - 1 BYTE LOCATION
RBA+SOB-2
LAST BYTE LOCATION
AVAILABLE in the Receive Buffer
AVAILABLE in the Receive Buffer
Note: for Motorola processors, a swap may be necessaryto read/write the Receive Buffer.
94/101
STLC5465B
IX - EXTERNAL REGISTERS (continued)
IX.3 - TransmitDescriptor
This transmitdescriptor is located in shared memory. The quantityof descriptorsis limited by the memory
size only.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TDA+00 BINT BOF
TDA+02
EOF
EOQ
Number of Bytes to be Transmitted (NBT)
Not used
CRC PRI
C
TBA High (8 bits)
TDA+04
TDA+06
TDA+08
Transmit Buffer Address Low (16 bits)
Not used
NTDA High (8 bits)
Next Transmit Descriptor Address Low (16 bits)
TDA+10
CFT
ABT
UND
The 5 first words located in shared memory to TDA+00 from TDA+08 are written by the microprocessor
and read by the DMAC only. The 6th word located in shared memory in TDA+10 is written by the DMAC
only during the frame reception and read by the microprocessor.
NBT : Number of Bytes to be transmitted(up to 4096).
TBA
: Transmit Buffer Address. LSB of TBALow is at Zero mandatory.
TDA : Transmit Descriptor Address.
NTDA : Next Transmit Descriptor Address. LSB of NTDALow is at Zero mandatory.
IX.3.1 - Bits written by the Microprocessor only
BINT : Interruptat the end of the frame or when the buffer is become empty.
BINT = 1,
if EOF = 1 the DMAC generatesan interruptwhen the frame has been transmitted ;
if EOF = 0 the DMAC generatesan interruptwhen the buffer is become empty.
BINT = 0, the DMAC does not generatean interrupt during the transmission of the frame.
BOF : BeginningOf Frame
BOF=1,thetransmitbufferassociatedtothistransmitdescriptorcontainsthebeginningofframe.
The DMA Controller will store automatically the current descriptor address in the Initialization
Block.
BOF = 0, the DMA Controller will not store the current descriptor address in the Initialization
Block.
EOF : End Of Frame
EOF = 1,the transmit buffer associated to this transmit descriptor contains the end of frame.
EOF = 0,the transmit buffer associated to this transmit descriptor does not contain the end of
frame.
EOQ : End Of Queue
EOQ = 1, the DMAC stops immediately its transmission, generates an interrupt (HDLC = 1 in
IR) and waits a command from the HTCR (HDLC Transmit Command Register).
EOQ= 0, the DMAC continues.
CRCC : CRC Corrupted
CRCC = 1,at the end of this frame the CRC will be corruptedby the Tx HDLC Controller.
PRI
: Priority Class 8 or 10
PRI = 1, if CSMA/CR is validated for this channel, the priority class is 8.
PRI = 0, if CSMA/CR is validated for this channel the priority class is 10.
(see Register CSMA)
95/101
STLC5465B
IX - EXTERNAL REGISTERS (continued)
IX.3.2 - Bits written by the DMAC only
CFT
ABT
: Frame correctly transmitted
CFT = 1, the Frame has been correctly transmitted.
CFT = 0, the Frame has not beencorrectly transmitted.
: FrameTransmitting Aborted
ABT = 1, the frame has been aborted by the microprocessor during the transmission.
ABT = 0, the microprocessor has not aborted the frameduring the transmission.
UND : Underrun
UND = 1, the transmit FIFO has not been fed correctly during the transmission.
UND = 0, the transmit FIFO has been fed correctly during the transmission.
IX.3.3 - Transmit Buffer
Each transmit buffer is defined by its transmit descriptor.
The maximum size of the bufferis 2048 words (1 word=2 bytes)
15
8
7
0
TBA
SECOND BYTE TO TRANSMIT
FIRST BYTE TO TRANSMIT
THIRD BYTE TO TRANSMIT
TBA + x ;
NBT is odd : x = NBT - 1
NBT is even : x = NBT - 2
LAST BYTE TO TRANSMIT
if NBT is even
LAST BYTE TO TRANSMIT
if NBT is odd
Note: for Motorola processors, a swap may be necessaryto read/write the Receive Buffer.
IX.4 - Receive & Transmit HDLC Frame Interrupt
bit15
bit8 bit7
bit 0
CFT/CFR BE/BF HALT EOQ RRLF/ERF
NS
0
Tx
A4
A3
A2
A1
A0
0
0
0
This word is locatedin the HDLC interruptqueue ; IQSR Registerindicates the size of this HDLC interrupt
queue located in the external memory.
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the status word of the frame
which has been transmitted or received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generatean interrupt (IR Register).
When the microprocessorhas read the status word, it puts this bit at ‘0’ to acknowledgethe new
status. This location becomes free for the InterruptController.
Transmitter
Tx
: Tx = 1, Transmitter
A4/0 : Tx HDLC Channel 0 to 31
RRLF : Ready to Repeat Last Frame
In consequenceof eventsuchas AbortCommandHDLC, Controlleris waiting Startor Continue.
EOQ : End of Queue
The Transmit DMA Controller (or the Receive DMA Controller) has encountered the current
Descriptor with EOQ at ”1”. DMAController is waiting ”Continue” from microprocessor.
HALT : TheTransmitDMAControllerhasreceivedHALTfromthemicroprocessor;itis waiting”Continue”
from microprocessor.
BE
: Buffer Empty
If BINT bit of Transmit Descriptor is at ‘1’, the Transmit DMAController puts BE at ”1” when the
bufferhas been emptied.
CFT
: Correctly Frame Transmitted
A frame has been transmitted. This status is provided only if BINT bit of Transmit Descriptor is
at ‘1’. CFT is located in the last descriptor if severaldescriptors are used to define a frame.
96/101
STLC5465B
IX - EXTERNAL REGISTERS (continued)
Receiver
Tx
: Tx = 0, Receiver
A4/0 : Rx HDLC Channel 0 to 31
ERF : Errordetected on Received Frame
An error such as CRC not correct, Abort, Overflow has been detected.
EOQ : End of Queue
The receive DMA Controller has encounteredthe current receive Descriptor with EOQ at ”1”.
DMAController is waiting ”Continue” from microprocessor.
HALT : The Receive DMAController has received HALT or ABORT (on the outside of frame) from the
microprocessor; it is waiting ”Continue” from the microprocessor.
BE
: Buffer Filled
If IBC bit of Receiver Descriptor is at ‘1’, the Receive DMAController puts BF at”1” when it has
filled the current buffer with data from the received frame.
CFR : Correctly Frame Received
Areceiveframeisended witha correctCRC. Theend oftheframe islocatedin thelastdescriptor
if several Descriptors.
IX.5 - Receive Command / Indicate Interrupt
IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0
Time Stamping not validated (bit of GCR Register)
bit15
bit8
bit7
Nu
bit 0
NS
Nu
S1
S0
G0
A2
A1
A0
Nu
C6/A C5/E C4/S1 C3/S2 C2/S3 C1/S4
This word is located in the Command/Indicate interrupt queue ; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has
been received.
if NS = 1, the Interrupt Controller puts INTFOV bit at ‘1’ to generate an interrupt (IR Interrupt
Register).
When the microprocessorhas read the status word, it puts this bit at ‘0’ to acknowledgethe new
status. This location becomes free for the InterruptController.
S0/S1 Source of the event:
S1
0
S0
0
G0
0
Word stored in shared memory
Primitive C1/6 received from GCI Multiplex 0 corresponding to DIN4
Primitive C1/6 received from GCI Multiplex 1 corresponding to DIN5
0
0
1
0
1
0
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 0 without
outgoing to DOUT4
0
1
1
1
1
0
0
1
1
0
1
X
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 1 without
outgoing to DOUT5
AIS detected during more 30 ms from any input timeslot and switched to B1, B2
channels (16 bits) of the GCI 0 (DOUT4) in transparent mode or not
AIS detected during more 30 ms from any input timeslot and switched to B1, B2
channels (16 bits) of the GCI 1 (DOUT5) in transparent mode or not.
Reserved
97/101
STLC5465B
IX - EXTERNAL REGISTERS (continued)
G0
: This bit defines one of two GCI y (DIN4/DOUT4 or DIN5/DOUT5).
G0 = 0, GCI0 (DIN4/DOUT4) is the source.
G0 = 1, GCI1 (DIN5/DOUT5) is the source.
A2/0 : GCI Channel 0 to 7 belongingto GCI 0 or GCI 1.
C6/1 : New Primitive received twice consecutively. Case of S0=S1=0.
A, E, S1/S4bits received twice consecutively.Case of S0 = 1 S1 = 0.
Bit0/5 are not Significant when S0 = 0, S1 = 1.
IX.5.2 - Receive Command / Indicate Interrupt when TSV = 1
Time Stamping validated (bit of GCR Register)
bit15
bit8
A0
bit7
Nu
T7
bit 0
NS
Nu
Nu
Nu
G0
A2
A1
T9
Nu
T6
C6/A C5/E C4/S1 C3/S2 C2/S3 C1/S4
T15
T14
T13
T12
T11
T10
T8
T5
T4
T3
T2
T1
T0
These two words are locatedin the Command/Indicateinterrupt queue.
First word see definitionabove.
T0/15: binary counter value when a new primitive is occured.
IX.6 - Receive Monitor Interrupt
IX.6.1 - Receive Monitor Interrupt when TSV = 0
TSV : Time Stamping not Validated (bit of GCR Register)
bit15
bit8
bit7
bit 0
L
NS
G0
A2
A1
A0
ODD
M4
A
F
M18 M17 M16 M15 M14 M13 M12 M11
M8
M7
M6
M5
M3
M2
M1
These two words are transferredinto the Monitor interruptqueue ; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the InterruptController stores two new bytes M1/8 and M11/18 then puts NS bit at ‘1’
when it writes the status of these two bytes which has been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generatean interrupt (IR Register).
G0
L
: G0 = 0, GCI 0 correspondingto DIN4 input and DOUT4 output.
G0 = 1, GCI 1 correspondingto DIN5 input and DOUT5 output.
: Last byte
L=1, two cases:
if ODD = 1, the following word of the InterruptQueue contains the Last byte of message
if ODD =0, the previous word of the Interrupt Queue(concerningthis channel) containsthe Last
byte of message.
L = 0, the followingword and the previousword does not containsthe Last byte of message.
F
A
: First byte
F=1, the following word contains the First byte of message.
F=0, the following word does not contain the First byte of message.
: Abort
A=1, Receivedmessage has been aborted.
98/101
STLC5465B
IX - EXTERNAL REGISTERS (continued)
ODD : Odd byte number
ODD = 1, one byte has been written in the following word.
ODD = 0, two bytes have been written in the following word.
In case of V* protocol ODD,A,F,Lbits are respectively 1,0,1,1.
M1/8 : New Byte received twice consecutivelyif GCI Protocol has been validated.
Byte received once if V* Protocol has been validated.
M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated.
This byte is at ”1” in case of V* protocol.
IX.6.2 - Receive Monitor Interrupt when TSV = 1
TSV : Time Stamping Validated (bit of GCR Register)
bit15
bit8
bit7
bit 0
NS
G0
A2
A1
A0
ODD
M4
T3
0
A
M3
T2
0
F
M2
T1
0
L
M1
T0
0
M18 M17 M16 M15 M14 M13 M12 M11
M8
T7
0
M7
T6
0
M6
T5
0
M5
T4
0
T15
0
T14
0
T13
0
T12
0
T11
0
T10
0
T9
0
T8
0
These four words are located in the Monitor interrupt queue ; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the InterruptController stores two new bytes M1/8 and M11/18 then puts NS bit at ‘1’
when it writes the status of these two bytes which has been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generatean interrupt (IR Register).
G0
L
: G0 = 0, GCI 0 correspondingto DIN4 input and DOUT4 output.
G0 = 1, GCI 1 correspondingto DIN5 input and DOUT5 output.
: Last byte
L=1, two cases:
if ODD = 1, the following word of the InterruptQueue contains the Last byte of message
if ODD =0, the Last byte of message has been stored at the previous access of the Interrupt
Queue (concerning this channel).
L=0, the following word and the previous word does not contain the Last byte of message.
F
A
: First byte
F=1, the following word contains the First byte of message.
F=0, the First byte of message is not the following word.
: Abort
A=1, Receivedmessage has been aborted.
ODD : Odd byte number
ODD = 1, one byte has been written in the following word.
ODD = 0, two bytes have been written in the following word.
M1/8 : New Byte received twice consecutivelyif GCI Protocol has been validated.
Byte received once if V* Protocol has been validated.
M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated.
This byte is at ”1” in case of V* protocol.
T15/0 : Binary counter value when a new primitive is occurred.
99/101
STLC5465B
X - PQFP160 PACKAGE MECHANICAL DATA
Millimeters
Dimensions
Inches
Typ.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
B
4.07
0.160
0.25
3.17
0.010
0.125
0.009
0.005
1.219
1.098
3.42
3.67
0.38
0.135
0.144
0.015
0.009
1.238
1.106
0.22
C
0.13
0.23
D
30.95
27.90
31.20
28.00
25.35
0.65
31.45
28.10
1.228
1.102
0.998
0.026
1.228
1.102
0.998
0.0315
0.063
D1
D3
e
E
30.95
27.90
31.20
28.00
25.35
0.80
31.45
28.10
1.219
1.098
1.238
1.106
E1
E3
L
0.65
0.95
0.026
0.0374
L1
K
1.60
0o (Min.), 7o (Max.)
100/101
STLC5465B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
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http://www.st.com
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