STV-USB/CIF-R01_技术文档

VV5410 & VV6410

®

Mono and Colour Digital Video CMOS Image Sensors

The VV5410/VV6410 are multi format digital output imaging

devices based on STMicroelectronics’s unique CMOS

sensor technology. Both sensors require minimal support

circuitry.

Key Features

•

3.3V operation

Multiple video formats available

Pan tilt image feature

VV5410 (monochrome) and VV6410 (colourised) produce

digital video output. The video streams from both devices

contain embedded control data that can be used to enable

frame grabbing applications as well as providing input data

for the external exposure controller.

Sub sampled image full FOV feature

On board 10 bit ADC

On board voltage regulator

Low power suspend mode for USB systems

Automatic black and dark calibration

On board audio amplifier

The pixel array in VV6410 is coated with a Bayer colour

pattern. This colourised sensor can interface to a range of

STMicroelectronics co-processors. A chipset comprising

VV6410 and STV0657 will output 8bit YUV or RGB digital

video. A USB camera can be realised by partnering VV6410

with STV0672. Finally a high quality digital stills camera can

be produced by operating VV6410 with STV0680B-001.

Please contact STMicroelectronics for ordering information

on all of these products.

I2C communications

Applications

•

PC camera

Personal digital assistant

Mobile video phones

Digital stills cameras

Both VV5410 and VV6410 are initialised in a power saving

mode and must be enabled via I2C control before they can

produce video. The I2C allows the master coprocessor to

reconfigure the device and control exposure and gain

settings.

Speciﬁcations

USB systems are catered for with an ultra low power, pin

driven, suspend mode.

Effective image sizes after

colour processing

352 x 288 (CIF,PAL)

176 x 144 (QCIF)

The on board regulator can supply sufficient current drive to

power external components, (e.g. the video coprocessor).

Pixel resolution

Pixel size

up to 356 x 292

7.5µm x 6.9µm

2.73mm x 2.04mm

+81dB

Functional block diagram

Array size

SRAM LINE STORE

Exposure control

Analogue gain

SNR

DATA

READOUT

STRUCTURE

+12dB (recommended max)

c.56dB

FST

LST

QCK

X-DECODER

COLUMN ADC

Random Noise

Sensitivity (Green channel)

Dark Current

VFPN

1.17mV

DIGITAL

CONTROL

LOGIC

2.1V/lux.sec

46mV/sec

SUSPEND

OEB

Y-

PIXEL ARRAY

DECODER

1.2mV

Supply voltage

Supply current

3.0V- 6.0V DC +/− 10%

SCL

SDA

26.2mA (max,CIF@30fps)

85µA (suspend mode)

VOLTAGE REFERENCES,VOLTAGE REGULATORS AND AUDIO AMP CIRCUITRY

o

Operating temperature

(ambient)

0 C - 40 C

Package type

36pin CLCC

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VV5410 & VV6410

Table of Contents

1.

2.

Document Revision History ............................................................................................ 4

Introduction ...................................................................................................................... 5

2.1 Overview ........................................................................................................................................5

2.2 Exposure Control............................................................................................................................5

2.3 Digital Interface ..............................................................................................................................5

2.4 Other Features ...............................................................................................................................7

3.

Operating Modes.............................................................................................................. 9

3.1 Video Timing ..................................................................................................................................9

3.2 Pixel Array....................................................................................................................................10

3.3 X-offset and Y-offset.....................................................................................................................11

3.4 QCIF Output Modes .....................................................................................................................16

4.

Black Offset Cancellation.............................................................................................. 18

Dark Offset Cancellation................................................................................................ 20

Exposure Control ........................................................................................................... 21

Timed Serial Interface Parameters ............................................................................... 24

Digital Video Interface Format ...................................................................................... 27

5.

6.

7.

8.

8.1 General description ......................................................................................................................27

8.2 Embedded control data ................................................................................................................28

8.3 Video timing reference and status/configuration data ..................................................................31

8.4 Detection of sensor using data bus state .....................................................................................48

8.5 Resetting the Sensor Via the Serial Interface ..............................................................................48

8.6 Resetting the Sensor Via the RESETB pin ..................................................................................48

8.7 Resynchronising the Sensor Via the RESETB pin configured as SINB .......................................48

8.8 Power-up, Low-power and Sleep modes .....................................................................................50

8.9 Suspend mode .............................................................................................................................52

8.10 Data Qualification Clock, QCK .....................................................................................................52

9.

Serial Control Bus.......................................................................................................... 60

9.1 General Description......................................................................................................................60

9.2 Serial Communication Protocol....................................................................................................60

9.3 Data Format .................................................................................................................................60

9.4 Message Interpretation.................................................................................................................61

9.5 The Programmers Model..............................................................................................................61

9.6 Types of messages ......................................................................................................................82

9.7 Serial Interface Timing .................................................................................................................85

10. Clock Signal.................................................................................................................... 86

11. Other Features................................................................................................................ 87

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11.1 Audio Amplifier .............................................................................................................................87

11.2 Voltage Regulators.......................................................................................................................89

11.3 Valid Supply Voltage Configurations............................................................................................89

11.4 Programmable Pins......................................................................................................................91

12. Characterisation Details ................................................................................................ 92

12.1 VV5410/VV6410 AC/DC Specification .........................................................................................92

12.2 VV5410/VV6410 Optical Characterisation Data...........................................................................92

12.3 VV5410/VV6410 Power Consumption .........................................................................................94

12.4 Digital Input Pad Pull-up and Pull-down Strengths.......................................................................94

13. Pixel Defect Specification.............................................................................................. 95

13.1 Pixel Fault Definitions...................................................................................................................95

13.2 Stuck at White Pixel Fault ............................................................................................................95

13.3 Stuck at Black Pixel Fault.............................................................................................................95

13.4 Column / Row Faults....................................................................................................................95

13.5 Image Array Blemishes ................................................................................................................96

14. Pinout and pin descriptions.......................................................................................... 98

14.1 36pin CLCC Pinout Map...............................................................................................................98

15. Package Details (36pin CLCC) .................................................................................... 101

16. Recommended VV5410/6410 support circuit............................................................. 102

17. Evaluation kits (EVK’s) ................................................................................................ 103

18. Ordering details............................................................................................................ 104

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1. Document Revision History

Revision

Date

Comments

1.0

2.0

13/06/2000

06/07/2000

•

Original release

Package drawing and pin description updated

Optical characterisation data added

Audio description extended

Pixel defect specification added

Product numbering updated

Reference design for BGA packaged 410 added

Gain ceiling recommendation

2.1

3.0

04/09/2000

28/09/2000

Remove all reference to BGA package option

Product maturity moves to Mat29 therefore d/s moves to Release3.0

Table 1 : Document Revision History

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VV5410 & VV6410

2. Introduction

2.1 Overview

VV5410/VV6410 is a CIF format CMOS image sensor. The VV5410 sensor is the basic monochrome device and VV6410 is the

colourised variant. The operation of VV5410 and VV6410 is very similar but any differences will be identified and explained.

VV6410 can output digital colourised pixel data at frame and line rates compatible with either NTSC or PAL video standards.

VV5410 and VV6410 contain the same basic video timing modes. Table 2 summarises these video modes.

The various operating modes are detailed in Section 3.

Important: VV5410 and VV6410’s output video data stream only contains raw data. A master co-processor is required to

generate a video waveform that can be displayed on a VDU

System

Clock

Divisor

Lines

per

Frame

Input Clock

(MHz)

Line Time

Frame Rate

(fps)

Mode

Image Size

(µs)

Note

8.00

8

4

2

180 x 148

356 x 292

306 x 244

356 x 292

250.00

208.00

160

320

525

625

25.00000

30.04807

60.09614

25.00000

30.04807

29.97003

25.00014

QCIF - 25 fps

QCIF - 30 fps

QCIF - 60 fps

CIF - 25 fps

16.00

104.00

16.00

125.00

16.00

104.00

CIF - 30 fps

28.636360 / 2.5

35.46895 / 2.5

63.555564

63.999639

NTSC (3.2 fsc)

PAL (3.2 fsc)

Table 2 : Video Modes

Note: The user can also provide a 24 MHz clock, rather than a 16 MHz clock, for the QCIF-60fps, CIF-25fps and CIF-30fps

modes, which the sensor then internally divides by 1.5, (see data_format[22]), to give an effective input clock frequency of 16

MHz.

2.2 Exposure Control

VV5410/VV6410 does not include any form of automatic exposure and/or gain control. Thus to produce a correctly exposed

image the integration period for the pixels, in the sensor array, an exposure control algorithm must be implemented externally.

The new exposure values are written to the sensor via the serial interface.

2.3 Digital Interface

The sensor’s offers a very flexible digital interface, the main components of which are listed below:

1. A tri-stateable 5-wire data bus (D[4:0]) for sending both video data and embedded timing references.

2. 4-wire and 8-wire data bus alternatives available. If the 8-wire option is selected then the FST/LST pins are reconﬁgured to

output data information.

3. A data qualiﬁcation clock, QCK, which can be programmable via the serial interface to behave in a number of different ways

(Tri-stateable).

4. A line start signal, LST (Tri-stateable).

5. A frame start signal, FST (Tri-stateable).

6. OEB tri-states all 5 data bus lines, D[4:0], the qualiﬁcation clock, QCK, LST, FST and D[7].

7. A 2-wire serial interface (SDA,SCL) for controlling and setting up the device.

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Introduction

SDA

SCL

OEB

OFFSET

IMAGE

FORMAT

EXPOSURE

CONTROL

SERIAL

INTERFACE

CLKI

CANCELLATION

RESETB

D[4:0]

QCK

OUTPUT

FORMAT

Y-

PHOTO DIODE

ARRAY

LST

DECODER

FST

Digital Logic

Analogue Core

Column ADC

X-Decoder

Readout

Structure

VREGS,

AUDIO AMP.,

& REFS

SRAM line store

Figure 1 : Block Diagram of VV5410/VV6410 Image Sensor (5-wire output)

2.3.1 Digital Data Bus

Along with the pixel data, codes representing the start and end of fields and the start and end of lines are embedded within the

video data stream to allow a co-processor to synchronise with video data the camera module is generating. Section 8. defines the

format for the output video data stream.

2.3.2 Frame Grabber Control Signals

To complement the embedded control sequences the data qualification clock (QCK), the line start signal (LST) and the field start

signal (FST) signals can be independently set-up as follows:

1. Disabled

2. Free-running.

3. Qualify only the control sequences and the pixel data.

4. Qualify the pixel data only

There is also the choice of two different QCK frequencies where one is twice the frequency of the other.

1. Fast QCK: the falling edge of the clock qualiﬁes every 8, 5 or 4 bit blocks of data that makes up a pixel value.

2. Slow QCK: the rising edge qualiﬁes 1st, 3rd, 5th, etc. blocks of data that make up a pixel value while the falling edge quali-

ﬁes the 2nd, 4th, 6th etc. blocks of data. For example in 4-wire mode the rising edge of the clock qualiﬁes the most signiﬁ-

cant nibbles while the falling edge of the clock qualiﬁes the least signiﬁcant nibbles.

2.3.3 2-wire Serial Interface

The 2-wire serial interface provides complete control over sensor setup and operation. Two serial interface broadcast addresses

are supported. One allows all sensors to be written to in parallel while the other allows all sensors and co-processors to be written

to in parallel.

Section 9. defines the serial interface communications protocol and the register map of all the locations which can be accessed

via the serial interface.

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2.3.4 Sensor/Co-processor Interface Options

There are 3 main ways of interfacing to the VV5410/VV6410 sensor based on the above signals:

1. The colour co-processor supplies the sensor clock, CLKI, and uses the embedded control sequences to synchronise with

the frame and line level timings. Thus the host and sensor are running off derivatives of the same fundamental clock. To

allow the co-processor to determine the best sampling position of the video data, during its power-up sequence the sensor

outputs a 101010... sequence on each of its data bus lines for the host to lock on to.

D[4:0]

VV5410/

VV6410

Sensor

CLKI

SDA

Co-processor

1.

SCL

2. The colour co-processor supplies the sensor clock, CLKI, and uses a free-running QCK supplied by the sensor to sample

the incoming video data stream. The embedded control sequences are used to synchronise the frame and line level timings.

D[4:0]

VV5410/

CLKI

Co-processor

VV6410

Sensor

QCK

SDA

2.

SCL

3. The colour co-processor supplies the sensor clock, CLKI, and uses FST, LST and the data only mode for QCK to synchro-

nise to the incoming video data. Primarily intended for interfacing to frame grabbers.

D[4:0]

CLKI

QCK

VV5410/

VV6410

Sensor

LST

FST

Co-processor

3.

SDA

SCL

2.4 Other Features

2.4.1 Audio Ampliﬁer

Pins AIN and AOUTP & AOUTN are the input and outputs respectively for an audio amplifier.

2.4.2 Voltage Regulator

The on-chip voltage regulator requires only a few external components to form a fully functional voltage regulator to 3.3V.

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Introduction

2.4.3 Serial Interface Programmable Pins

The FST and QCK pins are re-configurable to follow the state of 2-bits in a serial register. The user could then use these control

bits to control a peripheral device, a motor or shutter mechanism for example.

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3. Operating Modes

3.1 Video Timing

The video format mode on power-up is CIF 30fps by default. After power-up the mode can be changed by a serial interface to

write to the video_timing register. The frame/field rate is also programmable via the serial interface. Bit [3] of serial register [16]

selects between 30 and 25 frames per second for the CIF modes and 60/50 fields per second for the Digital and Analog Timing

modes. Please note that the sensor can exit low power in ANY of the available video modes.

The number of video lines in each frame is the same (320) for both the CIF modes. The slower frame rate (25 fps) is implemented

by simply extending the line period from 416 pixel periods to 500 pixel periods.

Table 3 details the setup for each of the video timing modes. A serial write to serial register [16] will force the contents of other

registers in the serial interface to change to the appropriate values, regardless of their present state. If for example a different

data output mode is required than the default for a particular video mode, a write to the appropriate register after the mode has

changed will restore the desired value.

System

Clock

Video Data

Line

Length

Field Length Data Output

Mode

Video Mode

Clock (MHz)

Divisor

PAL (3.2 fsc)

NTSC (3.2 fsc)

CIF - 25 fps

28.636360 / 2.5

2

4

8

356 x 292

306 x 244

356 x 292

180 x 148

454

364

500

416

250

208

312/313

262/263

320

5-wire

35.46895 / 2.5

16.0

8.0

CIF - 30 fps

320

QCIF - 25 fps

QCIF - 30 fps

QCIF - 60 fps

160

8.0

160

16.0

160

Table 3 : Video Timing Modes

3.1.1 Arbitration registers

When the operating video mode is changed a number of serial registers are forced into new states. The complete list is as

follows:

Video mode selected/value automatically programmed

Arbitrated

PAL

NTSC

CIF 25fps

CIF 30fps

PTQCIF

30fps

SSQCIF

30fps

feature

25fps

line length

ﬁeld length

453

311

2

363

261

2

499

319

4

415

319

4

249

159

8

207

159

8

249

159

8

207

159

8

system clock divi-

sion

free running

qck_note1

yes

no

extra black

lines_note2

Table 4 : Arbitration registers

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Operating Modes

note1: The free running qck, slow by default, is enabled by writing 8’h04 to serial register [20].

note2: The contents of the extra black lines are enabled on to the data bus by setting bit [5] of serial register [17]. If bit [0] of serial

register [24] is reset, indicating that the preferred coprocessor device is not the VP3 device, (a STMicroelectronics coprocessor),

then the extra black lines are enabled by default regardless of the basic video mode selected.

The registers that control the image position within the pixel array and also the order in which the pixels are read out have not

been included in the table as their values are subject to a secondary series of registers. We will discuss the former in sections 2.2

and 2.3.

3.1.2 Input Clock Frequencies

It is recommended that a 16 MHz clock is used to generate CIF-25fps,CIF-30fps and QCIF-60fps and that an 8 MHz clock is used

to generate QCIF-25fps and QCIF-30fps, however the sensor can adapt to a range of other input frequencies and still generate

the required frame rates. For example, a 24 MHz clock can be used to generate CIF-30fps. By setting bit [7] of serial register [22]

the sensor can automatically divide the incoming clock by 1.5 by setting bit [7] of serial register [22], such that the internal clock

generator logic will still receive a 16 MHz clock.

Note that the clock division register is internally an 8 bit value, although the user may only program the lower nibble. The upper

nibble is reserved for setting the clock divisor as we change between primary video modes. The lower nibble can be programmed

to reduce the effective frame rate within each video mode.

The system clock divisor column in Table 5 assumes that the programmable pixel clock divisor is set to the default of 0,

implementing a divide by 1 of the internal pixel clock. Consider the following scenario where a user requires 15 fps CIF resolution

image. As can be seen there are a wide range of options to achieve the same result.

clk in

(MHz)

Divide by 3/2

enabled?

System clock

divisor

Pixel clock

divisor

pclk (MHz)

Field Rate

8

no

yes

no

4

1

2

15

12

16

24

yes

Table 5 : System clock divisor options

3.2 Pixel Array

The physical pixel array is 364 x 296 pixels. The pixel size is 7.5 µm by 6.9 µm. The image size for NTSC is 306 x 244 pixels, for

PAL and CIF it is 356 x 292 pixels, while for the QCIF modes the image size is 180 x 148 pixels. The remaining 4 physical

columns on each side of the PAL image size prevent columns 1 and 2 in PAL/CIF modes from being distorted by the edge effects

which occur when a pixel is close to the outer edge of the physical pixel array. Please note that these columns can be enabled as

part of the visible image if the user is operating the sensor in the pantilt QCIF mode.

Figure 3 shows how the 306 x 244 and 180 x 148 sub-arrays are aligned within the bigger 364 x 296 pixel array. The Bayer

colourisation pattern requires that the top-left corner of the pixel sub-array is always a Green 1 pixel. To preserve this Bayer

colour pattern the NTSC sub-array has been offset relative to the centre of the array. The QCIF size images are centrally

orientated.

Image read-out is very flexible. Sections 3.3.2 - describe the options available to the user. By default the sensor read out is

configured to be horizontally ‘shuffled’ non-interlaced raster scan. The horizontally ‘shuffled’ raster scan order differs from a

conventional raster in that the pixels of individual rows are re-ordered, with the odd pixels within a row read-out first, followed by

the even pixels. This ‘shuffled’ read-out within a line, groups pixels of the same colour (according to the Bayer pattern - Figure 2)

together, reducing cross talk between the colour channels. This option is on by default and is controllable via the serial interface.

The horizontal shuffle option would normally only be selected with the colour sensor variant, VV6410.

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VV5410 & VV6410

Odd

Even

Columns Columns

(1,3,5,...) (2, 4, 6,...)

Odd Rows

(5, 7, 9,...)

Green 1 Red

Blue Green 2

Even Rows

(4, 6, 8,...)

Figure 2 : Bayer Colourisation Pattern (VV6410 only)

3.3 X-offset and Y-offset

The image information is retrieved from the pixel array via a 2 dimensional address. The x and y address busses count from a

starting point described by x-offset, y-offset up to a maximum count in x and y that is determined by the image size. The order of

this count and the count step size is dependent upon the special image format parameters described below. The detailed control

of the x and y address counters is entirely handled by the sensor logic

As can be seen in Figure 3 the visible array size is 364 columns by 296 rows. The PAL and CIF images are sized, 356 columns

by 292 rows, thus we have a “border” of visible pixels that we do not read out if either of these modes are selected.

The images that are read out of the sensor are always “centred” on the array, therefore we allow a border of 4 columns at either

end of the image in the x-direction and a border of 2 rows at the top and bottom of the image in the y-direction. The pantilt QCIF

and NTSC video modes are similarly centred within the full size array.

For all the modes except the pantilt QCIF the x and y offset coordinates are fixed. If the user selects the pantilt QCIF mode then

they may specify x and y-offsets in the range:

•

(xoffset >= 1) and (xoffset <= 185)

(yoffset >= 5) and (yoffset <= 149)

The sensor will automatically clip values outwith the specified ranges. The y addresses less than 5 are reserved for the sensor

black lines and the y address greater than 296 are reserved for the sensor dark lines. Neither the black lines nor the dark lines

contain visible image data

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Operating Modes

7

8

1

2

3

4

5

6

5

6

7

8

Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green

Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green

9

Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green

10

24 Pixels

26 Pixels

1, 2, 3, 4, 5, 6,...

..., 361, 362, 363, 364

306 Pixels

180 Pixels

88 Pixels

356 Pixels

364 Pixels

295

The colour dyes included in this

diagram are only applicable to

VV6100. The monochrome device

VV5410 has exactly the same

readout structure and array size as

VV6410 - but no colourised pixels

Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green

296

297

298

Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green

299

300

Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green

363 364

357 358 359 360 361 362

Figure 3 : Image Readout Formats

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3.3.1 Image readout parameters

The following parameters are available to process the sensor readout:

•

Shuffle horizontal readout, enabled by setting bit [7] of serial register [17]

Mirror horizontal readout, enabled by setting bit [3] of serial register [22]

Shuffle vertical readout, enabled by setting [2] or serial register [22]

Flip vertical readout, enabled by setting [4] of serial register [22]

The effect of each of these parameters is probably best described via a series of diagrams, see sections 3.3.2 - below.

Although all the above features may be used in conjunction with one another we will only display one special image readout

parameter at any one time.

3.3.2 Horizontal shufﬂe

Figure 5 is the reference figure that shows the image readout without any of the optional image parameters, shuffle or mirror,

selected. Figure 5 shows how the image will appear if the horizontal shuffle bit has been selected. Note that the even columns,

(column 2,4,6 etc), are read out first followed by the odd columns, (1,3,5,7 etc).‘

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

R

Where G - Green and R - Red

Figure 4 : Standard Image Readout

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Operating Modes

G

R

G

R

G

R

G

R

G

R

G

R

G

Where G - Green and R - Red

Figure 5 : Horizontal Shufﬂe Enabled

3.3.3 Horizontal mirror

Figure 6 shows the output image with the horizontal mirror feature enabled. Note that the columns are read out in reverse order.

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

R

G

Where G - Green and R - Red

Figure 6 : Horizontal mirror enabled

3.3.4 Vertical Flip

Figure 7 shows the output image with the vertical flip feature enabled. Note that the even rows (rows 2,4,6 etc), are read out first

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VV5410 & VV6410

followed by the odd rows, (rows 1,3,5 etc)

B

G

B

G

B

G

B

G

B

G

B

Where G - Green and B - Blue

Figure 7 : Vertical Shufﬂe enabled

3.3.5 Vertical Flip

Figure 3.4 shows the output image with the vertical flip feature enabled. Note that the rows are read out in reverse order.

B

G

B

G

B

G

B

G

B

G

B

G

B

G

B

G

B

G

B

Where G - Green and B - Blue

Figure 8 : Vertical Flip enabled

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Operating Modes

3.4 QCIF Output Modes

VV5410/VV6410 has two QCIF output modes, pan/tilt QCIF (ptQCIF) and sub sampled QCIF (ssQCIF), both of which have the

same output format. The data contained within the active QCIF image differs between the sub sampled and pan tilt modes. As

the QCIF mode contains a quarter of the data of the CIF mode, the effective pixel clock can be run at a quarter of the rate. This

means that in CIF mode a system clock of 16MHz will produce a field rate of 30fps, whereas in QCIF mode a system clock of only

8MHz is required to produce the same field rate. Note that the sensor divides the system clock internally by 4 for CIF mode and 8

for QCIF mode. If the user supplied the sensor with a 16Mhz system clock and selected QCIF mode then a field rate of 60fps is

possible.

3.4.1 Pan/Tilt QCIF

In this mode the QCIF image is generated by outputting a cropped portion of the CIF image as illustrated in Figure 9. When the

pan-tilt QCIF video mode is initially selected the image will be horizontally and vertically justified in the within the full size array

(364 pixels by 292 pixels). The coordinates which define the top left corner of the QCIF portion of the array to be output are

defined by the x-offset & y-offset parameters in serial registers [88 - 91] inclusive.

y-offset

x-offset

QCIF Image

180 pixels

364 pixels

Figure 9 : Pan/Tilt QCIF Image Format

The x-offset and y-offset parameters are subject to minimum and maximum values which are set according to the video output

mode (horizontal shuffle etc). Any clipping (against a maximum) or clamping (against a minimum) will be automatically controlled

by the sensor logic. Regardless of whether any of the shuffle/mirror modes have been selected the user should always identify

the top left corner coordinates as the x-offset and y-offset. To preserve the Bayer pattern at the sensor output the first pixel image

of the image should always be green followed by red. If the x or y offsets are adjusted by a single step, i.e. adjust the x-offset from

n to n+1, then this pattern will be corrupted. The user should always write an odd number to the x and y offset registers and this

will preserve the Bayer pattern. The 5410, monochrome sensor is unaffected by such an adjustment to the x-offset coordinate, as

the pixels do not contain any colour information.

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3.4.2 Sub-Sampled QCIF

VV5410 & VV6410

In this mode the QCIF image is generated by sub-sampling the CIF image in groups of 4 to preserve the Bayer pattern with every

second group of pixels & lines skipped as illustrated in Figure 10. Although the former would not necessarily apply to a

monochrome sensor the same address sequence is preserved. VV5410 users should ignore the colour references in Figure 10.

Due to the crude nature of the sub-sampling, the resultant output image will be of inferior quality but contains full field of view and

is intended for use in gesture recognition applications or perhaps as a preview option before switching to pan tilt QCIF mode to

view the required scene region in more detail.

Green Red Green Red Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green Blue Green Blue Green

Green Red Green Red Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green Blue Green Blue Green

Green Red Green Red Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green Blue Green Blue Green

Green Red Green Red Green Red Green Red Green Red Green Red

Blue Green Blue Green Blue Green Blue Green Blue Green Blue Green

Bayer Colourised Pixel Array

Green Red

Blue Green

Green Red

Blue Green

Green Red

Blue Green

Green Red

Blue Green

Green Red

Blue Green

Green Red

Blue Green

Sub-Sampled Bayer Colourised Pixel Array

Figure 10 : Sub-Sampled QCIF Image Format

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Black Offset Cancellation

4. Black Offset Cancellation

In order to produce a high quality output image from VV6410 it is important to maximise the dynamic range of the video output.

This can be achieved by accurately controlling the video signal black level. Within the sensor array of VV6410 there are a number

of lines that are specified to be black, that is they are exposed to the incident light but they are always held in minimum exposure.

VV6410 also has a number of dark lines, that is lines that are integrated for the same length of time as the visible lines but the

pixels within these dark lines are shielded from incident light by an opaque material (e.g. metal 3). The diagram below shows

where the different types of lines that appear within the full array.

Dark Lines

Visible Pixel Array

Black Lines

364 pixels

Figure 11 : Physical position of Black and Dark Lines

VV5410/VV6410 can perform automatic black offset cancellation. VV5410/VV6410 contains an algorithm that monitors the level

of the designated black pixels and applies a correction factor, if required, to provide an ideal black level for the video stream.

The user can control the application of the offset cancellation parameter. The internally calculated offset can be applied to the

video stream or alternatively an externally calculated offset can be applied or finally there is the option of applying no offset at all.

Details of how to select the aforementioned modes can be found in subsubsection 9.5.5.

The black offset cancellation algorithm accumulates data from the centre 2 of the 4 physical black lines. The internal cancellation

algorithm uses a leaky integrator model to control the size of the calculated offset. The leaky integrator model takes as input the

current offset plus a shifted version of the error between the ideal black level and the current offset. The magnitude of the shift in

the error is programmable. It is also possible to control the range of pixel values that will inhibit a change in the calculated offset.

A narrow band (128 +/- 2 codes) or a wide band (128 +/- 4 codes) can be selected. If the latter is selected and the pixel average

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returned in the current field lies between 124 and 132 then the offset cancellation will remain unchanged.

Following a gain change, or when exitting low-power, sleep or suspend modes, the internal (19bit) offset register will be reset to

the default resulting in an automatic black offset of -64.

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Dark Offset Cancellation

5. Dark Offset Cancellation

VV5410/VV6410 performs dark line offset cancellation as well as black line offset cancellation. A dark line is shielded from

incident light by an opaque material such as metal 3 (as an example) but these lines will be exposed to incident light for the same

length of time as the visible pixels. If the dark pixels are completely shielded from light then no incident light should reach the

pixels and the pixels will produce the same digital code as the black pixels, i.e. 128 internally (therefore 64 externally). The

algorithm used to calculate the dark offset cancellation is identical to that used to calculate the black offset cancellation, however

the dark algorithm does assume that the dark pixels have already been black corrected therefore the target dark average is 64

thus the dark offset cancellation is 0 by default.

The dark offset cancellation algorithm is configured by the dark offset cancellation setup register, [46], see subsubsection 9.5.3.

The only parameter in this that is different from the corresponding table that configures the black offset cancellation algorithm is

the control bit, [bit2], that determines the number of dark lines that are to be used by the cancellation algorithm. It is possible to

select half of the total number of available dark lines to be used to calculate the dark offset cancellation setting. When the former

is selected the dark lines used by the algorithm are always preceeded by another dark line, thereby giving extra immunity from

damaging edge effects that may occur on lines close to the edge of the shield material.

It should be noted that the black and dark offset cancellation are completely independent. For example it is possible for the user

to select internal automatic black offset cancellation but to opt for no dark offset cancellation or indeed choose to perform the dark

offset cancellation externally.

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6. Exposure Control

6.1 Calculating Exposure Period

The exposure time, comprising coarse and fine components, for a pixel and the analogue gain are programmable via the serial

interface.

The coarse exposure value sets the number of complete lines a pixel exposes for, while the fine exposure sets the number of

additional pixel clock cycles a pixel integrates for. The sum of the two gives the overall exposure time for the pixel array.

Exposure Time = ((Coarse setting x Line Period) + (Fine setting)) x (CLKI clock period) x Clock Divider Ratio_note1

note1: Clock Divider Ratio = 1/(Basic Clock Division * Optional Pixel Clock Divisor)

Default Clock Divider Ratio as follows: (Optional Pixel Clock Divisor = 1)

•

PAL/NTSC - 1/2

CIF - 1/4

QCIF - 1/8

The maximum coarse and fine exposure settings are a function of the field and line lengths respectively. The maximum coarse

exposure is current field length - 1 and the maximum fine exposure is current line length - fixed offset, see below. If an exposure

value is requested that is beyond the maximum then the applied exposure setting will be clipped to the current maximum.

Video Mode

Fine Exposure Offset (pck’s)

NTSC

PAL

51

86

51

23

CIF

QCIF

Table 6 : Fine Exposure Offset

The current revision of VV5410/VV6410 in the following modes of operation:

VP3 mode (OFF), QCIF and PAL (Video mode)

has an error in the application of coarse exposure. Please contact STMicroelectronics for more details.

6.2 Gain Components

The analogue gain in VV5410/VV6410 is programmed via the 8 bit gain register[36]. The analogue gain comprises 2

components, capacitive gain, (set by the ms nibble), and current gain, (set by the ls nibble). It is strongly recommended that the

capacitive gain setting is left at the default value of 4’b1111. Table 7 details the available gain settings in 9bit, (PAL or NTSC),

and 10bit, (CIF or QCIF), modes. We assume that mode_select[24], bit1 is 0. gain[7:0] is the value programmed in register[36].

The ls nibble of the gain value is limited to 4’he, with 4’hf not permitted.

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Exposure Control

10bit ADC mode

9bit ADC mode

igain[3:0] cgain[5:0]

Overall

Gain

Overall

Gain

gain[7:0]

igain[3:0]

cgain[5:0]

gain[7:0]

8’hfe

8’hfd

8’fc

1 (0001₂)

2 (0010₂)

3 (0011₂)

4 (0100₂)

5 (0101₂)

6 (0110₂)

7 (0111₂)

8 (1000₂)

9 (1001₂)

10 (1010₂)

11 (1011₂)

12 (1100₂)

13 (1101₂)

14 (1110₂)

15 (1111₂)

63

8.000

5.333

8’hfe

8’hfd

8’fc

1 (0001₂)

2 (0010₂)

3 (0011₂)

4 (0100₂)

5 (0101₂)

6 (0110₂)

7 (0111₂)

8 (1000₂)

9 (1001₂)

10 (1010₂)

11 (1011₂)

12 (1100₂)

13 (1101₂)

14 (1110₂)

15 (1111₂)

31

8.000

5.333

4.000

8’hfb

8’hfa

8’hf9

8’hf8

8’hf7

8’hf6

8’hf5

8’hf4

8’hf3

8’hf2

8’hf1

8’hf0

3.200

8’hfb

8’hfa

8’hf9

8’hf8

8’hf7

8’hf6

8’hf5

8’hf4

8’hf3

8’hf2

8’hf1

8’hf0

3.200

2.667

2.2857

2.0000

1.7778

1.6000

1.4545

1.3333

1.2308

1.1429

1.0667

1.0000

2.2857

2.0000

1.7778

1.6000

1.4545

1.3333

1.2308

1.1429

1.0667

1.0000

Table 7 : Analogue Gain Settings

note: The relationship between the programmed gain value as written to register[36] and the igain (current gain) and

cgain (capacitive gain) is as follows:

igain

If mode_select[24], bit 1 is set then igain[3:0] is the inverse of gain[3:0], i.e. if gain[3:0] = 6, igain[3:0] = 9.

If mode_select[24], bit 1 is reset then igain[3:0] is the inverse of the mirror of gain[3:0], i.e. bit 3 of igain is the inverse of bit 0 of

gain, i.e. gain = 4 and igain = 13.

cgain

cgain is a 6 bit value therefore we have to pad the 4 bits of the gain register. In 10bit modes cgain[1:0] is fixed at 2’b11 and

cgain[5:2] is set to gain[7:4]. In the 9bit modes cgain[1:0] is also set to 2’b11, however cgain[5:2] is set to gain[7:4] divided by 2,

thus gain[7:4] = 4’b1111 gives cgain[5:0] = 6’b011111.

6.2.1 Recommended Gain Settings

To ensure optimum sensor performance it is recommended that the igain setting, controlled by the ls nibble of serial

register[36₁₀], be limited to 12.

6.3 Clock Division

Although the clock divisor register is an 8 bit register the user only has write access to the lower 4 bits as described above. The

upper 4 bits of the register are altered automatically when the video mode is changed by writing to Setup0[16] register. The upper

4 bits are pre-programmed as follows:

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Video mode

Register[37], bits[7:4]

Effective system clock divisor

CIF

QCIF

4’b0001

4’b0011

4’b0000

Divide CLKI/CLKIP by 4

Divide CLKI/CLKIP by 8

Divide CLKI/CLKIP by 2

PAL/NTSC

Table 8 : System Clock Divisor Options

6.4 Updating Exposure, Gain and Clock Division Settings

Although the user can write a new exposure, gain or clock division parameter at any point within the field the sensor will only

consume these new external values at a certain point. The exceptions to this behaviour are when the user has selected

immediate update of gain and clock division. If the user has selected the former then the new gain or clock division value will be

applied as soon as the serial interface message has completed. The fine and coarse exposure values are always written in a

“timed” manner. There are a number of “update pending” flags available to the user (see Status0 reg[2] for details) that allows the

user to detect when the sensor has consumed one of the timed parameters. In the next section of this document we will detail all

the timed parameters and describe when they are updated.

It is important to realise that there is a 1 frame latency between a new exposure value being applied to the sensor array and the

results of this new exposure value being read-out. The same latency does not exist for the gain value. To ensure that the effect of

the new exposure and gain values are coincident the sensor delays the application of the new gain value by approximately one

frame relative to the application of the new exposure value.

If the user is using the autoincrement option in the serial interface when writing a new series of exposure/gain and clock division

parameters then it is important to ensure that the sensor receives the complete message bunch before updating any of the

parameters. It is also important that the timed parameters are updated in the correct order, we will discuss this fully in the next

section. If an autoincrement message sequence is in progress but we have reached the point in the field timing where the gain

value would normally be updated, we actually inhibit the update. We inhibit the update to ensure that the gain change is not

passed to the sensor while a change in the exposure is still pending.

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Timed Serial Interface Parameters

7. Timed Serial Interface Parameters

The previous section, Exposure Control, introduced the concept of a “timed parameter”, that is information that is written via the

serial interface but will not be used immediately by the sensor, rather there will be a delay before the information is passed to the

internal registers (referred to as the working registers) from the serial interface registers (referred to as the shadow registers). It is

the contents of the working registers that will determine sensor behaviour.

The architecture of VV5410/6410 requires that many of the programmable registers are handled in such a manner. This section

will identify all these registers, describe what they are all used for and then go on to explain when they are all updated.

7.1 Listing and Categorizing the Parameters

The timed parameters are split into 6 categories as follows:

•

fine exposure

coarse exposure

clock division

gain

pan parameter

tilt parameter

video timing

There is a “pending” flag for each of the above categories. These flags are stored in Status0 Register[2]. If one of the flags is high

this indicates that the working register/s controlled by that flag have yet to be updated from the according shadow register/s. This

feedback information could be useful if a user is, for example, attempting to write an exposure controller. The status of the

pending flags allows accurate timing of the serial interface communications.

7.1.1 Fine Exposure

The fine exposure category simply comprises registers[32,33].

7.1.2 Coarse Exposure

The coarse exposure category simply comprises registers[34,35].

7.1.3 Clock Division

The clock division category simply comprises register[37].

7.1.4 Gain

The gain category simply comprises register[36].

7.1.5 Pan Parameter

The pan parameter category comprises the following registers:

•

Setup0[16] (The “pan_pend” flag will only be set if the subsampled QCIF mode is entered or exited)

Setup1[17] (The “pan_pend” flag will only be set if the hshuffle control bit is changing state)

Data_format[22] (The “pan_pend” flag will only be set if the hmirror control bit is changing state)

X-offset[87,88] (The “pan_pend” flag set unconditionally)

7.1.6 Tilt Parameter

The tilt parameter category comprises the following registers:

•

Setup0[16] (The “tilt_pend” flag will only be set if the subsampled QCIF mode is entered or exited)

data_format[22] (The “tilt_pend” flag will be set if the hshuffle control bit or the hmirror control bit is changing state)

Y-offset[89,90] (The “tilt_pend” flag set unconditionally)

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7.1.7 Video Timing Parameter

VV5410 & VV6410

The video timing parameter category comprises all the other shadow/working register pairs. The video timing parameter update

pending flag will be unconditionally set if any of the following registers are written to:

•

Setup0[16]

Setup1[17]

fg_mode[20]

data_format[22]

op_format[23]

mode_select[24]

Dark Pixel Offset[44,45]

Dark Pixel Cancellation Setup Register

Black Pixel Offset[44,45]

Black Pixel Cancellation Setup Register

Line Length[82,83]

Field Length[97,98]

7.2 Timed Parameter Update Points

The timed parameter categories are updated as follows:

note: We refer to odd and even fields in the Table 9 below. In a video mode like CIF or QCIF the fields are all identical in length,

we still have to be able to differentiate between fields to enable correct updating of register parameters.

Timed parameter category

Updated point

ﬁne exposure

Conditional on a change pending in the line length register.

Line length change pending: update ﬁne exposure at the odd to even ﬁeld

transition

Line length change not pending: update ﬁne exposure during the start of

active video (SAV) region of the end of frame (EOF) line (the line that follows

the last line of active video) in the odd ﬁeld.

coarse exposure

clock division

gain

Updated during the SAV region of the ﬁrst dark line in an odd ﬁeld

Updated at the odd to even ﬁeld transition

Updated during the SAV region of the EOF line in the odd ﬁeld

Updated during the SAV region of the ﬁrst visible line in an odd ﬁeld

Updated at the odd to even ﬁeld transition

pan parameter

tilt parameter

video timing

Table 9 : Timed Parameter Update Points

The order that the above timed parameters are updated is critical. Let us assume that all the pending flags are set, i.e. we have

written to at least one register in each category. The working registers will be updated in the following order:

1. Coarse exposure

2. Tilt parameters

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3. Gain, Pan parameters and conditionally the fine exposure (see Table 9 for details)

4. Clock division, video timing parameters and conditionally the fine exposure (see Table 9 for details)

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8. Digital Video Interface Format

8.1 General description

The video interface consists of a bidirectional, tri-stateable 5-wire data bus. The nibble transmission is synchronised to the rising

edge of the system clock (Figure 31).

Read-out Order

Progressive Scan (Non-interlaced)

Form of encoding

Uniformly quantised, PCM, 8/10 bits per sample

Correspondence between video signal

levels and quantisation levels:

The internal10-bit pixel data is clipped to ensure that 0_Hand 3FF_H(5

Wire) or FF_H(4/8 Wire) values do not occur when pixel data is being

output on the data bus.

10-Bit Data

Pixel Values 1 to 1022

Black Level 64

8-Bit Data

Pixel Values 1 to 254

Black Level 16

Table 10 : Video encoding parameters

Digital video data may be either 8 or 10 bits per sample, and can be transmitted in one of the following ways:

10-bit data

1. A series pair of 5-bit nibbles, most signiﬁcant nibble ﬁrst, on 5 wires.

2. An 8-bit number e.g. line code. line numbers and status line data is padded with 00 in the least signiﬁcant two bits to make

up a 10-bit value.

8-bit data

1. A single 8 bit byte over 8 output wires_note

.

2. A series pair of 4-bit nibbles, most signiﬁcant nibble ﬁrst, on 4 wires.

3. The top 8-bits of a 10-bit value e.g. pixel data or line averages is used as the 8-bit equivalent.

note: if the 8-wire output mode has been selected then the normal FST/LST pin function is sacrificed as these pins are required

to output data information

10-bit Pixel Data

5 - wire Output Mode

D₄,D₃,D₂,D₁,D₀

D₉,D₈,D₇,D₆,D₅

D₄,D₃,D₂,D₁,D₀

D₉,D₈,D₇,D₆,D₅

8-bit Pixel Data

8- wire Output Mode

4 - wire Output Mode

....D₂,D₁,D₀

D₅,D₄,D₃,D₂

D₉,D₈,D₇,D₆,D₅,D₄,D₃,D₂

D₉,D₈,D₇,D₆D₅,D₄,D₃,D₂

D₉,D₈,D₇.........

D₉,D₈,D₇,D₆

Figure 12 : Possible Output Modes

In the following description the 4-wire mode is used as an example. The 5-wire mode can be viewed as a variant of the 4-wire

mode. Data is output on the least significant data wires available. e.g. in 4-wire mode, data is output on data wires D[3:0] while in

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Digital Video Interface Format

5-wire mode data is output on D[4:0].

Multiplexed with the sampled pixel data is control information including both video timing references, sensor status/configuration

data and the pixel average from the current line.

Video timing reference information takes the form of field start characters, line start characters, end of line characters and a line

counter.

Where hexadecimal values are used, they are indicated by a subscript H, such as FF_H; other values are decimal.

8.2 Embedded control data

To distinguish the control data from the sampled video data all control data is encapsulated in embedded control sequences.

These are 6 bytes long and include a combined escape/sync character sequence, 1 control byte (the ‘command byte’) and 2

bytes of supplementary data.

To minimise the susceptibility of the embedded control data to random bit errors redundant coding techniques have been used to

allow single bit errors in the embedded control words to be corrected. However, more serious corruption of control words or the

corruption of escape/sync characters cannot be tolerated without loss of sync to the data stream. To ensure that a loss of sync is

detected a simple set of rules has been devised. The four exceptions to the rules are outlined below:

1. Data containing a command word that has two bit errors.

2. Data containing two ‘end of line’ codes that are not separated by a ‘start of line’ code.

3. Data preceding an ‘end of ﬁeld’ code before a start of frame’ code has been received.

4. Data containing line that do not have sequential line numbers (excluding the ‘end of ﬁeld’ line).

If the host detects one of these violations then it should abandon the current field of video

8.2.1 The combined escape and sync character

Each embedded control sequence begins with a combined escape and sync character that is made up of three words. The first

two of these are FF_HFF_H- constituting two words that are illegal in normal data. The next word is 00_H- guaranteeing a clear

signal transition that allows a host to determine the position of the word boundaries in the serial stream of nibbles. Combined

escape and sync characters are always followed by a command byte - making up the four byte minimum embedded control

sequence.

8.2.2 The command word

The byte that follows the combined escape/sync characters defines the type of embedded control data. Three of the 8 bits are

used to carry the control information, four are ‘parity bits’ that allow the host to detect and correct a certain level of errors in the

transmission of the command words, the remaining bit is always set to 1 to ensure that the command word never has the value

00_H. The coding scheme used allows the correction of single bit errors (in the 8-bit sequence) and the detection of 2 bit errors

The three data bits of the command word are interpreted as shown in Figure 13.The even parity bits are based on the following

relationships:

1. An even number of ones in the 4-bit sequence (C₂, C₁, C₀and P₀).

2. An even number of ones in the 3-bit sequence (C₂, C₁, P₁).

3. An even number of ones in the 3-bit sequence (C₂, C₀, P₂).

4. An even number of ones in the 3-bit sequence (C₁, C₀, P₃).

Table 13 shows how the parity bits maybe used to detect and correct 1-bit errors and detect 2-bit errors.

8.2.3

Supplementary Data

The last 2 bytes of the embedded control sequence contains supplementary data. The are two options:

1. The last 2 bytes of the SAV 6 byte sequence contain the current 12-bit line number. The 12-bit line number is packaged up

by splitting it into two 6-bit values. Each 6-bit value is then converted into an 8-bit value by adding a zero to the start and an

odd word parity bit at the end.

2. The 5th byte of the EAV sequence contains a pixel average for that line either based upon the middle 256 pixels if the

CIF,PAL or NTSC video modes are selected or the middle 128 pixels if the QCIF video mode is selected. The ﬁnal byte is

FF_H.

Note: in 5-wire mode, the embedded control data is calculated as detailed above and output as the most significant 8-bits. The

least significant 2-bits are padded with zero.

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Line Code

Nibble X (1 C C C )

Nibble Y (P P P P )

H 3 2 1 0

H

2

1

0

End of Line

1000₂(8_H)

1001₂(9_H)

1010₂(A_H)

1011₂(B_H)

1100₂(C_H)

1101₂(D_H)

1110₂(E_H)

1111₂(F_H)

0000₂(0_H)

1101₂(D_H)

1011₂(B_H)

0110₂(6_H)

0111₂(7_H)

1010₂(A_H)

1100₂(C_H)

0001₂(1_H)

Blank Line (BL)

Black line (BK)

Visible Line (VL)

Start of Even Field (SOEF)

End of Even Field (EOEF)

Start of Odd Field (SOOF)_note1

End of Odd Field (EOOF)_note2

Table 11 : Embedded Line Codes

note1: This code is only generated in the PAL or NTSC video modes

note2: This code is only generated in the PAL or NTSC video modes

We include Table 12 to show how the 8 bit control codes are mapped onto the output data bits in the 5 wire mode.

Most signiﬁcant nibble

Data[4:0]

Least signiﬁcant nibble

Data[4:0]

Line Code

End of Line

1_0000₂(10_H)

1_0011₂(13_H)

1_0101₂(15_H)

1_0110₂(16_H)

1_1000₂(18_H)

1_1011₂(1B_H)

1_1101₂(1D_H)

1_1110₂(1E_H)

0_0000₂(00_H)

1_0100₂(14_H)

0_1100₂(0C_H)

1_1000₂(18_H)

1_1100₂(1C_H)

0_1000₂(08_H)

1_0000₂(10_H)

0_0100₂(04_H)

Blank Line (BL)

Black line (BK)

Visible Line (VL)

Start of Even Field (SOEF)

End of Even Field (EOEF)

Start of Odd Field (SOOF)

End of Odd Field (EOOF)

Table 12 : Mapping 8bit control codes to 5 wire output mode

Parity Checks

Comment

P

0

3

2

1

✔

Code word un-corrupted

✔

✘

✔

✘

✔

✘

✔

P₀corrupted, line code OK

P₁corrupted, line code OK

P₂corrupted, line code OK

Table 13 : Parity Checking

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Digital Video Interface Format

Parity Checks

Comment

P

0

3

2

1

✘

✔

P₃corrupted, line code OK

✘

✔

✘

✔

✘

✔

✘

C₀corrupted, invert sense of C₀

C₁corrupted, invert sense of C₁

C₂corrupted, invert sense of C₂

2-bit error in code word.

All other codes

Table 13 : Parity Checking

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Escape/Sync Sequence

8-bit Data

FF_H

00_H

XY_H

D₃D₂

D₁D₀

5-wire output

mode

1F_H1F_H1F_H1F_H00_H00_H

4-wire output

mode

F_HF_HF_HF_H0_H0_HX_HY_HD₃D₂D₁D₀

Command (Line Code)

Bit

7

1

6

5

4

3

2

1

0

C

P

0

2

1

0

3

2

1

Nibble X

Nibble Y

H

Supplementary Data

(i) Line Number (L₁₁MSB) output in SAV

Bit

7

0

6

5

4

3

2

1

0

Bit

7

0

6

5

4

3

2

1

0

L

P

L

0

P

11

10

9

8

7

6

5

4

3

2

1

Nibble D

0

3

2

1

Odd

word

parity

or (ii) Pixel average output in EAV (4-wire used as example, P₇MSB)

P

0

1

7

6

5

4

3

2

1

Nibble D = F

0

Nibble D

2

1

H

3

Figure 13 : Embedded Control Sequence

8.3 Video timing reference and status/conﬁguration data

Each frame of video sequence comprises 2 fields. Each field of data is constructed of the following sequence of data lines.

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Digital Video Interface Format

1. A start of ﬁeld line

2. A number of black lines

3. A number of blank (or dark) lines

4. A number active video lines

5. An end of ﬁeld line

6. A number of blank or black lines

Video Format

VP3 mode

NTSC

On

PAL

On

CIF

On

QCIF

Off

On

Off

Extra Black Lines

On Off N/A On Off N/A On Off N/A On Off N/A

1st Field

Start of Field Line

Black Lines

1

8

1

0

1

2

7

0

1

8

0

8

1

8

1

0

1

2

7

0

1

16

0

1

8

1

0

1

2

7

0

1

16

0

1

8

1

0

1

2

7

0

1

8

0

2

Blanking Lines

Dark Lines

2

10

Active Video lines

End of Field Line

Blanking Lines

Black Lines

244 244 244 292 292 292 292 292 292 148 148 148

1

0

7

1

7

0

1

0

1

0

9

1

9

0

1

0

1

0

1

17

0

1

0

1

0

1

0

1

0

17

Total

262 262 262 312 312 312 320 320 320 160 160 160

2nd Field

Start of Field Line

Black Lines

1

8

1

0

1

2

7

0

1

8

0

8

1

8

1

0

1

2

7

0

1

16

0

1

8

1

0

1

2

7

0

1

16

0

1

8

1

0

1

2

7

0

1

8

0

2

Blanking Lines

Dark Lines

2

10

Active Video lines

End of Field Line

Blanking Lines

Black Lines

244 244 244 292 292 292 292 292 292 148 148 148

1

0

8

1

8

0

1

0

1

0

1

10

0

1

0

1

0

1

17

0

1

0

1

0

1

0

1

0

10

17

Total

263 263 263 313 313 313 320 320 320 160 160 160

Table 14 : Field and Frame Formats

Table 14 details the number of each type of data lines for NTSC, PAL, CIF and QCIF output formats. Each line of data starts with

an embedded control sequence that identifies the line type (as outlined in Table 14). The control sequence is then followed by

two bytes that contain a coded line number. The line number sequences starts with the start-of-frame line at 00_Hand increments

one per line up until the end-of-frame line. Each line is terminated with an end-of-line embedded control sequence. The line start

embedded sequences must be used to recognise visible video lines as a number of null bytes may be inserted between

successive data lines.

There are a series of figures (Figure 14 - Figure 25) on the following pages that show line type construction of the fields in each

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of the available video modes in VV5410/VV6410.

8.3.1 Blank lines

In addition to padding between data lines, actual blank data lines may appear in the positions indicated above. These lines begin

with start-of-blank-line embedded control sequences and are constructed identically to active video lines except that they will

contain only blank bytes, 07_H, (expressed as 01C_Hin 10bit form).

8.3.2 Black line timing

The black lines (which are used for black offset calculation) are identical in structure to valid video lines except that they begin

with a start-of-black line code and contain either information from the sensor black lines or blanking data.

By default VP3 mode (see mode_select[24] for details) is selected. It is an option in any of the VP3 modes to select the additional

black lines to be output (line 3-8). If the VP3 mode is not selected then all the black lines are enabled - no blank lines are output.

Internally there is the concept of dark lines - to be used for dark offset cancellation (see following diagrams to identify their

position within the frame timing model), however externally the dark lines share the same line type code as the black lines.

8.3.3 Padding Lines and Fields

The user may choose to extend the inter-field period by increasing the field length by writing to serial registers 97 & 98. In this

event, the appropriate number of additional black or blank lines is inserted between the End Of Field (EOF) line and the Start Of

Field (SOF) line. This means that the distance between SOF and EOF will remain constant.

The user can also extend the line length by writing to serial registers 82 and 83. The line length padding is inserted after the EAV

sequence, ensuring that the distance between the SAV and EAV sequences will remain constant.

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Digital Video Interface Format

8 Blanking Lines

262

0

Start Of 1st Field Line

2 Black Lines

1

2

3

7 Blanking Lines

8

9

10

11

12

244 Visible Lines

251

252

253

254

255

End Of 1st Field Line

7 Blanking Lines

261

0

Start Of 2nd Field Line

2 Black Lines

1

2

3

7 Blanking Lines

8

9

10

11

12

244 Visible Lines

251

252

253

254

255

End Of 2nd Field Line

8 Blanking Lines

262

0

Start Of 1st Field Line

Figure 14 : NTSC Field and Frame Formats - VP3 Mode On, Extra Black Lines Off

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8 Blanking Lines

262

0

Start Of 1st Field Line

8 Black Lines

1

2

3

8

9

Blanking Line

10

11

12

244 Visible Lines

251

252

253

254

255

End Of 1st Field Line

7 Black Lines

261

0

Start Of 2nd Field Line

1

2

3

8 Black Lines

Blanking Line

8

9

10

11

12

244 Visible Lines

251

252

253

254

255

End Of 2nd Field Line

8 Black Lines

262

0

Start Of 1st Field Line

Figure 15 : NTSC Field and Frame Formats - VP3 Mode On, Extra Black Lines On

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261

262

0

End Of 2nd Field Line

1 Black Line

Start Of 1st Field Line

1

2

3

8 Black Lines

8 Dark Lines

8

9

10

16

17

18

19

244 Visible Lines

258

259

260

261

0

End Of 1st Field Line

Start Of 2nd Field Line

1

2

3

8 Black Lines

8 Dark Lines

8

9

16

17

18

19

244 Visible Lines

258

259

260

261

262

End Of 2nd Field Line

1 Black Line

0

Start Of 1st Field Line

Figure 16 : NTSC Field and Frame Formats - VP3 Mode Off

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10 Blanking Lines

312

0

Start Of 1st Field Line

2 Black Lines

1

2

3

8

7 Blanking Lines

292 Visible Lines

9

10

11

12

299

300

301

302

303

End Of 1st Field Line

9 Blanking Lines

311

0

Start Of 2nd Field Line

2 Black Lines

1

2

3

8

7 Blanking Lines

292 Visible Lines

9

10

11

12

299

300

301

302

303

End Of 2nd Field Line

10 Blanking Lines

312

0

Start Of 1st Field Line

Figure 17 : PAL Field and Frame Formats - VP3 Mode On, Extra Black Lines Off

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10 Black Lines

312

0

Start Of 1st Field Line

1

2

3

8 Black Lines

Blanking Line

8

9

10

11

12

292 Visible Lines

299

300

301

302

303

End Of 1st Field Line

9 Black Lines

311

0

Start Of 2nd Field Line

8 Black Lines

1

2

3

8

9

Blanking Line

10

11

12

292 Visible Lines

299

300

301

302

303

End Of 2nd Field Line

10 Black Lines

312

0

Start Of 1st Field Line

Figure 18 : PAL Field and Frame Formats - VP3 Mode On, Extra Black Lines On

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1 Black Line

312

0

Start Of 1st Field Line

1

2

3

16 Black Lines

14

15

16

17

18

19

20

21

2 Dark Lines

292 Visible Lines

308

309

310

311

0

End Of 1st Field Line

Start Of 2nd Field Line

1

2

3

16 Black Lines

2 Dark Lines

15

16

17

18

19

20

21

292 Visible Lines

308

309

310

311

312

0

End Of 2nd Field Line

1 Black Line

Start Of 1st Field Line

Figure 19 : PAL Field and Frame Formats - VP3 Mode Off

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17 Blanking Lines

319

0

Start Of 1st Field Line

2 Black Lines

1

2

3

8

7 Blanking Lines

292 Visible Lines

9

10

11

12

299

300

301

302

303

End Of 1st Field Line

17 Blanking Lines

319

0

Start Of 2nd Field Line

2 Black Lines

1

2

3

8

7 Blanking Lines

292 Visible Lines

9

10

11

12

299

300

301

302

303

End Of 2nd Field Line

17 Blanking Lines

319

0

Start Of 1st Field Line

Figure 20 : CIF Field and Frame Formats - VP3 Mode On, Extra Black Lines Off

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17 Black Lines

319

0

Start Of 1st Field Line

8 Black Lines

1

2

3

8

9

Blanking Line

10

11

12

292 Visible Lines

299

300

301

302

303

End Of 1st Field Line

17 Black Lines

319

0

Start Of 2nd Field Line

1

2

8 Black Lines

Blanking Line

3

8

9

10

11

12

292 Visible Lines

299

300

301

302

303

End Of 2nd Field Line

17 Black Lines

319

0

Start Of 1st Field Line

Figure 21 : CIF Field and Frame Formats - VP3 Mode On, Extra Black Lines On

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End Of 2nd Field Line

Start Of 1st Field Line

319

0

1

2

3

16 Black Lines

10 Dark Lines

16

17

18

26

27

28

29

30

292 Visible Lines

317

318

319

0

End Of 1st Field Line

Start Of 2nd Field Line

1

2

16 Black Lines

10 Dark Lines

3

16

17

18

26

27

28

29

30

292 Visible Lines

317

318

319

0

End Of 2nd Field Line

Start Of 1st Field Line

Figure 22 : CIF Field and Frame Formats - VP3 Mode Off

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158

159

0

End Of 2nd Field Line

Blanking Line

Start Of 1st Field Line

1

2 Black Lines

2

3

7 Blanking Lines

8

9

10

11

12

148 Visible Lines

155

156

157

158

159

0

End Of 1st Field Line

Blanking Line

Start Of 2nd Field Line

1

2 Black Lines

2

3

7 Blanking Lines

8

9

10

11

12

148 Visible Lines

155

156

157

158

159

0

End Of 2nd Field Line

Blanking Line

Start Of 1st Field Line

Figure 23 : QCIF Field and Frame Formats - VP3 Mode On, Extra Black Lines Off

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158

159

0

End Of 2nd Field Line

Black Line

Start Of 1st Field Line

1

2

8 Black Lines

Blanking Line

3

8

9

10

11

12

148 Visible Lines

155

156

157

158

159

0

End Of 1st Field Line

Black Line

Start Of 2nd Field Line

1

2

8 Black Lines

Blanking Line

3

8

9

10

11

12

148 Visible Lines

155

156

157

158

159

0

End Of 2nd Field Line

Black Line

Start Of 1st Field Line

Figure 24 : QCIF Field and Frame Formats - VP3 Mode On, Extra Black Lines On

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159

0

End Of 2nd Field Line

Start Of 1st Field Line

1

2

8 Black Lines

3

8

9

2 Dark Lines

10

11

12

148 Visible Lines

155

156

157

158

159

0

End Of 1st Field Line

Start Of 2nd Field Line

1

2

8 Black Lines

2 Dark Lines

3

8

9

10

11

12

148 Visible Lines

155

156

157

158

159

0

End Of 2nd Field Line

Start Of 1st Field Line

Figure 25 : QCIF Field and Frame Formats - VP3 Mode Off

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8.3.4 Valid video line timing

All valid video data is contained on active video lines. The pixel data appears as a continuous stream of bytes within the active

lines. The pixel data may be separated from the line header and end-of-line control sequence by a number of ‘blank’ bytes (07_H).

8.3.5 Start of frame line timing

The start of frame line which begins each video field contains no video data but instead contains the contents of the serial

interface register map. Immediately following the SAV sequence there are 2 padding pixels, (see Figure 27), output as blanking

levels, (07_H). There will be more blanking codes output after all the serial interface registers have been output . The padding

pixels continue to be output until terminated by an end-of-line control sequence. To ensure that no escape/sync characters, (the

reserved FF,FF,00 sequence), appear in the sensor status/configuration information the code 07_His output after each serial

interface value.

If a serial interface register location is unused then a default value, the DeviceH register, is output. The read-out order of the

registers is independent of whether the pixel read-out order is shuffled or un-shuffled.

8.3.6 End of frame line timing

The end of frame line contains no video data. Its sole purpose is to indicate the end of a frame.

8.4 Detection of sensor using data bus state

On power-up a sensor will pull all data lines high and these lines will remain high while the device is in the power up default, low

power state. The device is removed from this low power mode by the I2C host writing to sensor register, setup0 [address 10₁₆].

When the device exits the low power mode it will follow a defined power up sequence, please see Figure 30 for more details.

Upon completion of the power up sequence the sensor will begin streaming video.

8.5 Resetting the Sensor Via the Serial Interface

Bit 2 of setup0 register allows the VV5500/VV6500 sensor to be reset to its power-on state via the serial interface. Setting this

“Soft Reset” bit causes all of the serial interface registers including the “Soft Reset” bit to be reset to their default values. This

“Soft Reset” leaves the sensor in low-power mode.

8.6 Resetting the Sensor Via the RESETB pin

On power-up the RESETB pin is configured as an active low system reset which has the same effect as a soft reset issued via

the serial interface as described above.

8.7 Resynchronising the Sensor Via the RESETB pin conﬁgured as SINB

Bit 5 of the pin mapping register [21] allows the RESETB pin to be re-configured as an active low (edge triggered) system

synchronisation signal which will reset the video timing to the beginning of a field but will NOT reset the serial registers therefore

the host does not have to reconfigure the sensor following a resynchronisation.

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Digital Video Interface Format

8.8 Power-up, Low-power and Sleep modes

Please note that the following descriptions of low power and sleep modes assumes that the user has selected the optional 4 wire

output mode, that is D[3:0] will transmit the digital video data. If the 5-wire or 8-wire modes are selected the same basic behaviour

is followed however the contents of the data bus will differ slightly.

PU0

System Power Up

PU1

Sensor enters low power mode and databus bits driven high.

Host enables the sensor clock, CLKI.

PU2

PU3-PU4

The host sends a “Soft-Reset” command to the sensor via the serial interface. This ensures that

the sensor is in low-power mode.

PU5

Host issues command to remove sensor from low-power mode.

Sensors begins execution 4 frame start sequence.

PU6-PU7

PU8-PU9

One frame of alternating 9_H& 6_Hdata on D[3:0] for the host to determine the best sampling

phase for video data.

PU10-PU11

4 Frames after the “Exit Low-Power Mode” serial comms, the sensor starts outputing valid video

data.

Table 15 : Typical System Power-Up

8.8.1 Power-Up/Down (Figure 29)

The sensor enters low-power mode on power-up. On power-up all of the data bus lines are driven high immediately and the

device is in low-power mode (Section 8.8.2).

The sensor will remain in the low power mode until the external host sends the appropriate message over I2C to clear the low

power bit - bit0 of serial reguister, setup0, index 10₁₆

.

After the “Exit Low-Power Mode” command has been sent the sensor will output for one frame, a continuous stream of alternating

9_Hand 6_Hvalues on D[3:0] The patterns generated in 5 and 8 wire modes are given in Table 16 below. By locking onto the

resulting 0101/1010 patterns appearing on the data bus lines the host can determine the best sampling position for the nibble

data. After the last 9_H6_Hpair has been output the data bus returns to F_H,(1F_Hin 5 wire mode), until the start of fifth frame. At this

point the first active video frame will be output. After the host has determined the correct sampling position for the data, it should

then wait for the next start of frame line (SOF).

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Mode

10-bit Value

Output Data Bus Pattern

4-Wire

5-Wire

8-Wire

258_H

136_H

9_H/6_H(1001₂/0110₂)

09_H/16_H(01001₂/10110₂)

096_H/ 069H

25_H/1A_H(00100101₂/00011010₂)

Table 16 : Output Data Bus Patterns for determination of Best Sampling Position

8.8.2 Low-Power Mode (Figure 30)

Under the control of the serial interface the sensor analog circuitry can be powered down and then repowered. When the low-

power bit is set via the serial interface, all the data bus lines will go high at the end of the end of frame line of the current frame.

At this point the analog circuits in the sensor will power down. The system clock must remain active for the duration of low power

mode.

During low power mode only the analog circuits are powered down, the values of the serial interface registers e.g. exposure and

gain are preserved. The internal frame timing is reset to the start of a video frame on exiting low-power mode. In a similar manner

to the previous section, the first frame after the serial comms contains a continuous stream of alternating 9_Hand 6_H- or

equivalent for the alternative ouput databus widths - to allow the host to re-confirm its sampling position. Then three frames later

the first start of frame line is generated.

8.8.3 Sleep Mode

Sleep mode is similar to the low-power mode, except that analog circuitry remains powered. When the sleep command is

received via the serial interface the pixel array will be put into reset and the data lines all will go high at the end of the current

frame. Again the system clock must remain active for the duration of sleep mode.

When sleep mode is disabled, the CMOS sensor’s frame timing is reset to the start of a frame. During the first frame after exiting

from sleep mode the data bus will remain high, while the exposure value propagates through the pixel array. At the start of the

second frame the first start of field line will be generated.

8.8.4 System clock status during sensor low-power modes

To allow the sensor to enter and exit the low power and sleep modes the system clock, CLKI, must be active.

8.9 Suspend mode

Under the control of the SUSPEND pin VV5410/VV6410 can be forced into an ultra low power mode. The sensor will consume

less than 80uA of current while suspended. While the sensor is in this mode video output is turned off and no serial

communications can occur.

The SUSPEND mode is effectively identical to a power on reset - all the video timing blocks within the sensor are reset as are the

contents of the serial interface, therefore the user will have to perform a compete reconfiguration of the device on exitting

SUSPEND. The sensor will also repeat the full 4 field power up sequence.

Mode

Description

Approx. Sensor Current

Suspend

Sensor in lowest power state. Suspend has been

asserted by host.

c.80uA

Table 17 : VV5410/VV6410 suspend mode power consumption

8.10 Data Qualiﬁcation Clock, QCK

VV5410/VV6410 provides a data qualification clock, (see Figure 31), to qualify the information output on data bus. The sensor

can generate two styles of qualification clock:

•

Fast QCK, clocks at nibble rate. The falling edge of this clock qualifies data

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Digital Video Interface Format

•

The slow QCK, clocks at pixel rate. Both the falling and rising edge of this clock are used to qualify data. The most significant

data nibble is qualified by the rising edge of the slow QCK and the least significant nibble is qualified by the falling edge of

the slow QCK.

There are 4 modes of operation of QCK.

1. Disabled (Always low - default mode of operation)

2. Free running - qualiﬁes the entire output data stream.

3. Qualify embedded control sequences, status data, (from the SOF line), and pixel data.

4. Qualify pixel data only, (this will include data from the black lines).

The operating mode for QCK is set via the serial interface. The QCK output can be tri-stated either when OEB is driven high or

via the appropriate control bit in the serial interface, (see data_format register[22]).

The QCK pin can also be configured to output the state of a serial interface register bit. This feature allows the sensor to control

external devices, e.g. stepper motors, shutter mechanisms.

Full details of how to configure the QCK output pin can be found in 2 registers, fg_mode[20] and pin_mapping[21].

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8.10.5 Line Start Signal, LST

There are 4 modes of operation for the LST pin programmable via the serial interface, (see fg_mode[20]):

1. Disabled (Always Low- Default).

2. Free running - LST signal occurs once at the beginning of every line.

3. All lines except blanking lines are qualiﬁed by LST.

4. Only Black and Visible Lines are qualiﬁed by LST.

The LST is tri-stated either when OEB is driven high or via the appropriate control bit in the serial interface, (see data_format

register[22]). Table 18below details the LST timing for the different video modes, (see Figure 33 for specification of t1 and t2).

t1

t2

Video Mode

pck’s

us

pck’s

us

CIF

21

6

5.25

6.00

16

15

4.000

15.00

QCIF (both pan tilt and sub sampled,

16Mhz clock)

QCIF (both pan tilt and sub sampled,

8Mhz clock)

6

6.00

15

15.00

PAL

33

27

4.652

4.714

42

12

5.962

2.095

NTSC

Table 18 : LST Timing

8.10.6 Frame Start Signal, FST

There are 3 modes of operation for the FST pin programmable via the serial interface:

1. Disabled (Always Low- Default).

2. Frame start signal. The FST signal occurs once frame, is high for 356 pixel periods (712 system clock periods) and qualiﬁes

the data in the start of frame line.

3. Shutter/Electronic Flash Synchronisation Signal - FST rises a the start of the video data in the ﬁrst black/blank line after the

EOF line and falls at the end of data in the SOF line.

The FST output is tri-stated either when OEB is driven high or via the appropriate control bit in the serial interface, (see

data_format register[22]).

The configuration details for FST can be found in fg_mode register[20].

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Serial Control Bus

9. Serial Control Bus

9.1 General Description

Writing configuration information to the video sensor and reading both sensor status and configuration information back from the

sensor is performed via the 2-wire serial interface.

Communication using the serial bus centres around a number of registers internal to the video sensor. These registers store

sensor status, set-up, exposure and system information. Most of the registers are read/write allowing the receiving equipment to

change their contents. Others (such as the chip id) are read only.

The main features of the serial interface include:

•

Variable length read/write messages.

Indexed addressing of information source or destination within the sensor.

Automatic update of the index after a read or write message.

Message abort with negative acknowledge from the master.

Byte oriented messages.

The contents of all internal registers accessible via the serial control bus are encapsulated in each start-of-field line - see Section

8.3.5.

9.2 Serial Communication Protocol

The co- processor or host must perform the role of a communications master and the camera acts as either a slave receiver or

transmitter.The communication from host to camera takes the form of 8-bit data with a maximum serial clock host frequency of up

to 100 kHz. Since the serial clock is generated by the bus master it determines the data transfer rate. Data transfer protocol on

the bus is illustrated in Figure 35.

Acknowledge

Start condition

SDA

MSB

1

LSB

8

SCL

P

S

7

2

3

4

5

6

A

Address or data byte

Stop condition

Figure 35 : Serial Interface Data Transfer Protocol

9.3

Data Format

Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. The internal data is produced by sampling

sda at a rising edge of scl. The external data must be stable during the high period of scl. The exceptions to this are start (S) or

stop (P) conditions when sda falls or rises respectively, while scl is high.

A message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start, (Sr) followed

by another message.

The first byte contains the device address byte which includes the data direction read, (r), ~write, (~w), bit. The lsb of the address

byte indicates the direction of the message. If the lsb is set high then the master will read data from the slave and if the lsb is reset

low then the master will write data to the slave. After the r, ~w bit is sampled, the data direction cannot be changed, until the next

address byte with a new r, ~w bit is received.

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0

1

0

R/W

Figure 36 : VV5410/VV6410’s Serial Interface Address

The byte following the address byte contains the address of the first data byte (also referred to as the index). The serial interface

can address up to 128, byte registers. If the msb of the second byte is set the automatic increment feature of the address index is

selected.

Sensor acknowledges valid address

Acknowledge from slave

DATA[7:0]

A

[0]

address

S

address[7:1]

A

INC

INDEX[6:0]

A

R

Auto increment

Index bit

/

_Wbit

DATA[7:0]

A

P

Figure 37 : Serial Interface Data Format

9.4 Message Interpretation

All serial interface communications with the sensor must begin with a start condition. If the start condition is followed by a valid

address byte then further communications can take place. The sensor will acknowledge the receipt of a valid address by driving

the sda wire low. The state of the read/~write bit (lsb of the address byte) is stored and the next byte of data, sampled from sda,

can be interpreted.

During a write sequence the second byte received is an address index and is used to point to one of the internal registers. The

msbit of the following byte is the index auto increment flag. If this flag is set then the serial interface will automatically increment

the index address by one location after each slave acknowledge. The master can therefore send data bytes continuously to the

slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or

sends a repeated start, (Sr). If the auto increment feature is used the master does not have to send indexes to accompany the

data bytes.

As data is received by the slave it is written bit by bit to a serial/parallel register. After each data byte has been received by the

slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index.

During a read message, the current index is read out in the byte following the device address byte. The next byte read from the

slave device are the contents of the register addressed by the current index. The contents of this register are then parallel loaded

into the serial/parallel register and clocked out of the device by scl.

At the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. Although

VV5410/VV6410 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the

sensor.

At the end of a sequence of incremental reads or writes, the terminal index value in the register will be one greater the last

location read from or written to. A subsequent read will use this index to begin retrieving data from the internal registers.

A message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a

negative acknowledge after reading a complete byte during a read operation.

9.5 The Programmers Model

There may be up to 128, 8-bit registers within the camera, accessible by the user via the serial interface. They are grouped

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Serial Control Bus

according to function with each group occupying a 16-byte page of the location address space. There may be up to eight such

groups, although this scheme is purely a conceptual feature and not related to the actual hardware implementation, The primary

categories are given below:

•

Status Registers (Read Only).

Setup registers with bit significant functions.

Exposure parameters that influence output image brightness.

System functions and analog test bit significant registers.

Any internal register that can be written to can also be read from. There are a number of read only registers that contain device

status information, (e.g. design revision details).

Names that end with H or L denote the most or least significant part of the internal register. Note that unused locations in the H

byte are packed with zeroes.

STMicroelectronics sensors that include a 2-wire serial interface are designed with a common address space. If a register

parameter is unused in a design, but has been allocated an address in the generic design model, the location is referred to as

reserved. If the user attempts to read from any of these reserved or unused locations a default byte will be read back. In

VV5410/VV6410 this data is 19_H. A write instruction to a reserved (but unused) location is illegal and would not be successful as

the device would not allocate an internal register to the data word contained in the instruction.

A detailed description of each register follows. The address indexes are shown as decimal numbers in brackets [....] and are

expressed in decimal and hexadecimal respectively.

Index

Name

Length R/W

Default

Comments

10

16

Status Registers - [0-15]

0

1

2

0

1

2

deviceH

8

RO

0001_1001₂

1010_0000₂

0001_0000₂

Chip identification number including

revision indicator

deviceL

status0

User can determine whether timed

serial interface data has been

consumed by interrogating flag states

3

4

3

4

5

6

7

8

9

A

line_countH

line_countL

xendH

8

1

8

1

8

4

8

RO

n/a

359

Current line counter value

5

End x coordinate of image size

End y coordinate of image size

6

xendL

7

yendH

293

8

yendL

9

dark_avgH

dark_avgL

0

This is the average pixel value

returned from the dark line offset

cancellation algorithm

10

(2’s complement notation)

11

12

B

C

black_avgH

black_avgL

4

8

RO

0

This is the average pixel value

returned from the black line offset

cancellation algorithm

(2’s complement notation)

13

D

status1

unused

2

RO

00

Flags to indicate whether the x or y

image coordinates have been clipped

14-15

E-F

Setup Registers - [16-31]

Table 19 : Serial Interface Address Map.

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Index

Name

Length R/W

Default

Comments

10

16

10

setup0

8

R/W

0000_1001₂

Low-power/sleep modes & video

timing

17

18

11

12

setup1

8

R/W

1100_0000₂

0001_1111₂

Various parameters

sync_value

Contains pixel counter reset value

used by external sync

19

20

13

14

reserved

fg_modes

8

R/W

0000_0000₂

Frame grabbing modes

(FST, LST and QCK)

FST and QCK mapping modes.

Data resolution

21

22

23

24

15

16

17

18

pin_mapping

data_format

op_format

7

8

7

R/W

000_1000₂

0000_0001₂

001_1000₂

01₂

Output coding formats

Various mode select bits

mode_select

2

25 - 31

19-1F

unused

Exposure Registers - [32-47]

32

33

20

21

fineH

2

8

2

8

4

R/W

0

Fine exposure.

fineL

34

22

coarseH

coarseL

analog gain

clk_div

302

Coarse exposure

35

23

36

24

1111_0000

0

Analog gain setting

Clock division

37

25

38-43

44

26-2B

2C

reserved

dark offsetH

dark offsetL

3

8

R/W

0

dark line offset cancellation value

45

2D

(2’s complement notation)

46

2E

dark offset

setup

7

R/W

0110 0001₂

dark line offset cancellation enable

47

2F

reserved

Colour Registers - [48-79]

R/W

Video Timing Registers - [80-103]

48 - 79

30-4F

reserved

8

80-81

82

50-51

52

reserved

line_lengthH

line_lengthL

reserved

2

8

R/W

415

Line Length (Pixel Clocks)

83

53

84 - 86

87

54-56

57

x-offsetH

x-offsetL

1

8

1

8

R/W

5

3

x-co-ordinate of top left corner of

region of interest (x-offset)

88

58

89

59

y-offsetH

y-offsetL

y-co-ordinate of top left corner of

region of interest (y-offset)

90

5A

91 - 96

97

5B-60

61

reserved

field_lengthH

field_lengthL

reserved

2

8

R/W

319

Field length (Lines)

98

62

99-102

103

63-66

67

unused

R/W

Text Overlay Registers - [104-107]

104 - 105

106 - 107

68-69

6A-6B

reserved

unused

Table 19 : Serial Interface Address Map.

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Serial Control Bus

Index

Name

Length R/W

Default

Comments

10

16

Serial Interface Autoload Registers - [108-111]

108 - 109

110 - 111

6C-6D

6E-6F

reserved

unused

System Registers - [112-127]

112

113

70

71

black offsetH

black offsetL

3

8

R/W

- 64

black offset cancellation default value

(2’s complement notation)

114

72

black offset

setup

6

R/W

0011 0001₂

black offset cancellation setup

115

116

73

74

unused

reserved

cr0

117

75

8

R/W

0000 0000₂

0101 1010₂

0000 0000₂

0000 0001₂

Analog Control Register 0

Analog Control Register 1

ADC Setup Register

118

76

cr1

119

77

as0

120

78

at0

Analog Test Register

121

79

at1

Audio Amplifier Setup Register

122 - 125

126

7A-7D

7E

unused

reserved

127

7F

Table 19 : Serial Interface Address Map.

9.5.1 Status Registers - [0 - 15],[0-F]

[0-1],[0-1] - DeviceH and DeviceL

These registers provide read only information that identifies the sensor type that has been coded as a 12bit number and a 4bit

mask set revision identifier. The device identification number for VV5410/VV6410 is 410 i.e. 0001 1001 1010₂. The initial mask

revision identifier is 0 i.e. 0000₂.

Bits

Function

Default

Comment

7:0

Device type identifier

0001 1001₂

Most significant 8 bits of the 12 bit code identifying the

chip type.

Table 20 : [0],[0] - DeviceH

Bits

Function

Default

Comment

7:4

Device type identifier

1010₂

Least significant 4 bits of the 12 bit code identifying the

chip type.

3:0

Mask set revision identifier

0000₂

Table 21 : [1],[1] - DeviceL

[2],[2] - Status0

Bit

Function

Default

Comment

0

Fine exposure value update

pending

0

Fine exposure value sent but not yet consumed by the

sensor

Table 22 : [2],[2] - Status0

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Bit

Function

Default

Comment

1

Coarse exposure value update

pending

0

Coarse exposure value sent but not yet consumed by

the sensor

2

3

4

5

Gain value update pending

Clock division update pending

Odd/even frame

0

1

0

Gain value sent but not yet consumed by the sensor

Clock divisor sent but not yet consumed by the sensor

The flag will toggle state on alternate frames

Pan image parameters pending

Pan image parameters sent but not yet consumed by

the sensor

6

7

Tilt image parameters pending

0

Tilt image parameters sent but not yet consumed by

the sensor

Video timing parameter update

pending flag

Video timing parameters sent but not yet consumed

by sensor

Table 22 : [2],[2] - Status0

[3-4],[3-4] - Line_countH & Line_countL

Register

Bits

Function

Default

Comment

Index

3

4

0

Current line count MSB

Current line count LSB

-

Displays current line count

7:0

Table 23 : [3-4],[3-4] - Current Line Counter Value.

[5-6],[5-6] - XendH & XendL

Register

Bits

Function

Default

Comment

Index

5

6

0

Xend msb’s

Xend ls byte

359

These registers contain the end x

coordinate of the read out image size,

(the x offset register contains the start x

coordinate)

7:0

Table 24 : [5-6],[5-6] - Xend

[7-8],[7-8] - YendH & YendL

Register

Bits

Function

Default

Comment

Index

5

6

0

Yend ms bits

Yend ls byte

293

These registers contain the end y

coordinate of the read out image size,

(the y offset register contains the start y

coordinate)

7:0

Table 25 : [7-8],[7-8] - Yend

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[9-12],[9-C] - Black_Avg & Dark_Avg

Register

Bits

Function

Default

Comment

Index

9

3:0

7:0

Dark avg ms bits

Dark avg ls byte

0

The calculated pixel average over a

series of dark lines (1,2 or 4 lines). The

pixel sample size from each dark line

will be image size dependent up to a

maximum of 256

10

The average value is a signed 12 bit

number

11

12

3:0

7:0

Black avg ms bits

Black avg ls byte

0

The calculated pixel average over a

series of black lines (4 or 8 lines). The

pixel sample size from each black line

will be image size dependent up to a

maximum of 256

The average value is a signed 12 bit

number

Table 26 : [9-12],[9-C] - Black & Dark Averages

[13],[D] - Status1 Register

Bit

Function

Default

Comment

0

X image parameters clipped

Y image parameters clipped

unused

0

If this bit is set then the current x offset parameter

requested has caused the x coordinates to be

clipped

1

0

If this bit is set then the current y offset parameter

requested has caused the y coordinates to be

clipped

7:2

000000

Table 27 : [13],[D] - Status1

[14-15],[E-F] - unused

9.5.2 Setup Registers - [16 - 31],[10-1F]

[16],[10] - Setup0

[

Bit

Function

Default

Comment

0

Low Power Mode:

1

Powers down the sensor array. The output data bus

goes to F_H. On power-up the sensor enters low power

Off / On

mode.

1

Sleep Mode:

0

Puts the sensor array into reset. The output data bus

goes to F_H.

Off / On

Table 28 : [16],[10] - Setup0

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Bit

Function

Default

Comment

2

Soft Reset

0

Setting this bit resets the sensor to its power-up

defaults. This bit is also reset.

Off / On

3

Frame/Field Rate select:

1

25 fps (PAL) / 30 fps (NTSC)

reserved

5:4

7:6

00

Video Timing Mode Select

00 - CIF Timing Modes

01 - PAL/NTSC 3.2 fsc Timing Modes

10 - pan/tilt/QCIF Timing Modes

If this mode is selected a QCIF size image will be

output. The coordinates which deﬁne the top left

corner of the QCIF portion of the array to be output

are deﬁned by the parameters in registers 88 - 91

inclusive. By default the x- and y-sizes of the output

image are180 & 148 respectively.

11 - sub-sampled QCIF Timing Modes

If this mode is selected a QCIF size image will be

output. The CIF image is sub-sampled in groups of 4

to preserve the Bayer pattern with every second group

of pixels & lines skipped.

Table 28 : [16],[10] - Setup0

Comment

Video setup0 setup0 System

Video

Data

Line

Length

Field

Length

Data

Format

Mode

[7:6]

Clock

Divisor

[3]

(default)

5-wire

4

2

8

356 x 292

306 x 244

180 x 148

500

416

454

364

250

208

250

208

320

CIF 25fps

1

2

3

4

5

6

7

8

00

0

1

0

1

0

1

0

1

CIF 30fps

312/313

262/263

160

PAL (3.2 fsc)

01

10

11

NTSC (3.2 fsc)

pan/tilt QCIF 25fps

pan/tilt QCIF 30fps

sub-sampled QCIF 25fps

sub-sampled QCIF 30fps

160

Table 29 : Video Timing Modes

[17],[11] - Setup1

Bit

Function

Default

Comment

2:0

3

reserved

000

Enable immediate clock division

update. Off/On

0

Allow manual change to clock division to be

applied immediately

4

Enable immediate gain update.

0

Allow manual change to gain to be applied

immediately

Off/On

Table 30 : [17],[11] - Setup1

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Serial Control Bus

Bit

Function

Default

Comment

5

Enable additional black lines (lines 3-8)

0

If enabled this bit will also enable the lines

immediately following the end of frame line. This

bit can only set/reset if the VP3 mode (ON) has

been selected. In VP3 mode (OFF) operation all

possible black lines are always output.

Off/On

6

7

reserved

1

Pixel read-out order (hshuffle)

It is strongly recommended to use shuffled

horizontal read-out with VV6410 sensor.

Unshuffled or Shuffled

Table 30 : [17],[11] - Setup1

[18],[12] - sync_reset

Bit

Function

Default

Comment

7:0

Pixel counter reset value

31

During synchronisation the pixel counter can be

reset to the known value or offset by up to 255

pck’s into the pixel count sequence.

Table 31 : [18],[12] - sync_reset

[19],[13] - reserved

[20],[14] - fg_modes

Bits [3:2] of the fg_mode register are mode dependent. If the NTSC or PAL video modes are selected then the free running QCK

mode will be selected. The slow QCK is selected by default, regardless of the video mode.

Bit

Function

Default

Comment

1:0

FST/QCK pin modes

00

Selection of FST, QCK pin data

00 - if CIF & QCIF mode selected

3:2

QCK modes

01 - if NTSC and PAL mode selected

See Table 35 below for details

See Table 36 below for details

5:4

7:6

LST modes

FST modes

00

Table 32 : [20],[14] - fg_modes

fg_mode[1:0]

FST pin

QCK pin

0

1

0

1

0

1

FST

Slow QCK

Fast QCK

Slow QCK

Fast QCK

Fast QCK_note1

Invert of Fast QCK_note1

Table 33 : FST/QCK Pin Selection

note1: The FST pin will always output the free running version of QCK (either inverted or normal)

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fg_mode[3:2]

QCK state

0

1

0

1

0

1

Off

Free Running

Valid during data and control period of line

Valid only during data period of line

Table 34 : QCK Modes

fg_mode[5:4]

LST pin

0

1

0

1

0

1

Off

Free Running

Output for black, video data and status lines

Output only for black and video data lines.

Table 35 : LST Modes

.

fg_mode[7:6]

FST pin

0

1

Off

Normal behaviour, FST will qualify the visible pixels in

the status line

1

x

Special digital stills mode. FST will be asserted at the

beginning of valid data on the line following the EOF

line. FST will be cleared at the end of the visible pix-

els in the following status line.

Table 36 : FST Modes

The option to enable the qclk during the data and control period of the line must not be selected if monochrome (shuffled or

unshuffled) video has been selected.

[21],[15] - pin_mapping

Bit

Function

Default

Comment

0

Map serial interface register bits values

on to the QCK and FST pins

0

Off/On

1

2

Serial Interface Bit for QCK pin

Serial Interface Bit for FST pin

Output driver strength select

0

4:3

00

Default setting selects 2mA driver

Table 37 : [21],[15] - pin_mapping

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Serial Control Bus

Bit

Function

Default

Comment

5

Enable RESETB pin as SIN

0

On power up the RESETB pin is conﬁgured as an

active low system reset which will synchronise the

video timing logic and reset all serial registers to

their default state. Setting this bit conﬁgures the

RESETB pin as an active high system

Off / On

synchronisation

signal

(SIN)

which

will

synchronise the video timing but will NOT reset the

serial registers.

7:6

unused

0

Table 37 : [21],[15] - pin_mapping

Mapping Enable

FST pin

QCK pin

0

1

FST

QCK

pin_mapping[2]

pin_mapping[1]

Table 38 : FST/QCK Pin Selection

oeb_composite

pin_map[4]

pin_map[3]

Comments

0

1

0

1

x

0

1

0

1

x

Drive strength = 2mA (Default)

Drive strength = 4mA

Drive strength = 6mA

unallocated

Outputs are not being driven therefore

driver strength is irrelevant

Table 39 : Output driver strength selection

[22],[16] - data_format

Bit

Function

Default

Comment

1:0

2

Unused

1

0

Line read-out order (vertical)

If the line read out is shuffled then all the even address

rows will be read out first followed by all the odd

address rows

Unshuffled or Shuffled

3

4

Pixel read-out order (hmirror)

0

If the pixel read out is horizontally mirrored then the

columns are read out in reverse order, that is the

column on the right of the sensor array will appear on

the left of the displayed image and vice versa

Normal or Mirrored

Line read-out order (vertical flip)

If the line read out is vertically mirrored then the rows

are read out in reverse order, that is the row at the

bottom of the array will appear at the top of the

displayed image and vice versa.

Normal or Mirrored

Table 40 : [22],[16] - data_format

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Bit

Function

Default

Comment

5

FST/LST Enable/Tri-state

0

The FST/LST digital outputs can be tri-stated but are

enabled as outputs by default. The enabling/disabling

of FST/LST can be retimed to a ﬁeld boundary. The

state of this control bit is always available via a serial

interface read, i.e. it does not have to wait to change

state at a ﬁeld boundary

6

7

QCK Enable/Tri-state

0

The QCK output can be tri-stated independently. The

enabling/disabling of QCK can be retimed to a ﬁeld

boundary. The state of this control bit is always availa-

ble via a serial interface read, i.e. it does not have to

wait to change state at a ﬁeld boundary.

Pre clock generator divide

On/Off

The CIF and QCIF video modes expect a recom-

mended set of input clock frequencies, however the

acceptable range of clock frequencies can be extended

if this bit is set. If this bit is set then the primary input

clock will be divided down by 1.5 prior to the clock gen-

erator, thus if the expected clock input is 16 MHz, we

can set this bit and accept 24 MHz and achieve the

same ﬁnal frame rate.

Table 40 : [22],[16] - data_format

OEB pin

data_format[5]

oeb_composite

Comments

0

1

0

1

FST/LST outputs enabled.

FST/LST outputs are tri-stated by

data_format[5]

1

0

1

FST/LST outputs are tri-stated by OEB pin.

FST/LST outputs are tri-stated.

Table 41 : FST/LST output control

OEB pin

data_format[6]

oeb_composite

Comments

0

1

0

1

0

1

0

1

QCK output enabled.

QCK output is tri-stated by op_format[6]

QCK output is tri-stated by OEB pin.

QCK output is tri-stated.

Table 42 : QCK output control

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[23],[17] - op_format

Bit

Serial Control Bus

Function

Default

Comment

1:0

Data format select.

0

00 - 5 wire parallel output

01 - 4 wire parallel output

1x - 8 wire parallel output

Note: If the 8 wire output option has been selected then

the FST and LST pins will output data bits 5 and 6

respectively, normal FST and LST function is not

available

2

Embedded SAV/EAV Escape

Sequences¹

On / Off

0

0 - Insert Embedded Control Sequences e.g Start

and End of Active Video into Output Video data

1 - Pass-through mode. Output Video data equals ADC

data.

4:3

5

reserved

11

0

Tri-state output data bus

On power up the data bus pads are enabled by default.

This bit is OR’ed with the OEB pin to generate the

enable signal for the data pins as detailed in Table 44

Enabled / Tri-state

6

7

Re-time tri-state update.

0

Re-time new tri-state value to a field boundary. This bit

affects the updating of the op_format[5] as well as

data_format[6:5]

Off / On

unused

Table 43 : [23],[17] - op_format

1. Please note that if the embedded coding sequences are disabled then the FST signal is also disabled. The QCK

output will continue to function IF the free running option has been selected. The LST functionality is unaffected

by the state of this bit.

OEB pin

op_format[5]

oeb_composite

Comments

0

1

0

1

0

1

0

1

Data outputs enabled.

Data outputs are tri-stated by op_format[5]

Data outputs are tri-stated by OEB pin.

Data outputs are tri-stated.

Table 44 : Data bus output control

Note: oeb_composite is the logical OR of op_format[5] and the OEB pin.

[24],[18] - mode_select

This register allows the user to configure the sensor to operate with the present generation of coprocessors as well as anticipated

future devices.

Bit

Function

Default

Comment

0

Coprocessor device is VP3

No/Yes

1

By default the sensor expects the coprocessor to be a

VP3 device. If the sensor is not being used with a VP3

device then this bit should be reset. This bit controls

the arrangement of black/dark/visible lines within the

ﬁeld. It does not alter timing. Please see

Table 45 : [24],[18] - Mode Select

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Bit

Function

Default

Comment

1

2

Retro mode for gain application

Off/On

0

The gain passed to the CAB comprises 2 components,

IDAC[3:0] and CDAC[5:0]. If the user selects the retro

mode then the IDAC value will be the inverse of the ls

gain nibble. The user is barred from writing to the ms

gain nibble. In the non retro mode all 8 bits are availa-

ble to program. The 2 ls bits of CDAC[5:0] are ﬁxed at

2’b11.

Select log CDAC ramp

Off/On

0

By default the same CDAC value is applied for the

duration of every line of every ﬁeld. Setting this bit

causes the CDAC value to be varied during the line.

7:3

Table 45 : [24],[18] - Mode Select

[25-31],[19-1F] - unused

9.5.3 Exposure Control Registers [32 - 47],[20-2F]

There is a set of programmable registers which controls the sensitivity of the sensor. The registers are as follows:

1. Fine exposure.

2. Coarse exposure.

3. Analog gain.

4. Clock division

Note: As we know from an explanation earlier in this document (see Section 6. for further details) the exposure control

registers are not updated immediately, rather they are timed to be updated at a precise point in the field timing.

The range of some parameter values is limited and any value programmed out-with this range will be clipped to the maximum

currently permitted, (the fine and coarse maximum allowable settings are set by the current line and field length respectively).

Index

Bits

Function

Default

Comment

10

16

32

33

20

21

0

Fine MSB exposure value

Fine LSB exposure value

0

The maximum fine exposure is line

length dependent. The expressions

used to calculate the maximum fine

exposure for each of the default

video modes, that can be selected

via Setup0 register, are as follows

7:0

NTSC = line length - 51

PAL = line length - 86

CIF = line length - 51

QCIF = line length - 23

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Serial Control Bus

Index

Bits

Function

Default

Comment

10

16

34

35

22

23

0

Coarse MSB exposure value

Coarse LSB exposure value

302

The maximum allowable coarse

exposure setting is filed length

dependent. We provide the

maximum coarse exposure settings

for each of the standard video

modes.

7:0

NTSC = 260

PAL = 310

CIF (25 & 30 fps) = 318

QCIF (25 & 30 fps) = 158

36

37

24

25

7:0

3:0

Analog gain value

Clock divisor value

1111_0000 Bits [7:4] CDAC gain control

CDAC default = 63 (10-bit modes)

CDAC default = 31 (9-bit modes)

Bits[3:0] IDAC maximum

recommended IDAC value = 12.

0

The user can opt to slow the internal

clocks down form their default

settings. Table 47 describes the

range of clock divisors that may be

selected.

Table 46 : Exposure Related Registers

Clock Divisor Setting

Pixel Clock Divisor

0000

1

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Table 47 : Clock Divisor Values

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Clock Divisor Setting

Pixel Clock Divisor

1111

16

Table 47 : Clock Divisor Values

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Serial Control Bus

[38-43],[26-3B] - reserved

[44 - 45],[3C-3D] - Dark Pixel Offset

Bit

Function

Default

Comment

2:0

7:0

MS Dark line pixel offset

LS Dark line pixel offset

0

This register contains a ﬁxed offset that can

be applied to the digitised pixels in the dig-

ital output coding block. The offset is a 2’s

complement number, giving an offset range

-1024,+1023.

If this external offset cancellation is to be

applied then it register[46], bits[1:0] should

be reprogrammed to 2’b1x.

Table 48 : [44 - 45],[3C-3D] - Dark Pixel Offset

[46],[3E] - Dark Pixel Cancellation Setup Register

Bit

Function

Default

Comment

1:0

Dark line offset cancellation

01

x0 - Accumulate dark pixels, calculate dark

pixel average and report, but don’t apply

anything to data stream

01 - Accumulate dark pixels, calculate dark

pixel average and report and apply

internally calculated offset to data stream

11 - Accumulate dark pixels, calculate dark

pixel average and report, but apply an

externally calculated offset

2

Number of dark lines used

0

1

The dark line offset cancellation algorithm

can opt to only use pixels from dark lines

that are preceeded by another dark line, i.e

line choose only line 306 from line 305 and

line 306.

All dark lines/Use half the number of

dark lines.

5:3

6

reserved

Use narrow dark offset deadband

The deadband describes a range of dark

pixel averages that will force the leaky

integrator algorithm to hold it’s current

value.

Yes/No

0 - Target +/- 4 codes

1 - Target +/- 2 codes

7

unused

0

Table 49 : [46],[3E] - Dark Pixel Cancellation Setup Register

[47],[3F] - reserved

[48-79],[30-4F] - reserved

9.5.4 Video Timing Registers [80 - 103],[50-67]

Indexes in the range [80 - 103] control the generically named video timing registers, including the image pan/tilt parameters and

line & field length of the sensor. The registers are as follows:

1. line length.

2. x-offset of region of interest.

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3. y-offset of region of interest.

4. frame length.

The length of a line is specified in a number of pixel clocks, whereas the length of a field is specified in a number of lines.

The range of some parameter values is limited and any value programmed out-with this range will be clipped to the maximum

allowed. The x-offset and y-offset are only programmable if the user has selected the pan tilt QCIF mode. If the other video

modes are selected then the x-offset and y-offset registers will have pre-programmed values applied, but they cannot be

changed. The x-offset and y-offset default values are chosen such that the output image, regardless of video mode selected, will

be centered within the pixel array, (see Section 3.2 for details).

Index

Bit

Function

Default

Comment

10

16

80-81

82

50-51

52

reserved

1:0

7:0

Line Length MSB value

Line Length LSB value

415

Minimum mode dependent

Maximum = 1023

83

53

Actual line duration in pixel periods is

line length programmed +1.

84 - 86

87

54-56

57

reserved

0

x-offset MSB value

x-offset LSB value

y-offset MSB value

y-offset LSB value

reserved

5

3

Minimum (positive) value = 1

88

58

7:0

0

89

59

90

5A

7:0

91 - 96

97

5B-60

61

1:0

7:0

Field Length MSB value

Field Length LSB value

319

Minimum mode dependent

Maximum = 1023

98

62

Actual field duration in line periods is

field length programmed +1.

99-102

63-66

reserved

Table 50 : Video Timing Registers

[103],[67] - unused

[104-105],[68-69] - reserved

[106-107],[6A-6B] - unused

[108-109],[6C-6D] - reserved

[110-111],[6E-6F] - unused

9.5.5 System Registers -Addresses [112 - 127],[70-7F]

This page of the serial interface I2C address space comprises a wide range of registers including the registers required to control

the black offset cancellation algorithm, enable test modes and also control various aspects of the analogue behavior of the

sensor.

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Serial Control Bus

[112 - 113],[70-71] - Black Pixel Offset

Bit

Function

Default

Comment

2:0

7:0

MS Black line pixel offset

LS Black line pixel offset

- 64

This register contains a ﬁxed offset that can be applied to

the digitised pixels in the digital output coding block.The

offset is a 2’s complement number, giving an offset range

-1024,+1023.

If this external offset cancellation is to be applied then it

register[114], bits[1:0] should be reprogrammed to 2’b1x.

Table 51 : [112 - 113],[70-71] - Black Pixel Offset

[114],[72] - Black Pixel Cancellation Setup Register

Bit

Function

Default

Comment

1:0

Black line offset cancellation

01

x0 - Accumulate black pixels, calculate

black pixel average and report, but don’t

apply anything to data stream

01 - Accumulate black pixels, calculate

black pixel average and report and apply

internally calculated offset to data stream

11 - Accumulate black pixels, calculate

black pixel average and report, but apply an

externally calculated offset

4:2

5

reserved

100

1

The time constant controls the rate at which

a change in the black level is corrected for.

Use narrow black offset deadband

The deadband describes a range of pixel

averages that will cause the leaky integrator

algorithm to hold it’s current value.

Yes/No

0 - Target +/- 4 codes

1 - Target +/- 2 codes

7:6

unused

00

Table 52 : [114],[72] - Black offset cancellation setup

[115],[73] - unused

[116],[74] - reserved

[117 - 118],[75-76] - Control Registers 0 and 1- CR0 and CR1

Although we give the user access to the following 5registers it is not anticipated that the contents of these registers will have to be

altered. If the user does wish to alter any of the register bits then they are strongly advised to contact VIBU before doing so.

Bit

Function

Default

Comment

0

Enable bit line clamp

0

Off/On

1

Enable bit line test

0

Off/On

Table 53 : [117],[75] - Control Register CR0

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Bit

Function

Default

Comment

3:2

Bit line white reference

00

00 - 0.7V

01 - 1.1V

10 - 1.5V

11 - External

0.7 V / 1.1 V / 1.5V / Ext.

4

5

6

7

Enable anti blooming

0

Off/On

Power Down - LVDS input comparator

Powers down LVDS input. CMOS clock

input may still be used.

Off/On

Power Down - SRAM

Powers down SRAM comparator

Off/On

Power Down - VCCS

Powers down voltage controlled current

source

Off/On

Table 53 : [117],[75] - Control Register CR0

Bit

Function

Default

Comment

0

Stand-by

0

Powers down ALL analog circuitry with the

exception of the band gap

Off/On

1

2

3

4

5

6

7

Power Down - Internal Ramp Generator

0

Off/On

Power Down - Column ADC

Powers down preamp and comparators

Referred to in figures as pd_creg

Referred to in figures as pd_areg

Allows external VRT to be applied

0 - VRT-vtn ramp common mode voltage

Off/On

Power Down - CAB regulator

Off/On

Power Down - Audio Amplifier regulator

Off/On

Power Down - VRT Amplifier

Off/On

Ramp common mode voltage

VRT-vtn/1.5V

1- 1.5V ramp common mode voltage

0 - 75uA

Current boost to column comparator

75uA/50uA

1- 50uA

Table 54 : [118],[76] - Control Register CR1

[119][77] - ADC Setup Register AS0

Bit

Function

Default

Comment

1:0

reserved

10

Table 55 : [119],[77] - ADC Setup Register AS0

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Serial Control Bus

Bit

Function

Default

Comment

2

3

4

5

6

7

Enable voltage doubler

0

It is recommended that this bit is set if the sensor

is being used in a 3.3V supply environment

Off/On

Differential ramp enable

1

0

1

Ramp generator signal bpramp

Off//On

view column/view vcmtcas

0 - view column voltage Vx[363]

vcmtcas/column

1- view vcmtcas

ramp viewing/column comparator test

0 -view ramps on CPOS/CNEG

ramps/test comparator

1- input to test comparator 364

Stepped Ramp Enable

Setting this bit enables a stepped ramp.

Off/On

Clearing this bit enables a continuous ramp.

Table 55 : [119],[77] - ADC Setup Register AS0

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[120],[78] - Analog Test Register AT0

VV5410 & VV6410

Bit

Function

Default

Comment

0

SRAM test enable

0

Off/On

2:1

4:3

7:5

VRT Voltage

00

00 - VRT = 2.2V

2.2V / 2.5V / 2.8V / Ext.

01 - VRT = 2.5V

10 - VRT = 2.8V

11 - reserved

LineInt & ReadInt phasing

00- 0 degree phase delay

01 - 90 degree phase delay

10 - 180 degree phase delay

11 - 270 degree phase delay

unused

000

Table 56 : [120],[78] - Analog Test Register AT0

[121],[79] - Audio Ampliﬁer Setup Register AT1

Bit

0

Function

Default

1

Comments

First stage gain

0 - 0dB

1 - 30dB

1

2

Second stage gain[1]

Second stage gain[0]

0

gain[1] gain[0] - gain(dB)

0 0 - 0dB

0 1 - 6dB

1 0 - 12dB

1 1 - 18dB

3

Power Down

Output Select

Current Boost

Unused

1

0 - Powered up

1 - Power down

0 - Single ended

1 - Differential

4

0

5

0

0 - 1mA output drive in output buffers

1 - 2mA output drive in output buffers

7:6

00

Table 57 : [121],[79] - Audio Ampliﬁer Setup Register AT1

[122-125],[7A-7D] - unused

[126-127],[7E-7F] - reserved

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Serial Control Bus

9.6 Types of messages

This section gives guidelines on the basic operations to read data from and write data to the serial interface.

The serial interface supports variable length messages. A message may contain no data bytes, one data byte or many data

bytes. This data can be written to or read from common or different locations within the sensor. The range of instructions

available are detailed below.

•

Write no data byte, only sets the index for a subsequent read message.

Single location data write or read for monitoring (real time control)

Multiple location read or write for fast information transfers.

Examples of these operations are given below. A full description of the internal registers is given in the previous section. For all

examples the slave address used is 32₁₀for writing and 33₁₀for reading. The write address includes the read/write bit (the lsb)

set to zero while this bit is set in the read address.

9.6.1 Single location, single data write.

When a random value is written to the sensor, the message will look like this:

Device

address

Stop

Ack

Index

Data

Inc

Start

S

32

A 0

32

A

85

10

A

P

10

Figure 38 : Single location, single write.

In this example, the fineH exposure register (index = 32₁₀) is set to 85₁₀. The r/w bit is set to zero for writing and the inc bit (msbit

of the index byte) is set to zero to disable automatic increment of the index after writing the value. The address index is preserved

and may be used by a subsequent read. The write message is terminated with a stop condition from the master.

9.6.2 Single location, single data read.

A read message always contains the index used to get the first byte.

Master reads from slave, acknowledging

each byte

Device

address

Stop

A

Ack

Index

Data

Start

S

33

A 0

32

A

85

10

P

10

Figure 39 : Single location, single read.

This example assumes that a write message has already taken place and the residual index value is 32₁₀. A value of 85₁₀is read

from the fineH exposure register. Note that the read message is terminated with a negative acknowledge (A) from the master: it is

not guaranteed that the master will be able to issue a stop condition at any other time during a read message. This is because if

the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition.

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9.6.3 No data write followed by same location read.

VV5410 & VV6410

When a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written

first, specifying the index. The read message then completes the message sequence. To avoid relinquishing the serial to bus to

another master a repeated start condition is asserted between the write and read messages, i.e. no stop condition is asserted. In

this example, the gain value (index = 36₁₀) is read as 15₁₀

:

No data write

Read index and data

36

A

33

A

33

10

15

A P

S

36

Sr

A

0

A

0

10

Figure 40 : No data write followed by same location read.

As mentioned in the previous example, the read message is terminated with a negative acknowledge (A) from the master.

9.6.4 Same location multiple data write.

It may be desirable to write a succession of data to a common location. This is useful when the status of a bit (e.g. auto-load)

must be toggled.

The message sequence indexes sf_setup register 108. If bit 0 is toggled high, low this will initiate a fresh auto-load. This is

achieved by writing two consecutive data bytes to the sensor. There is no requirement to re-send the register index before each

data byte.

Write to pin_mapping

32 A 0 21

Toggle control bit

4

P

S

A

4

A

0

10

A

10

Figure 41 : Same location multiple data write.

9.6.5 Same location multiple data read

When an exposure related value (fineH, fineL, coarseH, coarse L, gain or clk_div) is written, it takes effect on the output at the

beginning of the next video frame, (remember that the application of the gain value is a frame later than the other exposure

parameters). To signal the consumption of the written value, a flag is set when any of the exposure or gain registers are written

and is reset at the start of the next frame. This flag appears in status0 register and may be monitored by the bus master. To

speed up reading from this location, the sensor will repeatedly transmit the current value of the register, as long as the master

acknowledges each byte read.

In the below example, a fineH exposure value of 0 is written, the status register is addressed (no data byte) and then constantly

read until the master terminates the read message.

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Serial Control Bus

Write ﬁneL with zero

Address the status0 register

A Sr 32

S

32

A 0 33

A

0

A

0

10

A

10

Read continuously...

Sr 33

A 0

0

A

1

A

1

A

1

10

A

10

...until ﬂag reset

1

A

0

A P

10

Figure 42 : Same location multiple data read.

9.6.6 Multiple location write

If the automatic increment bit is set (msb of the index byte), then it is possible to write data bytes to consecutive adjacent internal

registers, (i.e. 23,24,25,26 etc), without having to send explicit indexes prior to sending each data byte. An auto-increment write to

the exposure registers with their default values is shown in the following example, where we write 17₁₀to the pin_mapping

register[21] and 193₁₀to the data format register[22].

.

Incremental write

S

32

A 1 21

A

17

A

193

10

A P

10

Figure 43 : Multiple location write.

9.6.7 Multiple location read

In the same manner, multiple locations can be read with a single read message. In this example the index is written first, to

ensure the exposure related registers are addressed and then all six are read.

No data write

A 1 32

Incremental read

A 1 32 ﬁneH

S

32

A Sr

33

A

10

Incremental read

ﬁneL

A

coarseH A coarseL A

gain

A

clk_div A P

Figure 44 : Multiple location read.

Note: a stop condition is not required after the final negative acknowledge from the master, the sensor will terminate the

communication upon receipt of the negative acknowledge from the master.

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9.7 Serial Interface Timing

VV5410 & VV6410

Parameter

Symbol

Min.

Max.

Unit

SCL clock frequency

fscl

tbuf

0

2

100

kHz

us

ns

pF

Bus free time between a stop and a start

Hold time for a repeated start

LOW period of SCL

-

thd;sta

tlow

80

320

160

80

0

-

HIGH period of SCL

thigh

tsu;sta

thd;dat

tsu;dat

tr

-

Set-up time for a repeated start

Data hold time

-

Data Set-up time

0

-

Rise time of SCL, SDA

Fall time of SCL, SDA

Set-up time for a stop

-

300

-

tf

-

tsu;sto

Cb

80

-

Capacitive load of each bus line (SCL,

SDA)

200

Table 58 : Serial Interface Timing Characteristics

stop start

start

stop

SDA

SCL

...

tbuf

tlow tr

tf

thd;sta

...

thd;sta

thd;dat

thigh

tsu;dat

tsu;sta

tsu;sto

Figure 45 : Serial Interface Timing Characteristics

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10. Clock Signal

Clock Signal

VV5410/VV6410 system clock is supplied from an external clock source directly driving the CLKI pin. The clock pad has an

integral Schmitt buffer to filter noise from the clock source. Please note that there is no support for an external resonator circuit.

VV5410/VV6410

Clock

CLK

CLOCK

CLKI

Source

DIVISION

Figure 46 : CMOS Clock Source

The clock signal must be a square wave with, ideally a 50% ( 10%) mark:space ratio, although a non-ideal mark:space ratio can

be tolerated, please contact STMicroelectronics for details. The maximum input clock frequency for the module is 24.0 MHz. If

the 24MHz crystal is preferred then the user must select the pre-clock divide by 1.5 option such that the bulk of the internal logic

is driven by a 16MHz clock, see serial interface, register 16₁₀, data_format.

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11. Other Features

11.1 Audio Ampliﬁer

VV5410/VV6410 contains an on-chip audio amplifier which can be configured via the serial interface. The amplifier may also be

powered down via the serial interface.

The following document outlines the implementation of audio circuitry on the VV5410/VV6410 sensor.

11.1.1 Audio Ampliﬁer Conﬁguration

The audio circuit is controlled through a single eight bit register on the VV5410/VV6410. This includes bits for power down, output

select, first and second stage gains and current boosting. Table 59 describes the functionality of the control register bits.

The first stage provides a gain of 0dB or 30dB using a low noise amplifier design.

The reference is provided from the on-chip bandgap voltage. This is buffered by a cut down version of the low-noise amplifier

used in the first gain stage.

Bit

Function

Default

Comments

0

First stage gain

1

0 - 0dB

1 - 30dB

1

2

Second stage gain[1]

Second stage gain[0]

0

gain[1] gain[0] - gain(dB)

0 0 - 0dB

0 1 - 6dB

1 0 - 12dB

1 1 - 18dB

3

Power Down

Output Select

Current Boost

Unused

0

0 - Powered up

1 - Power down

4

0 - Single ended

1 - Differential

5

0 - 1mA output drive in output buffers

1 - 2mA output drive in output buffers

7:6

Table 59 : Control register summary for VV5410/VV6410 audio circuit.

The output of the first gain stage is fed to two output amplifiers. These can be configured with a 1mA or 2mA output drive current.

The inverting gain stage provides an additional gain between 0dB and 18dB.

The output of the inverting gain stage may be routed through the other output buffer to provide two single ended outputs.

Otherwise, the inverted and non-inverted outputs provide a fully differential output signal.

Some more circuit specifications may be found in Table 60.

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Other Features

11.1.2 AUD3V3 (Audio Supply Regulator)

Symbol

Parameter

Min

Typical

3.3

Max

3.46

Units

V

AUD3V3

Regulated supply

(No external load)

Regulated supply Vdrop

(Current Load 20mA)

Regulated supply

(Suspend mode)

3.13

AUD3V3_Ld

AUD3V3_sus

-50

Off

mV

V

ZAUD3V3_sus

PSRR

Output impedance in

Suspend mode

TBC

-48

KΩ

Power Supply Rejection

versus Vin

dB

Table 60 : Audio Circuit Speciﬁcation

11.1.3 Audio Ampliﬁer Parameters

Symbol

Parameter

Min

Typical

Max

Units

VAin

R_IN

Audio Regulator Input Voltage

Input impedance

V_bg

V

100

kΩ

dB

Gain1

Gain2

Gmatch

Ist stage (28dB) gain accuracy

2nd stage (0,6,12,18dB) gain accuracy¹

+/-0.5

+/-0.2

Differential output mode gain matching

(0dB)

(28dB)(

0.2

0.5

Out_max

OUT_DC

D-OUT_DC

Rout

Output Clipping Level²

Output DC Voltage

1.6

1.1

2.2

1.22

20

Vpp

V

1.3

Differential DC Offset (AoutN-AoutP)

Output Impedance

100

mV

kΩ

%

2

THD

THD (includes noise)

0.2

Vin = 20mVpp, f-1KHz, Gain =28dB

SNR

Signal to Noise ratio

(1KHz)

dB

65

75

(10KHz)³

PSRR

LFc

Power supply rejection ratio from Vin

Low frequency cutoff (Cin=100nF)

-55

15

dB

Hz

dB

Xtalk

Video crosstalk to audio outputs (gain = 28dB)

-56

Table 61 : Audio Ampliﬁer Parameters

1. 2nd stage gain is only available on AoutN with the audio ampliﬁer in differential mode

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2. Minimum dynamic range includes dcout (i.e. Vclip- OUT_DC is greater than Vppmin/2)

3. Assumes 10µF bypass capacitors on all supplies and well separated supplies and grounds

1

11.1.4 Audio Ampliﬁer Bandwidth

The audio circuit can be bandwidth limited to a first order, through the use of minimum external circuitry. The two outputs, AoutP

and AoutN, require compensation capacitors that may also be used to define the bandwidth of the circuit.

Compensation Capacitor (nF)

3dB Bandwidth

Units

kHz

1

175

41

10

100

4.2

Table 62 : Compensation capacitor values

In addition, the inclusion of a resistor (microphone biasing) and decoupling capacitor at the input allows a first order high pass

filter to be realised. This can easily be designed to remove frequencies below 50Hz/60Hz (mains electricity noise).

11.2 Voltage Regulators

VV5410/VV6410 contains three on-chip voltage regulators, two of which are capable of being powered-down via the serial

interface. The third regulator, controlling the band gap references is never powered down. The band gap circuitry is extremely low

power consuming only 30µA.

11.2.1 Regulator for Digital System

The output of the regulator, Reg3V3, powers the digital logic and can power an external co-processor. The regulator is powered

up by default. The regulator has its own discrete power supply and can source a load of 300µA -> 150mA and will regulate to

3.0V 10% from an input range of 4-6V. When VV5410/VV6410 is in the USB compatible suspend mode, the clocks to the digital

logic are removed to limit power consumption to approximately 80µA. If an external 3.3V supply is available, this regulator may

be overdriven by an external 3.3V supply to directly power the logic. This voltage regulator is never powered down.

11.2.2 Regulator for Audio Ampliﬁer

The output of the regulator for the audio amplifier, Aud3V3, drives the load resistor for the microphone and the audio pre-

amplifier. As this regulator is capable of being powered-down via the serial interface, all control signals from the digital logic are

low during low power/standby. This regulator will be powered up by default.

11.2.3 Regulator for Video Supply/Analogue Core

The output of the regulator for the video supply,Vid3V3, powers the analog core. This regulator is capable of being powered-

down via the serial interface but will be powered up by default. Note that the sensor will be in low power mode initially and

therefore

11.3 Valid Supply Voltage Conﬁgurations

The power supplies to the VV5410 and VV6410 sensors can be configured such that the sensor will operate in a number of

systems:

•

USB system (sensor will regulate the nominal 5V supply to 3V3 internally) with optional BJT to provide power for a companion

chip.

•

Direct drive the sensor with 3V3 (internal voltage regulators will be powered down in this mode).

The next 2figures will detail the options described above:

1. Each audio output must have a capacitor (Ccomp) connected to ground to avoid any oscillation

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Other Features

Vddio

Vddhi

Vddcore

Digital

Logic

Voltage

Doubler

100nF

pd

Vbase

390

Vbus

Digital

Regulator

VIN

Reg3v3

5V

Vbg

Vout

(5V)

27uF

VVL410

Aud3v3

5V

Audio

220nF

^pd_aregRegulator

Audio Amp

Vbg

(powered up)

Vid3v3

Vout

Analog

220nF

5V

_{pd_creg}Regulator

Analog Core

(powered up)

Vbg

100nF

Key:

5V0 supply

from USB cable

Figure 47 : USB Power Setup

Regulated 3V3

Vddio

DVDD

(3.3V)

Vddhi

Vddcore

Digital

Logic

Voltage

Doubler

100nF

pd

Vbase

N/C

Vbus

Digital

Regulator

Reg3v3

5V

Vbg

AVDD

Vout

(3.3V)

VVL410

Aud3v3

Vout

5V

Audio

220nF

^pd_aregRegulator

Audio Amp

Vbg

(powered down)

Vid3v3

Vout

Analog

5V

220nF

_{pd_creg}Regulator

Analog Core

(powered down)

Vbg

Key:

Vbg

Analogue 3V3

supply

100nF

Digital 3V3

supply

Figure 48 : Direct drive @3V3 Setup

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Supply

USB System

3.3V-only System

Vbus

Vddio

Supply from USB cable

connect to Vreg3v3

3.3V direct drive

BJT not populated

Vddcore

Vreg3v3

optionally populate external BJT for

added drive

Vid3v3

Aud3v3

generated by internal regulator

internal regulator powered down

Table 63 : Sensor Voltage Supply summary

11.4 Programmable Pins

The FST and QCK pins can be re-configured to follow the values of bits 1 and 2 in the serial interface.register pin_mapping. This

is to allow remote control of a electro-mechanical system, maybe two different crop settings, in a remote camera head via the

serial interface.

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Characterisation Details

12. Characterisation Details

12.1 VV5410/VV6410 AC/DC Speciﬁcation

Parameter

Comment

Units

-

Image Format

356 x 292 pixels (PAL/CIF)

306 x 244 pixels (NTSC)

180 x 148 pixels (QCIF)

Pixel Size

Technology

7.5 x 6.9

µm

-

0.5µm 3 level metal CMOS

Array Format

CIF

81

-

Exposure control range

db

(minimum exposure period 3µs and maximum exposure

1

period is 33ms)

Supply Voltage

3.0-6.0 DC +/-10%

0 - 40

V

^oC

V

Operating Temp. range

2

V_{OL_max}

0.512

3

V_{OH_min}

2.054

V

4

V_{I_maxL}

0.683

V

5

V_{IH_min}

2.237

V

Serial interface frequency

range

0-100kHz

1. We assume CIF (30fps) mode, input clock of 16MHz and internal clock divisor of 1.

2. This is worst case reading. Device outputs had signiﬁcant capacitive loading and supply voltage reduced to 2V7

3. This is worst case reading. Device outputs had signiﬁcant capacitive loading and supply voltage reduced to 2V7

4. This is worst case reading. Device outputs had signiﬁcant capacitive loading and supply voltage reduced to 2V7

5. This is worst case reading. Device outputs had signiﬁcant capacitive loading and supply voltage reduced to 2V7

Table 64 : VV5410/6410 DC speciﬁcation

12.2 VV5410/VV6410 Optical Characterisation Data

Optical Parameter

Min

Typical

Max

Units

Dark Current

Average Sensitivity

-

46

2.1

-

mV/sec

V/lux.sec

mV

Fixed Pattern Noise (FPN)

Vertical Fixed Pattern Noise (VFPN)

Random Noise

1.74

1.2

mV

1.17

c.56

0.9

mV

Sensor SNR

dB

Shading (Gross)

mV

Table 65 : VV5410/VV6410 Optical Characterisation Data

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12.2.1 Noise Parameters and Dark Current

Various noise parameters are measured on the 410 device as follows:

•

Fixed Pattern Noise (FPN)

Vertical Fixed Pattern Noise (VFPN)

Random Noise

Fine Shading

Gross Shading

The parameters will be described in more detail below along with the data produced by the characterisation programme.

12.2.2 Blooming

Blooming is a phenomenon that does not affect CMOS sensors in the same way as CCD imagers are afflicted. With a CCD

blooming can cause an entire column/columns to flood and saturate.

CMOS imagers are however affected by a different type of saturation. If an intense light source, (e.g. Maglite torch), is shone at

very close proximity to the image sensor the pixel sampling mechanism will break down and rather than displaying a saturated

white light a black image will occur.

The 410 pixel architecture uses Correlated Double Sampling (CDS) to help reduce noise in the system. The pixel is read normally

first, yielding the true integrated signal information, then the pixel is reset and very quickly read for a second time. This normally

yields black information - as the pixel has had no exposure time - that can be subtracted from the signal from the first read. This

subtraction will remove much of the noise from the pixel leaving only the useful signal information.

In an example where a pixel has saturated in both the first and the second reads due to an intense light source. When the noise

cancellation subtraction operation is then performed the result is close to zero signal from the pixel therefore resulting in the

displayed black image.

We do not perform any test measurements for this phenomenon.

12.2.3 Dark Current

This is defined as the rate at which the average pixel voltage increases over time with the device not illuminated. The dark current

will be measured at a gain setting of 4 and a clock divisor of 16 at a fixed temperature and will be expressed in mV.

12.2.4 Fixed Pattern Noise

The FPN of an image sensor is the average pixel non-temporal noise divided by the average pixel voltage. The illumination

source will be white light that has been IR filtered, producing a diffuse uniform illumination at the surface of the sensor package.

The FPN will be calculated at coarse exposure settings of 0,10,150,250 and 302 with gain set to 1. 10 frames are grabbed and

averaged to produce a temporally independent frame before each calculation. FPN will be expressed in mV.

12.2.5 Vertical Fixed Pattern Noise

VFPN describes the spatial noise in an image sensor related to patterns with a vertical orientation. The VFPN is defined as the

standard deviation over all columns of the average pixel voltage for each column determined at zero exposure and zero

illumination. VFPN will be expressed in mV.

12.2.6 Random Noise

Random noise is the temporal noise component within the image. Random noise will be expressed in mV.

12.2.7 Shading

This describes how average pixel values per “block” change across the image sensor array. For fine shading calculations the

image sensor array is split into 30 pixel by 30 pixel blocks. An average value is then calculated for each block and the averages

are then compared across the whole device. The blocks are increased in size to 60 pixels by 60 pixels for the gross shading

calculation. Shading will be expressed in mV.

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Characterisation Details

12.3 VV5410/VV6410 Power Consumption

Operating Condition

Current Consumption

Low power mode current consumption

Sleep mode current consumption¹

5.6mA

18mA

85uA

Suspend mode current consumption

(with CLKIP disabled)

Normal operating mode current consumption²

26.2mA

1. Estimated ﬁgures - this parameter was not measured during ﬁnal characterisation

2. Measured while device is clocked at 16MHz and streaming CIF video at 30fps

Table 66 : VV5410/6410 Current consumption in different modes

12.4 Digital Input Pad Pull-up and Pull-down Strengths

Pad Type

Pads

Min current

Max Current

Library pulldown

Library pullup

Custom pullup

suspend

scl, sda, oeb

resetb

35uA

25uA

66uA

52uA

42uA

250uA

Table 67 : Pad Pull-up/Pull-down Strengths

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13. Pixel Defect Speciﬁcation

13.1 Pixel Fault Deﬁnitions

Please find the pixel notation described in Figure 49 below. For the purposes of the test the 3x3 array describes 9 bayer pixels of

a common colour, i.e. ALL the pixels will either be Red, Green or Blue. The pixel under test is X.

[0] [1] [2]

[7]

X

[3]

[6] [5] [4]

Figure 49 : Pixel Numbering Notation

13.2 Stuck at White Pixel Fault

A pixel is said to be “stuck at white” - it can also be referred to as “hot” - if it is saturated (pixel output at maximum) even with no

incident light and exposure set to zero.

13.3 Stuck at Black Pixel Fault

A pixel is said to be “stuck at black” - it can also be referred to as “dead” - if the pixel output is zero even if the pixel is fully

exposed to incident light.

13.4 Column / Row Faults

A line of continuous pixel fails of length > 3 will be described as a row fault in the x-direction and a column fault in the y-direction.

If the array contains more than 1 row or column fault and the defective pixels overlap as shown in Figure 50 then this fault is

described as a double row or double column fault respectively. The minimum overlap is 1 pixel. A defective pixel is indicated by X

and a good pixel by ‘p’.

n

X

n+1

‘p’

p

X

‘p’

X

Figure 50 : Double Column Fault

In Figure 51 there are 2 column faults however there is no overlap between the 2 columns therefore there are 2 single column

faults but no double column faults.

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Pixel Defect Specification

n

X

n+1

‘p’

p

X

‘p’

X

‘p’

X

Figure 51 : Single Column Faults

13.5 Image Array Blemishes

The automatic test programme rejects any sensors that contain blemishes referred to as blobs and clusters (please see below for

definitions of these terms) as they cannot be successfully defect corrected by ST coprocessor devices. Up to 120 single pixel

faults can be corrected and sensors meeting this criteria will PASS this part of the test programme.

13.5.1 Cluster Deﬁnition

A failing pixel at X with a failing pixel at position [0] or [1] or [2] or [3] or [4] or [5] or [6] or [7] or any combination of these 8

positions except the case where all positions are defective. This is a special case and is described below. In the example in

Figure 52 there are additional pixel fails in positions [3] and [7].

[0] [1] [2]

[X]

X

[X]

[6] [5] [4]

Figure 52 : Cluster Example

Blob (special case of cluster):- a failing pixel at position X with failing pixels at position [0],[1],[2],[3],[4],[5],[6] and [7] as in Figure

53 below:

[X] [X] [X]

[X]

X

[X]

[X] [X] [X]

Figure 53 : Blob Example

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Single pixel:- a failing pixel with no immediate failing same colour neighbours. Pixels at position [0],[1],[2],[3],[4],[5],[6] and [7] are

all valid pixels. Please see Figure 54 below.

[0] [1] [2]

[7]

X

[3]

[6] [5] [4]

Figure 54 : Isolated pixel fail

13.5.2 Summary Pass Criteria

1

Clusters Blobs Row Fails (inc doubles) Column Fails (inc doubles) Single pixel fails Notes

0

<=120

Pass

Table 68 : Sensor Pixel Defect Pass Criteria

1. If there is a non-zero number of clusters, blobs or row/column faults and greater than 120 single pixel defects then the

device will be rejected and classed as a fail.

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Pinout and pin descriptions

14. Pinout and pin descriptions

14.1 36pin CLCC Pinout Map

16

21

17

23

22

20

18

15

19

D[1]

D[2]

24

25

26

27

28

29

SDA

14

PORB

13

12

D[3]

SUSPEND

D[4]

11 Vid3V3

LST/D[5]

FST/D[6]

AVSS

10

VDDhi

9

CLKI 30

8

Vbloom

D[7]

31

32

7

6

Vbltw

QCK

AoutN

33

1

34

35

36

3

2

4

5

Figure 55 : 36 pin CLCC package pin assignment

Name

Pin Number Type

Description

POWER SUPPLIES

AVSS

10

GND

Core analog ground and reference supplies.

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Name

Pin Number Type

Description

SRAMVSS

17

34

GND

PWR

In-column SRAM analog ground.

VDDcore/

Reg3V3

Digital logic power.

VDDio

33

22

23

11

3

PWR

GND

PWR

Digital pad ring power.

VSScore

VSSio

Digital logic ground.

Digital pad ring ground.

Vid3V3

Aud3V3

On-chip Video Supply Voltage Regulator Output

On-chip Audio Amplifier Voltage Regulator Output

ANALOG SIGNALS

VBG

1

OA

IA

Internally generated bandgap reference voltage 1.22V

Voltage doubler output, 4.6V -> 4.8V

Drive for base of external bipolar

VDDHI

VBase

Vbus

9

35

36

4

OA

IA

Incoming power supply 3.3 -> 6V

AIN

IA

Analog input to Audio Amplifier

AOutP

AOutN

PORB

5

OA

OD

Analog output of Audio Amplifier (positive)

Analog output of Audio Amplifier (negative)

Power-on Reset (Bar) Output.

6

13

DIGITAL VIDEO INTERFACE

D[4]

27

26

25

24

20

32

28

ODT

Tri-stateable 5-wire output data bus.

- D[4] is the most significant bit.

D[3]

D[2]

- D[4:0] have programmable drive strengths 2, 4 and 6 mA

D[1]

D[0]

QCK

LST/D[5]

ODT

Tri-stateable data qualification clock.

Tri-stateable Line start output

May be configured as tri-stateable output data bit 5 D[5].

Tri-stateable Frame start signal.

FST/D[6]

D[7]

29

31

16

ODT

ID↓

May be configured as tri-stateable output data bit 6 D[6].

Tri-stateable Data wire (ms data bit).

May be configured as tri-stateable output data bit 6 D[6].

Digital output (tri-state) enable.

OEB

DIGITAL CONTROL SIGNALS

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Pinout and pin descriptions

Name

Pin Number Type

Description

RESETB

21

ID↑

System Reset. Active Low.

May be configured as System Sync. Active Low.

USB Suspend Mode Control signal. Active High

SUSPEND

12

ID↑

If this feature is not required then the support circuit must pull the pin to

ground. The combination of an active high signal and pull up pad was

chosen to limit current drawn by the device while in suspend mode.

SERIAL INTERFACE

SCL

SDA

15

14

BI↑

Serial bus clock (input only).

Serial bus data (bidirectional, open drain).

SYSTEM CLOCKS

CLKI

30

ID↓

Schmitt Buffered Clock input or LVDS positive Clock input

Key

A

Analog Input

Analog Output

Bidirectional

D

Digital Input

OA

BI

ID↑

ID↓

OD

ODT

Digital input with internal pull-up

Digital input with internal pull-down

Digital Output

BI↑

BI↓

Bidirectional with internal pull-up

Bidirectional with internal pull-down

Tri-stateable Digital Output

Name

Type

Description

ANALOG SIGNALS

Anti-blooming pixel reset voltage¹

Bitline test white level reference ²

Pixel reset voltage³

Vbloom

8

7

2

OA

VBLTW

VRT

OA

IA

1. This pin has been removed from the production bonding diagram

2. This pin has been removed from the production bonding diagram

3. This pin has been removed from the production bonding diagram

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15. Package Details (36pin CLCC)

VV5410 & VV6410

2 . 0 2

1 . 0 2 0 . 1 3

8 . 1 3 0 . 1 3

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Recommended VV5410/6410 support circuit

16. Recommended VV5410/6410 support circuit

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17. Evaluation kits (EVK’s)

VV5410 & VV6410

It is highly recommended that an Evaluation Kit (EVK) is used for initial evaluation and design-in of the VV5410/6410. A VV5410/

VV6410 evaluation kit can now be ordered. Please contact STMicroelectronics for details.

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Ordering details

18. Ordering details

Part Number

Description

VV5410C036

VV6410C036

36pin CLCC packaged, microlensed CIF monochrome sensor

36pin CLCC packaged, microlensed CIF ColourMOS sensor

YUV/RGB CoProcessor

STV0657

STV0672

USB companion CoProcessor

STV0680B-001

STV-5410-R01

STV-6410-R01

STV-USB/CIF-R01

STV-YUV/CIF-R02

STV-DCA/CIF-R01

STV-5410/5500-E01

STV-6410/6500-E01

Digital stills companion CoProcessor

Reference design board for VV6410C036

Reference design board for VV6410C036 & STV0672

Reference design board for VV6410C036 & STV0657-001

Reference design board for VV6410C036 & STV0680B-001

Sensor only evaluation kit for VV6410C036 & VV6500-C048

Table 69 : VV6410/VV5410 Ordering Details

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CMOS Sensor; Customer Datasheet, Rev 3.0,28 September 2000

cd5410-6410f

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of STMicroelectronics

The ST logo is a registered trademark of STMicroelectronics

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Imaging Division

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型号：	STV-USB/CIF-R01
厂家：	ST
描述：	Mono and Colour Digital Video CMOS Image Sensors 黑白和彩色数字视频CMOS图像传感器传感器图像传感器
文件：	总105页 (文件大小：1077K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STV-USB/CIF-R01 [STMICROELECTRONICS]

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