STV0042 [STMICROELECTRONICS]
SATELLITE SOUND AND VIDEO PROCESSORS; 卫星声音和视频处理器
| 型号： | STV0042 |
| 厂家： | 
ST |
| 描述： | SATELLITE SOUND AND VIDEO PROCESSORS |
| 文件： | 总24页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STV0042A
SATELLITE SOUND AND VIDEO PROCESSORS
PRODUCT PREVIEW
SOUND
.
TWO INDEPENDENT SOUND DEMODULATORS
PLL DEMODULATION WITH 5-10MHz
FREQUENCY SYNTHESIS
.
.
PROGRAMMABLE FM
DEMODULATOR
BANDWIDTH ACCOMODATING FM DEVIA-
TIONS FROM ±30kHz TILL ±400kHz
.
µ
PROGRAMMABLE 50/75 s OR NO DE-EM-
PHASIS
SHRINK42
(Plastic Package)
.
.
DYNAMIC NOISE REDUCTION
ONE OR TWO AUXILIARY AUDIO INPUTS
AND OUTPUTS
GAIN CONTROLLED AND MUTEABLE
AUDIO OUTPUTS
ORDER CODE : STV0042A
.
.
HIGH IMPEDANCE MODE AUDIO OUTPUTS
FOR TWIN TUNER APPLICATIONS
PIN CONNECTIONS
VIDEO
FC R
PK IN
A GND R
FC L
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
.
COMPOSITE VIDEO 6-bit 0 to 12.7dB GAIN
CONTROL
COMPOSITE VIDEO SELECTABLE IN-
VERTER
TWO SELECTABLE VIDEO DE-EMPHASIS
NETWORKS
4 x 2 VIDEO MATRIX
HIGH IMPEDANCE MODE VIDEO OUTPUTS
FOR TWIN TUNER APPLICATIONS
2
.
.
SUM OUT
VOL R
PK OUT
IREF
3
4
S1 VID OUT
S2 VID OUT
VOL L
CPUMP R
U75 R
DET R
AMPLK R
A 12V
5
.
.
6
7
S2 VID RTN
S2 OUT L
CLAMP IN
S2 OUT R
UNCL DEEM
VIDEEM2/22kHz
V 12V
8
9
MISCELLANEOUS
VREF
10
11
12
13
14
15
16
17
18
19
20
21
.
22kHzTONE GENERATIONFOR LNB CONTROL
2
.
A GND L
AGC R
AMPLK L
U75 L
I C BUS CONTROL :
CHIP ADDRESSES = 06HEX
LOW POWER STAND-BY MODE WITH ACTIVE
AUDIO AND VIDEO MATRIXES
.
VIDEEM1
V GND
DET L
CPUMP L
GND 5V
VDD 5V
XTL
DESCRIPTION
B-BAND IN
S2 RTN L
S2 RTN R
FM IN
The STV0042ABICMOS integrated circuitrealizes
all the necessary signal processing from the tuner
to the Audio/Video input and output connectors
regardless the satellite system.
The STV0042 is intended for low cost satellite
receiver application.
SDA
AGC L
SCL
1/24
March 1997
STV0042A
PIN ASSIGNMENT
Pin Number
Name
FC R
Function
1
3
Audio Roll-off Right
SUM OUT
PK IN
Noise Reduction Summing Output
Noise Reduction Peak Detector Input
Volume Controlled Audio Out Right
TV-Scart 1 Video Output
VCR-Scart 2 Video Output
Volume Controlled Audio Out Left
VCR-Scart 2 Video Return
Fixed Level Audio Output Left
Sync-Tip Clamp Input
2
4
VOL R
5
S1 VID OUT
S2 VID OUT
VOL L
6
7
8
S2 VID RTN
S2 OUT L
CLAMP IN
S2 OUT R
UNCL DEEM
9
10
11
12
Fixed Level Audio Output Right
Unclamped Deemphasized Video Output
Video Deemphasis 2 or 22kHz Output
Video 12V Supply
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VIDEEM2/22kHz
V 12V
VIDEEM1
V GND
B-BAND IN
S2 RTN L
S2 RTN R
FM IN
Video Deemphasis 1
Video Ground
Base Band Input
Auxiliary Audio Return Left
Auxiliary Audio Return Right
FM Demodulator Input
AGC L
AGC Peak Detector Capacitor Left
I2C Bus Clock
SCL
SDA
I2C Bus Data
XTL
4/8MHz Quartz Crystal or Clock Input
Digital 5V Power Supply
VDD 5V
GND 5V
CPUMP L
DET L
Digital Power Ground
FM PLL Charge Pump Capacitor Left
FM PLL Filter Left
U75 L
Deemphasis Time Constant Left
Amplitude Detector Capacitor Left
AGC Peak Detector Capacitor Right
Audio Ground
AMPLK L
AGC R
A GND L
VREF
2.4V Reference
A 12V
Audio 12V Supply
AMPLK R
DET R
Amplitude Detector Capacitor Left
FM PLL Filter Right
U75 R
Deemphasis Time Constant Right
FM PLL Charge Pump Capacitor Right
Current Reference Resistor
Noise Reduction Peak Detector Output
Audio Roll-off Left
CPUMP R
IREF
PK OUT
FC L
A GND R
Audio Ground
2/24
STV0042A
PIN DESCRIPTION
1 - Sound Detection
FMIN
This is the input to the two FM demodulators. It
feeds two AGC amplifiers with a bandwidth of at
least 5-10MHz. There is one amplifier for each
channelboth with the same input. The AGC ampli-
fiers have a 0dB to +40dB range.
the chip, for the biasing of amplifiers with current
outputs into filters. It is also required for the Noise
reduction circuit to provide accurate roll-off fre-
quencies.
This pin should not be decoupled as it would inject
µ ±
current noise. The target current is 50 A 2% thus
a 47.5kΩ ±1% is required.
ZIN = 5kΩ, Min input = 2mVPP per subcarrier.
Max input = 500mVPP (max when all inputs are
added together, when their phases coincide).
A 12V
Double bonded main power pin for the audio/FM
section of the chip. The two bond connectionsare
to the ESD and to power the circuit and on chip
regulators/references.
AGC L, AGC R
AGC amplifiers peak detector capacitor connec-
tions. The output current has an attack/decayratio
of 1:32. That is the ramp up current is approxi-
mately 5µA and decay current is approximately
A GND L
This ground pin is double bonded :
1) to channel LEFT : RF section & VCO,
2) to both AGC amplifiers, channel LEFT and
RIGHT audio filter section.
µ
160 A. 11V gives maximum gain. These pins are
also driven by a circuit monitoring the voltage on
AMPLK L and AMPLK R respectively.
A GND R
AMPLK L, AMPLK R
This ground pin is double bonded :
1) to the volume control, noise reduction system,
ESD + Mux + VREF
The outputs of amplitude detectors LEFT and
RIGHT. Each requires a capacitorand a resistorto
GND. The voltage across this is used to decide
whether there is a signalbeing received by the FM
detector. The level detector output drives a bit in
the detector I2C bus control block.
2) to channel right : RF section & VCO
2 - Baseband Audio Processing
AMPLK L and AMPLK R drive also respectively
AGC L and AGC R. For instance when the voltage
on AMPLK L is > (VREF + 1 VBE) it sinks current to
PK OUT
The noise reduction control loop peak detector
output requires a capacitorto groundfrom this pin,
and a resistor to VREF pin to give some accurate
decaytimeconstant.Anon chip5k
and external capacitor give the attack time.
VREF from pin AGCL to reduce the AGC gain.
Ω ±
25 % resistor
DET L, DET R
Respectivelythe outputsof the FM phase detector
left and right. This is for the connection of an
external loop filter for the PLL. The output is a
push-pullcurrent source.
PK IN
This pin is an input to a control loop peak detector
and is connectedto theoutputof the offchipcontrol
loop band pass filter.
CPUMP L, CPUMP R
The output from the frequency synthesizer is a
push-pullcurrent sourcewhich requiresa capacitor
to ground to derive a voltage to pull the VCO to the
target frequency. The output is ±100µA to achieve
lockand ±2µAduringlock to providea trackingtime
constant of approximately10Hz.
SUM OUT
The two audio demodulated signals are summed
togetherby meansof an amplifierwith a gainof 0.5.
If both inputs are 1V then the output is 1V. This
amplifier has an input follower buffer which gives a
VBE offset in the DC bias voltage. Thus the filter
which this amplifier drives must include AC cou-
pling to the next stage (PK IN Pin).
VREF
This is the audio processorvoltage referenceused
through out the FM/audio section of the chip. As
such it is essential that it is well decoupled to
ground to reduce as far as possible the risk of
crosstalk and noise injection. This voltage is de-
rived directly from the bandgap reference of 2.4V.
The VREF output can sink up to 500µA in normal
operationand 100µA when in stand-by.
FC L, FC R
The variable bandwidth transconductance ampli-
fier has a current output which is variable depend-
ing on the input signal amplitude as defined by the
control loop of the noise reduction. The output
current is then dumped into an off-chip capacitor
which together with the accurate current reference
define the min/maxrolloff frequencies.A resistor in
serieswith a capacitorisconnected to ground from
these two pins.
IREF
Thisis a bufferedVREF outputto an off-chipresistor
to produce an accurate current reference, within
3/24
STV0042A
PIN DESCRIPTION (continued)
U75 L, U75 R
video at the clamp input is only 1VPP. This clamped
video which is de-emphasised, filtered and clamped
(energydispersalremoved)isnormal,negativesyncs,
video. This signal drives the Video Matrix input called
Normal Video. It has a weak (1.0µA ±15 %) stable
current source pulling the input towards GND. Other-
wise the input impedance is very high at DC to 1kHz
ZIN > 2MΩ. Video bandwidth through this is -1dB at
5.5MHz.The CLAMPinputDC restore voltageis then
usedas a meansforgettingthecorrectDC voltageon
theSCART outputs.
External deemphasis networks for channels left and
right. For each channel a capacitor and resistor in
parallel of 75µs time constant are connectedbetween
hereandVREF toprovide75µs de-emphasis.Internally
selectable is an internal resistor that can be pro-
grammedtobeaddedinparalleltherebyconvertingthe
networktoapprox50µsde-emphasis(seecontrolblock
map).Thevalue oftheinternalresistorsis30kΩ±30%.
Theamplifierforthisfilterisvoltageinput,currentoutput;
with ±500mVinputthe outputwill be ±55µA.
S2 VID RTN
VOL L, VOL R
Ω
External video input 1.0VPP AC coupled 75
Themainaudiooutputfromthevolumecontrolamplifier
the signal to get output signals as high as 2VRMS
(+12dB)ona DCbiasof4.8V.Controlisfrom+12dBto
-26.75dB plus Mute with 1.25dB steps. This amplifier
has short circuit protection and is intended to drive a
SCART connectordirectly via AC coupling and meets
thestandardSCARTdriverequirements.Theseoutputs
featurehighimpedancemodeforparallelconnection.
sourceimpedance.This input has a DCrestoration
clamp on its input. The clamp sink current is 1µA
15% with the buffer ZIN > 1M . This signal is an
±
Ω
input to the Video Matrix.
S1 VID OUT, S2 VID OUT
Videodrivers forSCART1 andSCART2. Anexternal
emitterfollowerbufferis requiredto drivea 150Ω load.
The average DC voltage to be 1.5V on the O/P. The
signalisvideo2.0VPP 5.5MHzBWwithsynctip=1.2V.
These pins get signals from the Video Matrix. The
signalselectedfromtheVideoMatrixforoutputon this
pin is controlled by a controlregister. This outputalso
featureahighimpedancemodeforparallelconnection.
S2 OUT L, S2 OUT R
These audio outputs are sourced directly from the
audioMUX, andas a resultdo notincludeany volume
controlfunction.Theywill outputa1VRMS signalbiased
at4.8V.Theyareshortcircuitprotected.Theseoutputs
featurehigh impedance mode for parallel connection
and meetSCART drive requirement.
V 12V
S2 RTN L, S2 RTN R
+12V double bonded : ESD+guardrings and video
circuit power.
These pins allow auxiliary audio signals to be con-
nected to the audio processor and hence makes
use of the on-chip volume control. For additional
details please refer to the audio switching table.
V GND
Doubled bonded. Clean VID IN GND. Strategically
placed video power ground connection to reduce
video currents getting into the rest of the circuit.
3 - Video Processing
B-BAND IN
AC-coupled video input from a tuner.
4 - Control Block
GND 5V
The main power ground connectionfor the control
logic, registers, the I2C bus interface, synthesizer
& watchdog and XTLOSC.
Ω ±
Z
IN >10k 25%. Thisdrivesanon-chipvideo ampli-
fier.TheotherinputofthisampisACgroundedbybeing
connectedtoan internal VREF. The videoamplifierhas
selectablegainfrom0dBto 12.7dBin 63 stepsand its
outputsignalcan be selectednormal or inverted.
VDD 5V
Digital +5V power supply.
UNCL DEEM
Deemphasized still unclamped output. It is also an
SCL
input of the video matrix.
Thisis theI2C busclock line.Clock= DCto100kHz.
VIDEEM1
Ω
Requires external pull up eg. 10k to 5V.
Connected to an external de-emphasis network
(for instance 625 lines PAL de-emphasis).
SDA
This is the I2C bus data line. Requires external pull
VIDEEM2 / 22kHz
up eg. 10kΩ to 5V.
Connected to an external de-emphasis network
(forinstance525 lines NTSCor othervideo de-em-
phasis).Alternativelya precise22kHz tone maybe
output by I2C bus control.
XTL
This pin allowsfor theon-chip oscillatorto be either
used with a crystal to ground of 4MHz or 8MHz, or
to be driven by an external clock source. The
external source can be either 4MHz or 8MHz. A
programmablebit in thecontrol blockremovesa 2
block when the 4MHz option is selected.
CLAMP IN
÷
Thispinclampsthemostnegativeextremeoftheinput
(thesync tips) to2.7VDC (orappropriatevoltage).The
4/24
STV0042A
GENERAL BLOCK DIAGRAM
B-BAND
Video
Processing
2
2
From Tuner
4 x 2
Video
Matrix
2
2
From
VCR/Decoder
1
To TV, VCR/Decoder
FM
From Tuner
Demodulation
2 Channels
Audio
Matrix
+
Volume
Noise
Reduction +
Deemphasis
I2C Bus
Interface
22kHz to LNB
Active in Stand-by
STV0042A
VIDEO PROCESSING BLOCK DIAGRAM
LPF
NTSC
PAL
UNCL DEEM
12
VIDEEM2/22kHz
13
VIDEEM1
15
22kHz
TONE
Deemphasized
÷ 2
B-BAND IN
CLAMP IN
± 1
17
G
Baseband
Normal
CLAMP
10
8
VCR / Decoder Return
CLAMP
S2 VID RTN
STV0042A
6
5
S2 VID OUT
To Decoder or VCR
S1 VID OUT
To TV
5/24
STV0042A
AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL RIGHT)
STV0042A
a
K2
a
c
K1
b
a
AUDIO
DEEMPHASIS
ANRS
5
MONO
STEREO
AUDIO R
K3
b
b
c
K5
-6dB
6dB
11
36
19 40
2
3
1
41
37
4
PLL
FILTER
TV
DECODER OR VCR
AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL LEFT)
STV0042A
a
b
K2
a
c
K1
a
AUDIO
DEEMPHASIS
ANRS
5
MONO
STEREO
AUDIO L
K3
b
b
c
K5
-6dB
6dB
9
28
18 40
2
3
1
41
29
7
PLL
FILTER
TV
DECODER OR VCR
6/24
STV0042A
AUDIO SWITCHING
K2
K3
AUDIO
DEEMPHASIS
+ ANRS
K1a
K5b
K5c
K5a
a
b1
b2
ON
ON
ON
No ANRS, No De-emphasis
No ANRS, 50µs
No ANRS, 75µs
a
b1
b2
OFF
OFF
OFF
ANRS, No De-emphasis
AUDIO PLL
AUX IN
ANRS, 50 s
µ
ANRS, 75 s
µ
K1c
VOL OUT AUX OUT
FM DEMODULATION BLOCK DIAGRAM
Phase
Detect
DET R
SW1
AGC
FM IN
AGC R
AUDIO R
FM dev.
Select.
LEVEL
DETECTOR 1
Bias
CPUMP R
LEVEL
DETECTOR 2
VREF
Amp. Detect
AMPLK R
90
VCO
0
SW2
SW4
WATCHDOG
VREF
Reg8 b4
SYNTHESIZER
AUDIO L
Phase
Detect
DET L
SW3
AGC
FM dev.
Select.
LEVEL
DETECTOR 1
Bias
AGC L
CPUMP L
LEVEL
DETECTOR 2
VREF
Amp. Detect
AMPLK L
90
VCO
0
WATCHDOG
VREF
Reg8 b0
STV0042A
7/24
STV0042A
CIRCUIT DESCRIPTION
1 - Video Section
The composite video is first set to a standard level
by means of a 64 step gain controlled amplifier. In
thecasethat themodulationis negative,an inverter
can be switched in.
recovered audio regardless of variations between
satellites or subcarriers, the PLLloop gain may be
programmed from 56 values.
Any frequency deviation can be accomodated
(from ±30kHz till ±400kHz).
In the typical application, the STV0042Aoffers two
audio de-emphasis75µs and 50µs. Whenrequired
a J17 de-emphasis can be implemented by using
specificapplicationdiagram(seeApplicationNote:
AN838, Chapter 4.2).
A dynamic noise reduction system (ANRS) is inte-
grated into the STV0042A using a lowpass filter,
the cut-off frequency of which is controlled by the
amplitude of the audio after insertion of a band-
pass filter.
One of two different external video de-emphasis
networks (for instance PAL and NTSC) is select-
able by an integrated bus controlled switch.
Then energy dispersal is removed by a sync tip
clamping circuit, which is used on all inputs to a
video switching matrix, thus making sure that no
DC steps occur when switching video sources.
The matrix can be used to feed video to and from
decoders, VCR’s and TV’s.
Additionaly all the video outputs are tristate type
(high impedance mode is supported), allowing a
simple parallel connections to the scarts (Twin
tuner applications).
Two types of audio outputs are provided : one is a
fixed 1VRMS and the other is a gain controlled
2VRMS max. The control range being from +12dB
to -26.75dBwith 1.25dBsteps.Thisoutputcanalso
be muted.
A matrix is implementedto feed audio to and from
decoders VCR’s and TV’s.
2 - Audio Section
The two audio channelsare totally independentex-
cept for the possibility given to output on bothchan-
nels onlyone of the selected input audio channels.
Noise reduction system and de-emphasis can be
inserted or by-passed through bus control.
To allow a very cost effective application, each
channel uses PLL demodulation. Neither external
complex filter nor ceramic filters are needed.
Also all the audio outputs are tristate-type (high
impedance mode is supported),allowinga simple
parallel connections to the scarts (Twin tuner
applications).
The frequency of the demodulated subcarrier is
chosen by a frequencysynthesizer which sets the
frequency of the internal local oscillator by com-
paring its phase with the internally generated
reference. When the frequency is reached, the
microprocessor switches in the PLL and the de-
modulationstarts. Atany momentthe microproces-
sor can read from the device (watchdog registers)
the actual frequency to which the PLL is locked. It
canalsoverifythat a carrierispresentatthe wanted
frequency(by reading AMPLK status bit) thanks to
a synchronous amplitude detector, which is also
used for the audio input AGC.
3 - Others
A 22kHz tone is generated for LNB control.
It is selectable by bus controland availableon one
of the two pins connected to the external video
de-emphasisnetworks.
By means of the I2C bus there is the possibility to
drive the ICs into a low power consumption mode
with active audio and video matrixes. Inde-
pendantly from the main power mode, each indi-
vidual audio and video outputcan be driven to high
impedance mode.
In order to maintain constant amplitude of the
8/24
STV0042A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
VDD
Supply Voltage
15
7.0
V
V
Ptot
Toper
Tstg
Total Power Dissipation
900
mW
oC
oC
Operating Ambient Temperature
Storage Temperature
0, + 70
-55, + 150
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction-ambient
Value
Unit
oC/W
Rth(j-a)
60
DC AND AC ELECTRICAL CHARACTERISTICS
(VCC = 12V, VDD = 5V, Tamb = 25oC unless otherwise specified)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
VCC
VDD
Sypply Voltage
Supply Current
11.4
4.75
12
12.6
5.25
V
V
5.0
IQCC
IQDD
All audio and all video outputs
activated
55
8
70
15
mA
mA
IQLPCC Supply Current at Low Power Mode
IQLPDD
All audio and all video outputs
are in high impedance mode
27
6
35
9
mA
mA
AUDIO DEMODULATOR
FMIN
FM Subcarrier Input Level
(Pin FMIN for AGC action)
VCO locked on carrier at 6MHz
560kΩ load on AMPLOCK Pins
180kΩ load on DET Pins
5
500 mVPP
DETH
Detector 1 and 2 (AMPLOCK Pins)
8mVPP FMIN 500mV
2.90 3.10 3.30
V
≤
≤
PP
(Threshold for activating Level Detector 2) Carrier without modulation
VCOMI VCO Mini Frequency
VCOMA VCO Maxi Frequency
V
CC : 11.4 to 12.6V,
5
MHz
MHz
VPP
Tamb : 0 to 70oC
10
AP50
1kHz Audio Level at PLL output
(DET Pins)
0.5VPP 50kHz dev. FM input,
Coarse deviation set to 50kHz
(Reg. 05 = 36HEX
0.6
1
1.35
)
APA50 1kHz Audio Level at PLL output
(DET Pins)
0.5VPP 50kHz dev. FM input,
Coarse and fine settings used
0.92
0
1
1.08
1
VPP
dB
FMBW FM Demodulator Bandwidth
Gain at 12kHz versus 1kHz
0.3
60
180k , 82k 22pF on DET Pins
Ω
Ω
DPCO Digital Phase Comparator Output Current
(CPUMP Pins)
Average sink and source
current to external capacitor
µA
AUTOMATIC NOISE REDUCTION SYSTEM
LRS
Output Level (Pin SUMOUT)
1VPP on left and right channel
0.9
4.0
1
1.1
6.8
VPP
LDOR Level Detector Output Resistance
(Pins PK OUT)
5.4
kΩ
NDFT
Level Detector Fall Time Constant
(Pins PK OUT)
External 22nF to GND and
1.2MΩ to VREF
26.4
ms
NDLL
LLCF
Bias Level (Pins PK OUT)
No audio in
2.40
0.85
V
Noise Reduction Cut-off Frequency at
Low Level Audio
100mVPP on DET Pins, External
capacitor 330pF (FC Pins)
kHz
HLCF
Noise Reduction Cut-off Frequency at
High Level Audio
1VPP on DET Pins, External
capacitor 330pF (FC Pins)
7
kHz
9/24
STV0042A
DC AND AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 12V, VDD = 5V, Tamb = 25oC unless otherwise specified)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
AUDIO OUTPUT (Pins VOL OUT R, VOL OUT L)
DCOL
AOLN
DC Output Level
4.8
V
Audio Output Level
with Reg 00 = 1A
FM input as for APA50
1.5
2.0
2.0
60
1.9 2.34 VPP
No de-emphasis, No pre-emphasis
No noise reduction
AOL50
AOL75
Audio Output Level
with Reg 00 = 1A
FM input as for APA50
50µs de-emphasis, 27kΩ//2.7nF load
No pre-emphasis, No noise reduction
3.3
3.3
4.0
4.0
VPP
Audio Output Level
with Reg 00 = 1A
FM input as for APA50
VPP
75 s de-emphasis, 27k //2.7nF load
µ
Ω
No pre-emphasis, No noise reduction
AMA1
MXAT
Audio Output Attenuation
with Mute-on. Reg 00 = 00.
1VPP - 1kHz from S2 RTN Pins
65
dB
dB
Max Attenuation before Mute.
Reg 00 = 01.
1kHz, from S2 RTN Pins
32.75
MXAG
ASTP
Audio Gain. Reg 00 = 1F.
Attenuation of each of the 31 steps
THD with Reg 00 = 1A
1kHz, from S2 RTN Pins
1kHz
5
6
7
dB
dB
%
1.25
0.15
0.3
THDA1
THDA2
1VPP -1kHz from S2 RTN Pins
2VPP -1kHz from S2 RTN Pins
FM input as for APA50
THD with Reg 00 = 1A
1
1
%
THDFM THD with Reg 00 = 1A
0.3
%
75 s de-emphasis, ANRS ON
µ
ACS
Audio Channel Separation
1VPP -1kHz on S2 RTN Pins
60
74
60
dB
dB
ACSFM Audio Channel Separation at 1kHz
- 0.5 VPP - 50kHz deviation FM input on
one channel
- 0.5VPP no deviation FM input on the
other channel
- Reg 05 = 36HEX
- 75 s de-emphasis, no ANRS
µ
SNFM
Signal to Noise Ratio
FM input as for APA50,
75µs de-emphasis,
56
69
dB
dB
no ANRS, Unweighted
SNFMNR Signal to Noise Ratio
FM input as for APA50
75µs de-emphasis,
ANRS ON, Unweighted
ZOUT L
ZOUT H
Audio Output Impedance
Low impedance mode
High impedance mode
18
44
Ω
kΩ
30
55
AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L)
DCOLAO DC output level Aux. input pins open circuit
4.8
2
V
AOLNS
Audio Output Level on S2
FM input as for APA50
No de-emphasis, No pre-emphasis
No noise reduction
1.55
2.0
2.42 VPP
AOL50S Audio Output Level on S2
AOL75S Audio Output Level on S2
THDAOFM THD on S2
FM input as for APA50
3.4
3.4
0.3
4.0
4.0
1
VPP
VPP
%
50µs de-emphasis, 27kΩ//2.7nF load
No pre-emphasis, No noise reduction
FM input as for APA50
2.0
75 s de-emphasis, 27k //2.7nF load
µ
Ω
No pre-emphasis, No noise reduction
FM input as for APA50
75 s de-emphasis, no ANRS
µ
ZOUT L
ZOUT H
Audio Output Impedance
Low impedance mode
High impedance mode
60
44
100
55
Ω
kΩ
30
10/24
STV0042A
DC AND AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 12V, VDD = 5V, Tamb = 25oC unless otherwise specified)
Symbol
RESET
Parameter
Test Conditions
Min. Typ. Max. Unit
RTCCU
RTCCD
RTDDU
RTDDD
End of Reset Threshold for VCC
Start of Reset Threshold for VCC
End of Reset Threshold for VDD
Start of Reset Threshold for VDD
VDD = 5V, VCC going up
8.7
7.9
3.8
3.5
V
V
V
V
VDD = 5V, VCC going down
VCC = 12V, VDD going up
VCC = 12V, VDD going down
COMPOSITE SIGNAL PROCESSING
VIDC
ZVI
VID IN
External load current < 1µA
2.25 2.45 2.65
V
kΩ
V
VID IN Input Impedance
DC Output Level (Pins VIDEEM)
7
11
14
DEODC
DEOMX
2.25 2.45 2.65
2
Max AC Level before Clipping
(Pins VIDEEM)
GV = 0dB, Reg 01 = 00
VPP
DGV
INVG
Gain error vs GV @ 100kHz
Inverter Gain
GV = 0 to 12.7dB, Reg 01 = 00 → 3F
-0.5
-0.9
0
-1
0
0.5
-1.1
1
dB
VISOG
Video Input to SCART Output Gain De-emphasis amplifier mounted in unity -1
gain, Normal video selected
dB
MHz
%
DEBW
DFG
Bandwidth for 1VPP input
measured on Pins VIDEEM
@ - 3dB with GV = 0dB, Reg 01 = 00
10
Differential Gain on Sync Pulses GV = 0dB, 1VPP CVBS + 0.5VPP
measured on Pins VIDEEM 25Hz sawtooth (input : VID IN)
1
ITMOD
Intermodulation of FM subcarriers 7.02 and 7.2MHz sub-carriers,
with chroma subcarrier 12.2dB lower than chroma
-60
dB
CLAMP STAGES (Pins CLAMP IN, S2)
ISKC
ISCC
Clamp Input Sink Current
V
IN = 3V
0.5
40
1
1.5
60
µA
µA
Clamp Input Source Current
VIN = 2V
@ 5MHz
@ 100kHz
50
VIDEO MATRIX
XTK
BFG
Output Level on any Output when
1VPP CVBS input is selected for
any other output
-60
2
dB
Output Buffer Gain
(Pins S1 VID OUT, S2 VID OUT)
1.87
16
2.13
DCOLVH DC Output Level
High impedance mode
High impedance mode
0
0.2
30
V
kΩ
V
ZOUT HV
VCL
Video Output Impedance
23
Sync Tip Level on Selected Outputs 1VPP CVBS through 10nF on input
(Pins S1 VID OUT, S2 VID OUT)
1.05 1.3 1.55
11/24
STV0042A
PIN INTERNAL CIRCUITRY
S2 VID RTN, CLAMP IN
VIDEEM1
Ron of the transistor gate is 10k .
µ
≈
Ω
50 A source is active only when VIDIN < 2.7V.
Figure 1
Figure 5
V
DD 9V
6µ/2µ
10µ/2µ
50µA
VIDEEM1
1
10kΩ
1µA
S2 VID RTN
CLAMP IN
125µA
1
1
VIDEEM2 / 22kHz
V
DD 5V
Ron of the transistor gate is ≈10kΩ.
GND 0V
Figure 6
6µ/2µ
10µ/2µ
S1 VID OUT, S2 VID OUT
Same as abovebut with no black level adjustment.
VIDEEM2/22kHz
1
Figure 3
125µA
60Ω
V
CC 12V
V
DD 5V
4
100µ/2µ
60µ/2µ
S1 VID OUT
S2 VID OUT
22kHz
2.3mA
VID MUX
10kΩ
20kΩ
GND 0V
V
REF 2.4V
VID IN
20kΩ
Figure 7
GND 0V
VREF 2.4V
UNCL DEEM
Same as above but with no black level adjustment
and slightly different gain.
10kΩ
VID IN
1
6.5kΩ
+
Figure 4
0.5pF
85µA
60
Ω
GND 0V
VCC 12V
PK OUT
Figure 8
4
UNCL DEEM
VREF 2.4V
2.3mA
IN
10kΩ
25kΩ
VDD 9V
Clamp
GND 0V
3.4V
Audio
1
16.7kΩ
1
5kΩ
Peak Detector
PK OUT
GND 0V
12/24
STV0042A
PIN INTERNAL CIRCUITRY (continued)
FC L, FC R
FM IN
The otherinputfor eachchannelis internallybiased
Ivar is controlled by the peak det audio level max.
±15µA (1VPP audio).
in the same way via 10kΩ to the 2.4V VREF
.
Figure 9
Figure 13
VDD 9V
10kΩ
10kΩ
Left Channel
2.4V
FC L
FC R
FM IN
1
1
1
50µA
1
Right Channel
Ivar
50µA
IREF
VOL OUT R, VOL OUT L
µ
±
The optimum value if IREF is 50 A 2% so an
external resistor of 47.5kΩ ±1% is required.
Audio output with volume and scart driver with
+12dB of gain for up to 2VRMS. The opamp has a
push-pulloutput stage.
Figure 14
Figure 10
2.4V
Audio
2.4V Bias
VOL OUT R
VOL OUT L
1
IREF
30kΩ
30kΩ
SCL
4.8V
Thisis theinput to a Schmittinput buffermade with
a CMOSamplifier.
15kΩ
Figure 15
GND 0V
205Ω
SCL
24µ/4µ
S2 OUT L, S2 OUT R
Same as above but with gain fixed at +6dB.
ESD
Figure 11
SDA
Audio
S2 OUT L
2.4V Bias
Input same as above.Output pull down only : relies
on external resistor for pull-up.
S2 OUT R
20kΩ
Figure 16
SDA
205Ω
24µ/4µ
20kΩ
ESD
600µ/2µ
GND 0V
GND 0V
S2 RTN L, S2 RTN R
4.8V bias voltage is the same as the bias level on
the audio outputs.
U75 L, U75 R
I1 - I2 = 2 x audio / 18kΩ. eg 1VPP audio : ±55µA.
The are internal switches to match the audio level
of the different standards.
Figure 12
25kΩ
Figure 17
4.8V
S2 RTN L
I1
S2 RTN R
1
U75 L
U75 R
50µA
I2
13/24
STV0042A
PIN INTERNAL CIRCUITRY (continued)
XTL
VREF
µ
The 400 A source is off during stand-by mode.
Figure 18
Figure 22
VREF (2.4V)
Vbg 1.2V
3
3
460Ω
460Ω
4
10kΩ
2
2
400µA
XTL
5pF
GND 0V
750µA
750µA
10kΩ
500µA
GND 0V
CPUMP L, CPUMP R
An offset on the PLL loop filter will cause an offset
in the two 1µA currents that will prevent the PLL
from drifting-off frequency.
SUMOUT
Figure 23
Figure 19
VREF 2.4V
1
100µA
Audio
SUMOUT
49kΩ
49kΩ
50kΩ
100µA
CPUMP L
CPUMP R
1µA
Dig Synth
Loop Filter Tracking
PK IN
1µA
Figure 24
VCO Input
100µA
VREF 2.4V
1
DET L, DET R
I2 - I1 = f (phase error).
To Peak Det
100µA
PK IN
67kΩ
Figure 20
I2
I1
V 12V
DET L
DET R
Doubled bonded (two bond wires and two pads for
one package pin) :
- One pad is connected to all of the 12V ESD and
video guard rings.
- The second pad is connected to power up the
video block.
AMPLK L, AMPLK R, AGC L, AGC R
I2 and I1 from the amplitude detectingmixer.
Figure 21
V GND
Doubled bonded :
To VCA
I2
I1
5µA
- Onepad is connectedto power-upall of thevideo
mux and I/O.
- The second pad is only as a low noise GND for
the video input.
AMPLK L
AMPLK R
AGC L
AGC R
2
10kΩ
VDD 5V, GND 5V
160µA
Connected to XTL oscillator and the bulk of the
CMOS logic and 5V ESD.
VREF 2.4V
14/24
STV0042A
PIN INTERNAL CIRCUITRY (continued)
A GND L
Doubled bonded :
A third bond wire on this pin is connected directly
to the die pad (substrate).
- One pad connected to the left VCO, dividers,
mixers and guard ring. the guard connection is
star connected directly to the pad.
- The second pad is connectedto both AGC amps
and the deemphasis amplifiers, frequency syn-
thesis and FM deviation selection circuit for both
channels.
Figure 25
V 12V
Video Pads
V GND
VDD 5V
A 12V
Doubled bonded :
- One pad connected to the ESD and guard ring.
- The second pad is connectedto the main power
for all of the audio parts.
Vpp
BIP 10vpl
Vmm
205Ω
Digital Pads
DZPN1
DZPN1
DZPN1
GND 5V
A GND R
Boubled bonded :
- One pad connected to the right VCO, dividers,
mixers and guard ring. The guard connection is
star connected directly to the pad.
- The second pad is connected to the bias block,
audio noise reduction, volume, mux and ESD.
A GND L
A 12V
+
BIP
12V
-
Audio Pads
Substrate
A GND R
15/24
STV0042A
I2C PROTOCOL
1) WRITING to the chip
S-Start Condition
P-Stop Condition
CHIP ADDR - 7 bits. 06H
W-Write/Read bit is the 8th bit of the chip address.
A-ACKNOWLEDGE after receiving 8 bits of data/adress.
REG ADDR
Address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are ’X’ or
don’t care ie only the first 3 bits are used.
DATA
8 bits of databeing written to the register. All 8 bitsmust be writtento atthe same
time.
REG ADDR/A/DATA/A can be repeated, the write process can continue untill terminated with a STOP
condition. If the REG ADDR is higher than 07 then IIC PROTOCOL will still be
met (ie an A generated).
Example :
S
06
W
A
00
A
55
A
01
A
8F
A
P
2) READING from the chip
When reading,thereis an auto-incrementfeature. Thismeans anyread command alwaysstarts by reading
Reg 8 and will continue to read the following registers in order after each acknowledge or until there is no
acknowledge or a stop. This function is cyclic that is it will read the same set of registers without
re-addressing the chip. There are two modes of operation as set by writing to bit 7 of register 0. Read 3
registers in a cyclic fashion or all 5 registers in a cyclic fashion. Note only the last 5 of the11 registers can
be read.
Reg0 bit 7 = L
Start / chip add / R / A / Reg 8 / A/ Reg9 / A / Reg 0A/ A/ Reg 8 / A / Reg 9 / A / Reg 0A
/... / P /
Reg0 bit 7 = H
Start / chip add / R / A / Reg 8 / A/ Reg 9 / A / Reg 0A / A / Reg 7 / A/ Reg 6 / A / Reg 8
/ A/ Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6 / ... / P /
CONTROL REGISTERS
Reg 0
write only
Bit (default 00HEX
)
0
1
2
3
4
5
6
7
L
L
L
L
L
L
L
L
Select 5 bits audio volume control 00H = MUTE
Select 5 bits audio volume control 01H = -26.75dB
Select 5 bits audio volume control : : : :
:
Select 5 bits audio volume control 1.25dB steps up to
Select 5 bits audio volume control 1FH = +12dB
Not to be used
Audio mux switch K3 - ANRSselect (L = no ANRS, H = ANRS)
L = read 3 registers, H = read 5 registers
Reg 1
write only
Bit (default 00HEX
)
0
1
2
3
4
5
6
7
L
L
L
L
L
L
L
L
Select video gain bits
Select video gain bits
Select video gain bits
Select video gain bits
Select video gain bits
Select video gain bits
00H = 0dB
01H = +0.202dB
02H = +0.404dB
n
= + 0.202 dB * n
3FH = + 12.73 dB
Selected video invert (H = inverted, L = non inverted)
Video deemphasis 1 / Video deemphasis2 (L : VID De-em 1)
16/24
STV0042A
CONTROL REGISTERS (continued)
Reg 2 write only
Bit (default F7HEX
)
0
1
2
3
4
5
6
7
H
H
H
L
H
H
H
H
Select video source for scart 1 O/P
Select video source for scart 1 O/P
Select video source for scart 1 O/P
Select 4.000MHz or 8.000MHzclock speed (L = 8MHz)
Select audio source for volume output (Switch K1)
Select audio source for volume output (Switch K1)
Select Left/Right/Stereofor volume output
Select Left/Right/Stereofor volume output
Reg 3
write only
Bit (default F7HEX
)
0
1
2
3
4
5
6
7
H
H
H
L
H
H
H
H
Select video source for scart 2 O/P
Select video source for scart 2 O/P
Select video source for scart 2 O/P
Video deemphais 2 / 22kHz (H : 22kHz)
Select audio source for Scart 2 output (Switch K5)
Select audio source for Scart 2 output (Switch K5)
Audio deemphasisselect (Switch K2)
Audio deemphasisselect (Switch K2)
Reg 4
write only
Bit (default BFHEX
)
0
1
2
3
4
5
6
7
H
H
H
H
H
H
L
Not to be used
Not to be used
Not to be used
Stand-by or low power mode (H = low power)
Not to be used
Not to be used
Not to be used
Not to be used
H
Reg 5
write only
Bit (default B5HEX
)
0
1
2
3
4
5
6
7
H
L
H
L
H
H
L
FM deviation selection -- default value for 50kHz modulation
FM deviation selection
FM deviation selection
FM deviation selection
FM deviation selection
FM deviation selection (L = double the FM deviation)
Not to be used
Not to be used
H
Reg 6
write/read
Bit (default 86HEX
)
0
1
2
3
4
5
6
7
L
Status of I/O
H
H
L
L
L
L
H
Select data direction of I/O 1 ( H = output)
Select frequency synthesizer 1 OFF/ON (L = OFF)
Select frequency synthesizer 2 OFF/ON (L = OFF)
Select RF source (L = OFF) to FM det 1
Select RF source (L = OFF) to FM det 2
Select frequency for PLL synthesizer- LSB (bit 0) of 10-bit value
Select frequency for PLL synthesizer- bit 1 of 10-bit value
17/24
STV0042A
CONTROL REGISTERS (continued)
Reg 7
write/read
Bit (default AFHEX
)
0
1
2
3
4
5
6
7
H
H
H
H
L
H
L
H
Select frequency for PLL synthesizer- bit 2 of 10-bit value
Select frequency for PLL synthesizer
Select frequency for PLL synthesizer
Select frequency for PLL synthesizer
Select frequency for PLL synthesizer
Select frequency for PLL synthesizer
Select frequency for PLL synthesizer
Select frequency for PLL synthesizer- bit 9, MSB (10th bit) of 10-bit value
Reg 8
read only
Bit
0
1
Subcarrier detection (DET 1) (L = No subcarrier)
Not used
2
3
4
5
Read frequencyof watchdog 1 - LSB (bit 0) of 10-bit value
Read frequencyof watchdog 1 - bit 1 of 10-bit value
Subcarrier detection (DET 2) (L = No subcarrier)
Not used
6
7
Read frequencyof watchdog 2 - bit 0 of 10-bit value
Read frequencyof watchdog 2 - bit 1 of 10-bit value
Reg 9
read only
Bit (default AFHEX
)
0
1
2
3
4
5
6
7
Read frequencyof watchdog 1 - bit 2 of 10-bit value
Read frequencyof watchdog 1
Read frequencyof watchdog 1
Read frequencyof watchdog 1
Read frequencyof watchdog 1
Read frequencyof watchdog 1
Read frequencyof watchdog 1
Read frequencyof watchdog 1 - bit 9, MSB (10th bit) of 10-bit
Reg 0A read only
Bit
0
1
2
3
4
5
6
7
Read frequencyof watchdog 2 - bit 2 of 10-bit value
Read frequencyof watchdog 2
Read frequencyof watchdog 2
Read frequencyof watchdog 2
Read frequencyof watchdog 2
Read frequencyof watchdog 2
Read frequencyof watchdog 2
Read frequencyof watchdog 2 - bit 9, MSB (10th bit) of 10-bit
18/24
STV0042A
CONTROL REGISTERS (continued)
Video Mux Truth Tables
Register 2 <0:2>
Register 3 <0:2>
Scart 1 video output control
Scart 2 video output control
The truth table for the three scart outputs are the same.
Register 2/3
Video Output
Bit<2>
Bit<1>
Bit<0>
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Baseband video
De-emphasized video
Normal video
Not to be used
Scart 2 return
Not to be used
Nothing selected
High Z or low power (default)
Audio Mux Truth Tables
Register 2
Switch K1/Audio Source Selection for Volume Output
Bit <5>
Bit <4>
Volume Output
0
1
0
1
0
0
1
1
A
C
B
-
Audio deemphasis (K2 switch O/P)
Scart 2 return
Not to be used
High Z or low power (default)
Register 3
Switch K2/Audio Deemphasis
Bit <7>
Bit <6>
Audio Deemphasis
No deemphasis
Not to be used
50µs
0
1
0
1
0
0
1
1
A
C
B
B
75µs (default)
Register 0
Switch K3 & K4
Bit <6>
Bit <5>
ANRS I/O Select
0
1
X
X
0
1
A
B
A
B
Noise reduction OFF
Noise reduction ON (default)
Not to be used
X
X
Not to be used
Register 3
Switch K5/Audio Source Selection for Scart 2
Bit <5>
Bit <4>
Aux Audio Output
0
1
0
1
0
0
1
1
C
A
B
-
PLL output
Not to be used
Audio deemphasis (K2 switch O/P)
High Z or low power state (default)
Register 2
Left / Right / Stereo on Volume Output
Bit <7>
Bit <6>
0
1
1
0
0
1
Mono left / channel 1
Mono right / channel 2
Stereo left & right (default)
19/24
STV0042A
CONTROL REGISTERS (continued)
Register 5 : FM Deviation Selection
Selected Nominal Carrier Modulation
Bit 5 = 1
4
3
2
1
0
Bit 5 = 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Do not use
Do not use
Do not use
Cal. set. (2V)
592kHz
534kHz
484kHz
436kHz
396kHz
358kHz
322kHz
292kHz
266kHz
240kHz
218kHz
196kHz
179kHz
161kHz
146kHz
122kHz
120kHz
109kHz
98kHz
cal : do not use = 0.3373V offset on VCO
cal : do not use = 0.3053V offset on VCO
cal : do not use = 0.2763V offset on VCO
calibration setting (1V offset on VCO)
296kHz modulation
267kHz modulation
242kHz
218kHz
198kHz
179kHz
161kHz
146kHz
133kHz
120kHz
109kHz
98.3kHz
89.7kHz
80.9kHz
73.1kHz
66.0kHz
60.0kHz
54.4kHz = default power up state
49.1kHz
89kHz
44.3kHz
78kHz
39.8kHz
71kHz
35.9kHz
65kHz
32.4kHz
58kHz
29.1kHz
53kHz
26.7kHz
48.6kHz
43.8kHz
39.6kHz
24.3kHz
21.9kHz
19.7kHz
Example : Default power up state 54.4kHz
±54.4kHz.
Register 1
Bit <7>
Register 3
Bit <3>
Video Deemphasis/22kHz
0
0
1
1
0
1
0
1
Deemphasis 1 (default)
Deemphasis 1 + 22kHz (Pin 13)
Deemphasis 2
Deemphasis 2
FM DEMODULATION SOFTWARE ROUTINE
Withthe STV0042Acircuit, for eachchannel, three
steps are required to acheive a FM demodulation:
- 1st step :To set the demodulationparameters :
• FM deviation selection,
two completesequenceshaveto bedoneone after
the other when demodulatingstereo pairs.
Detailed Description
• Subcarrier frequency selection.
Conventions:
- R = Stands for Register
- B = Stands for Bit
- 2nd step : To implement a waiting loop to check
the actual VCO frequency.
- 3rd step:To close the demodulationphaselocked
loop (PLL).
Example :
R05 B2 = Register 05, Bit 2
For clarity, the explanations are based on the fol-
lowing example : stereo pair 7.02MHz/L
7.20MHz/R, deviation 50kHz max.
Refering to the FM demodulation block diagram
(page 12), the frequency synthesis block is com-
monto bothchannels(leftand right); consequently
±
20/24
STV0042A
FM DEMODULATION SOFTWARE ROUTINE (continued)
1st Step(Left): SettingtheDemodulationParameters
the watchdog.
A. The FM deviation is selected by loadingR5 with
the appropriate value. (see R5 truth table).
NB : Very wide deviations (up to ±592kHz) can be
accomodatedwhen R5 B5 is low.
3rd Step (Left)
The FMdemodulationcanbe startedbyconnecting
the VCO to the phase locked loop (PLL).
In practice :
- SW3 closed R6 B4 = H
- SW4 opened R6 B2 = L
Corresponding bandwidth can be calculated as
follows :
Bw ≈ 2 (FM deviation + audio bandwidth)
≈
Bw 2 (value given in table + audio bandwidth)
After this sequence of 3 steps for left channel,
a similarsequenceis needed for the right channel.
In the example :
R5Bits 7
6
5
1
4
1
3
0
2
1
1
1
0
0
Note :
X
X
Inthesequencefortheright,thereisnoneedtoagain
selecttheFM deviation(once isenoughfor thepair).
General Remark
Before to enable the demodulated signal to the
audiooutput, it is recommandedto keepthemuting
and to checkwhether a subcarrier is present at the
wanted frequency.Suchan informationis available
in R8 B0 and R8 B4 which can be read.
Two differentstrategiescan be adoptedwhen ena-
bling the output :
B. The subcarrier frequencyis selectedby launching
afrequencysynthesis(theVCOisdriventothewanted
frequency).This operationrequirestwo actions:
- To connect the VCO to the frequency synthesis
loop. Referingto the FM blockdiagram(page 12):
•
SW4 closed
R6 B2 = H
R6 B4 = L
R6 B3 = L
R6 B5 = L
• SW3 to bias
• SW2 to bias
• SW1 opened
- Eitherbothleftandrightdemodulatedsignalsare simul-
taneouslyauthorizedwhenbothchannelare ready.
- Or while the right channel sequenceis running,the
already ready left signal is sent to the left and right
outputsandtherealstereosoundL/Risoutputwhen
both channels are ready. This second option gives
sounda few hundredsof msbefore thefirst one.
- To load R7 and R6 B6 B7 with the value corre-
sponding to the left channel frequency. This 10
bits value is calculated as follows :
Subcarrier frequency = coded value x 10kHz
(10kHz is the minimum step of the frequency
synthesis function). Considering that the tunning
range is comprised between 5 to 10MHz, the
coded value is a number between 500 and 1000
(210 = 1024) then 10 bits are required.
Example :
Table 1 : FrequencySynthesisRegisterSetting for
the Most Common Subcarrier Frequencies
Register 6
Bit 7 Bit 6
Register 7
(Hex)
Subcarrier Freq. (MHz)
7.02MHz = 702 x 10kHz
702
1010 1111 10
AF + 10
5.58
5.76
5.8
5.94
6.2
6.3
6.4
6.48
6.5
6.6
8B
90
91
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
0
1
R7 is loaded with AF and R6 B6 : L, R6 B7 : H.
The Table 1 givesthe settingfor the most common
subcarrier frequencies.
94
9B
9D
A0
A2
A2
A5
A6
AA
AB
AF
B4
B5
B8
BD
C1
C4
C6
CD
D8
2nd Step (Left) : VCO FrequencyChecking (VCO)
Thissecondstepisactuallyawaitingloopinwhichthe
actualrunning frequencyofthe VCOis measured.
To exit of this loop is allowed when : Subcarrier
≤
≤
Frequency - 10kHz Measured Frequency Sub-
carrierFrequency+10kHz(± 10kHzis themaximum
dispersionof the frequencysynthesisfunction).
Inpractice,R8B2B3andR9arereadandcompared
to thevalue loaded in R6 B6 B7 and R7 ±1 bit.
6.65
6.8
6.85
7.02
7.20
7.25
7.38
7.56
7.74
7.85
7.92
8.2
Note :
The duration of this step depends on how large is
frequency difference between the start frequency
and the targeted frequency. Typically :
- the rate of change of the VCO frequencyis about
µ
3.75MHz/s (Cpump = 10 F)
- In addition to this settling time, 100ms must be
added to takeinto accountthe samplingperiod of
8.65
21/24
STV0042A
TYPICAL APPLICATION (with 2 video deemphasis network)
22/24
STV0042A
TYPICAL APPLICATION (with 22kHz tone and three audio de-emphasis 50µs, 75µs, J17)
% - 1 Ω
R 5 0
4 7 . 5 k
Ω
Ω
4 . 7 k
3 6 k
Ω
4 . 7 k
Ω
5 6 0 7 k R 3
2 . 7 n F
Ω
2 7 k
Ω
Ω
4 . 7 k
Ω
Ω
4 . 7 k
4 . 7 k
3 6 k
2 . 7 n F
Ω
6 5 0 k R 3 6
Ω
2 7 k
23/24
STV0042A
PACKAGE MECHANICAL DATA
42 PINS - PLASTICSHRINK DIP
E
E1
B
B1
e
e1
e2
D
c
E
42
22
21
.015
0,38
Gage Plane
e3
e2
1
SDIP42
Millimeters
Typ.
Inches
Typ.
Dimensions
Min.
Max.
Min.
Max.
A
A1
A2
B
5.08
0.200
0.51
3.05
0.020
0.120
0.0149
0.035
0.0090
1.440
0.60
3.81
0.46
1.02
0.25
36.83
4.57
0.56
0.150
0.0181
0.040
0.180
0.0220
0.045
0.0150
1.460
0.629
0.570
0.38
B1
c
0.89
1.14
0.23
0.38
0.0098
1.450
D
36.58
15.24
12.70
37.08
16.00
14.48
E
E1
e
13.72
1.778
15.24
0.50
0.540
0.070
0.60
e1
e2
e3
L
18.54
1.52
3.56
0.730
0.060
0.140
2.54
3.30
0.10
0.130
Information furnishedis believed to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patentsor other rights of third parties which may result
from itsuse. No licence is grantedby implication orotherwise underany patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previouslysupplied. SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
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