首页 |元器件品牌

STV7612/WAF [STMICROELECTRONICS]

PLASMA DISPLAY PANEL DATA DRIVER; 等离子显示面板的数据驱动器
STV7612/WAF
型号： STV7612/WAF
厂家： ST    ST
描述：

PLASMA DISPLAY PANEL DATA DRIVER
等离子显示面板的数据驱动器

驱动器 接口集成电路 CD
文件： 总18页 (文件大小：448K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
STV7612  
PLASMA DISPLAY PANEL DATA DRIVER  
FEATURES  
■ 96 OUTPUTS PLASMA DISPLAY DRIVER  
■ 100 V ABSOLUTE MAXIMUM RATING  
■ 5 V SUPPLY FOR LOGIC  
■ -70/90 mA SOURCE/SINK OUTPUT MOS  
■ 6 bit CASCADABLE DATA BUS (20 MHz)  
■ BLANK, POLARITY CONTROL  
■ BCD TECHNOLOGY  
■ PACKAGING TQFP144 OR DICE  
DIE  
ORDER CODE: STV7612/WAF(1)  
(1): Unsawn tested wafer  
DESCRIPTION  
The STV7612 is a BCD data driver for Plasma  
Display Panel (PDP). Using a 6-bit wide cascada-  
ble data bus, it addresses 96 high current & high  
voltage outputs. By serially connecting several  
STV7612, any horizontal pixel definition can be  
performed. The 20 MHz shift clock gives an equiv-  
alent 120 MHz shift register. The STV7612 is sup-  
plied with a separated 90 V power output supply  
and a 5 V logic supply. All command inputs are  
CMOS compatible.  
TQFP144 (20 x 20 x 1.4 mm)  
(Thin Plastic Quad Flat Pack)  
ORDER CODE: STV7612  
Version 4.1  
August 2003  
ADCS 7399251  
1/18  
1
Table of Contents  
PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
PIN LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
PAD COORDINATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
AC TIMINGS REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
AC TIMINGS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
INPUT/OUTPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
TESTED WAFER DISCLAIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
2/18  
ADCS 7399251A  
2
STV7612  
PIN CONNECTIONS  
(DIE Pinout)  
VSSP  
VPP  
VSSP  
VPP  
VP  
VPP  
P
OUT64  
OUT65  
OUT66  
OUT67  
OUT68  
OUT69  
OUT70  
OUT71  
OUT72  
OUT73  
OUT74  
OUT75  
OUT33  
OUT32  
OUT31  
OUT30  
OUT29  
OUT28  
OUT27  
OUT26  
OUT25  
OUT24  
OUT23  
OUT22  
OUT21  
OUT20  
OUT19  
OUT18  
OUT17  
OUT16  
OUT15  
OUT14  
OUT13  
OUT12  
OUT11  
OUT10  
OUT9  
STV7612  
Bare Die  
Y
OUT7  
6
OUT77  
OUT78  
OUT7  
OUT80  
OUT8  
9
(0,0)  
1
X
OUT82  
OUT83  
OUT84  
OUT85  
OUT86  
OUT87  
OUT88  
OUT89  
OUT90  
OUT8  
OUT7  
OUT9  
1
OUT6  
OUT92  
OUT93  
OUT5  
OUT4  
OUT9  
4
OUT3  
OUT95  
OUT96  
OUT2  
OUT1  
ADCS 7399251  
3/18  
3
STV7612  
PIN CONNECTIONS  
(TQFP Pinout)  
VPP  
VPP  
1
108  
107  
106  
105  
104  
103  
102  
101  
100  
99  
VPP  
2
VPP  
NC  
3
NC  
OUT64  
OUT65  
OUT66  
OUT67  
OUT68  
OUT69  
OUT70  
OUT71  
OUT72  
OUT73  
OUT74  
OUT75  
OUT76  
OUT77  
OUT78  
OUT79  
OUT80  
OUT81  
OUT82  
OUT83  
OUT84  
OUT85  
OUT86  
OUT87  
OUT88  
OUT89  
OUT90  
OUT91  
OUT92  
OUT93  
OUT94  
OUT95  
OUT96  
4
OUT33  
OUT32  
OUT31  
OUT30  
OUT29  
OUT28  
OUT27  
OUT26  
OUT25  
OUT24  
OUT23  
OUT22  
OUT21  
OUT20  
OUT19  
OUT18  
OUT17  
OUT16  
OUT15  
OUT14  
OUT13  
OUT12  
OUT11  
OUT10  
OUT9  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
98  
97  
96  
95  
94  
93  
92  
STV7612  
TQFP144  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
OUT8  
79  
OUT7  
OUT6  
78  
77  
OUT5  
76  
OUT4  
75  
OUT3  
74  
OUT2  
73  
OUT1  
4/18  
ADCS 7399251  
3
STV7612  
PIN LIST  
(TQFP144)  
Pin N°  
Symbol  
Type  
Description  
3-37-38-39-41-43-48-65-67-69-  
70-71-72-106-110-111-142-143  
NC  
-
1-2-42-66-107-108  
V
V
Supply  
Ground  
Ground  
Ground  
Output  
Output  
Input  
High Voltage Supply of Power Outputs  
5V Logic Supply  
PP  
53  
CC  
40-68-109-144  
V
Ground of Power Outputs  
Logic Ground  
SSP  
54  
55  
V
SSLOG  
SSSUB  
V
Substrate Ground  
73 to 105  
112 to 141  
4 to 36  
50  
OUT 1 to OUT 33  
Power Output  
OUT 34 to OUT 63  
Power Output  
OUT 64 to OUT 96  
Input  
Power Output  
BLK  
POL  
Input  
Blanking Input  
51  
Input  
Polarity Input  
52  
F/R  
Input  
Selection of Shift Direction  
Clock of data Shift Register  
Latch of data to Outputs  
56  
CLK  
Input  
57  
STB  
Input  
59 to 64  
44 to 49  
A1 to A6  
B6 to B1  
Input/Output Forward Shift Register Input  
Input/Output Forward Shift Register Output  
PIN LIST  
(Power outputs)  
Output N°  
Pin N°  
Output N°  
Pin N°  
Output N°  
Pin N°  
Output N°  
Pin N°  
1
2
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
97  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
98  
3
99  
4
100  
101  
102  
103  
104  
105  
112  
113  
114  
115  
116  
117  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
ADCS 7399251  
5/18  
3
STV7612  
Output N°  
Pin N°  
Output N°  
Pin N°  
Output N°  
Pin N°  
Output N°  
Pin N°  
16  
17  
18  
19  
20  
21  
22  
23  
24  
88  
89  
90  
91  
92  
93  
94  
95  
96  
40  
41  
42  
43  
44  
45  
46  
47  
48  
118  
119  
120  
121  
122  
123  
124  
125  
126  
64  
65  
66  
67  
68  
69  
70  
71  
72  
4
5
88  
89  
90  
91  
92  
93  
94  
95  
96  
28  
29  
30  
31  
32  
33  
34  
35  
36  
6
7
8
9
10  
11  
12  
PAD COORDINATES  
(in µm)  
Centre  
Size  
Name  
Pad positions from the middle of the top side  
X
Y
X
Y
Centre  
Size  
Name  
OUT 33 2117.0  
OUT 32 2117.0  
OUT 31 2117.0  
OUT 30 2117.0  
OUT 29 2117.0  
OUT 28 2117.0  
OUT 27 2117.0  
OUT 26 2117.0  
OUT 25 2117.0  
OUT 24 2117.0  
OUT 23 2117.0  
OUT 22 2117.0  
OUT 21 2117.0  
OUT 20 2117.0  
OUT 19 2117.0  
OUT 18 2117.0  
OUT 17 2117.0  
OUT 16 2117.0  
OUT 15 2117.0  
OUT 14 2117.0  
OUT 13 2117.0  
OUT 12 2117.0  
OUT 11 2117.0  
1580.0  
1444.0  
1308.0  
1172.0  
1036.0  
900.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
X
Y
X
Y
OUT 48  
OUT 47  
OUT 46  
OUT 45  
OUT 44  
OUT 43  
OUT 42  
OUT 41  
OUT 40  
OUT 39  
OUT 38  
OUT 37  
OUT 36  
OUT 35  
OUT 34  
74.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
210.0  
346.0  
482.0  
618.0  
764.0  
754.0  
628.0  
890.0  
492.0  
1026.0  
1162.0  
1298.0  
1434.0  
1570.0  
1706.0  
1842.0  
1993.0  
356.0  
220.0  
84.0  
-52.0  
-188.0  
-324.0  
-460.0  
-596.0  
-732.0  
-868.0  
-1004.0  
-1140.0  
-1276.0  
-1412.0  
Pad positions along the right side  
Centre  
Name  
Size  
X
Y
X
Y
V
2116.0  
2029.8  
2041.5  
2795.0  
2496.5  
1843.0  
90.0  
90.0  
90.0  
80.0  
90.0  
80.0  
SSP  
V
PP  
PP  
V
6/18  
ADCS 7399251  
3
STV7612  
Centre  
Size  
Centre  
Size  
Name  
Name  
X
Y
X
Y
X
Y
X
Y
OUT 10  
OUT 9  
OUT 8  
OUT 7  
OUT 6  
OUT 5  
OUT 4  
OUT 3  
OUT 2  
OUT 1  
2117.0  
2117.0  
2117.0  
2117.0  
2117.0  
2117.0  
2117.0  
2117.0  
2117.0  
2117.0  
-1548.0  
-1684.0  
-1820.0  
-1956.0  
-2092.0  
-2228.0  
-2364.0  
-2500.0  
-2636.0  
-2832.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
A3  
A2  
1049.0  
899.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
A1  
749.0  
STB  
449.0  
CLK  
299.0  
GNDsub  
GND  
156.5  
3.0  
V
-158.0  
-299.0  
-449.0  
-599.0  
-749.0  
-899.0  
-1049.0  
-1199.0  
-1349.0  
-1499.0  
-1698.0  
-1904.0  
CC  
F/R  
POL  
BLK  
B1  
Pad positions along the bottom side  
Centre  
Name  
Size  
B2  
X
Y
X
Y
B3  
V
1904.0  
1698.0  
1499.0  
1349.0  
1199.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
-3034.0  
80.0  
80.0  
80.0  
80.0  
80.0  
90.0  
90.0  
90.0  
90.0  
90.0  
SSP  
B4  
V
PP  
B5  
A6  
A5  
A4  
B6  
V
PP  
V
SSP  
ADCS 7399251  
7/18  
3
STV7612  
Pad Positions along the left side  
Centre  
Size  
Name  
Centre  
Name  
Size  
X
Y
X
Y
X
Y
X
Y
OUT 69 -2117.0  
OUT 68 -2117.0  
OUT 67 -2117.0  
OUT 66 -2117.0  
OUT 65 -2117.0  
OUT 64 -2117.0  
900.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
OUT 96 -2117.0  
OUT 95 -2117.0  
OUT 94 -2117.0  
OUT 93 -2117.0  
OUT 92 -2117.0  
OUT 91 -2117.0  
OUT 90 -2117.0  
OUT 89 -2117.0  
OUT 88 -2117.0  
OUT 87 -2117.0  
OUT 86 -2117.0  
OUT 85 -2117.0  
OUT 84 -2117.0  
OUT 83 -2117.0  
OUT 82 -2117.0  
OUT 81 -2117.0  
OUT 80 -2117.0  
OUT 79 -2117.0  
OUT 78 -2117.0  
OUT 77 -2117.0  
OUT 76 -2117.0  
OUT 75 -2117.0  
OUT 74 -2117.0  
OUT 73 -2117.0  
OUT 72 -2117.0  
OUT 71 -2117.0  
OUT 70 -2117.0  
-2832.0  
-2636.0  
-2500.0  
-2364.0  
-2228.0  
-2092.0  
-1956.0  
-1820.0  
-1684.0  
-1548.0  
-1412.0  
-1276.0  
-1140.0  
-1004.0  
-868.0  
-732.0  
-596.0  
-460.0  
-324.0  
-188.0  
-52.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
1036.0  
1172.0  
1308.0  
1444.0  
1580.0  
1843.0  
2496.5  
2795.0  
V
V
-2041.5  
-2029.8  
-2116.0  
PP  
PP  
V
SSP  
Pad Positions along the top side  
Centre  
Name  
Size  
X
Y
X
Y
OUT 63 -1980.0  
OUT 62 -1830.0  
OUT 61 -1694.0  
OUT 60 -1558.0  
OUT 59 -1422.0  
OUT 58 -1286.0  
OUT 57 -1150.0  
OUT 56 -1014.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
3034.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
80.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
90.0  
OUT 55  
OUT 54  
OUT 53  
OUT 52  
OUT 51  
OUT 50  
OUT 49  
-878.0  
-742.0  
-606.0  
-470.0  
-334.0  
-198.0  
-62.0  
84.0  
220.0  
356.0  
492.0  
628.0  
764.0  
8/18  
ADCS 7399251  
3
STV7612  
BLOCK DIAGRAM  
CLK  
56  
F/  
R
52  
VCC  
16-BIT SHIFT REGISTER  
P1  
P91  
59  
60  
61  
62  
49  
A1  
A2  
A3  
A4  
B1  
B2  
B3  
B4  
16-BIT SHIFT REGISTER  
P2  
P92  
48  
47  
46  
16-BIT SHIFT REGISTER  
P3  
P93  
16-BIT SHIFT REGISTER  
P4  
P94  
16-BIT SHIFT REGISTER  
P5  
P95  
63  
64  
45  
44  
A5  
A6  
B5  
B6  
16-BIT SHIFT REGISTER  
P6  
P96  
54  
55  
P1  
P6  
P95P96  
Q95Q96  
VSSLOG  
VSSSUB  
57  
50  
51  
LATCH  
STB  
POL  
BLK  
Q1Q2  
VCC  
VCC  
53  
VCC  
VSSP  
LOGIC  
Pins40-68-109-144  
VPP  
Pins  
1-2-42-66-107-108  
STV7612  
73  
36  
OUT1  
OUT96  
ADCS 7399251  
9/18  
3
STV7612  
CIRCUIT DESCRIPTION  
The STV7612 contains all the logic and the power  
circuits necessary to drive the columns of a Plas-  
ma Display Panel (P. D. P.). The binary value of  
each pixel of the displayed line is loaded into the  
shift register. Data are input in a 6-bit wide data  
bus to A1 - A6 input (case of forward shift mode).  
Data are shifted at each low to high transition of  
the CLK shift clock. After 16 shifts the first data are  
available on B1 - B6 outputs. These B1 - B6 out-  
puts can be used to cascade several drivers to  
perform any horizontal resolution. The forward/re-  
verse (F/R) input is used to select the direction of  
the shift register, A1 - A6 and B1 - B6 data bus in-  
put/output status is set according to the selected  
direction. F/R= H, A is an input and B is an output.  
V
and V  
must be connected as close  
SSLOG  
SSSUB  
as possible to the logical reference ground of the  
application.  
Shift Register Truth Table  
Shift Register  
Input  
Input/Output  
Function  
F/R  
CLK  
Rise  
A
B
Output Q  
H
H
L
IN  
IN  
OUT Forward shift  
OUT Steady  
H or L  
Rise OUT  
H or L OUT  
IN  
IN  
Reverse shift  
Steady  
L
Serial inputs, CLK, STB inputs are Smith trigger in-  
puts. If not used in the application, Blanking (BLK),  
Polarity (POL are internally pulled to level “H”. The  
maximum frequency of the shift clock is 20 MHz.  
This leads to an equivalent 120 MHz serial shift  
register.  
Power Output Truth Table  
Driver  
Output  
Qn  
STB BLK POL  
Comments  
X
X
X
L
X
X
H
L
L
X
L
L
H
Output low  
On low level of STB, data is transferred from shift  
register to the latch stage. Data will not be re-  
freshed as long as STB is kept high.  
H
H
H
H
Output high  
Data latched  
Data copied  
Data copied  
H
H
H
Qn  
L
Blanking input (BLK) forces the power outputs to  
low level when pulled low. All the power outputs  
are set at high level when the Polarity command  
(POL) is pulled low and the Blanking (BLK) input is  
at high level.  
H
L
H
Note 1 Qn+1 = A1, Qn + 2 = A2, Qn + 3 = A3, Qn + 4 =  
A4, Qn + 5 = A5, Qn + 6 = A6, n = [0,6,12,18,...,90]  
10/18  
ADCS 7399251  
3
STV7612  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
V
Logic Supply Range (Pin 53)  
-0.3, +7  
V
V
CC  
OUTi  
VIN  
Output Pins (4 to 36, 73 to 105, 112 to 141)  
Logic Input Voltage (Pins 50, 51, 52, 56, 57, 59 to 64)  
Logic Output Voltage (Pin 44 to 49)  
Driver Output Current ( Note 2) ( Note 4) ( Note 5)  
Diode Output Current ( Note 3) ( Note 4) ( Note 5)  
Junction Temperature  
-0.3, +100  
-0.3, +V +0.3  
V
CC  
-0.3, +V + 0.3  
VOUT  
V
CC  
I
-150 / +150  
-200 / +300  
+150  
mA  
mA  
°C  
°C  
°C  
POUT  
I
DOUT  
Tj  
Toper  
Tstg  
Operating Temperature  
-20, +85  
-50, +150  
Storage Temperature  
Note 2 Through one power output (all power outputs).  
Note 3 Through one power output for all power outputs (see Test Diagram) with Junction temperature lower or equal than  
Tjmax.  
Note 4 These parameters are measured during ST’s internal qualification which includes temperature characterisation  
on standard batches and on corners batches of the process. These parameters are not tested on the parts.  
Note 5 Transient current. Spike current duration inferior to 300ns.  
THERMAL DATA  
Symbol  
Parameter  
Value  
Unit  
Rth(j-a)  
Junction-ambient Thermal Resistance  
Typ.  
41  
°C/W  
ADCS 7399251  
11/18  
3
STV7612  
ELECTRICAL CHARACTERISTICS  
(V  
= 5 V, V = 90 V, V  
= 0 V, V  
= 0 V, V  
= 0 V, T  
= 25°C, f  
= 20 MHz, unless  
CLK  
CC  
PP  
SSP  
SSLOG  
SSSUB  
amb  
otherwise specified)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
SUPPLY  
V
Logic Supply Voltage  
4.5  
5
-
5.5  
100  
-
V
µA  
mA  
V
CC  
I
Logic Supply Current (all inputs high)  
Logic Dynamic Supply Current  
Power Output Supply Voltage  
-
-
CCH  
I
f
= 20 MHz  
26  
-
CCL  
CLK  
V
15  
-
90  
PP  
Power Output Supply Current  
(steady outputs)  
-
100  
µA  
I
PPH  
OUTPUT (V = 15 V to 90 V)  
PP  
OUT 1- OUT 96  
Power Output Voltage Drop  
(High Level) (versus V  
I
I
= - 30 mA  
= - 45mA  
-
-
4.0  
4.5  
6.0  
6.5  
V
V
POUTH  
POUTH  
V
POUTH  
)
PP  
Power Output Voltage Drop  
(Low Level)  
V
V
I
= + 30 mA  
-
1.6  
4
V
POUTL  
POUTL  
Output Diode Voltage (High Level)  
Output Diode Low Level  
I
I
= +45 mA ( Note 6)  
= - 30mA ( Note 6)  
-
-
1.05  
4
V
V
DOUTH  
DOUTH  
V
-0.95  
-4  
DOUTL  
DOUTL  
A1-A6, B1-B6  
V
Logic Output (High Level)  
Logic Output (Low Level)  
I
I
= -1 mA  
4
-
4.2  
-
V
V
OH  
OH  
V
= +1 mA  
0.12  
0.4  
OL  
OL  
INPUT  
CLK, F/R, STB, POL, BLK, A1-A6, B1-B6  
V
0.8 V  
Input Voltage (High Level)  
Input Voltage (Low Level)  
High Level Input Current  
-
-
-
-
V
V
IH  
CC  
V
I
0.2V  
-
-
IL  
CC  
V
V
= V  
10  
µA  
IH  
IH  
IL  
CC  
I
Low Level Input Current  
CLK, A1-A6, B1-B6, STB,  
F/R, BLK, POL  
= 0 V  
IL  
-
-
-
-
-10  
-40  
µA  
µA  
Note 6 See test diagram page 14.  
12/18  
ADCS 7399251  
3
STV7612  
AC TIMINGS REQUIREMENTS  
(V = 4.5 V to 5.5 V, T  
= -20 to +85°C, input signals max leading edge & trailing edge (t , t ) = 10 ns)  
R F  
CC  
amb  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
t
Duration of clock (CLK) pulse at high level  
15  
15  
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WHCLK  
t
Duration of clock (CLK) pulse at low level  
WLCLK  
t
Set-up Time of data input before clock (low to high) transition  
Hold Time of data input after clock (low to high) transition  
F/R (FOR/REV) Set-up Time before clock (low to high) transition  
Minimum Delay to latch STB after clock (low to high) transition  
Minimum Delay to latch STB before clock (low to high) transition  
Latch STB Low Level Pulse Duration  
10  
SDAT  
t
10  
HDAT  
t
100  
10  
SFR  
t
-
-
-
-
-
-
-
-
-
-
DSTB  
t
10  
SSTB  
t
20  
STB  
t
Blanking BLK Pulse Duration  
500  
500  
BLK  
t
Polarity POL Pulse Duration  
POL  
AC TIMINGS CHARACTERISTICS  
(V = 5 V, V = 90 V V  
= 0 V, V  
= 0 V, V  
= 0 V, T  
= 25°C)  
CC  
PP  
,
SPP  
SSLOG  
SSSUB  
amb  
(V  
= 0.2 Vcc, V  
= 0.8 V , V = 4.0V, V = 0.4 V, unless otherwise specified)  
IL(Max.)  
IH(Min.) CC OH OL  
Symbol  
Parameter  
Min. Typ. Max. Unit  
t
Data clock Period  
50  
-
-
-
ns  
ns  
ns  
CLK  
t
Logical Data Output Rise Time (CL=10pF)  
Logical Data Output Fall Time (CL=10pF)  
12  
11  
20  
20  
RDAT  
t
-
FDAT  
t
t
Delay of logic data output (high to low transition) after clock (CLK) transition Note 7 15  
Delay of logic data output (low to high transition) after clock (CLK) transition Note 7 15  
35  
35  
50  
50  
ns  
ns  
PHL1  
PLH1  
t
t
Delay of power output change (high to low transition) after clock (CLK) transition  
Delay of power output change (low to high transition) after clock (CLK) transition  
-
-
135 180 ns  
80 180 ns  
PHL2  
PLH2  
t
t
Delay of power output change (high to low transition) after Latch (STB) transition  
Delay of power output change (low to high transition) after Latch (STB) transition  
-
-
115 165 ns  
70 165 ns  
PHL3  
PLH3  
t
PHL4  
PLH4  
Delay of power output change (high to low transition) to Blank or Polarity (BLK, POL)  
transition  
Delay of power output change (low to high transition) to Blank or Polarity (BLK, POL)  
transition  
-
-
100 160 ns  
55 160 ns  
t
t
Power Output Rise Time ( Note 8)  
Power Output Fall Time ( Note 8)  
-
-
50 150 ns  
80 200 ns  
ROUT  
t
FOUT  
Note 7 For IC in cascading configuration and in case a time delay is inserted on the clock signal of the cascaded IC, the  
maximum value of this time delay must be set at the minimum value of t (Figure 7).  
t
PHL1, PLH1  
Note 8 One output among 96, loading capacitor C = 50pF, other outputs at low level.  
L
ADCS 7399251  
13/18  
3
STV7612  
Figure 1: AC Characteristics Waveform  
t
CLK  
t
t
WHCLK  
WLCLK  
“1”  
“0”  
“1”  
50%  
CLK  
50%  
50%  
t
HDAT  
t
SDAT  
50%  
50%  
A INPUT  
“0”  
“1”  
t
t
FDAT  
PHL1  
90%  
90%  
10%  
B OUTPUT  
10%  
“0”  
t
RDAT  
t
PLH1  
t
t
STB  
DSTB  
“1”  
“0”  
STB  
50%  
50%  
t
SSTB  
t
SFR  
“1”  
“0”  
“1”  
F/R  
t
t
PHL3  
PHL2  
90%  
90%  
10%  
OUTn  
10%  
“0”  
“1”  
t
t
PLH2  
PLH3  
t
BLK  
(POL=#0#)  
50%  
50%  
BLK  
“0”  
“1”  
t
t
PHL4  
PLH4  
OUTn  
90%  
90%  
10%  
10%  
“0”  
t
t
F OUT  
R OUT  
14/18  
ADCS 7399251  
3
STV7612  
Figure 2: Test Configuration  
VPP  
V
VPP VSSP  
=
=
SSP  
VDOUTH  
IDOUTH  
VDOUTL  
IDOUTL  
VSSP  
VSSP  
Output sinking current as positive value, sourcing current as negative value  
INPUT/OUTPUT SCHEMATICS  
Figure 3: POL , BLK , F/R Input  
Figure 5: A1 to A6, B1 to B6  
VCC  
VCC  
VCC  
A1 to A6,  
B1 to B6  
VCC  
Pins 59 to 64,  
VCC  
49 to 44  
POL, BLK, F/R  
Pins 51, 50, 52  
GNDLOG  
GNDLOG  
GNDSUB  
GNDSUB  
Figure 4: CLK, STB Input  
Figure 6: Power Output  
VCC  
VPP  
VCC  
CLK, STB  
Pins 56, 57  
OUT1 to OUT 96  
Pins 73 to 105,  
112 to 141, 4 to 36  
GNDLOG  
VSSP  
GNDSUB  
ADCS 7399251  
15/18  
3
STV7612  
Figure 7: IC cascading mode suggestion  
Vcc  
time delay  
clock  
STV7612  
STV7612  
data in  
data in  
data out  
TESTED WAFER DISCLAIMER  
All wafers are tested and guaranteed to comply with all datasheet limits up to the point of wafer sawing for  
a period of ninety (90) days from the delivery date.  
We remind you that it is the customer’s responsibility to test and qualify their application in which the die  
is used. ST Microelectronics is ready to support the customer when qualifying the product.  
16/18  
ADCS 7399251  
STV7612  
PACKAGE MECHANICAL DATA  
144 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)  
A
A2  
A1  
e
144  
109  
0,076 mm  
0.03 inch  
SEATING PLANE  
108  
1
36  
73  
37  
72  
D3  
D1  
D
0,25 mm  
.010 inch  
GAGE PLANE  
K
Millimetres  
Dimensions  
Inches  
Typ.  
Min.  
Typ.  
Max.  
1.60  
0.15  
1.45  
0.27  
0.20  
Min.  
Max.  
0.063  
0.006  
0.057  
0.011  
0.008  
A
A1  
A2  
B
0.05  
1.35  
0.17  
0.09  
0.002  
0.053  
1.40  
0.22  
0.055  
0.0067  
0.0035  
0.0087  
C
D
22.00  
20.00  
17.50  
0.50  
0.866  
0.787  
0.689  
0.020  
0.866  
0.787  
0.689  
0.024  
0.039  
D1  
D3  
e
E
22.00  
20.00  
17.50  
0.60  
E1  
E3  
L
0.45  
0.75  
0.018  
0.030  
L1  
K
1.00  
0° (Min.), 7° (Max.)  
ADCS 7399251  
17/18  
STV7612  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no  
responsibility for the consequences of use of such information nor for any infringement of patents or other  
rights of third parties which may result from its use. No license is granted by implication or otherwise under  
any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied.  
STMicroelectronics products are not authorized for use as critical components in life support devices or  
systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics  
© 2003 STMicroelectronics - All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel -Italy - Japan  
- Malaysia - Malta-Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States  
www.st.com  
18/18  
ADCS 7399251  
4

相关型号：

STV7617

 PLASMA DISPLAY PANEL SCAN DRIVER
STMICROELECTR

STV7617D

 PLASMA DISPLAY PANEL SCAN DRIVER
STMICROELECTR

STV7617U

 PLASMA DISPLAY PANEL SCAN DRIVER
STMICROELECTR

STV7618

 PLASMA DISPLAY PANEL DATA DRIVER
STMICROELECTR

STV7618/WAF

 PLASMA DISPLAY PANEL DATA DRIVER
STMICROELECTR

STV7618WAF

 PLASMA DISPLAY PANEL DATA DRIVER
STMICROELECTR

STV7619

 DC PLASMA DISPLAY DRIVER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
STMICROELECTR

STV7619D

 DC PLASMA DISPLAY DRIVER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
STMICROELECTR

STV7619DU

 64 OUTPUT PLASMA DISPLAY PANEL SCAN DRIVER WITH 100MA/1A SOURCE/SINK OUTPUT MOS AND 120V ABSOLUTE MAXIMUM SUPPLY
ETC

STV7620

 PLASMA DISPLAY PANEL DATA DRIVER
STMICROELECTR

STV7620F

 PLASMA DISPLAY PANEL DATA DRIVER
STMICROELECTR

STV7620M

 PLASMA DISPLAY PANEL DATA DRIVER
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明