TSA1002CFT_技术文档

TSA1002

10-BIT, 50MSPS, 50mW A/D CONVERTER

■ 10-bit A/D converter in deep submicron

ORDER CODE

CMOS technology

■ Single supply voltage: 2.5V

■ Input range: 2Vpp differential

■ 50Msps sampling frequency

■ Ultra low power consumption: 50mW @

50Msps

Temperature

Part Number

Package

Conditioning

Marking

Range

TSA1002CF

TSA1002CFT

TSA1002IF

0°C to +70°C

-40°C to +85°C

TQFP48

Tray

SA1002C

SA1002I

Tape & Reel

Tray

■ ENOB=9.4 @ Fs=50Msps, Fin=15MHz

■ SFDR typically up to 72dB @ Fs=50Msps,

Fin=5MHz

TSA1002IFT

EVAL1002/AA

Tape & Reel

Evaluation board

■ Built-in reference voltage with external bias

capability

PIN CONNECTIONS (top view)

■ STMicroelectronics 8, 10, 12 and 14-bits ADC

pinout compatibility

DESCRIPTION

The TSA1002 is a 10-bit, 50Msps sampling

frequency Analog to Digital converter using a

CMOS technology combining high performances

and very low power consumption.

The TSA1002 is based on a pipeline structure and

digital error correction to provide excellent static

linearity and guarantee 9.4 effective bits at

Fs=50Msps, and Fin=15MHz.

A voltage reference is integrated in the circuit to

simplify the design and minimize external

components. It is nevertheless possible to use the

circuit with an external reference.

index

corner

37

48 47 46 45 44 43 42 41 40 39 38

NC

36

35

IPOL

1

VREFP

2

3

34

VREFM

AGND

4

5

33 D0 (LSB)

32

D1

VIN

31

30

29

28

6

7

D2

D3

D4

D5

D6

D7

D8

AGND

VINB

AGND

INCM

TSA1002

8

9

27

26

AGND 10

AVCC

11

12

25

13 14 15 16 17 18 19 20 21 22 23 24

Especially designed for high speed, low power

applications, the TSA1002 only dissipates 50mW

at 50Msps. A tri-state capability, available on the

output buffers, enables to address several slave

ADCs by a unique master.

The output data can be coded into two different

formats. A Data Ready signal is raised as the data

is valid on the output and can be used for

synchronization purposes.

The TSA1002 is available in commercial (0 to

+70°C) and extended (-40 to +85°C) temperature

range, in a small 48 pins TQFP package.

PACKAGE

7 × 7 mm TQFP48

APPLICATIONS

■ Medical imaging and ultrasound

■ Portable instrumentation

■ Cable Modem Receivers

■ High resolution fax and scanners

■ High speed DSP interface

October 2000

1/19

TSA1002

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Values

0 to 3.3

Unit

V

1)

AVCC

DVCC

Analog Supply voltage

1)

V

Digital Supply voltage

1)

VCCB

IDout

Tstg

0 to 3.3

-100 to 100

+150

V

Digital buffer Supply voltage

Digital output current

Storage temperature

Electrical Static Discharge

- HBM

mA

°C

ESD

2

KV

- CDM-JEDEC Standard

1.5

1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages

must never exceed -0.3V or VCC+0V

OPERATING CONDITIONS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

AVCC Analog Supply voltage

2.25

1.16

0

2.5

-

2.7

V

DVCC Digital Supply voltage

VCCB Digital buffer Supply voltage

VREFP Forced top reference voltage

VREFM Forced bottom reference voltage

2.7

AVCC

0.5

0

BLOCK DIAGRAM

VREFP

+2.5V

GNDA

VIN

Reference

circuit

stage

2

stage

1

stage

n

INCM

VINB

IPOL

VREFM

DFSB

OEB

Sequencer-phase shifting

Digital data correction

CLK

Timing

DR

DO

TO

Buffers

D9

OR

GND

2/19

TSA1002

PIN CONNECTIONS (top view)

index

corner

37

48 47 46 45 44 43 42 41 40 39 38

NC

36

35

IPOL

1

VREFP

2

3

34

VREFM

AGND

4

5

33 D0 (LSB)

32

VIN

D1

31

30

29

28

D2

D3

D4

D5

D6

D7

D8

6

7

AGND

VINB

AGND

INCM

TSA1002

8

9

27

26

AGND 10

AVCC

11

12

25

13 14 15 16 17 18 19 20 21 22 23 24

PIN DESCRIPTION

Pin No

Name

Description

Analog bias current input

Observation

Pin No

Name

Description

Digital output

Observation

1

2

IPOL

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

D8

D7

D6

D5

D4

D3

D2

D1

CMOS output (2.5V)

VREFP Top voltage reference

1V

Digital output

3

VREFM Bottom voltage reference

0V

4

AGND

VIN

Analog ground

0V

5

Analog input

1Vpp

0V

6

AGND

VINB

Analog ground

7

Inverted analog input

Analog ground

1Vpp

0V

8

AGND

INCM

AGND

AVCC

DVCC

DGND

CLK

9

Input common mode

Analog ground

0.5V

0V

D0(LSB) Least Significant Bit output CMOS output (2.5V)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

NC

Non connected

Data Ready output

Analog power supply

Digital power supply

Digital ground

2.5V

0V

NC

DR

CMOS output (2.5V)

VCCB

GNDB

VCCB

NC

Digital Buffer power supply 2.5V

Digital Buffer ground 0V

Clock input

2.5V compatible CMOS input

0V

DGND

NC

Digital ground

Digital Buffer power supply 2.5V

Non connected

DGND

GNDB

VCCB

OR

Digital ground

0V

NC

Non connected

Digital buffer ground

Digital buffer power supply

Out Of Range output

0V

OEB

DFSB

AVCC

AGND

Output Enable input

Data Format Select input

Analog power supply

Analog ground

2.5V compatible CMOS input

0V

2.5V compatible CMOS input

2.5V

0V

CMOS output (2.5V)

D9(MSB) Most Significant Bit output

3/19

TSA1002

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

TIMING CHARACTERISTICS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

FS

DC

Sampling Frequency

Clock Duty Cycle

0.5

45

9

50

55

Msps

%

50

10

TC1

TC2

Clock pulse width (high)

Clock pulse width (low)

ns

9

ns

Data Output Delay (Fall of Clock 10pF load capacitance

to Data Valid)

Tod

Tpd

Ton

5

6.5

1

ns

cycles

ns

Data Pipeline delay

Falling edge of OEB to digital

output valid data

Rising edge of OEB to digital

output tri-state

Toff

1

ns

TIMING DIAGRAM

N+4

N+5

N+3

N+6

N+7

N+2

N-1

N+1

N+8

N

CLK

6.5 clk cycles

OEB

Ton

Toff

Tod

DATA

OUT

N-8

N-4

N

N-6

N-5

N-2

N-3

N-7

N+1

DR

HZ state

4/19

TSA1002

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

ANALOG INPUTS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

VIN-VINB Full scale reference voltage

2.0

7.0

100

Vpp

pF

Cin

BW

Input capacitance

Analog Input Bandwidth

Vin@ Full scale, FS=50Msps

MHz

1)

ERB

60

MHz

Effective Resolution Bandwidth

1) See parameters definition for more information

REFERENCE VOLTAGE

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

0.91

0.88

1.20

1.18

50

1.03

1.14

1.16

1.35

1.36

100

V

VREFP Top internal reference voltage

1)

Tmin= -40°C to Tmax= 85°C

1.27

Vpol

Analog bias voltage

1)

Tmin= -40°C to Tmax= 85°C

Normal operating mode

Shutdown mode

Ipol

Analog bias current

70

0

µA

V

0.47

0.46

0.57

0.68

0.66

VINCM Input common mode voltage

1)

V

Tmin= -40°C to Tmax= 85°C

1) Not fully tested over the temperature range. Guaranted by sampling.

5/19

TSA1002

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

POWER CONSUMPTION

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

1)

15.6

18

mA

ICCA

Analog Supply current

2)

21

2

mA

Tmin= -40°C to Tmax= 85°C

1)

1.3

2.5

ICCD

Digital Supply Current

2

Tmin= -40°C to Tmax= 85°C

1)

5

ICCB

ICCBZ

Pd

Digital Buffer Supply Current

5

Tmin= -40°C to Tmax= 85°C

1)

Digital Buffer Supply Current in

High Impedance Mode

40

48

100

µA

1)

60

62

mW

Power consumption in normal

operation mode

2)

Tmin= -40°C to Tmax= 85°C

1)

Power consumption in High

Impedance mode

PdZ

43

80

48

mW

Junction-ambient thermal resis-

tor (TQFP48)

Rthja

°C/W

1) Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF

2) Not fully tested over the temperature range. Guaranted by sampling.

DIGITAL INPUTS AND OUTPUTS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Digital inputs

VIL

Logic "0" voltage

Logic "1" voltage

0.8

V

VIH

2.0

Digital Outputs

VOL

VOH

IOZ

Logic "0" voltage

Logic "1" voltage

Iol=10µA

Ioh=-10µA

0.4

V

2.4

High Impedance leakage current OEB set to VIH

Output Load Capacitance

-1.5

1.5

15

µA

pF

C

L

ACCURACY

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Fin= 2MHz, VIN@+1dBFS

OE

DNL

INL

Offset Error

-5

±0.2

±0.3

+5

%

Differential Non Linearity

Integral Non Linearity

-0.7

-0.8

+0.7

+0.8

LSB

Fin= 2MHz, VIN@+1dBFS

Monotonicity and no missing

codes

-

Guaranted

6/19

TSA1002

CONDITIONS

AVCC = DVCC = 2.5V, Fs= 40Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V

Tamb = 25°C (unless otherwise specified)

DYNAMIC CHARACTERISTICS

Symbol

Parameter

Test conditions

Fin= 5MHz

Min

Typ

Max

Unit

65.5

68.5

63.4

79.2

77

1)

2)

1)

2)

1)

2)

dBc

Fin= 10MHz

Fin= 24MHz

69

SFDR Spurious Free Dynamic Range

Fin= 5MHz

60

dBc

dB

Fin= 10MHz

Fin= 24MHz

Fin= 5MHz

58.5

58.3

57.4

59.5

59.4

59.0

Fin= 10MHz

Fin= 24MHz

SNR

Signal to Noise Ratio

Fin= 5MHz

48

dB

Fin= 10MHz

Fin= 24MHz

Fin= 5MHz

63.5

67.4

62.5

77.8

76

dB

Fin= 10MHz

Fin= 24MHz

68.1

THD

Total Harmonic Distortion

Fin= 5MHz

57

55

57

dB

Fin= 10MHz

Fin= 24MHz

Fin= 5MHz

58.5

58.2

57.0

59.4

59.3

58.5

1)

dB

Fin= 10MHz

Fin= 24MHz

Signal to Noise and Distortion-

Ratio

SINAD

Fin= 5MHz

48

2)

dB

Fin= 10MHz

Fin= 24MHz

Fin= 5MHz

9.6

9.5

9.3

9.76

9.71

9.60

1)

bits

Fin= 10MHz

Fin= 24MHz

ENOB Effective Number of Bits

Fin= 5MHz

7.9

2)

Fin= 10MHz

Fin= 24MHz

1) Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF

2) Tmin= -40°C to Tmax= 85°C. Not fully tested over the temperature range. Guaranted by sampling.

7/19

TSA1002

DEFINITIONS OF SPECIFIED PARAMETERS

STATIC PARAMETERS

Signal to Noise Ratio (SNR)

The ratio of the rms value of the fundamental

component to the rms sum of all other spectral

components in the Nyquist band (f /2) excluding

DC, fundamental and the first five harmonics.

SNR is reported in dB.

s

Static measurements are performed through

method of histograms on a 2MHz input signal,

sampled at 40Msps, which is high enough to fully

characterize the test frequency response. The

input level is +1dBFS to saturate the signal.

Signal to Noise and Distorsion Ratio (SINAD)

Similar ratio as for SNR but including the harmonic

distortion components in the noise figure (not DC

signal). It is expressed in dB.

Differential Non Linearity (DNL)

From the SINAD, the Effective Number of Bits

(ENOB) can easily be deduced using the formula:

SINAD= 6.02 × ENOB + 1.76 dB.

The average deviation of any output code width

from the ideal code width of 1LSB.

When the applied signal is not Full Scale (FS), but

Integral Non linearity (INL)

has an A amplitude, the SINAD expression

0

becomes:

An ideal converter presents a transfer function as

being the straight line from the starting code to the

ending code. The INL is the deviation for each

transition from this ideal curve.

SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A /FS)

The ENOB is expressed in bits.

0

Analog Input Bandwidth

The maximum analog input frequency at which the

spectral response of a full power signal is reduced

by 3dB. Higher values can be achieved with

smaller input levels.

DYNAMIC PARAMETERS

Dynamic measurements are performed by

spectral analysis, applied to an input sinewave of

various frequencies and sampled at 40Msps.

Effective Resolution Bandwidth (ERB)

The band of input signal frequencies that the ADC

is intended to convert without loosing linearity i.e.

the maximum analog input frequency at which the

SINAD is decreased by 3dB or the ENOB by 1/2

bit.

Spurious Free Dynamic Range (SFDR)

The ratio between the amplitude of fundamental

tone (signal power) and the power of the worst

spurious signal (not always an harmonic) over the

full Nyquist band. It is expressed in dBc.

Pipeline delay

Delay between time when the analog input is

initially sampled and time when the corresponding

digital data output is valid on the output bus. Also

called data latency. It is expressed as a number of

clock cycles.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first five harmonic

distortion components to the rms value of the

fundamental line. It is expressed in dB.

8/19

TSA1002

EQUIVALENT CIRCUITS

Figure 1 : Analog Input Circuit

Figure 3 : Input buffers

VCC buf=2.5V

AVCC=2.5V

VIN

355.5 Ω

278.5 Ω 208.2 Ω

DFS

(or VINB)

7 pF

PAD

CAPACITANCE

7 pF

Req # 33 Ω

k

PAD

CAPACITANCE

(if Fs=50 MHz)

AGND=0V

common mode

GND buff=0V

Figure 2 : Input clock circuit

Figure 4 : Tri-state output buffers

VCC buf=2.5V

DVCC=2.5V

OE

CLK

GND buff=0V

DATA

OUT

2 mA

VCC buf =2.5V

OUTPUT

BUFFER

7 pF

PAD

CAPACITANCE

PAD CAPACITANCE

7pF

GNDbuff=0V

DGND=0V

9/19

TSA1002

Static parameter: Integral Non Linearity

Fs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts

0 .8

0 .6

0 .4

0 .2

0

-0 .2

-0 .4

-0 .6

-0 .8

0

2 00

4 0 0

60 0

8 00

1 0 00

O u tp u t C o d e

Static parameter: Differential Non Linearity

Fs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts

0 .5

0 .4

0 .3

0 .2

0 .1

0

-0 .1

-0 .2

-0 .3

-0 .4

-0 .5

0

2 0 0

4 0 0

6 0 0

8 0 0

1 0 0 0

O u tp u t C o d e

Linearity vs. AVcc

Distortion vs. AVcc

Fs=50MSPS; Icca=20mA; Fin=1MHz

-69

-71

60

10

59.5

9.9

9.8

9.7

9.6

9.5

9.4

9.3

SNR

SFDR

59

-73

58.5

-75

SINAD

58

57.5

57

THD

-77

-79

-81

-83

-85

56.5

56

ENOB

55.5

55

2.25

2.35

2.45

2.55

2.65

2.25

2.35

2.45

2.55

2.65

AVCC (V)

10/19

TSA1002

Linearity vs. DVcc

Distortion vs. DVcc

Fs=50MSPS; Icca=20mA; Fin=1MHz

-65

-67

-69

-71

59.1

9.6

SNR

59.05

59

9.595

9.59

9.585

9.58

9.575

9.57

SFDR

-73

ENOB

58.95

58.9

58.85

58.8

-75

-77

THD

SINAD

-79

-81

-83

-85

2.25

2.35

2.45

2.55

2.65

2.25

2.35

2.45

2.55

2.65

DVCC (V)

Linearity vs. VccB

Distortion vs. VccB

Fs=50MSPS; Icca=20mA; Fin=1MHz

59.5

10

-72

-73

-74

9.9

9.8

9.7

9.6

9.5

9.4

SNR

59

58.5

58

THD

-75

SINAD

-76

-77

ENOB

-78

SFDR

57.5

57

-79

-80

2.25

2.35

2.45

2.55

2.65

2.25

2.35

2.45

2.55

2.65

VCCB (V)

Linearity vs. Fs

Distortion vs. Fs

Icca=20mA; Fin=5MHz

10

9.5

9

-50

-55

-60

ENOB

66

SNR

61

THD

-65

-70

SINAD

56

8.5

8

-75

SFDR

-80

51

46

-85

-90

7.5

25

35

45

55

65

75

25

35

45

55

65

75

Fs (MHz)

11/19

TSA1002

Linearity vs. Fs

Distortion vs. Fs

Icca=20mA; Fin=15MHz

10

9.5

9

-50

-55

-60

ENOB

66

THD

-65

SNR

61

-70

SINAD

56

8.5

8

SFDR

-75

-80

-85

-90

51

46

7.5

25

35

45

55

65

75

25

35

45

55

65

75

Fs (MHz)

Linearity vs. Fin

Distortion vs. Fin

Fs=50MSPS; Icca=20mA

-50

-55

-60

64

62

60

58

56

54

9.6

ENOB

9.1

8.6

8.1

7.6

THD

-65

-70

-75

-80

-85

SNR

SFDR

SINAD

0

20

40

60

0

20

40

60

Fin (MHz)

Linearity vs.Temperature

Distortion vs. Temperature

Fs=50MSPS; Icca=20mA; Fin=5MHz

Fs=50MSPS; Icca=20mA; Fin=5MHz;

80

10

64

9.8

9.6

9.4

9.2

9

8.8

8.6

8.4

8.2

8

ENOB

62

75

SFDR

60

58

56

54

52

50

SNR

70

THD

65

60

55

SINAD

-50

0

50

100

-50

0

50

100

Temperature (°C)

12/19

TSA1002 APPLICATION NOTE

DETAILED INFORMATION

couple for each stage. The corrected data are

outputed through the digital buffers.

Signal input is sampled on the rising edge of the

clock while digital outputs are delivered on the

falling edge of the Data Ready signal.

The advantages of such a converter reside in the

combination of pipeline architecture and the most

advanced technologies. The highest dynamic

performances are achieved while consumption

remains at the lowest level.

The TSA1002 is a High Speed analog to digital

converter based on a pipeline architecture and the

latest deep submicron CMOS process to achieve

the best performances in terms of linearity and

power consumption.

The pipeline structure consists of 9 internal

conversion stages in which the analog signal is

fed and sequencially converted into digital data.

Some functionalities have been added in order to

simplify as much as possible the application

board. These operational modes are described in

the following table.

The TSA1002 is pin to pin compatible with the

8bits/40Msps TSA0801, the 10bits/25Msps

TSA1001 and the 12bits/50Msps TSA1201. This

ensures a conformity within the product family and

above all, an easy upgrade of the application.

Each 8 first stages consists of an Analog to Digital

converter, a Digital to Analog converter, a Sample

and Hold and a gain of 2 amplifier. A 1.5bit

conversion resolution is achieved in each stage.

The latest stage simply is a comparator. Each

resulting LSB-MSB couple is then time shifted to

recover from the conversion delay. Digital data

correction completes the processing by

recovering from the redundancy of the (LSB-MSB)

OPERATIONAL MODES DESCRIPTION

Inputs

Outputs

Analog input differential level

DFSB

OEB

OR

DR

Most Significant Bit (MSB)

(VIN-VINB)

>

RANGE

H

L

H

CLK

HZ

D9

-RANGE

RANGE>

(VIN-VINB)

-RANGE

>

(VIN-VINB)

>-RANGE

RANGE

D9

(VIN-VINB)

L

D9

>

H

Complemented D9

HZ

>

(VIN-VINB)

X

(VIN-VINB)

>-RANGE

L

H

RANGE>

L

X

HZ

Data Format Select (DFSB)

lower consumption while the converter goes on

sampling.

When set to low level (VIL), the digital input DFSB

provides a two’s complement digital output MSB.

This can be of interest when performing some

further signal processing.

When OEB is set to low level again, , the data is

then valid on the output with a very short Ton

delay.

When set to high level (VIH), DFSB provides a

standard binary output coding.

The timing diagram summarizes this operating

cycle.

Output Enable (OEB)

Out of Range (OR)

When set to low level (VIL), all digital outputs

remain active and are in low impedance state.

When set to high level (VIH), all digital outputs

buffers are in high impedance state. This results in

This function is implemented on the output stage

in order to set up an "Out of Range" flag whenever

the digital data is over the full scale range.

13/19

TSA1002

Typically, there is a detection of all the data being

at ’0’ or all the data being at ’1’. This ends up with

an output signal OR which is in low level state

(VOL) when the data stay within the range, or in

high level state (VOH) when the data are out of the

range.

Single-ended input configuration

Some applications may require a single-ended

input which is easily achieved with the

configuration reported on Figure 6.

In this case, it is recommended to use an

AC-coupled analog input and connect the other

analog input to the common mode voltage of the

circuit (INCM) so as to properly bias the ADC. The

INCM may remain at the same internal level

(0.56V) thus driving only a 1Vpp input amplitude,

or it must be increased to 0.9V to drive a 2Vpp

input amplitude. You will get higher performances

using a 2Vpp signal.

Data Ready (DR)

The Data Ready output is an image of the clock

being synchronized on the output data (D0 to D9).

This is a very helpful signal that simplifies the

synchronization of the measurement equipment or

the controlling DSP.

As digital output, DR goes in high impedance state

when OEB is asserted to High level as described

in the timing diagram.

Figure 6 : Single-ended input configuration

Signal source

100nF

VIN

DRIVING THE ANALOG INPUT

Differential inputs

TSA1002

VINB

50Ω

INCM

The TSA1002 has been designed to obtain

optimum performances when being differentially

driven. An RF transformer is a good way to

achieve such performances.

330pF

10nF

470nF

0.9V

Figure 5 describes the schematics. The input

signal is fed to the primary of the transformer,

while the secondary drives both ADC inputs. The

common mode voltage of the ADC (INCM) is

connected to the center-tap of the secondary of

the transformer in order to bias the input signal

around this common voltage, internally set to

0.56V. The INCM is decoupled to maintain a low

noise level on this node. Our evaluation board is

mounted with a 1:1 ADT1-1 transformer from

Dynamic characteristics, while not being as

remarkable as for differential configuration, are

still of very good quality. Measurements done at

50Msps, 2MHz input frequency, -1dBFS input

level sum up these performances. An SFDR of

-64.5dBc, a SNR of 57.8dB and an ENOB Full

Scale of 9.3bits are achieved.

REFERENCE CONNECTION

Minicircuits. You might also use

impedance ratio (1:2 or 1:4) to reduce the driving

requirement on the analog signal source.

a higher

Internal reference

In the standard configuration, the ADC is biased

with the internal reference voltage. VREFM pin is

connected to Analog Ground while VREFP is

internally set to a voltage of 1.03V. It is

recommended to decouple the VREFP in order to

minimize low and high frequency noise. Refer to

Figure 7 for the schematics.

Each analog input can drive a 1Vpp amplitude

input signal, so the resultant differential amplitude

is 2Vpp.

Figure 5 : Differential input configuration

Figure 7 : Internal reference setting

ADT1-1

Analog source

1:1

VIN

1.03V

TSA1002

50Ω

470nF

10nF

330pF

100pF

VREFP

VINB

VIN

INCM

TSA1002

VINB

330pF

10nF

470nF

VREFM

14/19

TSA1002

External reference

The TSA1002 will combine highest performances

and lowest consumption at 50Msps when Rpol is

in the range of 12kΩ to 20kΩ.

At lower sampling frequency, this value of resistor

may be changed and the consumption will

decrease as well.

It is possible to use an external reference voltage

instead of the internal one for specific applications

requiring even better linearity or enhanced

temperature behaviour. In this case, the amplitude

of the external voltage must be at least equal to

The figure 9 sums up the relevant data.

the

internal

one

(1.03V).

Using

the

STMicroelectronics Vref TS821 leads to optimum

performances when configured as shown on

Figure 8.

Figure 9 : Analog Current consumption vs. Fs

According value of Rpol polarization resistance

Figure 8 : External reference setting

60

50

40

30

20

10

0

20

18

16

14

12

10

8

RPOL

1k

Ω

470nF

10nF

330pF

VCCA VREFP

VIN

TSA1002

TS821

6

VINB

external

reference

ICCA

4

VREFM

2

0

25

35

45

55

65

75

Fs (MHz)

At 15Msps sampling frequency, 1MHz input

frequency and -1dBFS amplitude signal,

performances can be improved of up to 2dBc on

SFDR and 0.3dB on SINAD. At 50Msps sampling

frequency, 1MHz input frequency and -1dBFS

amplitude signal, performances can be improved

of up to 1dBc on SFDR and 0.6dB on SINAD.

This can be very helpful for example for

multichannel application to keep a good matching

among the sampling frequency range.

Layout precautions

To use the ADC circuits in the best manner at high

frequencies, some precautions have to be taken

for power supplies:

- First of all, the implementation of 4 separate

proper supplies and ground planes (analog,

digital, internal and external buffer ones) on the

PCB is mandatory for high speed circuit

applications to provide low inductance and low

resistance common return.

Clock input

The quality of your converter is very dependant on

your clock input accuracy, in terms of aperture

jitter; the use of low jitter crystal controlled

oscillator is recommended.

The separation of the analog signal from the

digital part is essential to prevent noise from

coupling onto the input signal.

- Power supply bypass capacitors must be placed

as close as possible to the IC pins in order to

improve high frequency bypassing and reduce

harmonic distortion.

The duty cycle must be between 45% and 55%.

The clock power supplies must be separated from

the ADC output ones to avoid digital noise

modulation at the output.

- Proper termination of all inputs and outputs must

be incorporated with output termination resistors;

then the amplifier load will be only resistive and

the stability of the amplifier will be improved. All

leads must be wide and as short as possible

especially for the analog input in order to decrease

parasitic capacitance and inductance.

- To keep the capacitive loading as low as

possible at digital outputs, short lead lengths of

routing are essential to minimize currents when

the output changes. To minimize this output

It is recommended to always keep the circuit

clocked, even at the lowest specified sampling

frequency of 0.5Msps, before applying the supply

voltages.

Power consumption

The internal architecture of the TSA1002 enables

to optimize the power consumption according to

the sampling frequency of the application. For this

purpose, a resistor is placed between IPOL and

the analog Ground pins.

15/19

TSA1002

capacitance, buffers or latches close to the output

pins will relax this constraint.

The dataready signal is the acquisition clock of the

logic analyzer.

- Choose component sizes as small as possible

(SMD).

The ADC digital outputs are latched by the octal

buffers 74LCX573.

EVAL1002 evaluation board

All characterization measurements have been

made with:

The characterization of the board has been made

with a fully ADC devoted test bench as shown on

Figure 10. The analog signal must be filtered to be

very pure.

SFSR=+0.2dB

for

static

parameters.-

SFSR=-0.5dB for dynamic parameters.

Figure 10 : Analog to Digital Converter characterization bench

Power

HP8644B

data

ADC

evaluation

board

Vin

Sine wave

Generator

Logic

Analyzer

dataready

ck

TLA704

Pulse

Generator

HP8133A

HP8644B

Sine Wave

Generator

16/19

TSA1002

Figure 11 : TSA1002 Evaluation board schematic

2

1

+

2

1

2

D 0

D R

3

D 1

O R

3 7

3 8

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

+

2

1

F F

F

C C V 5 B . 2 U

G N D B

C C V 5 B . 2 U

F F

F

C C V 5 B . 2 U

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

U F

G N D B

D G N D

N C

D G N D

C L

D G N D

D V C

F F

N C

O E

F S D B

A V C

2

1

4

3

1

B

K

2

6

C

2

1

A V C

A G N D

C

1

2

+

1

2

17/19

TSA1002

Figure 12 : Printed circuit of evaluation board.

Printed circuit board - List of components

P a rt

D e s ig n F o o tp rin t

a t o r

P a rt

T yp e

D e s ig n F o o t prin t

a t o r

P a rt

D e s ign F o o tp rint

a t o r

P a rt

D e s ign F o o t prin t

a t o r

T yp e

10 u F

T ype

T yp e

C 2 4

C 2 3

C 4 1

C 2 9

12 10

6 0 3

ID C 3 2

3 3 0 p F C 3 3

3 3 0 p F C 2 0

3 3 0 p F C 8

3 3 0 p F C 2

3 3 0 p F C 5

3 3 0 p F C 11

3 3 0 p F C 3 0

3 3 0 p F C 17

3 3 0 p F C 14

6 0 3

C A P

8 0 5

47 0n F

C 7

8 05

A VC C

C LJ / S M B

A GN D

D F S B

J 12

J 4

F IC H E 2M M

S M B / H

C 16

C 19

C 3

8 05

J 19

J 9

F IC H E 2M M

A D T

8 05

10 0 p F C 1

47 K

Ω

R 12

R 14

R 11

R a j1

R 10

R 19

R 13

R 15

R 16

R 17

R 18

R 3

6 03

D GN D

D VC C

G ndB 1

G ndB 2

J 2 0

J 15

J 2 2

J 2 1

10 n F

C 12

C 3 9

C 15

C 4 0

C 2 7

C 4

6 03

VR 5

6 03

M e s c o m m o d e J 8

47u F

C 36

C 34

C 35

C 42

6 03

O E B

J 10

6 03

R e gl c o m m o de J 7

C 2 1

C 3 1

C 6

6 03

T 2-A T 1-1WT

Vc c B 1

T 2

T 1

J 18

J 17

J 1

6 03

A D T

4 7 0 n F C 2 2

4 7 0 n F C 3 2

4 7 0 n F C 3 7

4 7 0 n F C 3 8

4 7 0 n F C 13

4 7 0 n F C 2 8

4 7 0 n F C 10

6 03

F IC H E 2M M

S M B / H

C 9

6 03

VD D B UF F 3V

Vin

C 18

R 2

50

Ω

6 03

1K

Ω

R 1

6 03

Vre fM

J 5

F IC H E 2M M

T QF P 48

3 2 P IN J 6

74 LC X5 73 U3

74 LC X5 73 U2

T S S OP 2 0

S IP 2

Vre fP

J 2

3 30p F C 25

3 30p F C 26

6 0 3

T S A 100 2

U1

C O N 2

J 16

18/19

TSA1002

PACKAGE MECHANICAL DATA

48 PINS - PLASTIC PACKAGE

A

A2

A1

e

48

37

0,10 mm

.004 inch

SEATING PLANE

1

36

25

12

c

13

24

D3

D1

D

0,25 mm

.010 inch

GAGE PLANE

K

Millimeters

Typ.

Inches

Typ.

Dim.

Min.

Max.

Min.

Max.

A

1.60

0.15

1.45

0.27

0.20

0.063

0.006

0.057

0.011

0.008

A1

A2

B

0.05

1.35

0.17

0.09

0.002

0.053

0.007

0.004

1.40

0.22

0.055

0.009

C

D

9.00

7.00

5.50

0.50

9.00

7.00

5.50

0.60

1.00

0.354

0.276

0.216

0.0197

0.354

0.276

0.216

0.024

0.039

D1

D3

e

E

E1

E3

L

0.45

0.75

0.018

0.030

L1

K

0° (min.), 7° (max.)

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of STMicroelectronics.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco

Singapore - Spain - Sweden - Switzerland - United Kingdom

19/19


型号：	TSA1002CFT
厂家：	ST
描述：	10-BIT, 50MSPS, 50mW A/D CONVERTER 10位， 50MSPS ， 50mW的A / D转换器转换器模数转换器
文件：	总19页 (文件大小：241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TSA1002CFT [STMICROELECTRONICS]

相关型号：

TSA1002IF

TSA1002IFT

TSA1002_04

TSA1005

TSA1005-20IF

TSA1005-20IFT

TSA1005-40IF

TSA1005-40IFT

TSA1005I-40IF

TSA100A

TSA100C

TSA1015