TSX7192IYST [STMICROELECTRONICS]
Low-power, precision, rail-to-rail, 9.0 MHz, 16 V operational amplifiers;
| 型号： | TSX7192IYST |
| 厂家： | 
ST |
| 描述： | Low-power, precision, rail-to-rail, 9.0 MHz, 16 V operational amplifiers |
| 文件： | 总25页 (文件大小：702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSX7192
Low-power, precision, rail-to-rail, 9.0 MHz, 16 V operational
amplifiers
Datasheet - production data
Description
The TSX7192 dual, operational amplifier
(op amp) offers high precision functioning with
low input offset voltage down to a maximum of
200 µV at 25 °C. In addition, its rail-to-rail input
and output functionality allows this product to be
used on full range input and output without
limitation. This is particularly useful for a low-
voltage supply such as 2.7 V that the TSX7192 is
able to operate with.
Features
Thus, the TSX7192 has the great advantage of
offering a large span of supply voltages, ranging
from 2.7 V to 16 V. It can be used in multiple
applications with a unique reference.
•
•
•
•
•
•
•
•
•
•
Low input offset voltage: 200 µV max.
Rail-to-rail input and output
Low current consumption: 850 µA max.
Gain bandwidth product: 9 MHz
Low supply voltage: 2.7 to 16 V
Stable when used with Gain ≥ 10
Low input bias current: 50 pA max.
High ESD tolerance: 4 kV HBM
Extended temp. range: -40 °C to 125 °C
Automotive qualification
Low input bias current performance makes the
TSX7192 perfect when used for signal
conditioning in sensor interface applications. In
addition, low-side and high-side current
measurements can be easily made thanks to rail-
to-rail functionality. The TSX7192 is
a
decompensated amplifier and must be used with
a gain greater than 10 to ensure stability.
Related products
High ESD tolerance (4 kV HBM) and a wide
temperature range are also good arguments to
use the TSX7192 in the automotive market
segment.
•
See the TSX7191 for single op amp version
See the TSX712 for lower speeds with
similar precision
•
•
•
•
See the TSX562 for low-power features
See the TSX632 for micro-power features
See the TSX922 for higher speeds
Applications
•
•
•
•
•
Battery-powered instrumentation
Instrumentation amplifier
Active filtering
High-impedance sensor interface
Current sensing (high and low side)
March 2015
DocID027196 Rev 1
1/25
www.st.com
This is information on a product in full production.
Contents
TSX7192
Contents
1
2
3
4
Package pin connections................................................................3
Absolute maximum ratings and operating conditions .................4
Electrical characteristics ................................................................5
Application information ................................................................15
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
Operating voltages..........................................................................15
Input pin voltage ranges..................................................................15
Rail-to-rail input...............................................................................15
Rail-to-rail output.............................................................................15
Input offset voltage drift over temperature.......................................16
Long term input offset voltage drift..................................................16
High values of input differential voltage...........................................17
Capacitive load................................................................................18
PCB layout recommendations.........................................................19
Optimized application recommendation ..........................................19
5
Package information .....................................................................20
5.1
5.2
MiniSO8 package information.........................................................21
SO8 package information................................................................22
6
7
Ordering information.....................................................................23
Revision history ............................................................................24
2/25
DocID027196 Rev 1
TSX7192
Package pin connections
1
Package pin connections
Figure 1: Pin connections (top view)
MiniSO8 and SO8
DocID027196 Rev 1
3/25
Absolute maximum ratings and operating
TSX7192
conditions
2
Absolute maximum ratings and operating conditions
Table 1: Absolute maximum ratings (AMR)
Symbol
VCC
Vid
Parameter
Supply voltage (1)
Differential input voltage (2)
Value
Unit
V
18
±VCC
mV
V
Vin
Input voltage
(VCC-) - 0.2 to (VCC+) + 0.2
Iin
Input current (3)
10
-65 to 150
150
mA
Tstg
Tj
Storage temperature
°C
Maximum junction temperature
HBM: human body model (4)
MM: machine model (5)
CDM: charged device model (6)
Latch-up immunity
4000
100
ESD
V
1500
200
mA
Notes:
(1)All voltage values, except the differential voltage are with respect to the network ground terminal.
(2)Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. See
Section 4.7 for precautions to follow when using the TSX7192 with high differential input voltage.
(3)Input current must be limited by a resistor in series with the inputs.
(4)According to JEDEC standard JESD22-A114F.
(5)According to JEDEC standard JESD22-A115A.
(6)According to ANSI/ESD STM5.3.1.
Table 2: Operating conditions
Symbol
VCC
Parameter
Value
2.7 to 16
Unit
V
Supply voltage
Vicm
Common mode input voltage range
Operating free air temperature range
(VCC- ) - 0.1 to (VCC+) + 0.1
-40 to 125
Toper
°C
4/25
DocID027196 Rev 1
TSX7192
Electrical characteristics
3
Electrical characteristics
Table 3: Electrical characteristics at VCC+ = 4 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C,
and RL > 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
200
365
450
2.5
Unit
μV
T = 25 °C
Vio
Input offset voltage
Tmin < Top < 85 °C
Tmin < Top < 125 °C
ΔVio/ΔT Input offset voltage drift (1)
µV/°C
nV
month
--------------------------
Long term input offset
ΔVio
T = 25 °C
1
voltage drift (2)
Vout = VCC/2
1
1
50
200
50
Iib
Input bias current (1)
Input offset current (1)
Tmin < Top < Tmax
Vout = VCC/2
pA
Iio
Tmin < Top < Tmax
200
RIN
CIN
Input resistance
1
TΩ
Input capacitance
12.5
98
pF
V
icm = -0.1 to 4.1 V, Vout = VCC/2
80
78
Tmin < Top < Tmax
Common mode rejection
ratio 20 log (ΔVic/ΔVio)
CMRR
Vicm = -0.1 to 2 V, Vout = VCC/2
Tmin < Top < Tmax
91
103
136
140
28
86
dB
RL= 2 kΩ, Vout = 0.3 to 3.7 V
Tmin < Top < Tmax
110
96
Avd
Large signal voltage gain
RL= 10 kΩ, Vout = 0.2 to 3.8 V
Tmin < Top < Tmax
110
96
RL= 2 kΩ to VCC/2
Tmin < Top < Tmax
50
60
15
20
50
60
15
20
High level output voltage
(voltage drop from VCC+
VOH
)
RL= 10 kΩ tο VCC/2
Tmin < Top < Tmax
6
mV
RL= 2 kΩ tο VCC/2
Tmin < Top < Tmax
23
VOL
Low level output voltage
RL= 10 kΩ tο VCC/2
Tmin < Top < Tmax
5
V
out = VCC
25
15
35
20
37
Isink
Tmin < Top < Tmax
Vout = 0 V
Iout
mA
45
Isource
Tmin < Top < Tmax
No load, Vout = VCC/2
Tmin < Top < Tmax
570
800
900
ICC
Supply current per amplifier
μA
DocID027196 Rev 1
5/25
Electrical characteristics
TSX7192
Max. Unit
Symbol
Parameter
Conditions
Min.
Typ.
GBP
Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
5
7.7
MHz
Gain = 10, RL = 10 kΩ,
CL = 100 pF
ɸm
Phase margin
42
Degrees
Av = 10, Vout = 3 VPP
10 % to 90 %
,
1.3
1.0
1.5
1.1
2.3
SRn
Negative slew rate
Tmin < Top < Tmax
V/μs
Av = 10, Vout = 3 VPP
10 % to 90 %
,
2.5
SRp
en
Positive slew rate
Tmin < Top < Tmax
f = 1 kHz
22
19
nV
-----------
Equivalent input noise
voltage
Hz
f = 10 kHz
Total harmonic distortion +
noise
f =1 kHz, Av = 10, RL= 10 kΩ,
BW = 22 kHz, Vout = 3VPP
THD+N
0.003
%
Notes:
(1)Maximum values are guaranteed by design.
(2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6).
Table 4: Electrical characteristics at VCC+ = 10 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 °C, and RL > 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
200
365
450
2.5
Unit
μV
T = 25 °C
Vio
Input offset voltage
Tmin < Top < 85 °C
Tmin < Top < 125 °C
ΔVio/ΔT Input offset voltage drift (1)
μV/°C
nV
month
--------------------------
Long term input offset
ΔVio
T = 25 °C
25
voltage drift (2)
Vout = VCC/2
1
1
50
200
50
Iib
Input bias current (1)
Input offset current (1)
Tmin < Top < Tmax
Vout = VCC/2
pA
Iio
Tmin < Top < Tmax
200
RIN
CIN
Input resistance
1
TΩ
Input capacitance
12.5
100
pF
V
icm = -0.1 to 10.1 V, Vout = VCC/2
88
84
Tmin < Top < Tmax
Common mode rejection
ratio 20 log (ΔVic/ΔVio)
CMRR
Vicm = -0.1 to 8 V, Vout = VCC/2
Tmin < Top < Tmax
98
106
140
dB
92
RL= 2 kΩ, Vout = 0.3 to 9.7 V
Tmin < Top < Tmax
110
100
Avd
Large signal voltage gain
6/25
DocID027196 Rev 1
TSX7192
Symbol
Electrical characteristics
Parameter
Conditions
RL= 10 kΩ, Vout = 0.2 to 9.8 V
Tmin < Top < Tmax
Min.
110
100
Typ.
Max.
Unit
Avd
Large signal voltage gain
dB
RL= 2 kΩ tο VCC/2
Tmin < Top < Tmax
45
10
42
9
70
80
30
40
70
80
30
40
High level output voltage
VOH
(voltage drop from VCC+
)
RL= 10 kΩ tο VCC/2
Tmin < Top < Tmax
mV
RL= 2 kΩ tο VCC/2
Tmin < Top < Tmax
VOL
Low level output voltage
RL= 10 kΩ tο VCC/2
Tmin < Top < Tmax
V
out = VCC
30
15
50
40
39
69
630
Isink
Tmin < Top < Tmax
Iout
mA
Vout = 0 V
Isource
Tmin < Top < Tmax
No load, Vout = VCC/2
Tmin < Top < Tmax
850
ICC
Supply current per amplifier
μA
1000
GBP
Gain bandwidth product
Phase margin
RL = 10 kΩ, CL = 100 pF
G = 10, RL = 10 kΩ, CL = 100 pF
5
9
MHz
ɸm
48
Degrees
Av = 10, Vout = 8 VPP
10 % to 90 %
,
1.3
1.0
1.5
1.1
2.3
2.5
SRn
SRp
Negative slew rate
Positive slew rate
Tmin < Top < Tmax
V/μs
Av = 10, Vout = 8 VPP
10 % to 90 %
,
Tmin < Top < Tmax
f = 1 kHz
22
19
nV
-----------
Hz
Equivalent input noise
voltage
en
f = 10 kHz
Total harmonic distortion +
noise
f = 1 kHz, Av = 10, RL= 10 kΩ,
BW = 22 kHz, Vout = 9 VPP
THD+N
0.0001
%
Notes:
(1)Maximum values are guaranteed by design.
(2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6).
DocID027196 Rev 1
7/25
Electrical characteristics
TSX7192
Table 5: Electrical characteristics at VCC+ = 16 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 °C, and RL > 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
200
365
450
2.5
Unit
μV
T = 25 °C
Vio
Input offset voltage
Tmin < Top < 85 °C
Tmin < Top < 125 °C
ΔVio/ΔT Input offset voltage drift (1)
μV/°C
nV
month
--------------------------
Long term input offset
ΔVio
T = 25 °C
500
voltage drift (2)
Vout = VCC/2
1
1
50
200
50
Iib
Input bias current (1)
Input offset current (1)
Tmin < Top < Tmax
Vout = VCC/2
pA
Iio
Tmin < Top < Tmax
200
RIN
CIN
Input resistance
1
TΩ
Input capacitance
12.5
107
pF
V
icm = -0.1 to 16.1 V, Vout = VCC/2
94
90
Tmin < Top < Tmax
Common mode rejection
CMRR
SVRR
Avd
ratio 20 log (ΔVicm/ΔVio)
Vicm = -0.1 to 14 V, Vout = VCC/2
Tmin < Top < Tmax
100
90
107
131
146
149
100
16
V
cc = 4 to 16 V
100
90
Supply voltage rejection
ratio 20 log (ΔVcc/ΔVio)
dB
Tmin < Top < Tmax
RL= 2 kΩ, Vout = 0.3 to 15.7 V
Tmin < Top < Tmax
RL= 10 kΩ, Vout = 0.2 to 15.8 V
Tmin < Top < Tmax
RL= 2 kΩ
110
100
110
100
Large signal voltage gain
130
150
40
Tmin < Top < Tmax
RL= 10 kΩ
High level output voltage
(voltage drop from VCC+
VOH
VOL
Iout
)
Tmin < Top < Tmax
RL= 2 kΩ
50
mV
70
130
150
40
Tmin < Top < Tmax
RL= 10 kΩ
Low level output voltage
15
Tmin < Top < Tmax
Vout = VCC
50
30
15
50
45
40
Isink
Tmin < Top < Tmax
Vout = 0 V
mA
68
Isource
Tmin < Top < Tmax
No load, Vout = VCC/2
Tmin < Top < Tmax
660
900
ICC
Supply current per amplifier
μA
1000
8/25
DocID027196 Rev 1
TSX7192
Electrical characteristics
Symbol
GBP
Parameter
Gain bandwidth product
Phase margin
Conditions
Min.
Typ.
8.5
51
Max.
Unit
MHz
RL = 10 kΩ, CL = 100 pF
G = 10, RL = 10 kΩ, CL = 100 pF
5
ɸm
Degrees
Av = 10, Vout = 10 VPP
10 % to 90 %
,
1.5
1.1
1.5
1.1
2.4
SRn
SRp
Negative slew rate
Positive slew rate
Tmin < Top < Tmax
V/μs
Av = 10, Vout = 10 VPP
10 % to 90 %
,
2.5
Tmin < Top < Tmax
f = 1 kHz
22
19
nV
-----------
Hz
Equivalent input noise
voltage
en
f = 10 kHz
Total harmonic distortion +
Noise
f = 1 kHz, Av = 10, RL= 10 kΩ,
BW = 22 kHz, Vout = 10 VPP
THD+N
0.0001
%
Notes:
(1)Maximum values are guaranteed by design.
(2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6).
DocID027196 Rev 1
9/25
Electrical characteristics
TSX7192
Figure 2: Supply current vs. supply voltage
Figure 3: Input offset voltage distribution at VCC = 16 V
20
800
Vcc=16V
Vicm=8V
T=25°C
Vicm=Vcc/2
15
600
T=-40°C
10
5
400
T=25°C
T=125°C
200
0
0
0
2
4
6
8
10
12
14
16
-300 -250 -200 -150 -100 -50
0
50
100 150 200 250 300
SupplyVoltage (V)
Input offset voltage (µV)
Figure 4: Input offset voltage distribution
at VCC = 4 V
Figure 5: Input offset voltage vs. temperature
at VCC = 16 V
20
15
10
5
600
Vcc=4V
Vicm=2V
T=25°C
Vio limit
400
200
0
-200
-400
Vcc=16V
Vicm=8V
-600
0
-40 -20
0
20
40
60
80 100 120
-300 -250 -200 -150 -100 -50
0
50
100 150 200 250 300
Temperature (°C)
Input offset voltage (µV)
Figure 6: Input offset voltage
drift population
Figure 7: Input offset voltage vs. supply voltage
at VICM = 0 V
40
35
30
25
20
15
10
5
600
Vcc=16V
Vicm=8V
T=25°C
Vicm=0V
400
200
0
-200
T=125°C
14
T=-40°C
6
T=25°C
10
-400
-600
0
4
8
12
16
-4
-3
-2
-1
0
1
2
3
4
Supplyvoltage (V)
∆Vio/∆T (µV/ºC)
10/25
DocID027196 Rev 1
TSX7192
Electrical characteristics
Figure 8: Input offset voltage vs. common mode voltage
at VCC = 2.7 V
Figure 9: Input offset voltage vs. common mode voltage
at VCC = 16 V
600
600
Vcc=2.7V
400
400
200
0
Vcc=16V
200
0
-200
-400
-600
-200
T=125°C
0.5
T=25°C
1.5
T=-40°C
T=-40°C
T=125°C
T=25°C
8
-400
-600
0
2
4
6
10
12
14
16
0.0
1.0
2.0
2.5
Input Common Mode Voltage (V)
Input Common Mode Voltage (V)
Figure 10: Output current vs. output voltage
at VCC = 2.7 V
Figure 11: Output current vs. output voltage
at VCC = 16 V
30.0
Sink
22.5
15.0
7.5
100
Sink
Vid=-1V
75 Vid=-1V
50
25
T=-40°C
T=-40°C
0
0.0
T=25°C
T=25°C
T=125°C
T=125°C
-25
-7.5
-50
-75
-15.0
-22.5
-30.0
Source
Vid=1V
Source
Vcc=16V
8
Vcc=2.7V
1.5
Vid=1V
-100
0
2
4
6
10
12
14 16
0.0
0.5
1.0
2.0
2.5
Output Voltage(V)
Output Voltage(V)
Figure 12: Output low voltage
vs. supply voltage
Figure 13: Output high voltage (drop from VCC+) vs.
supply voltage
30
25
20
15
10
5
30
Vid=-0.1V
Rl=10kΩ to Vcc/2
Vid=0.1V
T=-40°C
T=-40°C
Rl=10kΩ to Vcc/2
25
20
15
10
5
T=25°C
T=25°C
T=125°C
T=125°C
0
0
4
6
8
10
12
14
16
4
6
8
10
12
14
16
SupplyVoltage (V)
SupplyVoltage (V)
DocID027196 Rev 1
11/25
Electrical characteristics
TSX7192
Figure 14: Output voltage vs. input voltage close to the
rail at VCC = 16 V
Figure 15: Slew rate vs.
supply voltage
3.0
2.0
16.00
15.95
15.90
15.85
15.80
15.75
1.0
Vicm=Vcc/2
Vload=Vcc/2
Gain=10
0.0
T=125°C
T=25°C
T=-40°C
0.20
0.15
0.10
Rl=10k
Ω
Cl=100pF
-1.0
-2.0
-3.0
Vcc=16V
Gain=10
0.05
0.00
4
6
8
10
12
14
16
Input voltage (V)
SupplyVoltage (V)
Figure 16: Negative slew rate at VCC = 16 V
Figure 17: Positive slew rate at VCC = 16 V
10
1.0
10
8
1.0
8
6
Vcc=16V
Vicm=Vcc/2
Gain=11
0.8
0.8
0.6
6
T=-40°C
0.6
Rl=10k
Ω
4
0.4
4
0.4
Cl=100pF
2
0.2
2
0.2
T=25°C
T=125°C
0
0
0.0
0.0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
-0.2
-0.4
-0.6
-0.8
-1.0
T=125°C
-0.2
-0.4
-0.6
-0.8
-1.0
Vcc=16V
Vicm=Vcc/2
Gain=11
T=25°C
T=-40°C
Rl=10k
Ω
Cl=100pF
0
2
4
6
8
0
2
4
Time (µs)
6
8
Time (µs)
Figure 18: Response to a small input
voltage step
Figure 19: Recovery behavior after a negative step on
the input
10
5
10
100
50
0.20
Vcc=16V
Vicm=8V
Gain=101
Rl=10k
Ω
8
6
0.16
0.12
0.08
0.04
0.00
-0.04
Rl=10k
Ω
Cl=100pF
T=25°C
Vin
Cl=100pF
Gain=10
T=25°C
Vcc=±8V
Vcc=±1.35V
0
4
0
2
-5
-50
0
-10
0
-100
-2
-10
2
4
6
8
10
12
0
10
Time (µs)
20
30
40
Time (µs)
12/25
DocID027196 Rev 1
TSX7192
Electrical characteristics
Figure 21: Bode diagram
Figure 20: Recovery behavior after a positive step on
the input
at VCC = 2.7 V
2
50
40
30
20
10
0
300
240
180
120
60
0.04
0
-2
0.00
Gain
T=25°C
-0.04
-0.08
-0.12
-0.16
-0.20
Vcc=±1.35V
Vcc=±8V
T=-40°C
Phase
-4
0
-10
-20
-30
-40
-60
-120
-180
-240
-6
Vcc=2.7V
Vicm=1.35V
Rl=10k
Cl=100pF
Gain=101
Gain=101
Rl=10k
Cl=100pF
Ω
Vin
Ω
-8
T=25°C
T=125°C
-10
-10
1k
10k
100k
1M
10M
0
10
20
30
40
Time (µs)
Frequency(Hz)
Figure 22: Bode diagram
at VCC = 16 V
Figure 23: Power supply rejection ratio (PSRR) vs.
frequency
100
50
40
30
20
10
0
300
240
180
120
60
PSRR+
Gain
80
T=25°C
60
T=-40°C
Phase
0
Vcc=16V
40
Vicm=8V
Gain=10
-10
-20
-30
-40
-60
-120
-180
-240
Vcc=16V
Vicm=8V
Rl=10k
Ω
Rl=10k
Ω
20
0
-
Cl=100pF
Vosc=20mVPP
T=25°C
PSRR
Cl=100pF
Gain=101
T=125°C
1k
10k
100k
1M
10M
10
100
1k
Frequency(Hz)
10k
100k
Frequency(Hz)
Figure 24: Output overshoot vs.
capacitive load
Figure 25: Output impedance vs. frequency in closed
loop configuration
10000
100
75
50
25
0
Vicm=Vcc/2
Gain=1
Vosc=30mVRMS
Vcc=16V
Unstable
Vicm=Vcc/2
Rl=10k
1000
100
10
Ω
T=25°C
Vin=10mVpp
Gain=10
T=25°C
Rf=9.1k
Ω
Vcc=16V
Vcc=2.7V
Rf=91k
Ω
1
0.1
1k
10k
100k
Frequency(Hz)
1M
10M
10
100
Cload (pF)
1000
DocID027196 Rev 1
13/25
Electrical characteristics
Figure 26: THD + N vs. frequency
TSX7192
Figure 27: THD + N vs. output voltage
1
1
Vcc=16V
Vicm=8V
Gain=10
Vout=10Vpp
BW=80kHz
T=25°C
Ω
Rl=2k
0.1
Rl=10k
Ω
0.1
Ω
Rl=2k
Rl=100k
Ω
0.01
1E-3
1E-4
Rl=10k
Rl=100k
Ω
Vcc=16V
Vicm=8V
Gain=10
f=1kHz
BW=22kHz
T=25°C
0.01
1E-3
Ω
0.01
0.1
1
10
100
1000
Frequency(Hz)
10000
Output Voltage (Vpp)
Figure 28: Noise vs. frequency
Figure 29: 0.1 to 10Hz noise
6
4
120
100
80
60
40
20
0
Vcc=16V
Vicm=8V
T=25°C
Vcc=16V
Vicm=Vcc/2
T=25°C
2
0
-2
-4
-6
0
2
4
6
8
10
10
100
1k
10k
Time (s)
Frequency(Hz)
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DocID027196 Rev 1
TSX7192
Application information
4
Application information
4.1
Operating voltages
The TSX7192 device can operate from 2.7 to 16 V. The parameters are fully specified for
4 V, 10 V, and 16 V power supplies. However, the parameters are very stable in the full VCC
range. Additionally, the main specifications are guaranteed in extended temperature ranges
from -40 to +125 °C.
4.2
Input pin voltage ranges
The TSX7192 device has internal ESD diode protection on the inputs. These diodes are
connected between the input and each supply rail to protect the input MOSFETs from
electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become
conductive and excessive current can flow through them. Without limitation this over
current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input
pin, as described in Figure 30.
Figure 30: Input current limitation
9R2
Vcc
R2
R1
Vin
4.3
4.4
Rail-to-rail input
The TSX7192 device has a rail-to-rail input, and the input common mode range is extended
from VCC- - 0.1 V to VCC+ + 0.1 V.
Rail-to-rail output
The operational amplifier output levels can go close to the rails: to a maximum of 40 mV
above and below the rail when connected to a 10 kΩ resistive load to VCC/2.
DocID027196 Rev 1
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Application information
TSX7192
4.5
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset
variation related to the offset value measured at 25 °C. The operational amplifier is one of
the main circuits of the signal conditioning chain, and the amplifier input offset is a major
contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated
during production at application level. The maximum input voltage drift over temperature
enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
∆Vio
∆T
°C
Vio(T) – Vio(25
T – 25 °C
)
= max
Where T = -40 °C and 125 °C.
The TSX7192 datasheet maximum value is guaranteed by measurements on a
representative sample size ensuring a Cpk (process capability index) greater than 1.3.
4.6
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
•
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum
junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2.
Equation 2
AFV = eβ . (V
S – VU
)
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3.
Equation 3
Ea
1
1
.
------
–
AFT = e k
TU TS
Where:
FT is the temperature acceleration factor
A
Ea is the activation energy of the technology based on the failure rate
16/25
DocID027196 Rev 1
TSX7192
Application information
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor (Equation 4).
Equation 4
AF = AFT × AFV
AF is calculated using the temperature and voltage defined in the mission profile of the
product. The AF value can then be used in Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
Equation 5
(
/
Months = AF × 1000 h × 12 months 24 h × 365 25 days)
.
To evaluate the op amp reliability, a follower stress condition is used where VCC is defined
as a function of the maximum operating voltage and the absolute maximum rating
(as recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see Equation 6).
Equation 6
VCC = maxVop with Vicm = VCC
2
/
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of
the calculated number of months (Equation 7).
Equation 7
Viodrift
∆Vio
=
(months)
Where Vio drift is the measured drift value in the specified test conditions after 1000 h
stress duration.
4.7
High values of input differential voltage
In a closed loop configuration, which represents the typical use of an op amp, the input
differential voltage is low (close to Vio). However, some specific conditions can lead to
higher input differential values, such as:
•
•
operation in an output saturation state
operation at speeds higher than the device bandwidth, with output voltage dynamics
limited by slew rate.
•
use of the amplifier in a comparator configuration, hence in open loop
Use of the TSX7191 in comparator configuration, especially combined with high
temperature and long duration can create a permanent drift of Vio.
DocID027196 Rev 1
17/25
Application information
TSX7192
4.8
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load
capacitance produces gain peaking in the frequency response, with overshoot and ringing
in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an
op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive
large capacitive loads.
Figure 31 shows the serial resistor that must be added to the output, to make a system
stable. Figure 32 shows the test configuration using an isolation resistor, Riso.
Figure 31: Stability criteria with a serial resistor at different supply voltages
Figure 32: Test configuration for Riso
100k
Ω
Vcc+
11k
Ω
Riso
Vout
Vin
Cl
Ω
10k
Vcc-
18/25
DocID027196 Rev 1
TSX7192
Application information
4.9
PCB layout recommendations
Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier,
load, and power supply. The power and ground traces are critical as they must provide
adequate energy and grounding for all circuits. The best practice is to use short and wide
PCB traces to minimize voltage drops and parasitic inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique
that connects the bottom and top layer ground planes together in many locations is often
used.
The copper traces that connect the output pins to the load and supply pins should be as
wide as possible to minimize trace resistance.
4.10
Optimized application recommendation
It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A
good decoupling will help to reduce electromagnetic interference impact.
DocID027196 Rev 1
19/25
Package information
TSX7192
5
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
20/25
DocID027196 Rev 1
TSX7192
Package information
5.1
MiniSO8 package information
Figure 33: MiniSO8 package outline
Table 6: MiniSO8 package mechanical data
Dimensions
Ref.
Millimeters
Inches
Min.
Typ.
Max.
1.1
Min.
Typ.
Max.
0.043
0.006
0.037
0.016
0.009
0.126
0.203
0.122
A
A1
A2
b
0
0.15
0.95
0.40
0.23
3.20
5.15
3.10
0
0.75
0.22
0.08
2.80
4.65
2.80
0.85
0.030
0.009
0.003
0.11
0.033
c
D
3.00
4.90
3.00
0.65
0.60
0.95
0.25
0.118
0.193
0.118
0.026
0.024
0.037
0.010
E
0.183
0.11
E1
e
L
0.40
0°
0.80
0.016
0°
0.031
L1
L2
k
8°
8°
ccc
0.10
0.004
DocID027196 Rev 1
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Package information
TSX7192
5.2
SO8 package information
Figure 34: SO8 package outline
Table 7: SO8 package mechanical data
Dimensions
Ref.
Millimeters
Inches
Typ.
Min.
Typ.
Max.
1.75
0.25
Min.
Max.
0.069
0.010
A
A1
A2
b
0.10
1.25
0.28
0.17
4.80
5.80
3.80
0.004
0.049
0.011
0.007
0.189
0.228
0.150
0.48
0.23
5.00
6.20
4.00
0.019
0.010
0.197
0.244
0.157
c
D
4.90
6.00
3.90
1.27
0.193
0.236
0.154
0.050
E
E1
e
h
0.25
0.40
0.50
1.27
0.010
0.016
0.020
0.050
L
L1
k
1.04
0.040
1°
8°
1°
8°
ccc
0.10
0.004
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DocID027196 Rev 1
TSX7192
Ordering information
6
Ordering information
Table 8: Order codes
Order code
Temperature range
Package
Packaging
Marking
TSX7192
K210
TSX7192IDT
SO8
MiniSO8
SO8
-40 to +125 °C
TSX7192IST
Tape and reel
TSX7192IYDT (1)
TSX7192IYST (1)
TSX7192Y
K213
-40 to +125 °C,
automotive grade
MiniSO8
Notes:
(1)Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001
& Q 002 or equivalent are on-going.
DocID027196 Rev 1
23/25
Revision history
TSX7192
7
Revision history
Table 9: Document revision history
Date
Revision Changes
06-Mar-2015
1
Initial release
24/25
DocID027196 Rev 1
TSX7192
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
DocID027196 Rev 1
25/25
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