VND7050AJ_技术文档

VND7050AJ

Double channel high-side driver with MultiSense analog

feedback for automotive applications

Datasheet - production data

−

Loss of ground and loss of V_CC

Reverse battery with external

components

−

Electrostatic discharge protection

Applications

•

All types of Automotive resistive, inductive

and capacitive loads

Features

Max transient supply voltage

Operating voltage range

Typ. on-state resistance (per Ch)

Current limitation (typ)

V_CC

40 V

•

Specially intended for Automotive Signal

Lamps (up to P27W or SAE1156 or LED

Rear Combinations)

V_CC4 to 28 V

R_ON

I_LIMH

50 mΩ

30 A

Description

Standby current (max)

I_STBY0.5 µA

The device is a double channel high-side driver

manufactured using ST proprietary VIPower^®M0-

7 technology and housed in PowerSSO-16

package. The device is designed to drive 12 V

automotive grounded loads through a 3 V and

5 V CMOS-compatible interface, providing

protection and diagnostics.

•

Automotive qualified

General

−

Double channel smart high-side driver

with MultiSense analog feedback

Very low standby current

−

The device integrates advanced protective

functions such as load current limitation, overload

active management by power limitation and

overtemperature shutdown with configurable

latch-off.

Compatible with 3 V and 5 V CMOS

outputs

•

MultiSense diagnostic functions

−

Multiplexed analog feedback of: load

current with high precision proportional

current mirror, V_CCsupply voltage and

T_CHIPdevice temperature

A FaultRST pin unlatches the output in case of

fault or disables the latch-off functionality.

−

Overload and short to ground (power

limitation) indication

A dedicated multifunction multiplexed analog

output pin delivers sophisticated diagnostic

functions including high precision proportional

load current sense, supply voltage feedback and

chip temperature sense, in addition to the

detection of overload and short circuit to ground,

short to V_CCand OFF-state open-load.

−

Thermal shutdown indication

OFF-state open-load detection

Output short to V_CCdetection

Sense enable/disable

•

Protections

−

Undervoltage shutdown

Overvoltage clamp

Load current limitation

Self limiting of fast thermal transients

Configurable latch-off on

A sense enable pin allows OFF-state diagnosis to

be disabled during the module low-power mode

as well as external sense resistor sharing among

similar devices.

overtemperature or power limitation

with dedicated fault reset pin

May 2015

DocID027396 Rev 1

1/46

www.st.com

This is information on a product in full production.

Contents

VND7050AJ

Contents

1

2

Block diagram and pin description................................................5

Electrical specification....................................................................7

2.1

2.2

2.3

2.4

2.5

Absolute maximum ratings................................................................7

Thermal data.....................................................................................8

Main electrical characteristics ...........................................................8

Waveforms......................................................................................19

Electrical characteristics curves ......................................................22

3

4

Protections.....................................................................................26

3.1

3.2

3.3

3.4

Power limitation...............................................................................26

Thermal shutdown...........................................................................26

Current limitation.............................................................................26

Negative voltage clamp...................................................................26

Application information ................................................................27

4.1

GND protection network against reverse battery.............................27

4.1.1

Diode (DGND) in the ground line ..................................................... 28

4.2

4.3

4.4

Immunity against transient electrical disturbances..........................28

MCU I/Os protection........................................................................28

Multisense - analog current sense ..................................................29

4.4.1

4.4.2

4.4.3

Principle of Multisense signal generation......................................... 30

TCASE and VCC monitor................................................................. 32

Short to VCC and OFF-state open-load detection ........................... 33

5

6

Maximum demagnetization energy (VCC = 16 V)........................35

Package and PCB thermal data....................................................36

6.1

PowerSSO-16 thermal data ............................................................36

7

Package information .....................................................................39

7.1

7.2

7.3

PowerSSO-16 package information................................................39

PowerSSO-16 packing information .................................................41

PowerSSO-16 marking information.................................................43

8

9

Order codes ...................................................................................44

Revision history ............................................................................45

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VND7050AJ

List of tables

Table 1: Pin functions .................................................................................................................................5

Table 2: Suggested connections for unused and not connected pins........................................................6

Table 3: Absolute maximum ratings ...........................................................................................................7

Table 4: Thermal data.................................................................................................................................8

Table 5: Power section ...............................................................................................................................8

Table 6: Switching.......................................................................................................................................9

Table 7: Logic inputs.................................................................................................................................10

Table 8: Protections..................................................................................................................................11

Table 9: MultiSense ..................................................................................................................................11

Table 10: Truth table.................................................................................................................................18

Table 11: MultiSense multiplexer addressing...........................................................................................19

Table 12: ISO 7637-2 - electrical transient conduction along supply line.................................................28

Table 13: MultiSense pin levels in off-state ..............................................................................................32

Table 14: PCB properties .........................................................................................................................36

Table 15: Thermal parameters .................................................................................................................38

Table 16: PowerSSO-16 mechanical data................................................................................................39

Table 17: Reel dimensions .......................................................................................................................41

Table 18: PowerSSO-16 carrier tape dimensions ....................................................................................42

Table 19: Device summary.......................................................................................................................44

Table 20: Document revision history ........................................................................................................45

DocID027396 Rev 1

3/46

List of figures

VND7050AJ

List of figures

Figure 1: Block diagram..............................................................................................................................5

Figure 2: Configuration diagram (top view).................................................................................................6

Figure 3: Current and voltage conventions.................................................................................................7

Figure 4: IOUT/ISENSE versus IOUT.......................................................................................................15

Figure 5: Current sense accuracy versus IOUT .......................................................................................16

Figure 6: Switching time and Pulse skew .................................................................................................16

Figure 7: MultiSense timings (current sense mode).................................................................................17

Figure 8: Multisense timings (chip temperature and VCC sense mode)..................................................17

Figure 9: TDSTKON..................................................................................................................................18

Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ......................19

Figure 11: Latch functionality - behavior in hard short circuit condition....................................................20

Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off)....20

Figure 13: Standby mode activation .........................................................................................................21

Figure 14: Standby state diagram.............................................................................................................21

Figure 15: OFF-state output current .........................................................................................................22

Figure 16: Standby current .......................................................................................................................22

Figure 17: IGND(ON) vs. Iout ...................................................................................................................22

Figure 18: Logic Input high level voltage ..................................................................................................22

Figure 19: Logic Input low level voltage....................................................................................................22

Figure 20: High level logic input current ...................................................................................................22

Figure 21: Low level logic input current ....................................................................................................23

Figure 22: Logic Input hysteresis voltage .................................................................................................23

Figure 23: FaultRST Input clamp voltage .................................................................................................23

Figure 24: Undervoltage shutdown...........................................................................................................23

Figure 25: On-state resistance vs. Tcase.................................................................................................23

Figure 26: On-state resistance vs. VCC ...................................................................................................23

Figure 27: Turn-on voltage slope..............................................................................................................24

Figure 28: Turn-off voltage slope..............................................................................................................24

Figure 29: Won vs. Tcase.........................................................................................................................24

Figure 30: Woff vs. Tcase.........................................................................................................................24

Figure 31: ILIMH vs. Tcase.......................................................................................................................24

Figure 32: OFF-state open-load voltage detection threshold ...................................................................24

Figure 33: Vsense clamp vs. Tcase..........................................................................................................25

Figure 34: Vsenseh vs. Tcase ..................................................................................................................25

Figure 35: Application diagram.................................................................................................................27

Figure 36: Simplified internal structure .....................................................................................................27

Figure 37: MultiSense and diagnostic – block diagram............................................................................29

Figure 38: MultiSense block diagram .......................................................................................................30

Figure 39: Analogue HSD – open-load detection in off-state ...................................................................31

Figure 40: Open-load / short to VCC condition.........................................................................................32

Figure 41: GND voltage shift ....................................................................................................................33

Figure 42: Maximum turn off current versus inductance ..........................................................................35

Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)............................................36

Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ...........................................36

Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on).....................37

Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ..............37

Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16..........................................38

Figure 48: PowerSSO-16 package outline ...............................................................................................39

Figure 49: PowerSSO-16 reel 13" ............................................................................................................41

Figure 50: PowerSSO-16 carrier tape ......................................................................................................42

Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape ..................................................42

Figure 52: PowerSSO-16 marking information.........................................................................................43

4/46

DocID027396 Rev 1

VND7050AJ

Block diagram and pin description

1

Block diagram and pin description

Figure 1: Block diagram

Table 1: Pin functions

Function

Name

V_CC

Battery connection.

OUTPUT_0,1Power output.

Ground connection. Must be reverse battery protected by an external diode / resistor

network.

GND

INPUT_0,1

MultiSense

SEn

Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs.

It controls output switch state.

Multiplexed analog sense output pin; it delivers a current proportional to the selected

diagnostic: load current, supply voltage or chip temperature.

Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense

diagnostic pin.

Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense

multiplexer.

SEL_0,1

Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in

case of fault; If kept low, sets the outputs in auto-restart. mode

FaultRST

DocID027396 Rev 1

5/46

Block diagram and pin description

VND7050AJ

Figure 2: Configuration diagram (top view)

Table 2: Suggested connections for unused and not connected pins

SEn, SELx,

Connection /

MultiSense

N.C. Output

Input

FaultRST

Floating

Not allowed

X ⁽¹⁾

X

Through 1 kΩ

Not

allowed

Through 15 kΩ

To ground

resistor

Notes:

⁽¹⁾X: do not care.

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DocID027396 Rev 1

VND7050AJ

Electrical specification

2

Electrical specification

Figure 3: Current and voltage conventions

I_S

V_CC

V_Fn

I_FR

I_OUT

FaultRST

SE_n

OUTPUT_0,1

MultiSense

I_SEn

V_OUT

I_SENSE

I_SEL

SEL_0,1

V_SENSE

I_IN

INPUT_0,1

I_GND

GAPGCFT00315

V_Fn= V_OUTn- V_CCduring reverse battery condition.

2.1

Absolute maximum ratings

Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to the conditions in table below for extended

periods may affect device reliability.

Table 3: Absolute maximum ratings

Symbol

V_CCDC supply voltage

-V_CCReverse DC supply voltage

Parameter

Value

38

Unit

V

0.3

Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped

to 40V; R_L= 4 Ω)

V_CCPK

40

V

V_CCJSMaximum jump start voltage for single pulse short circuit protection

-I_GNDDC reverse ground pin current

28

V

200

mA

Internally

limited

I_OUTOUTPUT_0,1DC output current

A

-I_OUTReverse DC output current

11

-1 to 10

7.5

I_IN

INPUT_0,1DC input current

SEn DC input current

I_SEn

I_SEL

I_FR

mA

SEL_0,1DC input current

FaultRST DC input current

FaultRST DC input voltage

V_FR

V

DocID027396 Rev 1

7/46

Electrical specification

VND7050AJ

Symbol

Parameter

Value

Unit

MultiSense pin DC output current (V_GND= V_CCand V_SENSE< 0 V)

MultiSense pin DC output current in reverse (V_CC< 0 V)

Maximum switching energy (single pulse) (T_DEMAG= 0.4 ms;

10

I_SENSE

mA

-20

E_MAX

30

mJ

T

_jstart= 150 °C)

Electrostatic discharge (JEDEC 22A-114F)

4000

2000

4000

V

•

INPUT_0,1

MultiSense

SEn, SEL_0,1, FaultRST

OUTPUT_0,1

V_CC

V_ESD

V_ESDCharge device model (CDM-AEC-Q100-011)

750

V

T_j

Junction operating temperature

Storage temperature

-40 to 150

-55 to 150

°C

T_stg

2.2

Thermal data

Table 4: Thermal data

Parameter

Symbol

Typ. value Unit

R_thj-boardThermal resistance junction-board (JEDEC JESD 51-5 / 51-8) ⁽¹⁾⁽²⁾

R_thj-ambThermal resistance junction-ambient (JEDEC JESD 51-5)⁽¹⁾⁽³⁾

R_thj-ambThermal resistance junction-ambient (JEDEC JESD 51-7)⁽¹⁾⁽²⁾

6.4

59

25

°C/W

Notes:

⁽¹⁾One channel ON.

⁽²⁾Device mounted on four-layers 2s2p PCB

⁽³⁾Device mounted on two-layers 2s0p PCB with 2 cm²heatsink copper trace

2.3

Main electrical characteristics

7 V < V_CC< 28 V; -40°C < T_j< 150°C, unless otherwise specified.

All typical values refer to V_CC= 13 V; T_j= 25°C, unless otherwise specified.

Table 5: Power section

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

Operating supply

voltage

V_CC

4

13 28

V

V_USDUndervoltage shutdown

4

5

Undervoltage shutdown

V_USDReset

reset

Undervoltage shutdown

hysteresis

V_USDhyst

0.3

50

V

I

_OUT= 2 A; T_j= 25°C

On-state resistance ⁽¹⁾I_OUT= 2 A; T_j= 150°C

I_OUT= 2 A; V_CC= 4 V; T_j= 25°C

R_ON

100 mΩ

75

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VND7050AJ

Electrical specification

Symbol

Parameter

Test conditions

I_S= 20 mA; 25°C < T_j< 150°C

I_S= 20 mA; T_j= -40°C

Min. Typ. Max. Unit

41 46 52

38

V

V_clampClamp voltage

V_CC= 13 V; V_IN= V_OUT= V_FR= V_SEn= 0 V;

0.5

V_SEL0,1= 0 V; T_j= 25°C

Supply current in

V_CC= 13 V; V_IN= V_OUT= V_FR= V_SEn= 0 V;

V_SEL0,1= 0 V; T_j= 85°C

I_STBYstandby at V_CC= 13 V

0.5 µA

3

(3)

(2)

V_CC= 13 V; V_IN= V_OUT= V_FR= V_SEn= 0 V;

V_SEL0,1= 0 V; T_j= 125°C

V_CC= 13 V;

Standby mode blanking

t_{D_STBY}

time

V_IN= V_OUT= V_FR= V_SEL0,1= 0 V; V_SEn= 5 V 60 300 550 µs

to 0 V

V_CC= 13 V; V_SEn= V_FR= V_SEL0,1= 0 V;

V

_IN0= 5 V; V_IN1= 5 V;

I_S(ON)Supply current

Control stage current

5

8

mA

I

_OUT0= 0 A; I_OUT1= 0 A

V_CC= 13 V; V_SEn= 5 V; V_FR= V_SEL0,1= 0 V;

_IN0= 5 V; V_IN1= 5 V; I_OUT0= 2 A;

consumption in ON

state. All channels

I_GND(ON)

V

12 mA

I_OUT1= 2 A

active.

V_IN= V_OUT= 0 V; V_CC= 13 V; T_j= 25°C

V_IN= V_OUT= 0 V; V_CC= 13 V; T_j= 125°C

0

0.01 0.5

3

Off-state output current

I_L(off)

µA

V

at V_CC= 13 V ⁽²⁾

Output - V_CCdiode

V_F

I

_OUT= -2 A; T_j= 150°C

0.7

voltage ⁽²⁾

Notes:

⁽¹⁾For each channel

⁽²⁾PowerMOS leakage included.

⁽³⁾Parameter specified by design; not subject to production test.

Table 6: Switching

V_CC= 13 V; -40°C < T_j< 150°C, unless otherwise specified

Symbol

Parameter

Test conditions Min. Typ. Max. Unit

(1)

t_d(on)

Turn-on delay time at T_j= 25 °C

Turn-off delay time at T_j= 25 °C

10

60

40

120

100

0.7

R_L= 6.5 Ω

µs

(1)

t_d(off)

(1)

(dV_OUT/dt)_onTurn-on voltage slope at T_j= 25 °C

0.1 0.3

V/µs

(1)

(dV_OUT/dt)_offTurn-off voltage slope at T_j= 25 °C

0.1 0.32 0.7

W_ON

Switching energy losses at turn-on (t_won

Switching energy losses at turn-off (t_woff

)

R_L= 6.5 Ω

—

0.25 0.33⁽²⁾mJ

0.23 0.31 ⁽²⁾mJ

W_OFF

(1)

t_SKEW

Differential Pulse skew (t_PHL- t_PLH

)

-80 -30

20

µs

Notes:

⁽¹⁾See Figure 6: "Switching time and Pulse skew".

⁽²⁾Parameter guaranteed by design and characterization; not subject to production test.

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Electrical specification

VND7050AJ

Table 7: Logic inputs

7 V < V_CC< 28 V; -40°C < T_j< 150°C

Symbol Parameter

INPUT_0,1characteristics

Test conditions

Min. Typ. Max. Unit

V_IL

I_IL

Input low level voltage

0.9

V

µA

V

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V_IN= 0.9 V

V_IN= 2.1 V

1

V_IH

2.1

I_IH

10

µA

V

V_I(hyst)

0.2

5.3

I

_IN= 1 mA

7.2

V_ICL

Input clamp voltage

V

I_IN= -1 mA

-0.7

FaultRST characteristics

V_FRL

I_FRL

V_FRH

I_FRH

Input low level voltage

0.9

V

µA

V

Low level input current

Input high level voltage

High level input current

V_IN= 0.9 V

V_IN= 2.1 V

1

2.1

10

µA

V

V_FR(hyst)Input hysteresis voltage

V_FRCLInput clamp voltage

SEL_0,1characteristics (7 V < V_CC< 18 V)

0.2

5.3

I

_IN= 1 mA

7.5

V

I_IN= -1 mA

-0.7

V_SELL

I_SELL

V_SELH

I_SELH

Input low level voltage

Low level input current

Input high level voltage

High level input current

0.9

V

µA

V

V_IN= 0.9 V

V_IN= 2.1 V

1

2.1

10

µA

V

V_SEL(hyst)Input hysteresis voltage

V_SELCLInput clamp voltage

SEn characteristics (7 V < V_CC< 18 V)

0.2

5.3

I

_IN= 1 mA

7.2

V

I_IN= -1 mA

V_SEnL

I_SEnL

V_SEnH

I_SEnH

Input low level voltage

Low level input current

Input high level voltage

High level input current

0.9

V

µA

V

V_IN= 0.9 V

V_IN= 2.1 V

1

2.1

10

µA

V

V_SEn(hyst)Input hysteresis voltage

0.2

5.3

I

_IN= 1 mA

7.2

V_SEnCLInput clamp voltage

V

I_IN= -1 mA

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DocID027396 Rev 1

VND7050AJ

Electrical specification

Table 8: Protections

7 V < V_CC< 18 V; -40°C < T_j< 150°C

Symbol

Parameter

Test conditions

Min.

Typ.

Max. Unit

V

_CC= 13 V

21

30

I_LIMH

DC short circuit current

42

4 V < V_CC< 18 V ⁽¹⁾

A

V_CC= 13 V;

Short circuit current

during thermal cycling

I_LIML

10

T_R< T_j< T_TSD

T_TSD

T_R

Shutdown temperature

Reset temperature⁽¹⁾

150

175

200

T_RS+ 1 T_RS+ 7

Thermal reset of fault

diagnostic indication

°C

T_RS

V_FR= 0 V; V_SEn= 5 V

135

Thermal hysteresis

(T_TSD- T_R)⁽¹⁾

T_HYST

7

ΔT_{J_SD}Dynamic temperature

T_j= -40°C; V_CC= 13 V

60

K

V_FR= 5 V to 0 V; V_SEn= 5 V;

Fault reset time for

t_{LATCH_RST}

V_IN= 5 V; V_SEL0= 0 V;

3

10

20

µs

output unlatch ⁽¹⁾

V_SEL1= 0 V

I_OUT= 2 A; L = 6 mH;

T_j= -40°C

V_CC- 38

V

Turn-off output voltage

V_DEMAG

clamp

I_OUT= 2 A; L = 6 mH;

T_j= 25°C to 150°C

V_CC- 41 V_CC- 46 V_CC- 52

20

Output voltage drop

limitation

V_ON

I_OUT= 0.2 A

mV

Notes:

⁽¹⁾Parameter guaranteed by design and characterization; not subject to production test.

Table 9: MultiSense

7 V < V_CC< 18 V; -40°C < T_j< 150°C

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

V_SEn= 0 V; I_SENSE= 1 mA

-17

-12

MultiSense clamp

voltage

V_{SENSE_CL}

V

V_SEn= 0 V; I_SENSE= -1 mA

7

Current sense characteristics

I_OUT= 0.01 A; V_SENSE= 0.5 V;

K_OL

dK_cal/K_cal

K_LED

I_OUT/I_SENSE

440

-30

V_SEn= 5 V

I_OUT= 0.01 A to 0.05 A;

I_cal= 30 mA; V_SENSE= 0.5 V;

Current sense ratio drift

at calibration point

(1)(2)

30

%

V

_SEn= 5 V

I_OUT= 0.05 A; V_SENSE= 0.5 V;

_SEn= 5 V

I_OUT= 0.05 A; V_SENSE= 0.5 V;

_SEn= 5 V

I_OUT/I_SENSE

530 1450 2200

-25 25

V

(1)(2)

dK_LED/K_LED

Current sense ratio drift

%

V

DocID027396 Rev 1

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Electrical specification

7 V < V_CC< 18 V; -40°C < T_j< 150°C

VND7050AJ

Symbol

Parameter

I_OUT/I_SENSE

Test conditions

Min. Typ. Max. Unit

I_OUT= 0.2 A; V_SENSE= 0.5 V;

V_SEn= 5 V

K₀

830 1400 1935

I

_OUT= 0.2 A; V_SENSE= 0.5 V;

(1)(2)

dK₀/K₀

K₁

Current sense ratio drift

I_OUT/I_SENSE

-20

20

%

V_SEn= 5 V

I_OUT= 0.4 A; V_SENSE= 4 V;

V_SEn= 5 V

915 1300 1700

I

_OUT= 0.4 A; V_SENSE= 4 V;

(1)(2)

dK₁/K₁

K₂

Current sense ratio drift

I_OUT/I_SENSE

-15

15

V_SEn= 5 V

I_OUT= 1.5 A; V_SENSE= 4 V;

V_SEn= 5 V

980 1230 1470

I

_OUT= 1.5 A; V_SENSE= 4 V;

(1)(2)

dK₂/K₂

K₃

Current sense ratio drift

I_OUT/I_SENSE

-10

10

V_SEn= 5 V

I_OUT= 4.5 A; V_SENSE= 4 V;

V_SEn= 5 V

1095 1215 1335

I

V

_OUT= 4.5 A; V_SENSE= 4 V;

_SEn= 5 V

dK₃/K₃

Current sense ratio drift

-5

0

5

MultiSense disabled:

V_SEn= 0 V

0.5

MultiSense disabled:

-1 V < V_SENSE< 5 V⁽¹⁾

-0.5

MultiSense enabled:

V_SEn= 5 V; All channels ON;

I_OUTX= 0 A; Ch_Xdiagnostic

selected;

0

2

•

E.g. Ch₀:

_IN0= 5 V; V_IN1= 5 V;

MultiSense leakage

current

I_SENSE0

µA

V

V_SEL0= 0 V; V_SEL1= 0 V;

I_OUT0= 0 A; I_OUT1= 2 A

MultiSense enabled:

V_SEn= 5 V; Ch_Xchannel OFF;

Ch_Xdiagnostic selected:

•

E.g. Ch₀:

_IN0= 0 V; V_IN1= 5 V;

V

V_SEL0= 0 V; V_SEL1= 0 V;

I_OUT1= 2 A

V

_SEn= 5 V; R_SENSE= 2.7 kΩ;

Output Voltage for

MultiSense shutdown

•

E.g. Ch₀:

V_IN0= 5 V; V_SEL0= 0 V;

(1)

V_{OUT_MSD}

5

V

_SEL1= 0 V; I_OUT0= 2 A

V

_CC= 7 V; R_SENSE= 2.7 kΩ;

_SEn= 5 V; V_IN0= 5 V;

Multisense saturation

voltage

V_{SENSE_SAT}

5

4

V_SEL0= 0 V; V_SEL1= 0 V;

I_OUT0= 4.5 A; T_j= 150°C

V

_CC= 7 V; V_SENSE= 4 V;

_IN0= 5 V; V_SEn= 5 V;

(1)

I_{SENSE_SAT}

CS saturation current

mA

V_SEL0= 0 V; V_SEL1= 0 V;

T_j= 150°C

12/46

DocID027396 Rev 1

VND7050AJ

Electrical specification

7 V < V_CC< 18 V; -40°C < T_j< 150°C

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

V

_CC= 7 V; V_SENSE= 4 V;

_IN0= 5 V; V_SEn= 5 V;

(1)

I_{OUT_SAT}

Output saturation current

6

A

V

V_SEL0= 0 V; V_SEL1= 0 V;

T_j= 150°C

OFF-state diagnostic

V_SEn= 5 V; Ch_XOFF;

OFF-state open-load

voltage detection

threshold

Ch_Xdiagnostic selected

V_OL

2

3

4

•

E.g: Ch₀

V_IN0= 0 V; V_SEL0= 0 V;

V

_SEL1= 0 V

OFF-state output sink

current

I_L(off2)

V_IN= 0 V; V_OUT= V_OL

-100

-15 µA

V

_SEn= 5 V; Ch_XON to OFF

transition;

OFF-state diagnostic

delay time from falling

edge of INPUT (see

Figure 9: "TDSTKON")

Ch_Xdiagnostic selected

t_DSTKON

100 350 700 µs

•

E.g: Ch₀

_IN0= 5 V to 0 V;

V

V_SEL0= 0 V; V_SEL1= 0 V;

I_OUT0= 0 A; V_OUT= 4 V

Settling time for valid

OFF-state open load

diagnostic indication from V_SEL1= 0 V; V_OUT0= 4 V;

V_IN0= 0 V; V_IN1= 0 V;

V_FR= 0 V; V_SEL0= 0 V;

t_{D_OL_V}

60

30

µs

rising edge of SEn

V_SEn= 0 V to 5 V

_SEn= 5 V; Ch_XOFF;

Ch_Xdiagnostic selected

E.g: Ch₀

_IN0= 0 V; V_SEL0= 0 V;

V

OFF-state diagnostic

delay time from rising

edge of V_OUT

•

t_{D_VOL}

5

V

V_SEL1= 0 V;

V_OUT= 0 V to 4 V

Chip temperature analog feedback

V_SEn= 5 V; V_SEL0= 0 V;

_SEL1= 5 V; V_IN0,1= 0 V;

R_SENSE= 1 kΩ; T_j= -40°C

V

2.325 2.41 2.495

1.985 2.07 2.155

V

MultiSense output

voltage proportional to

chip temperature

V_SEn= 5 V; V_SEL0= 0 V;

V_SEL1= 5 V; V_IN0,1= 0 V;

R_SENSE= 1 kΩ; T_j= 25°C

V_{SENSE_TC}

V_SEn= 5 V; V_SEL0= 0 V;

V_SEL1= 5 V; V_IN0,1= 0 V;

1.435 1.52 1.605

-5.5

R_SENSE= 1 kΩ; T_j= 125°C

mV/

K

dV_{SENSE_TC}/dT Temperature coefficient T_j= -40°C to 150°C

Transfer function

V_{SENSE_TC}(T) = V_{SENSE_TC}(T₀) + dV_{SENSE_TC}/ dT * (T - T₀)

V_CCsupply voltage analog feedback

V_CC= 13 V; V_SEn= 5 V;

MultiSense output

V_SEL0= 5 V; V_SEL1= 5 V;

V_{SENSE_VCC}

voltage proportional to

V_CCsupply voltage

3.16 3.23 3.3

V

V_IN0,1= 0 V; R_SENSE= 1 kΩ

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13/46

Electrical specification

7 V < V_CC< 18 V; -40°C < T_j< 150°C

VND7050AJ

Symbol

Parameter

Test conditions

V_{SENSE_VCC}= V_CC/ 4

Min. Typ. Max. Unit

Transfer function ⁽³⁾

Fault diagnostic feedback (see Table 10: "Truth table")

V_CC= 13 V; R_SENSE= 1 kΩ;

•

E.g: Ch₀in open load

V_IN0= 0 V; V_SEn= 5 V;

MultiSense output

voltage in fault condition

V_SENSEH

5

7

6.6

30

V

V_SEL0= 0 V; V_SEL1= 0 V;

I_OUT0= 0 A; V_OUT= 4 V

MultiSense output

current in fault condition

I_SENSEH

V

_CC= 13 V; V_SENSE= 5 V

20

mA

MultiSense timings (current sense mode - see Figure 7: "MultiSense timings (current sense

mode)")⁽⁴⁾

Current sense settling

time from rising edge of

SEn

V

R

_IN= 5 V; V_SEn= 0 V to 5 V;

_SENSE= 1 kΩ; R_L= 6.5 Ω

t_DSENSE1H

t_DSENSE1L

t_DSENSE2H

60

20

µs

Current sense disable

delay time from falling

edge of SEn

V

_IN= 5 V; V_SEn= 5 V to 0 V;

5

R_SENSE= 1 kΩ; R_L= 6.5 Ω

Current sense settling

time from rising edge of

INPUT

V

R

_IN= 0 V to 5 V; V_SEn= 5 V;

_SENSE= 1 kΩ; R_L= 6.5 Ω

100 250 µs

Current sense settling

time from rising edge of

I_OUT(dynamic response

to a step change of I_OUT

V_IN= 5 V; V_SEn= 5 V;

R_SENSE= 1 kΩ; I_SENSE= 90 % of

Δt_DSENSE2H

100 µs

I

_SENSEMAX; R_L= 6.5 Ω

)

Current sense turn-off

delay time from falling

edge of INPUT

V_IN= 5 V to 0 V; V_SEn= 5 V;

R_SENSE= 1 kΩ; R_L= 6.5 Ω

t_DSENSE2L

50

250 µs

MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip

temperature and VCC sense mode)")⁽⁴⁾

V_{SENSE_TC}settling time

from rising edge of SEn

V_SEn= 0 V to 5 V; V_SEL0= 0 V;

t_DSENSE3H

60

20

µs

V_SEL1= 5 V; R_SENSE= 1 kΩ

V_{SENSE_TC}disable delay

V

_SEn= 5 V to 0 V; V_SEL0= 0 V;

t_DSENSE3L

time from falling edge of

SEn

V_SEL1= 5 V; R_SENSE= 1 kΩ

MultiSense timings (V_CCvoltage sense mode - see Figure 8: "Multisense timings (chip

temperature and VCC sense mode)")⁽⁴⁾

V_{SENSE_VCC}settling time

from rising edge of SEn V_SEL1= 5 V; R_SENSE= 1 kΩ

V_SEn= 0 V to 5 V; V_SEL0= 5 V;

t_DSENSE4H

60

20

µs

V_{SENSE_VCC}disable delay

V_SEn= 5 V to 0 V; V_SEL0= 5 V;

t_DSENSE4L

time from falling edge of

SEn

V_SEL1= 5 V; R_SENSE= 1 kΩ

MultiSense timings (Multiplexer transition times)⁽⁴⁾

V_IN0= 5 V; V_IN1= 5 V;

MultiSense transition

delay from Ch_Xto Ch_Y

V

_SEn= 5 V; V_SEL1= 0 V;

V_SEL0= 0 V to 5 V; I_OUT0= 0 A;

_OUT1= 3 A; R_SENSE= 1 kΩ

t_{D_XtoY}

20

µs

I

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VND7050AJ

Electrical specification

7 V < V_CC< 18 V; -40°C < T_j< 150°C

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

MultiSense transition

V_IN0= 5 V; V_SEn= 5 V;

t_{D_CStoTC}

delay from current sense V_SEL0= 0 V; V_SEL1= 0 V to 5 V;

60

20

60

20

µs

to T_Csense

I_OUT0= 1.5 A; R_SENSE= 1 kΩ

MultiSense transition

delay from T_Csense to

current sense

V_IN0= 5 V; V_SEn= 5 V;

t_{D_TCtoCS}

t_{D_CStoVCC}

t_{D_VCCtoCS}

t_{D_TCtoVCC}

t_{D_VCCtoTC}

V_SEL0= 0 V; V_SEL1= 5 V to 0 V;

I_OUT0= 1.5 A; R_SENSE= 1 kΩ

MultiSense transition

V_IN1= 5 V; V_SEn= 5 V;

delay from current sense V_SEL0= 5 V; V_SEL1= 0 V to 5 V;

to V_CCsense

I_OUT1= 1.5A; R_SENSE= 1 kΩ

MultiSense transition

delay from V_CCsense to

current sense

V_IN1= 5 V; V_SEn= 5 V;

V_SEL0= 5 V; V_SEL1= 5 V to 0 V;

I_OUT1= 1.5 A; R_SENSE= 1 kΩ

MultiSense transition

delay from T_Csense to

V_CCsense

V

_CC= 13 V; T_j= 125°C;

V_SEn= 5 V; V_SEL0= 0 V to 5 V;

V_SEL1= 5 V; R_SENSE= 1 kΩ

MultiSense transition

delay from V_CCsense to

T_Csense

V_CC= 13 V; T_j= 125°C;

V_SEn= 5 V; V_SEL0= 5 V to 0 V;

V_SEL1= 5 V; R_SENSE= 1 kΩ

MultiSense transition

V_IN0= 5 V; V_IN1= 0 V;

delay from stable current V_SEn= 5 V; V_SEL1= 0 V;

sense on Ch_Xto V_SENSEHV_SEL0= 0 V to 5 V; I_OUT0= 3 A;

t_{D_CStoVSENSEH}

20

µs

on Ch_Y

V_OUT1= 4 V; R_SENSE= 1 kΩ

Notes:

⁽¹⁾Parameter guaranteed by design and characterization; not subject to production test.

⁽²⁾All values refer to V_CC= 13 V; T_j= 25°C, unless otherwise specified.

(3)

V

sensing and T_Csensing are referred to GND potential.

CC

⁽⁴⁾Transition delay are measured up to +/- 10% of final conditions.

Figure 4: IOUT/ISENSE versus IOUT

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15/46

Electrical specification

VND7050AJ

Figure 5: Current sense accuracy versus IOUT

Figure 6: Switching time and Pulse skew

twon

twoff

VOUT

Vcc

80% Vcc

20% Vcc

ON

OFF

dV_OUT/dt

t

INPUT

td(off)

td(on)

tpLH

tpHL

t

GAPG2609141134CFT

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VND7050AJ

Electrical specification

Figure 7: MultiSense timings (current sense mode)

IN1

High

SEn

Low

High

SEL0

Low

High

SEL1

I_OUT1

Low

CURRENT SENSE

t_DSENSE2H

t_DSENSE1L

t_DSENSE1Ht_DSENSE2L

GAPGCFT00318

Figure 8: Multisense timings (chip temperature and VCC sense mode)

High

SEn

Low

High

SEL0

Low

High

SEL1

V_CC

Low

V_SENSE= V_{SENSE_VCC}

V_SENSE= V_{SENSE_TC}

SENSE

t_DSENSE4H

t_DSENSE4L

t_DSENSE3H

t_DSENSE3L

VCC VOLTAGE SENSE MODE

CHIP TEMPERATURE SENSE MODE

GAPGCFT00319

DocID027396 Rev 1

17/46

Electrical specification

VND7050AJ

Figure 9: TDSTKON

V_{INPU T}

V_{OU T}

V_{OU T}> V_OL

MultiSense

T_DSTKON

GAPG2609141140CFT

Table 10: Truth table

Mode

Conditions

IN_XFR SEn SEL_XOUT_XMultiSense

Comments

Low quiescent current

consumption

Standby

All logic inputs low

L

X

L

Hi-Z

See ⁽¹⁾

Nominal load

connected;

Outputs configured for

auto-restart

H

Normal

See ⁽¹⁾

T_j< 150 °C

Outputs configured for

Latch-off

H

L

H

X

H

L

See ⁽¹⁾

Overload or short

to GND causing:

Output cycles with

temperature

Overload

H

X

L

H

X

See ⁽¹⁾

H

L

See ⁽¹⁾

T_j> T_TSDor

hysteresis

ΔT_j> ΔT_{j_SD}

Output latches-off

Re-start when

L

Hi-Z

V_CC> V_USD

+

Undervoltage

V_CC< V_USD(falling)

X

V_USDhyst(rising)

Short to V_CC

Open-load

L

X

H

See ⁽¹⁾

OFF-state

diagnostics

See ⁽¹⁾

External pull-up

Negative output Inductive loads

L

X

< 0 V

See ⁽¹⁾

voltage

turn-off

Notes:

⁽¹⁾Refer to Table 11: "MultiSense multiplexer addressing"

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Electrical specification

Table 11: MultiSense multiplexer addressing

MultiSense output

OFF-state

diag. ⁽¹⁾

SEn SEL₁SEL₀MUX channel

Negative

output

Normal mode

Overload

L

X

L

X

L

Hi-Z

Channel 0

diagnostic

I_SENSE

1/K * I_OUT0

=

V_SENSE

V_SENSEH

=

V_SENSE

V_SENSEH

=

H

Hi-Z

Channel 1

diagnostic

I_SENSE

1/K * I_OUT1

=

V_SENSE

V_SENSEH

=

V_SENSE

V_SENSEH

=

H

L

H

L

T_CHIPSense

V_CCSense

V_SENSE= V_{SENSE_TC}

V_SENSE= V_{SENSE_VCC}

H

Notes:

⁽¹⁾In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is

low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN₀= 0; OUT₀= L

(latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN₀= 0; OUT₀= latched,

V_OUT0> V_OL; MUX channel = channel 0 diagnostic; Mutisense = V_SENSEH

2.4

Waveforms

Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)

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Electrical specification

VND7050AJ

Figure 11: Latch functionality - behavior in hard short circuit condition

Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode +

latch off)

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Electrical specification

Figure 13: Standby mode activation

Figure 14: Standby state diagram

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Electrical specification

VND7050AJ

2.5

Electrical characteristics curves

Figure 15: OFF-state output current

Figure 16: Standby current

Figure 17: IGND(ON) vs. Iout

Figure 18: Logic Input high level voltage

Figure 19: Logic Input low level voltage

Figure 20: High level logic input current

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Electrical specification

Figure 21: Low level logic input current

Figure 22: Logic Input hysteresis voltage

Figure 23: FaultRST Input clamp voltage

Figure 24: Undervoltage shutdown

VFRCL [V]

8

7

Iin = 1mA

6

5

4

3

2

1

Iin = -1mA

0

-1

-50

-25

0

25

50

75

100

125

150

175

T [°C]

GAPG2110131613CFT

Figure 25: On-state resistance vs. Tcase

Figure 26: On-state resistance vs. VCC

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Electrical specification

Figure 27: Turn-on voltage slope

VND7050AJ

Figure 28: Turn-off voltage slope

Figure 29: Won vs. Tcase

Figure 30: Woff vs. Tcase

Figure 32: OFF-state open-load voltage

detection threshold

Figure 31: ILIMH vs. Tcase

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Electrical specification

Figure 34: Vsenseh vs. Tcase

Figure 33: Vsense clamp vs. Tcase

VSENSEH [V]

10

9

8

7

6

5

4

3

2

1

0

-50

-25

0

25

50

75

100

125

150

175

T [°C]

GAPG1905151315CFT

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Protections

VND7050AJ

3

Protections

3.1

Power limitation

The basic working principle of this protection consists of an indirect measurement of the

junction temperature swing ΔT_jthrough the direct measurement of the spatial temperature

gradient on the device surface in order to automatically shut off the output MOSFET as

soon as ΔT_jexceeds the safety level of ΔT_{j_SD}. According to the voltage level on the

FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis

according to the maximum instantaneous power which can be handled (FaultRST = Low)

or remains off (FaultRST = High). The protection prevents fast thermal transient effects

and, consequently, reduces thermo-mechanical fatigue.

3.2

3.3

Thermal shutdown

In case the junction temperature of the device exceeds the maximum allowed threshold

(typically 175°C), it automatically switches off and the diagnostic indication is triggered.

According to the voltage level on the FaultRST pin, the device switches on again as soon

as its junction temperature drops to T_R(FaultRST = Low) or remains off (FaultRST = High).

Current limitation

The device is equipped with an output current limiter in order to protect the silicon as well

as the other components of the system (e.g. bonding wires, wiring harness, connectors,

loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or

during load power-up, the output current is clamped to a safety level, I_LIMH, by operating the

output power MOSFET in the active region.

3.4

Negative voltage clamp

In case the device drives inductive load, the output voltage reaches a negative value during

turn off. A negative voltage clamp structure limits the maximum negative voltage to a

certain value, V_DEMAG, allowing the inductor energy to be dissipated without damaging the

device.

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Application information

4

Application information

Figure 35: Application diagram

4.1

GND protection network against reverse battery

Figure 36: Simplified internal structure

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Application information

VND7050AJ

4.1.1

Diode (DGND) in the ground line

A resistor (typ. R_GND= 4.7 kΩ) should be inserted in parallel to D_GNDif the device drives an

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this

case, the presence of the ground network produces a shift (≈600 mV) in the input threshold

and in the status output values if the microprocessor ground is not common to the device

ground. This shift does not vary if more than one HSD shares the same diode/resistor

network.

4.2

Immunity against transient electrical disturbances

The immunity of the device against transient electrical emissions, conducted along the

supply lines and injected into the V_CCpin, is tested in accordance with ISO7637-2:2011 (E)

and ISO 16750-2:2010.

The related function performance status classification is shown in Table 12: "ISO 7637-2 -

electrical transient conduction along supply line".

Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and

in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present

device only, without components and accessed through V_CCand GND terminals.

Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as

follows: “The function does not perform as designed during the test but returns

automatically to normal operation after the test”.

Table 12: ISO 7637-2 - electrical transient conduction along supply line

Test pulse severity

Test

Pulse

Minimum

number of

pulses or test

time

level with Status II

functional performance

status

Burst cycle / pulse

repetition time

Pulse duration and

pulse generator

internal impedance

2011(E)

(1)

Level

III

U_S

min

0,5 s

max

1

-112V

+55V

-220V

+150V

-7V

500 pulses

1h

2ms, 10Ω

50µs, 2Ω

2a

3a

3b

4 ⁽²⁾

III

0,2 s

5 s

IV

90 ms

100 ms

0.1µs, 50Ω

100ms, 0.01Ω

IV

1h

IV

1 pulse

Load dump according to ISO 16750-2:2010

Test B ⁽³⁾

40V

5 pulse

1 min

400ms, 2Ω

Notes:

⁽¹⁾U_Sis the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.

⁽²⁾Test pulse from ISO 7637-2:2004(E).

⁽³⁾With 40 V external suppressor referred to ground (-40°C < T_j< 150°C).

4.3

MCU I/Os protection

If a ground protection network is used and negative transients are present on the V_CCline,

the control pins will be pulled negative. ST suggests to insert a resistor (R_prot) in line both to

prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.

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Application information

The value of these resistors is a compromise between the leakage current of

microcontroller and the current required by the HSD I/Os (Input levels compatibility) with

the latch-up limit of microcontroller I/Os.

Equation

V_CCpeak/I_latchup≤ R_prot≤ (V_OHµC- V_IH- V_GND) / I_IHmax

Calculation example:

For V_CCpeak= -150 V; I_latchup≥ 20 mA; V_OHµC≥ 4.5 V

7.5 kΩ ≤ R_prot≤ 140 kΩ.

Recommended values: R_prot= 15 kΩ

4.4

Multisense - analog current sense

Diagnostic information on device and load status are provided by an analog output pin

(MultiSense) delivering the following signals:

•

Current monitor: current mirror of channel output current

V_CCmonitor: voltage propotional to V_CC

T_CASE: voltage propotional to chip temperature

Those signals are routed through an analog multiplexer which is configured and controlled

by means of SELx and SEn pins, according to the address map in MultiSense multiplexer

addressing Table.

Figure 37: MultiSense and diagnostic – block diagram

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Application information

VND7050AJ

4.4.1

Principle of Multisense signal generation

Figure 38: MultiSense block diagram

Current monitor

When current mode is selected in the MultiSense, this output is capable to provide:

•

Current mirror proportional to the load current in normal operation, delivering current

proportional to the load according to known ratio named K

•

Diagnostics flag in fault conditions delivering fixed voltage V_SENSEH

The current delivered by the current sense circuit, I_SENSE, can be easily converted to a

voltage V_SENSEby using an external sense resistor, R_SENSE, allowing continuous load

monitoring and abnormal condition detection.

Normal operation (channel ON, no fault, SEn active)

While device is operating in normal conditions (no fault intervention), V_SENSEcalculation can

be done using simple equations

Current provided by MultiSense output: I_SENSE= I_OUT/K

Voltage on R_SENSE: V_SENSE= R_SENSE· I_SENSE= R_SENSE· I_OUT/K

Where:

•

V_SENSEis voltage measurable on R_SENSEresistor

I_SENSEis current provided from MultiSense pin in current output mode

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Application information

•

I_OUTis current flowing through output

K factor represents the ratio between PowerMOS cells and SenseMOS cells; its

spread includes geometric factor spread, current sense amplifier offset and process

parameters spread of overall circuitry specifying ratio between I_OUTand I_SENSE

.

Failure flag indication

In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin

which is switched to a “current limited” voltage source, V_SENSEH

.

In any case, the current sourced by the MultiSense in this condition is limited to I_SENSEH

.

The typical behavior in case of overload or hard short circuit is shown in Waveforms

section.

Figure 39: Analogue HSD – open-load detection in off-state

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Application information

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Figure 40: Open-load / short to VCC condition

Table 13: MultiSense pin levels in off-state

Condition

Output

MultiSense

SEn

L

Hi-Z

V_SENSEH

Hi-Z

0

V_OUT> V_OL

H

L

Open-load

V_OUT< V_OL

V_OUT> V_OL

V_OUT< V_OL

H

L

Hi-Z

V_SENSEH

Hi-Z

0

Short to V_CC

Nominal

H

L

H

4.4.2

TCASE and VCC monitor

In this case, MultiSense output operates in voltage mode and output level is referred to

device GND. Care must be taken in case a GND network protection is used, because of a

voltage shift is generated between device GND and the microcontroller input GND

reference.

Figure 41: "GND voltage shift" shows link between V_MEASUREDand real V_SENSEsignal.

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Application information

Figure 41: GND voltage shift

V_CCmonitor

Battery monitoring channel provides V_SENSE= V_CC/ 4.

Case temperature monitor

Case temperature monitor is capable to provide information about the actual device

temperature. Since a diode is used for temperature sensing, the following equation

describes the link between temperature and output V_SENSElevel:

V_{SENSE_TC}(T) = V_{SENSE_TC}(T₀) + dV_{SENSE_TC}/ dT * (T - T₀)

where dV_{SENSE_TC}/ dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C).

Short to VCC and OFF-state open-load detection

Short to V_CC

4.4.3

A short circuit between V_CCand output is indicated by the relevant current sense pin set to

V_SENSEHduring the device off-state. Small or no current is delivered by the current sense

during the on-state depending on the nature of the short circuit.

OFF-state open-load with external circuitry

Detection of an open-load in off mode requires an external pull-up resistor R_PUconnecting

the output to a positive supply voltage V_PU.

It is preferable V_PUto be switched off during the module standby mode in order to avoid the

overall standby current consumption to increase in normal conditions, i.e. when load is

connected.

R_PUmust be selected in order to ensure V_OUT> V_OLmaxin accordance with the following

equation:

DocID027396 Rev 1

33/46

Application information

VND7050AJ

Equation

V_PU- 4

I_{L(off2)min @ 4V}

R_PU<

34/46

DocID027396 Rev 1

VND7050AJ

Maximum demagnetization energy (VCC = 16 V)

5

Maximum demagnetization energy (VCC = 16 V)

Figure 42: Maximum turn off current versus inductance

VND7050AJ

- Maximum turn off current versus inductance

100

10

1

VND7050AJ- Single Pulse

Repetitive pulse Tjstart=100°C

Repetitive pulse Tjstart=125°C

0.1

1

10

100

1000

L (mH)

- Maximum turn off Energy versus Tdemag

VND7050AJ

1000

VND7050AJ- Single Pulse

Repetitive pulse Tjstart=100°C

Repetitive pulse Tjstart=125°C

100

10

1

0.01

0.1

1

10

100

Tdemag [ms]

GAPGCFT01245

Values are generated with R_L= 0 Ω.

In case of repetitive pulses, T_jstart(at the beginning of each demagnetization) of

every pulse must not exceed the temperature specified above for curves A and B.

DocID027396 Rev 1

35/46

Package and PCB thermal data

VND7050AJ

6

Package and PCB thermal data

6.1

PowerSSO-16 thermal data

Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)

Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)

Table 14: PCB properties

Dimension

Value

1.6 mm +/- 10%

77 mm x 86 mm

FR4

Board finish thickness

Board dimension

Board Material

Copper thickness (top and bottom layers)

Copper thickness (inner layers)

Thermal vias separation

0.070 mm

0.035 mm

1.2 mm

Thermal via diameter

0.3 mm +/- 0.08 mm

0.025 mm

Copper thickness on vias

Footprint dimension (top layer)

Heatsink copper area dimension (bottom layer)

2.2 mm x 3.9 mm

Footprint, 2 cm²or 8 cm²

36/46

DocID027396 Rev 1

VND7050AJ

Package and PCB thermal data

Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on)

Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)

Equation: pulse calculation formula

Z_THδ= R_TH· δ + Z_THtp(1 - δ)

where δ = t_P/T

DocID027396 Rev 1

37/46

Package and PCB thermal data

VND7050AJ

Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16

The fitting model is a simplified thermal tool and is valid for transient evolutions

where the embedded protections (power limitation or thermal cycling during

thermal shutdown) are not triggered.

Table 15: Thermal parameters

Area/island (cm²)

R1 = R7 (°C/W)

R2 = R8 (°C/W)

R3 (°C/W)

Footprint

1.8

2

8

4L

3.2

8

6

8

6

4

3

7

R4 (°C/W)

14

R5 (°C/W)

30

20

10

18

R6 (°C/W)

26

C1 = C7 (W.s/°C)

C2 = C8 (W.s/°C)

C3 (W.s/°C)

0.00035

0.005

0.05

0.2

C4 (W.s/°C)

0.3

1

0.3

1

0.4

4

C5 (W.s/°C)

0.4

C6 (W.s/°C)

3

5

7

18

38/46

DocID027396 Rev 1

VND7050AJ

Package information

7

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK^®packages, depending on their level of environmental compliance. ECOPACK^®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK^®is an ST trademark.

7.1

PowerSSO-16 package information

Figure 48: PowerSSO-16 package outline

Table 16: PowerSSO-16 mechanical data

Dimensions

Ref.

Millimeters

Typ.

Min.

0°

Max.

Θ

Θ1

Θ2

Θ3

A

8°

0°

5°

15°

5°

1.70

DocID027396 Rev 1

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Package information

VND7050AJ

Dimensions

Millimeters

Typ.

Ref.

Min.

0.00

1.10

0.20

0.19

Max.

0.10

1.60

0.30

0.28

0.25

0.23

A1

A2

b

b1

c

0.25

c1

D

0.20

4.9 BSC

D1

e

2.90

3.50

0.50 BSC

6.00 BSC

3.90 BSC

E

E1

E2

h

2.20

0.25

0.40

2.80

0.50

0.85

L

0.60

1.00 REF

16

L1

N

R

0.07

0.20

R1

S

Tolerance of form and position

aaa

bbb

ccc

ddd

eee

fff

0.10

0.08

0.10

0.15

ggg

40/46

DocID027396 Rev 1

VND7050AJ

Package information

7.2

PowerSSO-16 packing information

Figure 49: PowerSSO-16 reel 13"

Table 17: Reel dimensions

Value⁽¹⁾

Description

Base quantity

Bulk quantity

A (max)

2500

330

1.5

B (min)

C (+0.5, -0.2)

D (min)

13

20.2

100

12.4

18.4

N

W1 (+2 /-0)

W2 (max)

Notes:

⁽¹⁾All dimensions are in mm.

DocID027396 Rev 1

41/46

Package information

VND7050AJ

Figure 50: PowerSSO-16 carrier tape

P₂

P₀

2.0 0.1

4.0 0.1

X

1.55 0.05

1.6 0.1

1.75 0.1

0.30 0.05

Y

R 0.5

Typical

K₁

K₀

X

P₁

A₀

SECTION X - X

REF 4.18

REF 0.5

SECTION Y - Y

GAPG2204151242CFT

Table 18: PowerSSO-16 carrier tape dimensions

Value⁽¹⁾

Description

A₀

B₀

K₀

K₁

F

6.50 ± 0.1

5.25 ± 0.1

2.10 ± 0.1

1.80 ± 0.1

5.50 ± 0.1

8.00 ± 0.1

12.00 ± 0.3

P₁

W

Notes:

⁽¹⁾All dimensions are in mm.

Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape

42/46

DocID027396 Rev 1

VND7050AJ

Package information

7.3

PowerSSO-16 marking information

Figure 52: PowerSSO-16 marking information

Marking area

1

2

3

4

5

6

7

8

Special function digit

&: Engineering sample

<blank>: Commercial sample

PowerSSO-16 TOP VIEW

(not in scale)

GAPG0401151415CFT

Engineering Samples: these samples can be clearly identified by a dedicated

special symbol in the marking of each unit. These samples are intended to be

used for electrical compatibility evaluation only; usage for any other purpose may

be agreed only upon written authorization by ST. ST is not liable for any customer

usage in production and/or in reliability qualification trials.

Commercial Samples: fully qualified parts from ST standard production with no

usage restrictions.

DocID027396 Rev 1

43/46

Order codes

VND7050AJ

8

Order codes

Table 19: Device summary

Order codes

Tape and reel

VND7050AJTR

Package

PowerSSO-16

44/46

DocID027396 Rev 1

VND7050AJ

Revision history

9

Revision history

Table 20: Document revision history

Revision

Date

Changes

19-May-2015

1

Initial release.

DocID027396 Rev 1

45/46

VND7050AJ

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST

products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the

design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

46/46

DocID027396 Rev 1


型号：	VND7050AJ
厂家：	ST
描述：	Double channel high-side driver with MultiSense analog feedback
文件：	总46页 (文件大小：1921K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VND7050AJ [STMICROELECTRONICS]

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