VNH5050ATR-E [STMICROELECTRONICS]
Automotive fully integrated H-bridge motor driver; 汽车完全集成H桥电机驱动器型号: | VNH5050ATR-E |
厂家: | ST |
描述: | Automotive fully integrated H-bridge motor driver |
文件: | 总33页 (文件大小:790K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
VNH5050A-E
Automotive fully integrated H-bridge motor driver
Features
Type
RDS(on)
Iout
Vccmax
50 mΩ max
(per leg)
VNH5050A-E
30 A
41 V
PowerSSO-36 TP
proprietary VIPower® M0 technology that allows
to efficiently integrate on the same die a true
Power MOSFET with an intelligent
■ Output current: 30 A
■ 3 V CMOS compatible inputs
■ Undervoltage and overvoltage shutdown
■ Overvoltage clamp
signal/protection circuitry. The three dies are
assembled in a PowerSSO-36 TP package on
electrically isolated lead frames. This package,
specifically designed for the harsh automotive
environment offers improved thermal
■ Thermal shutdown
■ Cross-conduction protection
■ Current and power limitation
■ Very low standby power consumption
■ PWM operation up to 20 KHz
performance thanks to exposed die pads.
Moreover, its fully symmetrical mechanical design
allows superior manufacturability at board level.
The input signals INA and INB can directly
interface to the microcontroller to select the motor
direction and the brake condition. The DIAGA/ENA
or DIAGB/ENB, when connected to an external
pull-up resistor, enables one leg of the bridge.
Each DIAGA/ENA provides a digital diagnostic
feedback signal as well. The normal operating
condition is explained in the truth table. The CS
pin allows monitoring the motor current by
delivering a current proportional to its value when
CS_DIS pin is driven low or left open. When
CS_DIS is driven high, CS pin is in high
impedance condition. The PWM, up to 20 KHz,
allows to control the speed of the motor in all
possible conditions. In all cases, a low level state
on the PWM pin turns off both the LSA and LSB
switches.
■ Protection against loss of ground and loss of
VCC
■ Current sense output proportional to motor
current
■ Output protected against short to ground and
short to VCC
■ Package: ECOPACK®
Description
The VNH5050A-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side driver and two low-side
switches. All switches are designed using
STMicroelectronics® well known and proven
Table 1.
Device summary
Order codes
Tape and reel
Package
Tube
PowerSSO-36 TP
VNH5050A-E
VNH5050ATR-E
December 2011
Doc ID 16009 Rev 10
1/33
www.st.com
1
Contents
VNH5050A-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.1
4.1.2
4.1.3
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal resistances definition (values according to the PCB heatsink
area) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
6
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
®
5.1
5.2
5.3
ECOPACK packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-36 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-36 TP packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/33
Doc ID 16009 Rev 10
VNH5050A-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin definitions and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin functions description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching (VCC = 13 V, RLOAD = 1.5 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current sense (9 V < VCC < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 25
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSSO-36 TP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Doc ID 16009 Rev 10
3/33
List of figures
VNH5050A-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 16
Definition of delay response time of sense current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Waveforms in full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Waveforms in full-bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 21
Figure 12. Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. PowerSSO-36™ PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . 25
Figure 18. Detailed chipset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 27
Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 27
Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22. PowerSSO-36 TP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 23. PowerSSO-36 TP tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4/33
Doc ID 16009 Rev 10
VNH5050A-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
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Table 2.
Block description
Name
Description
Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the truth table.
Logic control
Undervoltage/overvoltage
Shuts down the device for battery voltage outside the range
(4,5...24V).
Protect the high-side and the low-side switches from high
voltage on the battery line.
High-side and low-side clamp voltage
Drive the gate of the concerned switch to allow a proper
RDS(on) for the leg of the bridge.
High-side and low-side driver
Current limitation
Limits the motor current in case of short circuit.
In case of short-circuit with the increase of the junction
temperature, it shuts down the concerned driver to prevent
degradation and to protect the die.
High-side and low-side
overtemperature protection
Detects when low-side current exceeds shutdown current
and latches off the concerned low-side.
Low-side overload detector
Fault detection
Signalizes an abnormal condition of the switch (output
shorted to ground or output shorted to battery) by pulling
down the concerned ENx/DIAGx pin.
Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
Power limitation
Doc ID 16009 Rev 10
5/33
Block diagram and pin description
VNH5050A-E
Table 3.
Suggested connections for unused and not connected pins
INPUTx, PWM
DIAGx/ENx
CS_DIS
Connection / pin Current sense
N.C. SOURCE_HSx DRAIN_LSx
Floating
Not allowed
X
X
X
X
X
X
Through 1 kΩ
Through 10 kΩ
To ground
Not allowed
resistor
resistor
Figure 2.
Configuration diagram (top view)
GND_A
DRAIN LS
1
GND_B
36
A
DRAIN LS
GND_B
GND_B
GND_B
GND_B
GND_B
B
GND_A
GND_A
GND_A
Slug2
Slug3
GND_A
GND_A
DRAIN LS
A
DRAIN LS
B
SOURCE HS
B
SOURCE HS
SOURCE HS
A
A
A
A
SOURCE HS
SOURCE HS
SOURCE HS
B
B
B
SOURCE HS
SOURCE HS
V
V
CC
CC
SOURCE HS
A
SOURCE HS
IN
EN
B
Slug1
B
INA
ENA/DIAGA
B
/DIAGB
IN_PWM
NC
CS_DIS
CS
18
19
Table 4.
Pin definitions and functions
Pin N°
Symbol
Function
VCC, Heat
slug1
13, 24
Drain of high-side switches and power supply voltage.
18
15
NC
INA
Not connected.
Clockwise input.
Status of high-side and low-side switches A;
Open drain output.
16
ENA/DIAGA
17
19
IN_PWM PWM input.
CS
Output of current sense.
6/33
Doc ID 16009 Rev 10
VNH5050A-E
Table 4.
Block diagram and pin description
Pin definitions and functions (continued)
Pin N°
Symbol
Function
Active high CMOS compatible pin to disable current sense
pin.
20
CS_DIS
Status of high-side and low-side switches B;
Open drain output.
21
22
ENB/DIAGB
INB
Counter clockwise input.
OUTB Heat
,
23, 25, 26, 27, 28, 29, 35
30, 31, 32, 33, 34,36
2, 8, 9, 10, 11, 12, 14
1, 3, 4, 5, 6, 7
Source of high-side switch B / drain of low-side switch B.
Source of low-side switch B.
Slug3
GND_B
OUTA, Heat
Slug2
Source of high-side switch A / drain of low-side switch A.
Source of low-side switch A.
GND_A
Table 5.
Name
Pin functions description
Description
VCC
Battery connection.
Power ground.
GND
OUTA
OUTB
Power connections to the motor.
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins
control the state of the bridge in normal operation according to the truth table (brake
to VCC, Brake to GND, clockwise and counterclockwise).
INA
INB
Voltage controlled input pin with hysteresis, CMOS compatible.Gates of low-side
FETS get modulated by the PWM signal during their on phase allowing speed control
of the motor.
PWM
Open drain bidirectional logic pins.These pins must be connected to an external pull
up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault
detection (thermal shutdown of a high-side FET or excessive on-state voltage drop
across a low-side FET), these pins are pulled low by the device (see truth table in fault
condition).
ENA/DIAGA
ENB/DIAGB
Analog current sense output. This output delivers a current proportional to the motor
current if CS_DIS is low or left open. The information can be read back as an analog
voltage across an external resistor.
CS
CS_DIS
Active high CMOS compatible pin to disable the current sense pin.
Doc ID 16009 Rev 10
7/33
Electrical specifications
VNH5050A-E
2
Electrical specifications
Figure 3.
Current and voltage conventions
I
S
V
CC
I
INA
V
CC
I
OUTA
IN
A
OUT
A
I
INB
I
OUTB
I
SENSE
IN
B
OUT
B
V
I
OUTA
ENA
CS
DIAG /EN
A
A
I
CSD
V
I
OUTB
ENB
CS_DIS
V
SENSE
DIAG /EN
B
B
PWM
GND
I
pw
V
CSD
I
GND
V
V
V
V
V
ENB
INA
INB
pw
ENA
2.1
Absolute maximum ratings
Table 6.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
Imax
IR
Supply voltage
+ 41
V
A
DC output current
Internally limited
25
Reverse output current (continuous)(1)
A
IIN
Input current (INA and INB pins)
+/- 10
mA
mA
mA
mA
V
IEN
Ipw
Enable input current (DIAGA/ENA and DIAGB/ENB pins)
PWM Input current
+/- 10
+/- 10
ICS_DIS CS_DIS input current
+/- 10
VCS
Current sense maximum voltage
VCC-41/+VCC
Electrostatic discharge
VESD
2
kV
(Human body model: R = 1.5 kΩ, C = 100 pF)
Tc
Junction operating temperature
Storage temperature
-40 to 150
-55 to 150
200
°C
°C
TSTG
IGND
DC reverse ground pin current
mA
1. Based on the internal wires capability.
8/33
Doc ID 16009 Rev 10
VNH5050A-E
Electrical specifications
2.2
Thermal data
Table 7.
Symbol
Thermal data
Parameter
Max. value
Unit
HSD
LSD
3.7
3.9
°C/W
°C/W
°C/W
Rthj-case
Rthj-amb
Thermal resistance junction-case (per leg)
Thermal resistance junction-ambient
See Figure 17
Doc ID 16009 Rev 10
9/33
Electrical specifications
VNH5050A-E
2.3
Electrical characteristics
VCC = 9 V up to 18 V; -40 °C < Tj < 150 °C, unless otherwise specified.
Table 8.
Symbol
Power section
Parameter
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
5.5
18
V
Off-state with all fault cleared
and ENx = 0 (standby)
INA = INB = PWM = 0;
Tj = 25 °C; VCC = 13 V
3
6
µA
Off-state with all fault cleared
and ENx = 0 (standby)
V
CC = 13 V;
10
5
µA
INA = INB = PWM = 0;
Tj = -40 °C to 150 °C
IS
Supply current
Off-state (no standby)
INA = INB = PWM = 0;
ENx = 5 V;
mA
Tj = -40 °C to 150 °C
On-state:
INA or INB = 5V; no PWM
3
6
8
mA
mA
On-state:
INA or INB = 5 V;
PWM = 20 kHz
IOUT = 8.5 A; Tj = -40 °C
OUT = 8.5 A; Tj = 25 °C
17
26
52
mΩ
mΩ
mΩ
Static high-side
resistance
RONHS
IOUT = 8.5 A; Tj = 150 °C
IOUT = 8.5 A;
Tj = - 40 °C to 150 °C
60
mΩ
mΩ
mΩ
IOUT = 8.5 A; Tj = 25 °C
20
RONLS
Static low-side resistance
IOUT = 8.5 A;
Tj = - 40 °C to 150 °C
40
0.9
3
High-side free-wheeling
diode forward voltage
Vf
IOUT = -8.5 A; Tj = 150 °C
0.7
V
µA
µA
A
Tj = 25 °C; VCC = 13V;
VOUTX = ENX = 0 V
0
0
High-side off-state output
current (per channel)
IL(off)
Tj = 125°C; VCC = 13V;
VOUTX = ENX = 0 V
5
Dynamic cross-
conduction current
IRM
IOUT = 8.5 A (see Figure 7)
1
10/33
Doc ID 16009 Rev 10
VNH5050A-E
Electrical specifications
Min. Typ. Max. Unit
Table 9.
Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS)
Symbol
Parameter
Test conditions
Normal operation
VIL
Input low level voltage
(DIAGX/ENX pin acts as an
input pin)
0.9
V
V
V
Normal operation
(DIAGX/ENX pin acts as an
input pin)
VIH
Input high level voltage
2.1
Normal operation
(DIAGX/ENX pin acts as an 0.15
input pin)
VIHYST
Input hysteresis voltage
Input clamp voltage
IIN = 1 mA
IIN = -1 mA
VIN = 0.9 V
VIN = 2.1 V
5.5
-1.0
1
6.3
7.5
V
V
VICL
-0.7
-0.3
IINL
IINH
Input current
Input current
µA
µA
10
Fault operation
(DIAGX/ENX pin acts as an
output pin); IEN = 1 mA
Enable output low level
voltage
VDIAG
0.4
V
Table 10. Switching (VCC = 13 V, RLOAD = 1.5 Ω)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
f
PWM frequency
0
20
kHz
µs
Input rise time < 1µs
(see Figure 6)
td(on)
Turn-on delay time
Turn-off delay time
250
Input rise time < 1µs
(see Figure 6)
td(off)
250
µs
tr
tf
Rise time
Fall time
See Figure 5
See Figure 5
1
1
2
2
µs
µs
Delay time during change
of operating mode
tDEL
See Figure 4
See Figure 7
200
400 1600
100
µs
ns
High-side free wheeling
diode reverse recovery
time
trr
Table 11. Protections and diagnostics
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VUSD
Undervoltage shutdown
3
5
V
V
Undervoltage shutdown
hysteresis
VUSDhyst
0.5
VOV
VCC overvoltage shutdown
High-side current limitation
24
30
27
42
30
60
V
A
ILIM_H
Doc ID 16009 Rev 10
11/33
Electrical specifications
Table 11. Protections and diagnostics (continued)
VNH5050A-E
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
ISD_LS
Shutdown LS current
30
41
50
46
70
52
A
V
Total clamp voltage
(VCC to GND)
VCLP
VCLPH
TSD_LS
VCLPLS
IOUT = 8.5 A
High-side clamp voltage
(VCC to OUTA =0 or
OUTB =0)
IOUT = 8.5 A
41
46
10
52
V
µs
V
Time to shutdown for the
low-side
Low-side clamp voltage
(OUTA = VCC or
I
OUT = 8.5 A
25
28
31
OUTB = VCC to GND)
Thermal shutdown
temperature
(1)
TTSD
VIN = 2.1 V
150
135
175
200
°C
°C
°C
(2)
TTR
Thermal reset temperature
Thermal hysteresis
(TSD-TR)
(2)
THYST
16
Low-side thermal
shutdown temperature
TTSD_LS
VIN = 0 V
150
175
200
°C
1.
T
is the minimum threshold temperature between HS and LS
TSD
2. Valid for both HSD and LSD.
Table 12. Current sense (9 V < VCC < 18 V)
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
IOUT = 5 A; VSENSE = 0.8 V;
VCSD = 0 V;
K1
IOUT/ISENSE
4350 5100 6270
Tj = - 40 °C to 150 °C
IOUT = 10 A;
K2
K3
IOUT/ISENSE
VSENSE = 1.6 V; VCSD = 0 V; 4350 5030 5870
Tj = - 40 °C to 150 °C
IOUT = 25 A; VSENSE = 4 V;
IOUT/ISENSE
VCSD = 0 V;
4100 4930 5490
Tj = - 40 °C to 150 °C
I
OUT = 5 A; VSENSE = 0.8 V;
Analog sense current
drift
(1)
dK1/K1
VCSD = 0 V;
Tj = - 40 °C to 150°C
-14
-13
-13
14
13
13
%
%
%
I
OUT = 10 A; VSENSE = 1.6 V;
Analog sense current
drift
(1)
dK2/K2
VCSD = 0 V;
Tj = - 40 °C to 150°C
IOUT = 25 A; VSENSE = 4 V;
Analog sense current
drift
(1)
dK3/K3
VCSD = 0 V;
Tj = - 40 °C to 150 °C
12/33
Doc ID 16009 Rev 10
VNH5050A-E
Table 12. Current sense (9 V < VCC < 18 V) (continued)
Electrical specifications
Min. Typ. Max. Unit
Symbol
Parameter
Test conditions
Max analog sense
output voltage
IOUT = 10 A; VCSD = 0 V;
RSENSE = 800 Ω
VSENSE
5
V
IOUT = 500 mA; VCC = 13 V;
Tj = - 40 °C
87
91
µA
µA
µA
IOUT = 500 mA; VCC = 13 V;
Tj = 25 °C
ISENSETYP_500 Typical analog sense
IOUT = 500 mA; VCC = 13 V;
Tj = 150 °C
100
IOUT = 0 A; VSENSE = 0 V;
VCSD = 5 V; VIN = 0 V;
Tj = - 40 °C to 150°C
0
5
µA
Analog sense leakage
ISENSE0
current
VCSD = 0 V; VIN = 5 V;
Tj = - 40 °C to 150 °C
0
0
180
5
µA
µA
VCSD = 5 V; VIN = 5 V;
IOUT = 8.5 A
VIN = 5 V; VSENSE < 4 V,
Delay response time
from falling edge of
CS_DIS pin
IOUT = 8.5 A;
tDSENSEH
50
20
µs
µs
ISENSE = 90 % of ISENSEmax
(see Figure 8)
VIN = 5 V; VSENSE < 4 V;
Delay response time
from rising edge of
CS_DIS pin
IOUT = 8.5 A;
tDSENSEL
ISENSE = 10 % of ISENSEmax
(see Figure 8)
1. Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and
9 V < V < 18 V) with respect to its value measured at T = 25 °C, V = 13 V.
CC
j
CC
Doc ID 16009 Rev 10
13/33
Electrical specifications
VNH5050A-E
Figure 4.
Definition of the delay times measurement
VINA
t
VINB
t
PWM
t
ILOAD
tDEL
tDEL
t
14/33
Doc ID 16009 Rev 10
VNH5050A-E
Figure 5.
Electrical specifications
Definition of the low-side switching times
PWM
t
V
OUTA, B
90%
80%
t
f
t
t
10%
20%
r
Figure 6.
Definition of the high-side switching times
V
INA
t
t
D(off)
D(on)
t
V
OUTA
90%
10%
t
Doc ID 16009 Rev 10
15/33
Electrical specifications
Figure 7.
VNH5050A-E
Definition of dynamic cross conduction current during a PWM operation
IN = 1, IN = 0
A
B
PWM
t
I
MOTOR
t
V
OUTB
t
I
CC
I
RM
t
t
rr
Figure 8.
Definition of delay response time of sense current
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
t
t
DSENSEH
DSENSEL
16/33
Doc ID 16009 Rev 10
VNH5050A-E
Electrical specifications
Operating mode
Table 13. Truth table in normal operating conditions
INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB
CS
1
0
1
0
H
L
High Imp.
Brake to VCC
1
0
H
L
Clockwise (CW)
Counterclockwise (CCW)
Brake to GND
1
1
ISENSE = IOUT/K
High Imp.
H
L
Table 14. Truth table in fault conditions (detected on OUTA)
INA
INB
DIAGA/ENA
DIAGB/ENB
OUTA
OUTB
CS (VCSD=0V)
1
0
1
0
X
H
High
impedance
1
L
H
1
0
0
OPEN
I
OUTB/K
High
0
L
impedance
X
OPEN
Fault Information
Protection Action
Note:
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
Doc ID 16009 Rev 10
17/33
Electrical specifications
VNH5050A-E
Table 15. Electrical transient requirements (part 1/3)
Burst cycle/pulse
repetition time
Test levels(1)
ISO 7637-2:
2004(E)
Test pulse
Number of
pulses or
test times
Delays and
Impedance
III
IV
Min.
Max.
1
2a
3a
3b
4
-75V
+37V
-100V
+75V
-6V
-100V
+50V
-150V
+100V
-7V
5000 pulses
5000 pulses
1h
0.5s
0.2s
5s
2 ms, 10Ω
50µs, 2Ω
5s
90ms
90ms
100ms
100ms
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
1h
1 pulse
1 pulse
5b(2)
+65V
+87V
1. The above test levels must be considered referred to V = 13.5V except for pulse 5b.
CC
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 16. Electrical transient requirements (part 2/3)
ISO 7637-2:
2004E
Test pulse
Test level results
III
VI
1
2a
3a
3b
4
C
C
C
C
C
C
C
C
C
C
C
C
5b(1)
1. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 17. Electrical transient requirements (part 3/3)
Class
Contents
C
All functions of the device performed as designed after exposure to disturbance.
One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
18/33
Doc ID 16009 Rev 10
VNH5050A-E
Electrical specifications
2.4
Waveforms
Figure 9.
Waveforms in full-bridge operation
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS (*)
tDEL
tDEL
CS_DIS
(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS
CS_DIS
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
INA
INB
ILIM
IOUTA->OUTB
TTSD_HSA
TTR_HSA
Tj =TTSD
Tj < TTSD
Tj > TTR
TjHSA
DIAGA/ENA
DIAGB/ENB
CS
CS_DIS
power limitation
current
limitation
normal operation
normal operation
OUTA shorted to ground
Doc ID 16009 Rev 10
19/33
Electrical specifications
VNH5050A-E
Figure 10. Waveforms in full-bridge operation (continued)
OUTA shorted to VCC (resistive short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
I
SD_LS
ILSA
T
TSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA softly shorted to VCC
normal operation
undervoltage shutdown
OUTA shorted to VCC (pure short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
I
SD_LS
ILSA
T
TSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA hardly shorted to VCC
normal operation
undervoltage shutdown
20/33
Doc ID 16009 Rev 10
VNH5050A-E
Application information
3
Application information
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
PWM pin usage: In all cases, a “0” on the PWM pin turns off both LSA and LSB switches.
When PWM rises back to “1”, LSA or LSB turn on again depending on the input pin state.
Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit
protection
VCC
+5V
3.3K
Reg 5V
+ 5V
VCC
3.3K
1K
DIAGB/ENB
1K
DIAG /EN
A
A
1K
HSA
HSB
PWM
μC
OUT
A
OUTB
INA
CS
1K
INB
1K
LSA
LSB
10K
C
M
33nF
1.5K
GND
GND
B
A
S
100K
G
b) N MOSFET
D
Note:
The value of the blocking capacitor (C) depends on the application conditions and defines
voltage and current ripple on supply line at PWM operation. Stored energy of the motor
inductance may fly back into the blocking capacitor, if the bridge driver goes into 3-state.
This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation,
500µF per 10A load current is recommended.
In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.
The fault conditions are:
–
–
Overtemperature on one or both high-sides
Short to battery condition on the output (over current detection on the low-side
Power MOSFET)
Possible origins of fault conditions may be:
OUTA is shorted to ground → overtemperature detection on high-side A
OUTA is shorted to VCC → low-side Power MOSFET over current detection
When a fault condition is detected, the user can identify which power element is in fault by
monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.
Doc ID 16009 Rev 10
21/33
Application information
VNH5050A-E
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the
respective output (OUTX) again, the input signal must rise from low to high level.
Figure 12. Behavior in fault condition (how a fault can be cleared)
Note:
In case of the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle: INA if ENA = 0 or INB if ENB = 0)
- Pull low all inputs, PWM and Diag/EN pins within tDEL
.
If the Diag/En pins are already low, PWM = 0, the fault can be cleared simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.
3.1
Reverse battery protection
Three possible solutions can be considered:
–
–
–
A Schottky diode D connected to VCC pin
An N-channel MOSFET connected to the GND pin (see Figure 11)
A P-channel MOSFET connected to the VCC pin
The device sustains no more than -25 A in reverse battery conditions because of the two
body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH5050A-E is pulled down to the VCC line (approximately -1.5 V).
22/33
Doc ID 16009 Rev 10
VNH5050A-E
Application information
Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If
Rmax is the maximum target reverse current through µC I/Os, series resistor is:
I
V
– V
IOs
I
CC
R = ---------------------------------
Rmax
Figure 13. Half-bridge configuration
V
CC
IN
IN
IN
A
A
B
IN
B
DIAG /EN
DIAG /EN
A
A
A
A
B
DIAG /EN
DIAG /EN
B
B
B
PWM
PWM
OUT
A
OUT
OUT
OUT
B
M
B
A
GND
GND
Note:
The VNH5050A-E can be used as a high power half-bridge driver.
Figure 14. Multi-motors configuration
V
CC
IN
IN
IN
IN
A
B
A
B
DIAG /EN
DIAG /EN
A
A
A
A
B
DIAG /EN
DIAG /EN
B
PWM
B
B
PWM
OUT
A
OUT
OUT
OUT
B
M
2
B
A
GND
GND
M
M
1
3
Note:
The VNH5050A-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor has to be driven at a time. DIAGX/ENX pins allow
to put unused half-bridges in high impedance.
Doc ID 16009 Rev 10
23/33
Package and PCB thermal data
VNH5050A-E
4
Package and PCB thermal data
4.1
PowerSSO-36 thermal data
Figure 15. PowerSSO-36™ PC board
Double layers: footprint
2
Double layers: 2cm of Cu
2
Double layers: 8cm of Cu
2
2
Four layers: Cu on top layer: 16 cm ; Cu on bottom layer: 32 cm ; Cu on middle layer: total coverage
Note:
24/33
Board finish thickness 1.6 mm +/- 10%, Board double layers and four layers, Board
dimension 129x60, Board Material FR4, Cu thickness 0.070mm (front and back side),
Thermal vias spaced on a 1.2 mm x 1.2 mm grid, Vias pad clearance thickness 0.2 mm,
Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm, Footprint
dimension 4.1 mm x 6.5 mm.
Doc ID 16009 Rev 10
VNH5050A-E
Figure 16. Chipset configuration
Package and PCB thermal data
HIGH SIDE
CHIP
HSAB
LOW SIDE
CHIP A
LOW SIDE
CHIP B
LSB
LSA
Figure 17. Auto and mutual Rthj-amb vs PCB copper area in open box free air
condition
80
RthA
70
60
50
40
30
20
10
0
RthB = RthC
RthAB = RthAC
RthBC
0
2
4
6
8
10
12
cm2 of Cu Area (refer to PCB layout)
4.1.1
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
Table 18. Thermal calculation in clockwise and anti-clockwise operation in steady-
state mode
HSA HSB LSA LSB
TjHSAB
TjLSA
TjLSB
PdHSA x RthHS + PdLSB PdHSA x RthHSLS
+
PdHSA x RthHSLS + PdLSB
ON OFF OFF ON
x RthHSLS + Tamb
PdLSB x RthLSLS + Tamb x RthLS + Tamb
PdHSB x RthHS + PdLSA PdHSB x RthHSLS
+
PdHSB x RthHSLS + PdLSA
x RthLSLS + Tamb
OFF ON ON OFF
x RthHSLS + Tamb
PdLSA x RthLS + Tamb
4.1.2
Thermal resistances definition (values according to the PCB heatsink
area)
R
thHS = RthHSA = RthHSB = High Side Chip Thermal Resistance Junction to Ambient (HSA or
HSB in ON state)
R
thLS = RthLSA = RthLSB = Low Side Chip Thermal Resistance Junction to Ambient
Doc ID 16009 Rev 10
25/33
Package and PCB thermal data
VNH5050A-E
R
thHSLS = RthHSALSB = RthHSBLSA = Mutual Thermal Resistance Junction to Ambient
between High Side and Low Side Chips
R
thLSLS = RthLSALSB = Mutual Thermal Resistance Junction to Ambient between Low Side
Chips
(a)
4.1.3
Thermal calculation in transient mode
T
T
T
jHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA + PdLSB) + Tamb
jLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS x PdLSB + Tamb
jLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + ZthLS x PdLSB + Tamb
Single pulse thermal impedance definition (values according to the PCB heatsink area).
Z
Z
Z
thHS = High Side Chip Thermal Impedance Junction to Ambient
thLS = ZthLSA = ZthLSB = Low Side Chip Thermal Impedance Junction to Ambient
thHSLS = ZthHSABLSA = ZthHSABLSB = Mutual Thermal Impedance Junction to Ambient
between High Side and Low Side Chips
Z
thLSLS = ZthLSALSB = Mutual Thermal Impedance Junction to Ambient between Low Side
Chips
Figure 18. Detailed chipset configuration
CHIP 1
Zhs
Zhsls
Zhsls
CHIP 2
CHIP 3
Zls
Zls
Zlsls
Equation 1: pulse calculation formula
Z
= R
• (δ + Z
(1 – δ))
THtp
THδ
where
TH
δ = t ⁄ T
p
a. Calculation is valid in any dynamic operating condition. P values set by user.
d
26/33
Doc ID 16009 Rev 10
VNH5050A-E
Package and PCB thermal data
Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse
100
HSD-footprint
HSD-2 cm^2 Cu
HSD-8 cm^2 Cu
HSD-4 Layer
HsLsD-footprint
HsLsD-2 cm^2 Cu
10
HsLsD-8 cm^2 Cu
HsLsD-4 Layer
W
/
C°
1
0.1
0.001
0.01
0.1
1
10
100
1000
time (sec)
Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse
100
10
Z ls
W
/
C°
Z lsls
LSD-footprint
LSD-2 cm^2 Cu
LSD-8 cm^2 Cu
LSD-4 Layer
1
LsLsD-footprint
LsLsD-2 cm^2 Cu
LsLsD-8 cm^2 Cu
LsLsD-4 Layer
0.1
0.001
0.01
0.1
1
10
100
1000
time (sec)
Doc ID 16009 Rev 10
27/33
Package and PCB thermal data
Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36
VNH5050A-E
Table 19. Thermal parameters(1)
Area/island (cm2)
Footprint
2
8
4L
R1 = R7 (°C/W)
R2 = R8 (°C/W)
R3 (°C/W)
0.4
2
8
R4 (°C/W)
30
16
22
28
16
12
10
10
5
R5 (°C/W)
40
R6 (°C/W)
36
6
R9 = R15 (°C/W)
R10 = R16 (°C/W)
R11 = R17 (°C/W)
R12 = R18 (°C/W)
R13 = R19 (°C/W)
R14 = R20 (°C/W)
R21 = R22 (°C/W)
R23 (°C/W)
0.1
3.6
22
14
30
36
32
60
50
14
30
28
26
50
45
14
20
16
18
40
30
49
52
50
80
80
C1 = C7 = C9 = C15 (W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
0.0005
0.008
0.09
0.5
0.8
5
C4 (W.s/°C)
0.8
1.4
6
0.8
2
0.8
3
C5 (W.s/°C)
C6 (W.s/°C)
8
10
C10 = C16 (W.s/°C)
C11 = C17 (W.s/°C)
C12 = C18 (W.s/°C)
C13 = C19 (W.s/°C)
C14 = C20 (W.s/°C)
C21 = C22 = C23 (W.s/°C)
0.009
0.07
0.45
0.8
4
0.45
1
0.45
1.2
0.6
2.5
5
6
8
0.01
0.006
0.005
0.005
1. The blank space means that the value is the same as the previous one.
28/33
Doc ID 16009 Rev 10
VNH5050A-E
Package and packing information
5
Package and packing information
®
5.1
ECOPACK packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-36 TP package information
Figure 22. PowerSSO-36 TP package dimensions
Doc ID 16009 Rev 10
29/33
Package and packing information
VNH5050A-E
Table 20. PowerSSO-36 TP mechanical data
Millimeters
Symbol
Min.
2.15
2.15
0
Typ.
Max.
2.47
2.40
0.1
A
A2
a1
b
-
-
-
0.18
0.23
10.10
7.4
-
-
0.36
0.32
10.50
7.6
c
-
D
-
-
E
e
0.5
8.5
2.3
-
-
e3
F
-
-
G
-
10.1
-
0.1
10.5
0.4
H
-
h
-
k
0 deg
0.6
8 deg
1
L
-
M
N
4.3
-
-
10 deg
O
1.2
0.8
2.9
3.65
1.0
Q
S
T
U
X1
Y1
X2
Y2
X3
Y3
Z1
Z2
1.85
3
2.35
3.5
1.85
3
2.35
3.5
4.7
3
-
5.2
-
3.5
0.4
0.4
30/33
Doc ID 16009 Rev 10
VNH5050A-E
Package and packing information
5.3
PowerSSO-36 TP packing information
Figure 23. PowerSSO-36 TP tube shipment (no suffix)
Base Qty
49
1225
532
3.5
Bulk Qty
Tube length ( 0.5)
A
C
B
B
13.8
0.6
C ( 0.1)
All dimensions are in mm.
A
Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”)
Reel dimensions
Base Qty
Bulk Qty
A (max)
B (min)
C ( 0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 ( 0.1)
P
12
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.55
1.5
11.5
2.85
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
No components
500mm min
Top
cover
tape
No components Components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
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Revision history
VNH5050A-E
6
Revision history
Table 21. Document revision history
Date
Revision
Description of changes
06-Jul-2009
1
Initial release.
Updated Figure 1: Block diagram.
Updated following tables:
– Table 2: Block description
– Table 6: Absolute maximum ratings
– Table 8: Power section
15-Sep-2009
2
– Table 11: Protections and diagnostics
– Table 12: Current sense (9 V < VCC < 18 V)
– Table 14: Truth table in fault conditions (detected on OUTA)
Updated Chapter 3: Application information.
Modified Table 12: Current sense (9 V < VCC < 18 V).
Updated following tables:
– Table 8: Power section
– Table 10: Switching (VCC = 13 V, RLOAD = 1.5 Ω)
– Table 11: Protections and diagnostics
– Table 12: Current sense (9 V < VCC < 18 V)
Added Chapter 4: Package and PCB thermal data
02-Dec-2009
3
16-Dec-2009
02-Mar-2010
4
5
Updated Table 4: Pin definitions and functions
Updated Table 14: Truth table in fault conditions (detected on
OUTA).
Updated following tables:
30-Apr-2010
30-Jun-2010
6
7
– Table 10: Switching (VCC = 13 V, RLOAD = 1.5 Ω)
– Table 11: Protections and diagnostics
Updated following tables:
– Table 7: Thermal data
– Table 8: Power section
– Table 12: Current sense (9 V < VCC < 18 V)
05-Jul-2010
19-Oct-2010
8
9
Updated Table 19: Thermal parameters.
Updated Table 12: Current sense (9 V < VCC < 18 V)
Updated Section 4.1.3: Thermal calculation in transient mode
Added Figure 18: Detailed chipset configuration
Updated Figure 1: Block diagram
Added Table 3: Suggested connections for unused and not
connected pins
22-Dec-2011
10
Table 11: Protections and diagnostics:
– TTSD, TTR, THYST: added note
Updated Figure 9: Waveforms in full-bridge operation and
Figure 10: Waveforms in full-bridge operation (continued)
32/33
Doc ID 16009 Rev 10
VNH5050A-E
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