VNQ600P-E [STMICROELECTRONICS]
QUAD CHANNEL HIGH SIDE DRIVER; 四通道高端驱动器
| 型号： | VNQ600P-E |
| 厂家： | 
ST |
| 描述： | QUAD CHANNEL HIGH SIDE DRIVER |
| 文件： | 总20页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VNQ600P-E
QUAD CHANNEL HIGH SIDE DRIVER
Figure 1. Package
Table 1. General Features
TYPE
R
(*)
I
V
CC
DS(on)
lim
VNQ600P-E
35mΩ
25A
36 V
(*) Per each channel
■ DC SHORT CIRCUIT CURRENT: 22A
■ CMOS COMPATIBLE INPUTS
■ PROPORTIONAL LOAD CURRENT SENSE
■ UNDERVOLTAGE & OVERVOLTAGE
SHUT-DOWN
■ OVERVOLTAGE CLAMP
■ THERMAL SHUT-DOWN
SO-28 (DOUBLE ISLAND)
■ CURRENT LIMITATION
■ VERY LOW STAND-BY POWER DISSIPATION
■ PROTECTION AGAINST:
LOSS OF GROUND & LOSS OF V
CC
■ REVERSE BATTERY PROTECTION (**)
■ IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
The VNQ600P-E is intended for driving any type of
multiple loads with one side connected to ground.
This device has four independent channels and
four analog sense outputs which deliver currents
proportional to the outputs currents. Active current
limitation combined with thermal shut-down and
automatic restart protect the device against
overload. Device automatically turns off in case of
ground pin disconnection.
DESCRIPTION
The VNQ600P-E is a quad HSD formed by
assembling two VND600-E chips in the same SO-
28 package. The VND600-E is a monolithic device
designed in| STMicroelectronics VIPower M0-3
Technology.
Table 2. Order Codes
Package
Tube
VNQ600P-E
Tape and Reel
SO-28
VNQ600PTR-E
Note: (**) See application schematic at page 11.
Rev. 1
October 2004
1/20
VNQ600P-E
Figure 2. Block Diagram
V
CC
1,2
OVERVOLTAGE
UNDERVOLTAGE
DEMAG 1
DRIVER 1
OUTPUT 1
INPUT 1
I
LIM1
LOGIC
I
OUT1
CURRENT
SENSE 1
K
INPUT 2
GND 1,2
DEMAG 2
DRIVER 2
OUTPUT 2
I
LIM2
OVERTEMP. 1
OVERTEMP. 2
I
OUT2
CURRENT
SENSE 2
K
V
CC
3,4
OVERVOLTAGE
UNDERVOLTAGE
DEMAG 3
DRIVER 3
OUTPUT 3
INPUT 3
I
LIM3
LOGIC
I
OUT3
CURRENT
SENSE 3
K
INPUT 4
GND 3,4
DEMAG 4
DRIVER 4
OUTPUT 4
I
LIM4
OVERTEMP. 3
OVERTEMP. 4
I
OUT4
CURRENT
SENSE 4
K
2/20
VNQ600P-E
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Value
41
Unit
V
V
CC
Supply voltage (continuous)
-V
Reverse supply voltage (continuous)
Output current (continuous), for each channel
-0.3
15
V
CC
I
A
OUT
Reverse output current (continuous), for each chan-
nel
I
R
-15
A
I
IN
Input current
+/- 10
mA
-3
V
V
V
Current sense maximum voltage
CSENSE
+15
I
Ground current at T
< 25°C (continuous)
pins
-200
mA
GND
Electrostatic Discharge (Human Body Model:
R=1.5KΩ; C=100pF)
4000
2000
5000
5000
V
V
V
V
- INPUT
V
ESD
MAX
- CURRENT SENSE
- OUTPUT
- V
CC
Maximum Switching Energy
(L=0.11mH; R =0Ω; V =13.5V; T =150ºC;
jstart
E
126
mJ
L
bat
I =40A)
L
P
Power dissipation (per island) at T
Junction operating temperature
Storage temperature
=25°C
lead
6.25
W
°C
°C
tot
T
Internally Limited
-55 to 150
j
T
stg
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
V
CC
1,2
1
28
V
CC
1,2
GND 1,2
OUTPUT 2
OUTPUT 2
OUTPUT 2
INPUT 2
INPUT 1
CURRENT SENSE 1
CURRENT SENSE 2
OUTPUT 1
OUTPUT 1
OUTPUT 1
V
1,2
3,4
CC
V
CC
OUTPUT 4
OUTPUT 4
OUTPUT 4
OUTPUT 3
GND 3,4
INPUT 4
INPUT 3
CURRENT SENSE 3
OUTPUT 3
OUTPUT 3
CURRENT
SENSE 4
V
CC
3,4
V
CC
3,4
14
15
Connection / Pin
Floating
Current Sense
N.C.
X
Output
Input
X
X
To Ground
Through 1KΩ resistor
X
Through 10KΩ resistor
3/20
VNQ600P-E
Figure 4. Current and Voltage Conventions
I
I
S1,2
S3,4
V
V
CC1,2
CC3,4
V
CC3,4
V
V
(*)
V
CC1,2
F1
I
IN1
INPUT1
I
I
I
OUT1
SENSE1
IN1
CUR. SENSE1
OUTPUT1
OUTPUT2
OUTPUT3
I
IN2
V
SENSE1
V
OUT1
I
INPUT2
OUT2
I
SENSE2
V
IN2
CUR. SENSE2
I
V
IN3
OUT2
V
SENSE2
OUT3
INPUT3
I
SENSE3
V
IN3
V
CUR. SENSE3
V
OUT3
I
IN4
I
OUT4
SENSE3
INPUT4
I
SENSE4
OUTPUT4
V
IN4
V
OUT4
CUR. SENSE4
V
GND
SENSE4
3,4
GND
1,2
I
I
GND1,2
GND3,4
(*) V = V
- V during reverse battery condition
OUTn
Fn
CCn
Table 4. Thermal Data
Symbol
Parameter
Value
15
Unit
°C/W
°C/W
°C/W
R
Thermal resistance junction-case
(MAX)
(MAX)
(MAX)
thj-case
(1)
(2)
(2)
R
R
Thermal resistance junction-ambient (one chip ON)
Thermal resistance junction-ambient (two chips ON)
60
46
44
31
thj-amb
thj-amb
(1)
2
Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm of Cu (at least 35µm thick) connected to all V pins. Horizontal
CC
mounting and no artificial air flow.
2
Note: 2. When mounted on a standard single-sided FR-4 board with 6cm of Cu (at least 35µm thick) connected to all V pins. Horizontal
CC
mounting and no artificial air flow.
4/20
VNQ600P-E
ELECTRICAL CHARACTERISTICS (8V<V <36V; -40°C<T <150°C unless otherwise specified)
CC
j
(Per each channel)
Table 5. Power
Symbol
Parameter
Operating supply voltage
(**) Undervoltage shut-down
Test Conditions
Min.
5.5
3
Typ.
13
4
Max.
36
Unit
V
V
CC
(**)
V
USD
5.5
V
V
(**)
Overvoltage shut-down
On state resistance
Clamp Voltage
36
V
OV
I
I
I
1,2,3,4=5A; T =25°C
35
70
mΩ
mΩ
mΩ
OUT
OUT
OUT
j
R
1,2,3,4=5A; T =150°C
ON
j
1,2,3,4=3A; V =6V
CC
120
V
I
=20mA (see note 3)
CC
41
48
12
55
40
V
clamp
µA
Off State; V =13V; V =V
=0V
OUT
CC
IN
Off State; V =13V; V =V
=0V;
OUT
CC
IN
I (**)
S
Supply current
12
25
µA
T =25°C
j
On State; V =13V; V =5V; I =0A;
OUT
CC
IN
R
=3.9KΩ
SENSE
6
50
0
mA
µA
µA
µA
µA
I
I
I
I
Off state output current
Off State Output Current
Off State Output Current
Off State Output Current
V =V =0V
IN OUT
0
L(off1)
L(off2)
L(off3)
L(off4)
V =0V; V
IN
=3.5V
-75
OUT
V =V
IN
=0V; V =13V; T =125°C
5
OUT
OUT
CC
j
V =V
IN
=0V; V =13V; T =25°C
3
CC
j
Note: 3. V
and V are correlated. Typical difference is 5V.
OV
clamp
Note: (**) Per island.
Table 6. Switching (V =13V)
CC
Symbol
Parameter
Turn-on delay time
Turn-off delay time
Test Conditions
R =2.6Ω channels 1,2,3,4 (see fig. 1)
Min.
Typ.
40
Max.
Unit
µs
t
t
d(on)
L
R =2.6Ω channels 1,2,3,4 (see fig. 1)
L
40
µs
d(off)
See
relative
diagram
(dV
dt)
/
/
OUT
Turn-on voltage slope
Turn-off voltage slope
R =2.6Ω channels 1,2,3,4 (see fig. 1)
V/µs
V/µs
L
on
See
relative
diagram
(dV
dt)
OUT
R =2.6Ω channels 1,2,3,4 (see fig. 1)
L
off
Table 7. V - Output Diode
CC
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
F
Forward on Voltage
-I
=2.3A; T =150°C
0.6
V
OUT
j
5/20
VNQ600P-E
ELECTRICAL CHARACTERISTICS (continued)
Table 8. Logic Input
Symbol
Parameter
Low level input voltage
High level input voltage
Input hysteresis voltage
Input current
Test Conditions
Min.
Typ.
Max.
Unit
V
V
1.25
IL
V
IH
3.25
0.5
1
V
V
I(hyst)
V
I
V =1.5V
µA
µA
IL
IN
I
IN
Input current
V =3.5V
IN
10
8
I =1mA
IN
6
6.8
V
V
V
ICL
Input clamp voltage
I = -1mA
IN
-0.7
Table 9. Protections (See note 4)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
=13V
25
40
70
70
A
A
CC
I
lim
DC Short circuit current
5.5V<V <36V
CC
Thermal shut-down
temperature
T
150
175
15
200
°C
TSD
Thermal reset tempera-
ture
T
135
7
°C
°C
V
R
T
Thermal hysteresis
hyst
Turn-off output voltage
clamp
V
CC
-
V
CC
-
V
demag
I
I
=2A; L=6mH
V
-48
OUT
CC
41
55
Output voltage drop
limitation
V
=0.5A; T = -40°C...+150°C
50
mV
ON
OUT
j
Note: 4. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles.
6/20
VNQ600P-E
ELECTRICAL CHARACTERISTICS (continued)
Table 10. CURRENT SENSE (9V ≤ VCC ≤ 16V) (See Figure 5)
Symbol
Parameter
Test Conditions
=0.5A; V =0.5V;
SENSE
Min
Typ
Max
Unit
I
or I
OUT1
OUT2
K
1
I
/I
3300
4400
6000
OUT SENSE
other channels open; T = -40°C...150°C
j
I
or I
=0.5A; V
=0.5V;
SENSE
OUT1
OUT2
dK /K
Current Sense Ratio Drift
-10
+10
%
1
1
2
other channels open; T = -40°C...150°C
j
I
or I
=5A; V
SENSE
=4V; other
=4V; other
OUT1
OUT2
channels open; T =-40°C
K
2
I
/I
j
4200
4400
4900
4900
6000
5750
OUT SENSE
T =25°C...150°C
j
I
or I
=5A; V
OUT1
OUT2 SENSE
channels open;
dK /K
Current Sense Ratio Drift
-6
+6
%
%
2
T =-40°C...150°C
j
I
or I
=15A; V
SENSE
=4V; other
=4V; other
OUT1
OUT2
channels open; T =-40°C
j
K
3
I
/I
4200
4400
4900
4900
5500
5250
OUT SENSE
T =25°C...150°C
j
I
or I
=15A; V
OUT1
OUT2 SENSE
channels open;
dK /K
Current Sense Ratio Drift
-6
+6
3
3
T =-40°C...150°C
j
Max analog sense
output voltage
V
CC
V
CC
=5.5V; I
=2.5A; R =10kΩ
SENSE
2
4
V
V
OUT1,2
V
SENSE1,2
>8V, I
=5A; R
=10kΩ
SENSE
OUT1,2
Analog sense output
voltage in overtemperature
condition
V
CC
=13V; R
=3.9kΩ
SENSE
V
5.5
V
SENSEH
Analog Sense Output
Impedance in
Overtemperature
Condition
R
t
V
=13V; T >T ; All channels open
TSD
400
Ω
VSENSEH
CC
j
Current sense delay
response
to 90% I
(see note 5)
500
µs
DSENSE
SENSE
Note: 5. Current sense signal delay after positive input slope.
7/20
VNQ600P-E
Figure 5. I
/I
versus I
OUT SENSE
OUT
I
/I
OUT SENSE
6500
6000
5500
5000
4500
4000
3500
3000
max.Tj=-40°C
max.Tj=25...150°C
min.Tj=25...150°C
typical value
min.Tj=-40°C
0
2
4
6
8
10
12
14
16
I
(A)
OUT
Figure 6. Switching Characteristics (Resistive load R =2.6Ω)
L
V
OUT
90%
80%
dV
/dt
OUT (off)
dV /dt
OUT (on)
10%
t
f
t
r
t
t
t
I
SENSE
90%
t
DSENSE
INPUT
t
d(on)
t
d(off)
8/20
VNQ600P-E
Table 11. Truth Table (Per channel)
CONDITIONS
INPUT
OUTPUT
SENSE
L
L
0
Normal operation
Nominal
H
H
L
L
L
0
Overtemperature
Undervoltage
Overvoltage
H
V
SENSEH
L
L
L
0
0
H
L
L
L
0
0
H
L
H
H
L
L
L
0
Short circuit to GND
(T <T
) 0
j
TSD
(T >T
) V
j
TSD
SENSEH
L
H
H
0
Short circuit to V
CC
H
< Nominal
Negative output voltage
clamp
L
L
0
Table 12. Electrical Transient Requirements on V Pin
CC
ISO T/R 7637/1
Test Pulse
TEST LEVELS
III
I
II
IV
Delays and
Impedance
1
2
-25 V
+25 V
-25 V
-50 V
+50 V
-50 V
-75 V
+75 V
-100 V
+75 V
-6 V
-100 V
+100 V
-150 V
+100 V
-7 V
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
3a
3b
4
+25 V
-4 V
+50 V
-5 V
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
ISO T/R 7637/1
Test Pulse
TEST LEVELS RESULTS
I
II
C
C
C
C
C
E
III
C
C
C
C
C
E
IV
C
C
C
C
C
E
1
2
C
C
C
C
C
C
3a
3b
4
5
CLASS
CONTENTS
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
9/20
VNQ600P-E
Figure 7. Waveforms (Per each chip)
NORMAL OPERATION
INPUT
n
LOAD CURRENT
n
SENSE
n
UNDERVOLTAGE
V
CC
VUSDhyst
VUSD
INPUT
n
LOAD CURRENT
n
SENSE
n
OVERVOLTAGE
VOV
VCC < VOV
V
CC
VCC > VOV
INPUT
n
LOAD CURRENT
n
SENSE
n
SHORT TO GROUND
INPUT
n
LOAD CURRENT
n
LOAD VOLTAGE
n
SENSE
n
SHORT TO V
CC
INPUT
n
LOAD VOLTAGE
n
LOAD CURRENT
n
SENSE
n
<Nominal
<Nominal
OVERTEMPERATURE
TTSD
TR
T
j
INPUT
n
LOAD CURRENT
n
VSENSEH
SENSE
ISENSE
=
n
RSENSE
10/20
VNQ600P-E
Figure 8. Application Schematic
+5V
R
prot
INPUT1
V
CC1,2
V
CC3,4
D
ld
R
prot
OUTPUT1
OUTPUT2
C. SENSE 1
INPUT2
R
prot
µC
R
prot
C. SENSE 2
R
prot
INPUT3
OUTPUT3
OUTPUT4
R
prot
C. SENSE 3
INPUT4
R
prot
R
prot
C. SENSE 4
GND3,4
GND1,2
R
GND
R
SENSE1,2,3,4
D
GND
V
GND
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
GND PROTECTION NETWORK AGAINST
REVERSE BATTERY
Solution 1: Resistor in the ground line (R
can be used with any type of load.
only). This
GND
The following is an indication on how to dimension the
R
resistor.
GND
1) R
2) R
where -I
≤ 600mV / 2(I
).
S(on)max
Series resistor in INPUT line is also required to prevent
that, during battery voltage transient, the current exceeds
the Absolute Maximum Rating.
Safest configuration for unused INPUT pin is to leave it
unconnected, while unused SENSE pin has to be
connected to Ground pin.
GND
GND
≥ (−V ) / (-I
)
GND
CC
is the DC reverse ground pin current and can
GND
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in R
battery situations) is:
(when V <0: during reverse
CC
GND
LOAD DUMP PROTECTION
2
P = (-V ) /R
D
is necessary (Voltage Transient Suppressor) if the
D
CC
GND
ld
load dump peak voltage exceeds V
max DC rating.
CC
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
The same applies if the device will be subject to
transients on the V
line that are greater than the ones
CC
calculated with formula (1) where I
becomes the
S(on)max
shown in the ISO T/R 7637/1 table.
sum of the maximum on-state currents of the different
devices.
µC I/Os PROTECTION:
Please note that if the microprocessor ground is not
If a ground protection network is used and negative
common with the device ground then the R
will
GND
transients are present on the V line, the control pins will
CC
produce a shift (I
* R
) in the input thresholds
GND
S(on)max
be pulled negative. ST suggests to insert a resistor (R
in line to prevent the µC I/Os pins to latch-up.
)
prot
and the status output values. This shift will vary
depending on how many devices are ON in the case of
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
several high side drivers sharing the same R
.
GND
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2 (see
below).
Solution 2: A diode (D
A resistor (R
-V
/I
≤ R
≤ (V
-V -V
OHµC IH GND
) / I
CCpeak latchup
prot
IHmax
Calculation example:
) in the ground line.
GND
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
CCpeak
latchup
OHµC
=1kΩ) should be inserted in parallel to
GND
D
if the device will be driving an inductive load.
5kΩ ≤ R
≤ 65kΩ.
GND
prot
Recommended R
value is 10kΩ.
prot
11/20
VNQ600P-E
Figure 9. Off State Output Current
Figure 10. Low Level Input Current
Iil (µA)
6
IL(off1) (µA)
4
5.5
Vcc=13V
3.5
Vin=1.5V
Vcc=13V
5
3
4.5
4
2.5
2
3.5
3
1.5
1
2.5
2
0.5
0
1.5
1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 11. Input Clamp Voltage
Figure 13. Input High Level
Vicl (V)
10
Vih (V)
5
9.5
4.5
4
Iin=1mA
9
8.5
8
3.5
3
7.5
7
2.5
2
6.5
6
1.5
1
5.5
5
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 12. Input Low Level
Figure 14. Input Hysteresis Voltage
Vil (V)
4
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
3.5
3
2.5
2
0.9
0.8
0.7
0.6
0.5
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
12/20
VNQ600P-E
Figure 15. Overvoltage Shutdown
Figure 16. I
Vs T
LIM case
Ilim (A)
80
Vov (V)
55
52.5
50
70
60
50
40
30
20
10
0
Vcc=13V
47.5
45
42.5
40
37.5
35
32.5
30
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100 125 150 175
Tc (°C)
Tc (°C)
Figure 17. Turn-on Voltage Slope
Figure 19. Turn-off Voltage Slope
dVout/dt(off) (V/ms)
dVout/dt(on) (V/ms)
1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.9
Vcc=13V
Rl=2.6Ohm
Vcc=13V
0.8
Rl=2.6Ohm
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-50-25
0
25
50
75
100125150
175
-50
-25
0
25
50
75
100
125
150
175
Tc(°C)
Tc (°C)
Figure 18. On State Resistance Vs T
case
Ron (mOhm)
80
70
Vcc=13V
Iout=5V
60
50
40
30
20
10
0
-50
-25
0
25
50
75
100 125 150 175
Tc (°C)
13/20
VNQ600P-E
Figure 20. Maximum Turn Off Current Versus Load Inductance
LMAX (A)
I
100
A
B
C
10
1
0.001
0.01
0.1
1
10
100
L(mH)
A = Single Pulse at T
=150ºC
Jstart
B= Repetitive pulse at T
=100ºC
Jstart
C= Repetitive Pulse at T
=125ºC
Jstart
Conditions:
V
=13.5V
CC
Values are generated with R =0Ω
L
In case of repetitive pulses, T
(at beginning of each demagnetization) of every pulse must not exceed
jstart
the temperature specified above for curves B and C.
V , I
IN
L
Demagnetization
Demagnetization
Demagnetization
t
14/20
VNQ600P-E
SO-28 Thermal Data
Figure 21. SO-28 Double Island PC Board
Layout condition of R and Z measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
th
th
2
2
2
Cu thickness=35µm, Copper areas: 0.5cm , 3cm , 6cm ).
Table 13. Thermal Calculation According to the PCB Heatsink Area
Chip 1 Chip 2
Tjchip1
Tjchip2
Note
ON
OFF
ON
OFF
ON
ON
ON
R
R
R
x P
x P
+ T
R
R
R
x P
x P
+ T
thA
thC
thB
dchip1
amb
amb
thC
thA
thB
dchip1
amb
+ T
+ T
dchip2
dchip2
amb
x (P
+ P
) + T
x (P
+ P
) + T
P
P
=P
dchip1
dchip2
amb
dchip1
dchip2
amb
dchip1
dchip2
ON
(R
x P
) + R
dchip1
x P
+ T
(R x P
) + R x P
+ T
amb
≠P
thA
thC
dchip2
amb
thA
dchip2
thC
dchip1
dchip1
dchip2
Note:R
= Thermal resistance Junction to Ambient with one chip ON
thA
Note:R = Thermal resistance Junction to Ambient with both chips ON and P
=P
dchip2
thB
dchip1
Note:R
= Mutual thermal resistance
thC
Figure 22. R
Vs PCB Copper Area In Open Box Free Air Condition
thj-amb
RTHj_am b
(°C/W)
70
60
50
40
30
20
R
R
thA
thB
R
thC
10
0
1
2
3
4
5
6
7
PCB Cu heatsink area (cm^2)/island
15/20
VNQ600P-E
Figure 23. SO-28 Thermal Impedance Junction Ambient Single Pulse
Zth(°C/W)
100
0,5 cm ^2/is land
3 cm ^2/is land
6 cm ^2/is land
10
One channel ON
Two channels
ON on same chip
1
0.1
0.01
0.0001
0.001
0.01
0.1
time(s)
1
10
100
1000
Figure 24. Thermal Fitting Model of a Quad
Channels HSD in SO-28
Pulse Calculation Formula
= RTH δ + ZTHtp(1 – δ)
THδ
δ = tp ⁄ T
where
Tj_1
C1
C2
R2
C3
R3
C4
R4
C5
R5
C6
R6
R1
Pd1
Table 14. Thermal Parameter
C13
R13
C14
Area/island (cm2)
R1=R7=R13=R15 (°C/W)
R2=R8=R14=R16 (°C/W)
R3=R9 (°C/W)
0.5
0.05
0.3
3.4
11
6
Tj_2
R14
Pd2
R17
R18
R4=R10 (°C/W)
Tj_3
C7
R7
C8
C9
R9
C10
R10
C11
R11
C12
R12
R5=R11 (°C/W)
15
Pd3
R6=R12 (°C/W)
30
13
R8
C1=C7=C13=C15 (W.s/°C)
0.001
C15
R15
C16
Tj_4
C2=C8=C14=C16 (W.s/°C)
C3=C9 (W.s/°C)
5.00E-03
1.00E-02
0.2
R16
Pd4
C4=C10 (W.s/°C)
C5=C11 (W.s/°C)
C6=C12 (W.s/°C)
R17=R18 (°C/W)
1.5
T_amb
5
8
150
16/20
VNQ600P-E
PACKAGE MECHANICAL
Table 15. SO-28 Mechanical Data
Symbol
millimeters
Typ
Min
Max
A
a1
b
2.65
0.30
0.49
0.32
0.10
0.35
0.23
b1
C
0.50
c1
D
45 (typ.)
17.7
18.1
E
10.00
10.65
e
1.27
e3
F
16.51
7.40
0.40
7.60
1.27
L
S
8 (max.)
Figure 25. SO-28 Package Dimensions
17/20
VNQ600P-E
Figure 26. SO-28 Tube Shipment (no suffix)
Base Q.ty
28
700
532
3.5
Bulk Q.ty
Tube length (± 0.5)
C
B
A
B
13.8
0.6
C (± 0.1)
All dimensions are in mm.
A
Figure 27. Tape and Reel Shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
1000
1000
330
1.5
13
20.2
16.4
60
G (+ 2 / -0)
N (min)
T (max)
22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
W
P0 (± 0.1)
P
16
4
Tape Hole Spacing
Component Spacing
Hole Diameter
12
D (± 0.1/-0) 1.5
Hole Diameter
D1 (min)
F (± 0.05)
K (max)
1.5
7.5
6.5
2
Hole Position
Compartment Depth
Hole Spacing
P1 (± 0.1)
End
All dimensions are in mm.
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
18/20
VNQ600P-E
REVISION HISTORY
Table 16. Revision History
Date
Revision
Description of Changes
Oct. 2004
1
First issue.
19/20
VNQ600P-E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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