AT9932 [SUPERTEX]
Automotive Boost-Buck LED Lamp Driver IC;
| 型号： | AT9932 |
| 厂家： | 
Supertex, Inc |
| 描述： | Automotive Boost-Buck LED Lamp Driver IC |
| 文件： | 总10页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
AT9932
Automotive Boost-Buck
LED Lamp Driver IC
Features
General Description
The AT9932 is an advanced fixed frequency PWM
controller IC designed to control an LED lamp driver using
a boost-buck topology that can step the input voltage up
or down automatically. The IC provides fast output current
transient response and very low susceptibility to input
voltage transients, which allows the lamp driver to pass the
rigorous electrical transient requirements of SAE J1455 or
ISO 7637-2, making the AT9932 an ultimate solution for
automobile lighting. Capacitive isolation protects the LED
Lamp from failure of the switching MOSFET.
► Constant output current
► Steps output voltage up or down
► Very low susceptibility to Input voltage transients
► Frequency jitter
► Externally programmable fixed switching frequency
► Temperature foldback with external NTC resistor
► Internal 40V voltage regulator
► +/-1A MOSFET gate driver
► Short LED protection
► Open LED protection
The AT9932 features a unique feed-forward current control
scheme, differential output current sensing, soft start,
protection from short or open LED load. Switching frequency
can be programmed with a single external resistor.
► Input undervoltage protection
► Enable & PWM dimming
► Trimmed reference (±3% accurate)
► AEC-Q100 compliant
The AT9932 includes a temperature fold-back of the output
current using an external NTC resistor. This feature allows
maximizing the light output of the LED load over the entire
operating temperature range.
Applications
► Automobile lighting
► Battery powered LED lamps
► Other low voltage AC/DC or DC/DC LED drivers
Typical Application Circuit
C1
L2
L1
CO
Rd
CIN
Cd
M1
VIN
AVDD
GATE
FFP
RIN
D1
RP
ZD1
PVDD
LED(s)
RN
CVDD
FFN
REF
PWMD
UVLO
ROV
RFB
RT
RREF
RINC
FLT
FB
RT
RFLT
SS
RS
CSS
RDRP
PGND
GND
CREF
DRP
CC
RNTC
COMP
NTC
T1
R3
T2
R2
R1
CJTR
DIV
JTR
AT9932
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
AT9932
Ordering Information
24-Lead TSSOP
7.80x4.40mm body
1.20mm height (max)
0.65mm pitch
Device
AT9932
AT9932TS-G
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
24
1
Absolute Maximum Ratings
Parameter
VIN
REF
AVDD
PVDD
GATE
PGND
GND
JTR
Value
-0.5V to +45V
UVLO
NC
NC
DRP
FB
COMP
SS
PWMD
FLT
DIV
VIN to GND
PVDD, AVDD to GND voltage
GATE to GND voltage
All other pins to GND voltage
FFN, FFP current
-0.3V to +6.0V
-0.3V to (PVDD+0.3V)
-0.3V to (AVDD+0.3V)
+2.0mA
RT
FFN
FFP
T2
T1
NTC
REF current
+5.0mA
24-Lead TSSOP (TS)
Continuous Power Dissipation (TA = +25°C)
Junction temperature
1000mW*
-40°C to +150°C
-65°C to +150°C
(top view)
Product Marking
Storage temperature range
Top Marking
YY = Year Sealed
WW = Week Sealed
L = Lot Number
YYWW AAA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
9932TS
LLLLLLLL
C = Country of Origin*
A = Assembler ID
Bottom Marking
*
RθJA = 125OC/W (max.)
CCCCCCCCC
= “Green” Packaging
*May be part of ejector pin
Package may or may not include the following marks: Si or
24-Lead TSSOP (TS)
Electrical Characteristics (Specifications are at TA = 25OC, VIN = 12V, VPWMD = UVLO = AVDD = PVDD, GATE open, RT = 200KΩ,
CREF = 0.1µF, CAVDD = CPVDD = 1.0µF, IT1 = IT2 = 100µA unless otherwise noted.)
Sym
Input
Parameter
Min
Typ
Max
Units Conditions
VIN
IINEN
IINDIS
Input DC supply voltage range
Input supply current
-
*
*
5.3
-
-
-
40
2.0
100
V
---
-
-
mA
µA
PWMD = GND
Input current, UVLO mode
UVLO = GND, PWMD = GND
Internal Regulator
IDD = 0 - 20mA, VIN = 6.0 - 40V,
PWMD = GND
VDD
Regulated output voltage
*
4.65
5.00
5.35
V
∆VDD,OFF Hysteresis
-
-
250
-
-
mV
V
VDD falling
VDD rising
VDD,ON
Start voltage
*
4.25
4.85
Notes:
*
Specifications apply over the full operating ambient temperature range of -40ºC < TA < +125ºC. Guaranteed by design and characterization.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
2
AT9932
Electrical Characteristics (Specifications are at TA = 25OC, VIN = 12V, VPWMD = UVLO = AVDD = PVDD, GATE open, RT = 200KΩ,
CREF = 0.1µF, CAVDD = CPVDD = 1.0µF, IT1 = IT2 = 100µA unless otherwise noted.)
Sym
Description
Min
Typ
Max
Units Conditions
Reference
VREF
Reference output voltage
*
-
-
1.210
1.250
1.290
-
V
IREF = 0
Reference output voltage,
UVLO mode
VREF,DIS
∆VREF
-
0
-
mV
mV
UVLO = GND
IREF = 0 - 1.0mA
Load regulation
0
2.0
GATE Output
tR
tF
Gate output rise time
-
-
*
-
-
20
20
-
35
35
93
ns
ns
%
CGATE = 4.0nF,
VIN = AVDD= PVDD= 5.0V
Gate output fall time
Maximum duty cycle
DMAX
87
---
Feed-Forward Ramp Generator
tON(MIN)
tON(MAX)
Minimum GATE ON time
Maximum GATE ON time
*
*
250
6.0
-
-
400
13
ns
µs
IFFN = 500μA, IFFP = 0, VCOMP = 3.5V
IFFN = 10μA, IFFP = 0, VCOMP = 3.5V
IFFN = 110μA, IFFP = 10μA,
VCOMP = 3.5V
tON
GATE ON time
*
1.0
-
-
2.0
3.0
µs
%
∆tON/tON
FFN/FFP current balancing
#
-3.0
IFFN = 100μA, IFFP = 0, VCOMP = 3.5V
Transconductance Operation Amplifier
VFB, VDRP Input common-mode range
#
*
-0.3
-9.0
-
-
3.0
V
---
---
VOS
Gm
AV
Input offset voltage
Transconductance
-
9.0
mV
-
0.95
-
mA/V ---
Open loop voltage gain
Gain bandwidth product
COMP sink current
COMP source current
Input bias current
-
65
1.0
0.2
-0.2
-
-
-
-
-
dB
COMP open
GB
#
#
#
#
#
-
MHz CCOMP = 150pF
-
-
mA
mA
nA
V
VFB = 0.1V, COMP = GND
ICOMP
IBIAS
VCOMP
ILEAK
-
-
VFB = -0.1V, COMP = VDD
0.5
-
1.0
VDD
-
---
Output voltage range
Hiccup threshold
0.7
-
---
700
0.5
mV
nA
---
Output leakage current
#
-
1.0
PWMD = GND
Oscillator
fOSC1
*
90
105
505
-
120
583
800
kHz
kHz
kHz
RT = 1.0MΩ
RT = 200kΩ
---
Output frequency
fOSC2
*
427
100
fOSC
Output frequency range
#
Notes:
*
#
Specifications apply over the full operating ambient temperature range of -40ºC < TA < +125ºC. Guaranteed by design and characterization.
Specifications guaranteed by design and not tested in production
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
3
AT9932
Electrical Characteristics (Specifications are at TA = 25OC, VIN = 12V, VPWMD = UVLO = AVDD = PVDD, GATE open, RT = 200KΩ,
CREF = 0.1µF, CAVDD = CPVDD = 1.0µF, IT1 = IT2 = 100µA unless otherwise noted.)
Sym
Jitter
Description
Min
Typ
Max
Units Conditions
-
-
-
-
-
50
500
-
-
-
-
Hz
Hz
CJTR = 0.1µF
CJTR = 0.01µF
---
FJTR
Jitter frequency
ΔF
Change in switching frequency
±4.5
kHz
Temperature Foldback Circuit
INTC
NNTC
NT1
NTC current range
#
-
-
-
-
-
-
-
1.0
mA
---
NTC to DRP current gain
NTC to T1 current gain
NTC to T2 current gain
T1 and T2 reference voltage
0.13
3.0
6.0
3.5
-
-
-
-
-
-
INTC = 0.5mA
INTC = 0.5mA
INTC = 0.5mA
---
-
NT2
-
-
VT1, VT2
-
V
Soft Start
ISS,CHG
Charging current
Discharging current
Reset voltage
-
-
-
10
1.0
-
-
-
-
25
-
µA
mA
mV
---
ISS,DIS
VSS = 5.0V
---
VSS,RST
100
Fault Detect Comparator
VFLT
IBIAS
Trip voltage
-
-20
-
-
20
mV
nA
---
---
Input bias current
#
0.5
1.0
Input Under Voltage Lockout
Under voltage threshold
hysteresis
∆VUVLO
-
-
200
-
mV
UVLO falling
VUVLO,ON
IBIAS
Under voltage threshold
Input bias current
*
1.15
-
1.25
0.5
1.40
1.0
V
UVLO rising
---
#
nA
PWM Dimming
Enable voltage level
*
*
-
2.0
-
-
-
-
-
V
V
---
---
---
VEN, VPWM
Disable voltage level
Pull-down resistor
0.8
280
RPWMD
120
kΩ
Notes:
*
#
Specifications apply over the full operating ambient temperature range of -40ºC < TA < +125ºC. Guaranteed by design and characterization.
Specifications guaranteed by design and not tested in production
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
4
AT9932
Functional Block Diagram
VIN
REF
4.25V/
4.50V
Regulator
Current Mirror 2
-
S/D: INTC > 3I + 6IT2
Recovery: INTTC1 < 3IT1
T1
AVDD
+
IT1
+
FLT
INTC
T2
IT2
-
Reset
DIV
+
-
+
UVLO
1.25V/
1.45V
-
POR
NTC
4/30(INTC - 3IT1
)
OSC
RT
0.7V
-
+
DRP
JTR
Jitter
Gm
0.7V
PVDD
-
S
-
GATE
+
FB
R Q
+
PGND
COMP
PWMD
FFN
IP
15µA
IN - IP
Current
Mirror 1
SS
Reset
Reset
FFP
GND
IP
takes a voltage up to 40V. When VIN voltage is applied,
AT9932 seeks to maintain constant voltage at the AVDD pin.
When the under-voltage threshold is exceeded at AVDD, the
gate driver is enabled after a 100μs power-on reset (POR)
delay. The output of the gate driver (GATE) controls the gate
of an external N-channel power MOSFET. The maximum
duty cycle of the GATE signal is limited to 0.9(typ). The un-
der voltage protection comparator disables it when the volt-
age falls below the under voltage threshold.
Functional Description
Power Topology
The AT9932 is optimized to drive a continuous conduction
mode (CCM) boost-buck DC/DC converter topology com-
monly referred to as “Čuk converter”. (See the circuit dia-
gram on page 1.) This power converter topology offers nu-
merous advantages useful for driving high-brightness light
emitting diodes (HB LEDs). These advantages include step-
up or step-down voltage conversion ratio and low input and
output current ripple. The output load is decoupled from the
input voltage with a capacitor, making the driver inherently
failure-safe for the output load.
A separate PVDD input is provided to power the GATE
output to decouple the high switching currents of the gate
driver from AVDD. Both pins (AVDD, PVDD) must be wired
together on the printed circuit board (PCB). AVDD needs
to be bypassed to GND by a low ESR capacitor (≥0.1µF).
PVDD needs to be bypassed to PGND by a low ESR capaci-
tor (≥0.1µF).
The AT9932 features an optimal control method for use with
a boost-buck LED driver. This method achieves very low
susceptibility to input voltage transients, which makes it in-
dispensable for automotive LED lighting applications. The
AT9932 can maintain constant output current even under
vigorous input transient conditions. Its output current control
loop is inherently stable and can be compensated using a
single capacitor with the appropriate damping at the cou-
pling capacitor.
The input current drawn from the external power supply (or
VIN pin) is a sum of the 2.0mA (max) current drawn by the all
the internal circuitry and the current drawn by the gate driver
(which in turn depends on the switching frequency and the
gate charge of the external FET).
Regulator (VIN, AVDD) and Gate Driver (GATE, PVDD)
The AT9932 can be powered directly from its VIN pin that
IIN = 2.0mA + QG • fS
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5
AT9932
In the previous equation, fS is the switching frequency of output is disabled. This feature reduces power dissipation in
the converter and QG is the gate charge of the external FET the Zener diode ZD1 during open circuit condition.
(which can be obtained from the FET datasheet).
Soft Start (SS)
The soft start feature can determine the initial ramp-up of
the error voltage at the COMP pin. Connecting a single ca-
pacitor between SS to GND can program the soft-start time.
Upon the first applying voltage to the VDD pin, a current of
15μA is supplied from the SS pin gradually charging the soft
start capacitor. The COMP voltage is tracking the voltage at
the SS pin until regulation of the output current is reached.
When VDD falls below the under-voltage threshold, the soft
start capacitor is discharged rapidly.
Timing Resistor (RT)
The switching frequency fS is programmed by selecting an
external sense resistor RT. The resistance value can be com-
puted as:
1
RT =
fS • CT
where CT = 9.5pF.
Feed-Forward Ramp Generator (FFP, FFN) and PWM
Comparator
The heart of the AT9932 is the feed-forward circuit having
two inputs: FFN and FFP. This circuit generates a voltage
ramp proportional to the difference between the FFN and
FFP currents.
Jitter (JTR)
Clock frequency can be modulated by an externally pro-
grammed saw-tooth wave shape to reduce conducted elec-
tro-magnetic emission (EMI) from the LED driver. The devia-
tion of the oscillator frequency is set internally to ±5.0kHz.
The modulation frequency is programmed by connecting a
capacitor at JTR. The value of the capacitor required for the
jitter frequency is given by:
L2
L1
CD
C1
RD
5µF
D1
Q1
CJTR
=
VREF
FJTR(Hz)
RFFN
FFN
Note that the jitter frequency must be chosen to be signifi-
cantly lower than the cross over frequency of the closed loop
control. If not, the controller will not be able to reject the jitter
frequency and the LED current will have a current ripple at
the jitter frequency.
FFP
RFFP
CEFF
VCOMP - 0.7V
+
-
Reference Voltage (REF)
Figure 1. Feed-Forward Ramp Generator
The AT9932 provides a 1.25V reference voltage at the REF
pin. This voltage is used to derive the various internal volt-
ages required by the IC and is also used to set the LED cur-
rent externally. It should be bypassed with a low impedance
capacitor (0.01 -0.1μF).
As shown in Fig. 1, the resistor RFFN is connected between
FFN and the negative terminal of the coupling capacitor C1.
A resistor of the same value (RFFP = RFFN) is connected be-
tween FFP and GND. The on-time of the GATE output can
be computed as:
Internal 1.0MHz Transconductance Amplifier
The AT9932 includes a 1.0MHz transconductance amplifier,
which can be used to close the LED current feedback loop.
The output state of the amplifier is controlled by the signal
applied to the PWMD pin. When PWMD is high, the output
of the amplifier is connected to the COMP pin. When PWMD
is low, COMP is left open. This enables the integrating ca-
pacitor at the COMP pin to hold its charge when the PWMD
signal has turned off the gate drive. When the IC is enabled,
the voltage at COMP will be positioned for the converter to
return to its steady state condition.
RFFN • CEFF • (VCOMP - 0.7V)
tON
=
VC1
where CEFF = 50pF±40%, VCOMP is the COMP voltage, and
VC1 is the voltage across the coupling capacitor C1.
The duty cycle of a continuous conduction mode boost-buck
converter is given as:
VOUT
VC1
VOUT
D = tON • fS =
=
VOUT + VIN
When the voltage at COMP falls below 700mV, the GATE
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6
AT9932
where VIN is the input supply voltage, and VOUT is the forward
voltage of the LED string. Since the output voltage at COMP Programming LED Current and Temperature Foldback
is limited to VCOMP = VDD, the feed-forward resistors must be The AT9932 offers a temperature foldback feature that al-
selected in accordance with:
lows programming the output current in accordance with the
temperature derating characteristics provided by the LED
manufacturers. A typical derating curve is shown in Figure
2.
VOUT
RFFN = RFFP
≥
CEFF • fS • (VDD -0.7V)
Otherwise, the steady-state duty cycle D will not be reached,
and the LED driver will be unable to develop the desired
current.
I1
The feed-forward loop provides instantaneous response to
any transient at C1, and therefore achieves excellent rejec-
tion of the input voltage transients along the supply line. It is
inherently stable with proper selection of the damping net-
work Rd and Cd. Optimal selection of Rd and Cd is complex.
However, the worst case design of the damping circuit can
be performed under the assumption that VOUT(MAX) >> VIN(MIN)
for most automotive applications of the AT9932. The simpli-
fied equations given below produce very good results under
this assumption.
I2
T1
T2
Figure 2. Temperature Derating Curve of LED Current
AT9932
AVDD
FB
NTC
T1 DIV
T2
DRP REF
10KΩ
R6
R5
CREF
RS
2
9DMAX
L1 • IO
VIN(MIN)
Cd =
Rd =
•
(1 - DMAX
)
Figure 3. Output Current Feedback without Temperature
Foldback
VIN(MIN)
3DMAX O
I
When no temperature foldback is required, NTC and
T1 should be connected to AVDD, DIV and DRP should
be connected to GND. T2 still requires a resistor to GND
(10~100kΩ). No pins should be left floating. The DRP pin
can be connected to GND (Figure 3). In this case, the output
current of the AT9932 LED driver is programmed using the
following equation:
In the cases where the above assumption is not valid, the
equations for Rd and Cd could still be used. However, they
may produce somewhat too conservative results. Power dis-
sipation in the damping resistor Rd can be computed as:
2
∆VC1
PRd
=
12 • Rd
VREF
RS
R6
R5
I1 =
•
where:
where VREF is voltage at the REF pin (VREF = 1.25V).
IOUT • D
fS • C1
∆VC1 =
The same equation for calculating I1 is used when tempera-
ture fold-back is required, to calculate the current below T1.
is the peak-to-peak voltage ripple at the coupling capacitor
C1.
When an external NTC resistor is connected (Figure 4), both
temperatures T1 and T2, as well as the current I2 can be ac-
curately programmed to maximize the light output of the
LED lamp.
Output Over Voltage Protection
The AT9932 LED lamp driver supplies constant current to
the load. Therefore, an output circuit protection is needed to
prevent dramatic failures when the output load fails open. A
simple addition of a Zener diode (ZD1 in the Typical Applica-
tion Circuit on page 1) will limit the output voltage when the
output LED connection is lost.
The ratio of the resistor divider R2 /(R1 + R2) programs the
voltage at the NTC pin. The voltage at T1 is approximately
3.5V. The currents sourced by NTC and T1 are mirrored into
DRP in accordance with the following equation:
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
7
AT9932
tection comparator input is provided. Connecting a resistor
divider between VIN and GND programs the UVLO thresh-
olds as follows:
INTC
3
IDRP
=
– IT1 > 0
No current is sourced from DRP when INTC < 3 • IT1.
Temperature T1 is programmed by selecting R2 such that:
R2 = 3RNTC (T1)
(RIN1 + RIN2 ) • 1.25V
VIN(START)
=
RIN2
VIN(STOP) = 0.84 • VIN(START)
where RNTC(T1) is the resistance of the NTC resistor at the The hysteresis is provided to prevent oscillation.
temperature T1.
The AT9932 becomes disabled and draws less than 100µA
of current from VIN or VDD when the UVLO pin voltage falls
AT9932
NTC DIV
T1
T2
DRP
REF
FB
below the threshold. The 1.25V reference at the REF pin
becomes 0V at this condition. Hence, the UVLO input can be
also used as a low stand-by power disable input.
R1
R2
RNTC
R3
R4
R5
CREF
R6
RS
Fault Comparator (FLT)
Figure 4. Output Current Feedback with Temperature
Foldback
AT9932
REF
FLT
FB
Further reduction of the NTC resistance RNTC will create a
proportional offset of the current feedback reference at DRP,
and hence will cause decrease of the LED current. To pro-
gram the desired current I2 at the temperature T2, the resistor
R4 at DRP can be calculated as:
R52
R51
CREF
Figure 5. Output Short Circuit Protection
R6
RS
I2 • RS
R6 −
• R5
RNTC (T2)(R1 + R2 )
R2 - 3RNTC(T2 )
VREF
VREF
VT1
30
4
The AT9932 also provides an internal protection compara-
tor that can be used for protection against short and open
LED string conditions. When the voltage at the FLT input
falls below the GND potential, the AT9932 shuts down. The
soft-start capacitor at SS is discharged. Switching resumes
automatically after a POR delay.
R4 =
•
•
•
R5 + R6
where RNTC(T2) is resistance of the NTC resistor at the tem-
perature T2, and VT1 is voltage at the T1 pin (VT1 ≈ 3.5V).
When the current from the NTC pin exceeds (3 • IT1 + 6 •
IT2), over-temperature shutdown is triggered. The voltage at
T2 is approximately equal to the voltage at T1. Selecting re-
sistance of R3 at the T2 pin programs the desired shutdown
temperature T2.
Configuring the FLT input to protect against a short LED
string is illustrated by Figure 5. The short circuit current can
be calculated as:
VREF • R6 + R52
ISHORT
=
RS
R51
6RNTC(T2 ) • (R1 +R2 )
R3 =
R2 - 3RNTC(T2 )
The same resistor divider can be used to protect the LED
The over-temperature recovery threshold is independent of driver from the open LED condition, as shown in the sche-
the current in T2. The AT9932 recovers from thermal shut- matic diagram on Page 1. The addition of a Zener diode ZD1
down at the break temperature T1, where:
causes the FLT comparator to trip when VOUT > VZ.
INTC < 3 • IT1
Input Under Voltage Protection (UVLO)
To protect the AT9932 against excessive input current at low
input supply voltage, the under-voltage lockout (UVLO) pro-
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8
AT9932
Pin Description
Pin Name Description
1
2
VIN
This pin is the input of a 40V high voltage regulator.
This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to GND
(at least 0.1µF).
AVDD
This is the power supply pin for the gate driver. It should be connected externally to AVDD and bypassed
with a low ESR capacitor to PGND (at least 0.1µF).
3
PVDD
4
5
GATE This pin is the output gate driver for an external logic level N-channel power MOSFET.
PGND Ground return for the gate drive circuitry.
Ground return for all the low power analog internal circuitry. This pin must be connected to the return path
from the input.
6
GND
7
8
JTR
RT
This pin controls the jitter of the clock programmed by a capacitor connected at this pin.
Connecting an external resistor from this pin to GND sets the frequency of the oscillator circuit.
Connecting a resistor between this pin and a negative terminal of the coupling capacitor in the boost-buck
9
FFN converter programs positive PWM ramp signal. The slew rate is proportional to the current sunk from this
pin. When the ramp voltage exceeds the voltage at COMP, the GATE signal terminates.
Connecting a resistor between this pin and GND cancels the FFN current error due to non-zero voltage
at FFN. The FFN and FFP current mirrors are internally matched.
10
11
12
FFP
Connecting a resistor to this current output programs the over-temperature shutdown threshold tempera-
ture detected by an external NTC resistor.
T2
Connecting a resistor to this current input programs the temperature threshold beyond which the LED
current is reduced.
T1
Connect an external NTC resistor to this pin for temperature foldback of the output current and over-tem-
perature shutdown.
13
14
15
NTC
DIV
FLT
This is the reference input that programs the voltage at the NTC pin.
This pin is an input of the fault comparator. This comparator is used for open and short LED protection.
The IC shuts down and restarts after a POR delay when this comparator is triggered.
When this pin is pulled to GND (or left open), the GATE output is disabled. The COMP pin becomes high-
impedance and holds its voltage level. When this pin is logic-high, switching of GATE resumes.
16 PWMD
17
18
SS
Connecting a capacitor from this pin to GND programs the soft start time of the LED driver.
This pin is the output of the error amplifier. Stable closed-loop control of the output LED current can be
COMP achieved by connecting a compensation network between COMP and GND. This pin is pulled to GND
internally upon a start-up or detection of a fault condition.
This pin is the high impedance non-inverting input of the error amplifier. The output current reference is
19
20
FB
programmed by connecting a resistor divider between REF and the negative terminal of the current sense
resistor.
This is the output current reference input. Connect this pin to GND when no NTC derating is used. Con-
nect a resistor from this pin to GND to program temperature droop of the LED current.
DRP
21
22
NC
NC
No Connection.
This pin provides input under voltage protection. When voltage at this pin falls below its threshold, AT9932
halts switching, and the soft start capacitor is discharged rapidly. The voltage at the REF pin becomes 0V,
and the entire IC consumes quiescent current less ofthan 100μA. The switching resumes when the input
voltage exceeds the start-up threshold. Hysteresis is provided between the two thresholds.
23
24
UVLO
REF This pin provides accurate reference voltage. It must be bypassed with a 0.01-0.1μF capacitor to GND.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
9
AT9932
24-Lead TSSOP Package Outline (TS)
7.80x4.40mm body, 1.20mm height (max), 0.65mm pitch
D
24
θ1
E1
E
Gauge
Plane
L2
Note 1
(Index Area
D/2 x E1/2)
Seating
Plane
L
θ
L1
1
Top View
Side View
View B
A
View
B
A A2
Seating
Plane
e
b
A1
A
View A-A
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
A
0.85*
-
A1
0.05
-
A2
b
0.19
-
D
E
E1
e
L
L1
L2
θ
0O
-
θ1
MIN
0.80
1.00
1.15†
7.70
7.80
7.90
6.20*
6.40
6.60*
4.30
4.40
4.50
0.45
0.60
0.75
Dimension
(mm)
0.65
BSC
1.00
REF
0.25
BSC
12O
REF
NOM
MAX
1.20
0.15
0.30
8O
JEDEC Registration MS-153, Variation AD, Issue F, May 2001.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-24TSSOPTS, Version B041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2010 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-AT9932
B081110
10
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