MAS3529FBL [TDK]
Consumer Circuit, PBGA81, PLASTIC, LFBGA-81;
| 型号： | MAS3529FBL |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | Consumer Circuit, PBGA81, PLASTIC, LFBGA-81 |
| 文件： | 总90页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
MAS 35x9F
MPEG Layer 2/3,
AAC Audio Decoder,
G.729 Annex A Codec
Edition April 09, 2001
6251-505-3AI
MICRONAS
MAS 35X9F
ADVANCE INFORMATION
Contents
Page
Section
Title
5
5
6
7
1.
Introduction
1.1.
1.2.
1.3.
Features
Features of the MAS 35x9F Family
Application Overview
8
2.
Functional Description of the MAS 35x9F
Overview
8
2.1.
8
2.2.
Architecture of the MAS 35x9F
DSP Core
8
2.3.
8
2.3.1.
2.3.2.
2.3.2.1.
2.3.2.2.
2.4.
RAM and Registers
9
Firmware and Software
Internal Program ROM and Firmware, MPEG-Decoding
Program Download Feature
Audio Codec
9
9
9
9
2.4.1.
2.4.2.
2.4.2.1.
2.4.2.2.
2.4.2.3.
2.4.2.4.
2.4.3.
2.4.4.
2.5.
A/D Converter and Microphone Amplifier
Baseband Processing
9
9
Bass, Treble, and Loudness
Micronas Dynamic Bass (MDB)
Automatic Volume Control (AVC)
Balance and volume
9
10
10
10
10
11
11
11
11
11
12
12
14
15
15
15
15
15
15
15
16
16
16
16
17
17
17
D/A Converters
Output Amplifiers
Clock Management
2.5.1.
2.5.2.
2.6.
DSP Clock
Clock Output At CLKO
Power Supply Concept
Power Supply Regions
DC/DC Converters
2.6.1.
2.6.2.
2.6.3.
2.7.
Power Supply Configurations
Battery Voltage Supervision
Interfaces
2.8.
2.8.1.
2.8.2.
2.8.3.
2.8.4.
2.8.5.
2.8.6.
2.9.
I2C Control Interface
SPDIF Input Interface
S/PDIF Output
Multiline Serial Audio Input (SDI, SDIB)
Multiline Serial Output (SDO)
Parallel Input/Output Interface (PIO)
MPEG Synchronization Output
Default Operation
2.10.
2.10.1.
2.10.2.
2.10.3.
2.10.4.
2.10.5.
Stand-by Functions
Power-Up of the DC/DC Converters and Reset
Control of the Signal Processing
Start-up of the Audio Codec
Power-Down
2
Micronas
ADVANCE INFORMATION
MAS 35X9F
Contents, continued
Page
Section
Title
18
18
18
18
19
20
20
20
25
25
26
26
27
27
28
28
29
29
30
30
30
30
31
31
32
32
32
32
42
42
43
44
44
44
45
52
3.
I2C Interface
3.1.
General
3.1.1.
Device Address
3.1.2.
I2C Registers and Subaddresses
Naming Convention
3.1.3.
3.2.
Direct Configuration Registers
Write Direct Configuration Registers
Read Direct Configuration Register
DSP Core
3.2.1.
3.2.2.
3.3.
3.3.1.
Access Protocol
3.3.1.1.
3.3.1.2.
3.3.1.3.
3.3.1.4.
3.3.1.5.
3.3.1.6.
3.3.1.7.
3.3.1.8.
3.3.1.9.
3.3.1.10.
3.3.1.11.
3.3.1.12.
3.3.1.13.
3.3.1.14.
3.3.2.
Run and Freeze
Read Register (Code Ahex)
Write Register (Code Bhex)
Read D0 Memory (Code Chex)
Short Read D0 Memory (Code C4hex)
Read D1 Memory (Code Dhex)
Short Read D1 Memory (Code D4hex)
Write D0 Memory (Code Ehex)
Short Write D0 Memory (Code E4hex)
Write D1 Memory (Code Fhex)
Short Write D1 Memory (Code F4hex)
Clear SYNC Signal (Code 5hex)
Default Read
Serial Program Download
List of DSP Registers
3.3.3.
List of DSP Memory Cells
Application Select and Running
Application Specific Control
Ancillary Data
3.3.3.1.
3.3.3.2.
3.3.4.
3.3.5.
DSP Volume Control
3.3.6.
Explanation of the G.729 Data Format
Audio Codec Access Protocol
Write Codec Register
3.4.
3.4.1.
3.4.2.
Read Codec Register
3.4.3.
Codec Registers
3.4.4.
Basic MDB Configuration
53
53
55
58
58
58
58
58
58
59
4.
Specifications
4.1.
Outline Dimensions
4.2.
Pin Connections and Short Descriptions
Pin Descriptions
4.3.
4.3.1.
4.3.2.
4.3.3.
4.3.4.
4.3.5.
4.3.6.
Power Supply Pins
Analog Reference Pins
DC/DC Converters and Battery Voltage Supervision
Oscillator Pins and Clocking
Control Lines
Parallel Interface Lines
Micronas
3
MAS 35X9F
ADVANCE INFORMATION
Contents, continued
Page
Section
Title
59
59
59
59
59
59
59
59
60
61
63
65
65
66
69
70
72
74
76
77
78
79
80
84
85
87
88
4.3.6.1.
4.3.7.
4.3.8.
4.3.9.
4.3.10.
4.3.11.
4.3.12.
4.3.13.
4.3.14.
4.4.
PIO Handshake Lines
Serial Input Interface (SDI)
Serial Input Interface B (SDIB)
Serial Output Interface (SDO)
S/PDIF Input Interface
S/PDIF Output Interface
Analog Input Interfaces
Analog Output Interfaces
Miscellaneous
Pin Configurations
4.5.
Internal Pin Circuits
4.6.
Electrical Characteristics
4.6.1.
4.6.2.
4.6.3.
4.6.3.1.
4.6.3.2.
4.6.3.3.
4.6.3.4.
4.6.3.5.
4.6.3.6.
4.6.3.7.
4.6.4.
4.6.5.
4.6.6.
4.7.
Absolute Maximum Ratings
Recommended Operating Conditions
Digital Characteristics
I2C Characteristics
Serial (I2S) Input Interface Characteristics (SDI, SDIB)
Serial Output Interface Characteristics (SDO)
S/PDIF Input Characteristics
S/PDIF Output Characteristics
PIO as Parallel Input Interface: DMA Mode
PIO as Parallel Output Interface
Analog Characteristics
DC/DC Converter Characteristics
Typical Performance Characteristics
Typical Application in a Portable Player
Recommended DC/DC Converter Application Circuit
4.8.
90
5.
Data Sheet History
License Notice
MPEG 2 AAC technology is developed in cooperation with Fraunhofer IIS (http://www.iis.fhg.de)
Supply of this implementation of AAC technology does not convey a license nor imply any right to use this implemen-
tation in any finished end-user or ready-to-use final product. An independent license for such use is required.
contact: aacla@dolby.com
G.729 License Notice
Please contact:
Sipro Lab Telecom Inc.
email: patriciam@sipro.com
http://www.sipro.com
Fax: +1 (514) 737-2327
4
Micronas
ADVANCE INFORMATION
MAS 35X9F
MPEG Layer 2/3, AAC Audio Decoder,
G.729 Annex A Codec
1.1. Features
Firmware
Release Note: Revision bars indicate significant
changes to the previous edition. This data sheet
applies to MAS 35x9F version A2 .
– MPEG 1/2 layer 2 and layer 3 decoder
– Extension to MPEG 2 layer 3 for low bit rates
(“MPEG 2.5”)
1. Introduction
– Extraction of MPEG Ancillary Data
– MPEG 2 AAC2) decoder (low complexity profile)
– Master or slave clock operation
The MAS 35x9F is a single-chip, low-power MPEG
layer 2/3 and MPEG2-AAC audio stereo decoder. It
also contains the G.729 Annex A speech compression
and decompression technology for use in memory-
based or broadcast applications. Additional functional-
ity is achievable via download software (e.g. CELP
voice decoder, Micronas SC4 (ADPCM) encoder /
decoder)
– Adaptive bit rates (bit rate switching)
– Intelligent power management (processor clock is
dependent on sampling frequencies)
– Micronas G.729 Annex A speech compression and
decompression
The MAS 35x9F decoding block accepts compressed
digital data streams as serial bitstreams, or parallel for-
mat and provides serial PCM and/or S/PDIF output1)
of decompressed audio. In addition to the signal pro-
cessing function the IC incorporates a high-perfor-
mance stereo D/A converter, headphone amplifiers, a
stereo A/D converter, a microphone amplifier, and two
DC/DC converters.
– SDMI-compliant security technology
– Stereo channel mixer
– Bass, treble and loudness function
– Micronas Dynamic Bass (MDB)
– Automatic Volume Control (AVC)
Interfaces
Thus, the MAS 35x9F provides a true ’ALL-IN-ONE’
solution that is ideally suited for highly optimized mem-
ory based portable music players with integrated
speech decoding function.
– 2 serial asynchronous interfaces for bitstreams and
uncompressed digital audio
– Parallel handshake bit stream input
– Serial audio output via I2S and related formats
– S/PDIF data input and output
In MPEG 1 (ISO 11172-3), three hierarchical layers of
compression have been standardized. The most
sophisticated and complex, layer 3, allows compres-
sion rates of approximately 12:1 for mono and stereo
signals while still maintaining CD audio quality. Layer 2
(widely used in e.g. in DVD) achieves a compression of
8:1 without significant losses in audio quality.
– Controlling via I2C interface
Hardware Features
– Two independent embedded DC/DC converters
(e.g. for DSP and flash RAM supply)
The MAS 35x9F supports the ’Advanced Audio Cod-
ing’ (AAC) that is also defined as aprt of MPEG 2. AAC
provides compression rates up to 16:1. MPEG 2
defines several profiles for different applications. This
IC decodes the ’low complexity profile’ that is espe-
cially optimized for portable applications.
– Low DC/DC converter start-up voltage (0.9 V)
– DC converter efficiency up to 95 %
– Battery voltage monitor
– Low supply voltage (down to 2.5 V)
– Low power dissipation down to 70 mW
– High-performance RISC DSP core
– On-chip crystal oscillator
The MAS 35x9F also implements a voice encoder and
decoder that is compliant to the ITU Standard G.729
Annex A.
SC4 is a proprietary Micronas speech codec technol-
ogy that can be downloaded to the MAS 35x9F to
allow recording and playing back speech at various
sampling rates.
– Hardware power management and power-off func-
tions
– Microphone amplifier
– Stereo A/D converter for FM/AM-radio and speech
input
– CD quality stereo D/A converter
– Headphone amplifier
Micronas
5
MAS 35X9F
ADVANCE INFORMATION
– Noise and power-optimized volume
– External clock or crystal frequency of 13...20 MHz
– Standby current < 10 µA
1) Not yet supported in version A2
2) See License Note on page 4
1.2. Features of the MAS 35x9F Family
Feature
3509
X
3519
X
3529
3539
3549
3559
Layer 3 Decoder
G.729 Encoder/Decoder
AAC Decoder
X
X
X
X
X
X
X
X
6
Micronas
ADVANCE INFORMATION
MAS 35X9F
1.3. Application Overview
Fig. 1–1 depicts a portable audio application that is
power optimized. The two embedded DC/DC convert-
ers of the MAS 35x9F generate optimum power supply
voltages for the DSP core and also for state-of-the art
flash memories that typically require 2.7 to 3.3 V sup-
ply.
The following block diagram shows an example appli-
cation for the MAS 35x9F in a portable audio player
device. Besides a simple controller and the external
flash memories, all required components are inte-
grated in the MAS 35x9F. The MAS 35x9F supports
both speech and radio quality audio encoding, as well
as compressed-audio decoding tasks.
The performance of the DC/DC converters reaches
efficiencies up to 95 %.
Portable Digital Music Player
MAS 35x9F
optional
line in
Audio
baseband
features
D/A
A/D
DSP Core
MP3
AAC
G.729
Microphone
amplifier
Headphone
Headphone
amplifier
Volume
Optional
Software
optional
digital in
Downloads
digital out
S/PDIF or serial
S/PDIF
or
serial
Crystal
Osc./PLL
Battery
Voltage
Monitor
I2C
DC/DC1
DC/DC2
System clock
e.g. 2.5 V e.g. 3.0 V
e.g. 1.0 V
I2C
Display
µC
Keyboard
PC Connector
Fig. 1–1: Example application for the MAS 35x9F in a portable audio player device
Micronas
7
MAS 35X9F
ADVANCE INFORMATION
2. Functional Description of the MAS 35x9F
2.1. Overview
and appropriate interfaces. A hardware overview of the
IC is shown in Fig. 2–1.
The MAS 35x9F is intended for use in portable con-
sumer audio applications. It receives S/PDIF, parallel
or serial data streams and decodes MPEG Layer 2
and 3 (including the low sampling frequency exten-
sions) and MPEG 2 AAC. In addition, special down-
loadable software expands the function to a low-bitrate
CELP codec for speech recording. Other download
options (SDMI, other audio encoders/decoders) are
available on request. Compressed speech data may
be stored in an external memory via the parallel port.
2.3. DSP Core
The internal processor is a dedicated DSP for
advanced audio applications.
2.3.1. RAM and Registers
The DSP core has access to two RAM banks denoted
D0 and D1. All RAM addresses can be accessed in a
20-bit or a 16-bit mode via I2C bus. For fast access of
internal DSP states the processor core has an address
space of 256 data registers which can be accessed by
I2C bus. For more details please refer to Section 3.3.
on page 25.
2.2. Architecture of the MAS 35x9F
The hardware of the MAS 35x9F consists of a high-
performance RISC Digital Signal Processor (DSP),
Mic. Input
(incl. Bias)
Audio Codec
1
2
2
Audio
2
Output
Audio
Proc.
Line Input
A/D
MIX
D/A
DSP Core
Serial
Audio
S/PDIF Input 1
ALU
MAC
2
S/PDIF Input 2
Serial Audio
(I S, SDO)
Accumulators
ROM
S/PDIF
Output
2
(I S, SDI)
Serial Audio
(stream, SDIB)
Control
VBAT
Volt.
Mon.
I2C
DCCF
DCFR
DSP
I2C
Interface
D0
D1
control
Codec
Registers
V1
V2
Div.
Parallel
I/O Bus
(PIO)
Div.
CLKO
Xtal
18.432 MHz
PLL
Synth.
Osc.
Scaler
÷2
Synthesizer
Clock
Fig. 2–1: The MAS 35x9F architecture
8
Micronas
ADVANCE INFORMATION
MAS 35X9F
2.3.2. Firmware and Software
2.4. Audio Codec
2.3.2.1. Internal Program ROM and Firmware,
MPEG-Decoding
A sophisticated set of audio converters and sound fea-
tures has been implemented to comply with various
kinds of operating environments that range up to high-
end equipment (see Fig. 2–2 on page 10).
The firmware implemented in the program ROM of the
MAS 35x9F provides MPEG 1/2 Layer 2, MPEG 1/2
Layer 3 and MPEG 2 AAC-decoding as well as a
G.729 encoder and decoder.
2.4.1. A/D Converter and Microphone Amplifier
The DSP operating system starts the firmware in the
“Application Selection Mode”. By setting the appropri-
ate bit in the Application Select memory cell (see
Table 3–6 on page 33) the MPEG audio decoder or
the G.729 Codec can be activated.
A pair of A/D converters is provided for recording or
loop-through purposes. In addition, a microphone
amplifier including voltage supply function for an elec-
tret type microphone has been integrated.
The MPEG decoder provides an automatic standard
detection mode. If all MPEG audio decoders are
selected, the Layer 2, Layer 3 or AAC bitstream is rec-
ognized and decoded automatically.
2.4.2. Baseband Processing
The several baseband functions are applied to the dig-
ital audio signal immediately before D/A conversion.
To add/remove MPEG layers while running in MPEG
decoding mode (e.g. Layer 2, Layer 3 (0x0c) to
Layer 2, Layer 3, AAC (0x1c)), the application selec-
tion has to be reset before writing the new value.
2.4.2.1. Bass, Treble, and Loudness
Standard baseband functions such as bass, treble,
and loudness are provided.
For general control purposes, the operation system
provides a set of I2C instructions that give access to
internal DSP registers and memory areas.
2.4.2.2. Micronas Dynamic Bass (MDB)
An auxiliary digital volume control and mixer matrix is
applied to the digital stereo audio data. This matrix is
capable of performing the balance control and a simple
kind of stereo basewidth enhancement. All four factors
LL, LR, RL, and RR are adjustable, please refer to Fig.
3–3 on page 42.
The Micronas Dynamic Bass system (MDB) was
developed to extend the frequency range of loud-
speakers or headphones below the cutoff frequency of
the speakers. In addition to dynamically amplifying the
low frequency bass signals, the MDB exploits the psy-
choacoustic phenomenon of the ‘missing fundamen-
tal’. Adding harmonics of the frequency components
below the cutoff frequency gives the impression of
actually hearing the low frequency fundamental, while
at the same time retaining the loudness of the original
signal. Due to the parametric implementation of the
MDB, it can be customized to create different bass
effects and adapted to various loudspeaker character-
istics.
2.3.2.2. Program Download Feature
The standard functions of the MAS 35x9F can be
extended or substituted by downloading up to
4 kWords (1 Word = 20 bits) of program code and
additionally up to 4 kWords of coefficients into the
internal RAM .
Micronas
9
MAS 35X9F
ADVANCE INFORMATION
Mic-In
output level
dBr
Mic-Amplifier incl. Bias
Mono
A
−9
D
D
Line-In
A
−15
−21
Mixer
Q-peak
Mono/Stereo
AVC
Q-peak
−30
−24
−18
−12
−6
0
+6
input level
dBr
Bass/Treble
Audio
Codec
Loudness
MDB
Fig. 2–3: Simplified AVC characteristics
Right invert
D
2.4.2.4. Balance and volume
A
Volume
Balance
Output
D
To minimize quantization noise, the main volume con-
trol is automatically split into a digital and an analog
part. The volume range is −114...+12 dB with an addi-
tional mute position. A balance function is provided.
A
Fig. 2–2: Signal flow block diagram of Audio Codec
2.4.3. D/A Converters
2.4.2.3. Automatic Volume Control (AVC)
A pair of Micronas’ unique multibit sigma-delta D/A
converters is used to convert the audio data with high
linearity and a superior S/N. In order to attenuate high-
frequency noise caused by noise-shaping, internal
low-pass filters are included. They require additional
external capacitors between pins FILTx and OUTx.
In a collection of tracks from different sources fairly
often the average volume level varies. Especially in a
noisy listening environment the user must adjust the
volume to achieve a comfortable listening enjoyment.
The Automatic Volume Correction (AVC) solves this
problem by equalizing the volume level.
To prevent clipping, the AVC’s gain decreases quickly
in dynamic boost conditions. To suppress oscillation
effects, the gain increases rather slowly for low level
inputs. The decay time is programmable by means of
the AVC register (see Table 3–13 on page 45).
2.4.4. Output Amplifiers
The integrated output amplifiers are capable of directly
driving stereo headphones or loudspeakers of
16...32 Ω impedance via 22-Ω series resistors. If more
output power is required, the right output signal can be
inverted and a single loudspeaker can be connected
as a bridge between pins OUTL and OUTR. In this
case for optimized power the source should be set to
mono.
For input levels of -18 dBr to 0 dBr, the AVC maintains
a fixed output level of -9 dBr. Fig. 2–3 shows the AVC
output level versus its input level. For volume and
baseband registers set to 0 dB, a level of 0 dBr corre-
sponds to full scale input/output.
MASF
DAC
OUTL
DAC
OUTR
R ≥ 32 Ω
Fig. 2–4: Bridge operation mode
10
Micronas
ADVANCE INFORMATION
MAS 35X9F
2.5. Clock Management
2.6. Power Supply Concept
The MAS 35x9F is driven by a single crystal-controlled
clock with a frequency of 18.432 MHz. It is possible to
drive the MAS 35x9F with other reference clocks. In
this case, the nominal crystal frequency must be writ-
ten into memory location D0:348. The crystal clock
acts as a reference for the embedded synthesizer that
generates the internal clock.
The MAS 35x9F has been designed for minimal power
dissipation. In order to optimize the battery manage-
ment in portable players, two DC/DC converters have
been implemented to supply the complete portable
audio player with regulated voltages.
2.6.1. Power Supply Regions
For compressed audio data reception, the MAS 35x9F
may act either as the clock master (Demand Mode) or
as a slave (Broadcast Mode) as defined by bit 1 in
IOControlMain memory cell (see Table 3–7 on
page 34). In both modes, the output of the clock syn-
thesizer depends on the sample rate of the decoded
data stream as shown in Table 2–1.
The MAS 35x9F has five power supply regions.
The VDD/VSS pin pair supplies all digital parts includ-
ing the DSP core, the XVDD/XVSS pin pair is con-
nected to the digital signal pin output buffers, the
AVDD0/AVSS0 supply is for the analog output amplifi-
ers, AVDD1/AVSS1 for all other analog circuits like
clock oscillator, PLL circuits, system clock synthesizer
and A/D and D/A converters. The I2C interface has an
own supply region via pin I2CVDD. Connecting this to
the microcontroller supply assures that the I2C bus
always works as long as the microcontroller is alive so
that the operating modes can be selected.
In the BROADCAST MODE (PLL on), the incoming
audio data controls the clock synthesizer via a PLL.
In the DEMAND MODE (PLL off) the MAS 35x9F acts
as the system master clock. The data transfer is trig-
gered by a demand signal at pin EOD.
Beside these regions, the DC/DC converters have
start-up circuits of their own which get their power via
pin VSENSx.
2.5.1. DSP Clock
The DSP clock has separate divider. For power con-
servation it is set to the lowest acceptable rate of the
synthesizer clock which is capable to allow the proces-
sor core to perform all tasks.
Table 2–1: Settings of bits 8 and 17 in OutClkConfig
and resulting CLKO output frequencies
Output Frequency at CLKO/MHz
2.5.2. Clock Output At CLKO
Synth.
Scaler On
Scaler Plus
Clock bit 8=0, bit 17=0 Extra Division
fs/kHz
If the DSP or audio codec functions are enabled (bits
11 or 10 in the Control Register at I2C subaddress
6ahex), the reference clock at pin CLKO is derived from
the synthesizer clock.
bit 8=1
24.576
bit 8=0, bit 17=1
48
24.576
12.288
512 fs
256 fs
44.1
32
22.5792
22.5792
11.2896
Dependent on the sample rate of the decoded signal a
scaler is applied which automatically divides the clock-
out by 1, 2, or 4, as shown in Table 2–1. An additional
division by 2 may be selected by setting bit 17 of the
OutClkConfig memory cell (see Table 3–7 on
page 34). The scaler can be disabled by setting bit 8 of
this cell.
768 fs 24.576 384 fs 12.288
24.576
24
12.288
6.144
512 fs
256 fs
22.05 22.5792
16
11.2896
5.6448
768 fs 12.288 384 fs 6.144
24.576
12
6.144
3.072
The controlling at OutClkConfig is only possible as
long as the DSP is operational (bit 10 of the Control
Register). Settings remain valid if the DSP is disabled
by clearing bit 10.
512 fs
256 fs
11.025 22.5792
5.6448
2.8224
8
24.576 768 fs 6.144
384 fs 3.072
Micronas
11
MAS 35X9F
ADVANCE INFORMATION
2.6.2. DC/DC Converters
If both DC/DC-converters are off, a high signal may be
applied at pin DCEN. This will start the converters in
their default mode (PWM with 3.0 V output voltage).
The PUP signal will change from low to high when both
converters have reached their nominal output voltage
and will return to low when both converters output volt-
ages have dropped 200 mV below their programmed
output voltage. The signal at pin PUP can be used to
control the reset of an external microcontroller (see
Section 2.10.2. on page 16 for details on start up pro-
cedure).
The MAS 35x9F has two embedded high-performance
step-up DC/DC converters with synchronous rectifiers
to supply both the DSP core itself and external circuitry
such as a controller or flash memory at two different
voltage levels. An overview is given in Fig. 2–9 on
page 14.
The DC/DC converters are designed to generate an
output voltage between 2.0 V and 3.5 V which can be
programmed separately for each converter via the I2C
interface (see table 3.3). Both converters are of boot-
strapped type allowing to start up from a voltage down
to 0.9 V for use with a single battery or NiCd/NiMH cell.
The default output voltages are 3.0 V. Both converters
are enabled with a high level at pin DCEN and
enabled/disabled by the I2C interface.
If only DC/DC-converter 1 is used, the output of the
unused converter 2 (VSENS2) must be connected to
the output of converter 1 (VSENS1) to make the PUP
signal work properly. Also, if a DC/DC-converter is not
used (no inductor connected), the pin DCSO must be
left vacant.
The MAS 35x9F DC/DC converters feature a constant-
frequency, low noise pulse width modulation (PWM)
mode and a low quiescent current, pulse frequency
modulation (PFM) mode for improved efficiencies at
low current loads. Both modes – PWM or PFM – can
be selected independently for each converter via I2C
interface. The default mode is PWM.
2.6.3. Power Supply Configurations
One of the following supply configurations may be
used:
– Power-optimized solution (recommended opera-
tion). DC/DC 1 (e.g. 2.5 V) drives the MAS 35x9F
DSP and the audio circuitry, DC/DC 2 (e.g. 2.7 V)
supplies controller and flash (see Fig. 2–5 on
page 13)
In PWM mode the switching frequency of the power-
MOSFET-switches is derived from the crystal oscilla-
tor. Switching harmonics generated by constant fre-
quency operation are consistent and predictable.
When the audio codec is enabled the switching fre-
quency of the converters is synchronised to the audio
codec clock to avoid interferences into the audio band.
The actual switching frequency can be selected via the
I2C-interface between 300 kHz and 580 kHz (for
details see DCFR Register in Table 3–3 on page 21).
– Volume-optimized solution. DC/DC 1 (e.g. 2.7 V)
supplies controller, flash and MAS 35x9F audio
parts, DC/DC 2 generates e.g. 2.5 V for the
MAS 35x9F DSP (see Fig. 2–6 on page 13).
– Minimized external components. DC/DC 1 operates
on e.g. 2.7 V and feeds all components, DC/DC 2
remains off (see Fig. 2–7 on page 13).
In PFM operation mode the switching frequency is
controlled by the converters themself, it will be just
high enough to service the output load thus resulting in
the best possible efficiency at low current loads. PFM
mode does not need a clock signal from the crystal
oscillator. If both converters do not use the PWM-
mode, the crystal clock will be shut down as long it is
not needed from other internal blocks.
– External power supply. All components are powered
by an external source, no DC/DC converter is used
(see Fig. 2–8 on page 13).
If DC/DC converter 1 is used, it must supply the analog
circuits (pins AVDD0, AVDD1) of the MAS 35x9F.
If only one DC/DC converter is required, DC/DC1 must
be used. Pin DCSO2 must be left vacant, pin VSENS2
should be connected to pin VSENS1.
The synchronous rectifier bypasses the external
Schottky diode to reduce losses caused by the diode
forward voltage providing up to 5% efficiency improve-
ment. By default, the P-channel synchronous rectifier
switch is turned on when the voltage at pin(s) DCSOn
exceeds the converter’s output voltage at pin(s)
VSENSn and turns off when the inductor current drops
below a threshold. If one or both converters are dis-
abled, the corresponding P-channel switch will be
turned on, connecting the battery voltage to the DC/
DC converters output voltage at pin VSENSn. How-
ever, it is possible to individually disable both synchro-
nous rectifier switches by setting the corresponding
bits (bit 8 and 0 in DCCF-register).
If the DC/DC converters are not used, pin DCEN must
be connected to VSS, DCSOx must be left vacant.
12
Micronas
ADVANCE INFORMATION
MAS 35X9F
VSENS1
VSENS1
Flash
DC/DC 1
Flash
DC/DC1
on
on
e.g. 2.7 V
2
2
I CVDD
I CVDD
I2C
I2C
µC
µC
XVDD
VDD
XVDD
VDD
DSP
DSP
VSENS2
VSENS2
DC/DC 2
DC/DC2
on
off
AVDD0/1
AVDD0/1
Analog
Parts
Analog
Parts
e.g. 2.7 V
e.g. 2.5 V
Fig. 2–5: Solution 1: Power-optimized
Fig. 2–7: Solution 3: Minimized components
VSENS1
VSENS1
Flash
DC/DC1
Flash
DC/DC1
on
off
2
2
I CVDD
I CVDD
I2C
I2C
µC
µC
XVDD
VDD
VDD
DSP
DSP
XVDD
VSENS2
VSENS2
DC/DC2
DC/DC2
on
off
External
Supply
AVDD0/1
AVDD0/1
Analog
Parts
Analog
Parts
e.g. 2.7 V
e.g. 2.7 V
e.g. 2.5 V
Fig. 2–6: Solution 2: Volume-optimized
Fig. 2–8: Solution 4: External power supply
Micronas
13
MAS 35X9F
ADVANCE INFORMATION
battery
voltage
monitor
VBAT
supply
I2CVDD
to I2C interface
DCCF (76hex
output 1
)
L1
DCSO2
DCSG2
15
8
22 µH
DC/DC
converter 2
D1
VSENS2
+
C1
330 µF
−
set voltage
voltage
monitor
PUP2
Start
DCEN
PUP
S
V
in
+
−
frequency
divider
R
+
system
or crystal
clock
−
factor
voltage
monitor
3
0
DCFR (77hex
)
DC/DC
converter 1
DCCF (76hex
)
7
0
VSS
Fig. 2–9: DC/DC converter overview. The DCEN input must be connected to pin I2CVDD via the start-up push
button.
2.7. Battery Voltage Supervision
A battery voltage supervision circuit (at pin VBAT) is
provided which is independent of the DC/DC convert-
ers. It can be programmed to supervise one or two bat-
tery cells. The voltage is measured by subsequently
setting a series of voltage thresholds and checking the
respective comparison result in register 77hex
.
14
Micronas
ADVANCE INFORMATION
MAS 35X9F
2.8. Interfaces
In case of the Demand Mode (see Section 2.5.), the
signal clock coming from the data source must be
higher than the nominal data transmission rate (e.g.
128 kbit/s). Pin EOD is used to interrupt the data flow
whenever the input buffer of the MAS 35x9F is filled.
The MAS 35x9F uses an I2C control interface, a serial
input interface for MPEG bit streams, and a digital
audio output interface for the decoded audio data (I2S
or similar). Alternatively, SPDIF input and output inter-
faces can be used. A parallel I/O interface (PIO) may
be used for fast data exchange.
For controlling details please refer to Table 3–7 on
page 34.
2.8.1. I2C Control Interface
2.8.5. Multiline Serial Output (SDO)
For controlling and program download purposes, a
standard I2C slave interface is implemented. A detailed
description of all functions can be found in Section 3.
The serial audio output interface of the MAS 35x9F is
a standard I2S-like interface consisting of the data
lines SOD, the word strobe SOI and the clock signal
SOC. It is possible to choose between two standard
interface configurations (16-bit data words with word
strobe time offset or 32-bit data words with inverted
SOI-signal).
2.8.2. SPDIF Input Interface
The SPDIF interface receives a one-wire serial bus
signal. In addition to the signal input pin SPDI1/SPDI2,
a reference pin SPDIR is provided to support balanced
signal sources or twisted pair transmission lines.
If the serial output generates 32 bits per audio sample,
only the first 20 bits will carry valid audio data. The
12 trailing bits are set to zero by default.
The synchronization time on the input signal is
< 50 ms.
2.8.6. Parallel Input/Output Interface (PIO)
The SPDIF input signal can also be switched to the
SPDO pin. In this case the analog input circuit of the
SPDIF inputs (see Fig. 4–19 on page 64) restores the
SPDIF input signal to a full swing signal at SPDO.
The parallel interface of the MAS 35x9F consists of the
8 data lines PI12...PI19 (MSB) and the control lines
PCS, PR, PRTR, PRTW, and EOD. It can be used for
data exchange with an external memory, for fast pro-
gram download and for other special purposes as
defined by the DSP software.
For controlling details please refer to Table 3–7 on
page 34.
For MPEG-data input, the PIO interface is activated by
setting bits 9,8 in D0:346 to 01. For the handshake
protocol please refer to Section 4.6.3.6. on page 78
2.8.3. S/PDIF Output
In the next version of the IC the S/PDIF output of the
baseband audio signals will be provided at pin SPDO.
2.8.4. Multiline Serial Audio Input (SDI, SDIB)
There are two multiline serial audio input interfaces
(SDI, SDIB) each consisting of the three pins SI(B)C,
SI(B)I, and SI(B)D. The standard firmware only sup-
ports SDIB for bitstream signals.
The interfaces can be configured as continuous bit
stream or word-oriented inputs. For the MPEG bit-
streams the word strobe pin SIBI must always be con-
nected to VSS, bits must be sent MSB first as created
by the encoder.
If the optional downloadable software uses the inputs
for PCM data, the interface acts as a I2S-type with
SI(B)I as a word strobe.
Micronas
15
MAS 35X9F
ADVANCE INFORMATION
2.9. MPEG Synchronization Output
2.10.Default Operation
The signal at pin SYNC is set to ‘1’ after the internal
decoding for the MPEG header has been finished for
one frame. The rising edge of this signal can be used
as an interrupt input for the controller that triggers the
read out of the control information and ancillary data.
As soon as the MAS 35x9F has received the SYNC
reset command (see Section 3.3.1.12. on page 30),
the SYNC signal is cleared. If the controller does not
issue a reset command, the SYNC signal returns to ’0’
as soon as the decoding of the next MPEG frame is
started. MPEG status and ancillary data become
invalid until the frame is completely decoded and the
signal at pin SYNC rises again. The controller must
have finished reading all MPEG information before it
becomes invalid. The MPEG Layer 2/3 frame lengths
are given in Table 2–2. AAC has no fixed frame length.
This sections refers to the standard operation mode
”power-optimized solution” (see Section 2.6.3.).
2.10.1.Stand-by Functions
After applying the battery voltage, the system will
remain stand-by, as long as the DCEN pin level is kept
low. Due to the low stand-by current of CMOS circuits,
the battery may remain connected to DCSOn/VSENSn
at all times.
2.10.2.Power-Up of the DC/DC Converters and
Reset
The battery voltage must be applied to pin DCSOn via
the 22-µH inductor and, furthermore, to the sense pin
VSENSn via a Schottky diode (see Fig. 2–9 on
page 14).
tframe = 24...72 ms
For start-up, the pin DCEN must be connected via an
external “start” push button to the I2CVDD supply,
which is equivalent to the battery supply voltage
(> 0.9 V) at start-up.
V
V
h
tread
l
Fig. 2–10: Schematic timing of the signal at pin SYNC.
The signal is cleared at tread when the controller has
issued a Clear SYNC Signal command (see Section
3.3.1.12. on page 30). If no command is issued, the
signal returns to ’0’ just before the decoding of the next
MPEG frame.
The supply at DCEN must be applied until the DC/DC
converters have started up (signal at pin PUP) and
then removed for normal operation.
As soon as the output voltage at VSENSn reaches the
default voltage monitor reset level of 3.0 V, the respec-
tive internal PUPn bit will be set. When both PUPn bits
are set, the signal at pin PUP will go high and can be
used to start and reset the microcontroller.
Table 2–2: Frame length in MPEG Layer 2/3
fs/kHz
Frame Length
Layer 2
Frame Length
Layer 3
Before transmitting any I2C commands, the controller
must issue a power-on reset to pin POR. The separate
supply pin I2CVDD assures that the I2C interface
works indepentently of the DSP or the audio codec.
Now the desired supply voltage can be programmed at
48
24 ms
24 ms
44.1
32
26.12 ms
36 ms
26.12 ms
36 ms
I2C subaddress 76hex
.
The signal at pin PUP will return to low only when both
PUPn flags (I2C subaddress 76hex) have returned to
zero. Care must be taken when changing both DC/DC
output voltages to higher values. In this case, both out-
put voltages are momentarily insufficient to keep the
PUPn flags up; the resulting dip in the signal at the
PUP pin may in turn reset the microcontroller. To avoid
this condition, only one DC/DC output voltage should
be changed at a time. Before modifying the second
voltage, the microcontroller must wait for the PUPn flag
of the first voltage to be set again.
24
24 ms
24 ms
22.05
16
26.12 ms
36 ms
26.12 ms
36 ms
12
not available
not available
not available
48 ms
11.025
8
52.24 ms
72 ms
The operating mode (pulse width modulation or pulse
frequency modulation, synchronized rectifier for higher
efficiency) are controlled at I2C subaddress 76hex, the
operating frequency at I2C subaddress 77hex
.
16
Micronas
ADVANCE INFORMATION
MAS 35X9F
2.10.3.Control of the Signal Processing
2.10.5.Power-Down
Before starting the DSP, the controller should check for
a sufficient voltage supply (respective flag PUPn at I2C
subaddress 76hex). The DSP is enabled by setting the
appropriate bit in the Control register (I2C subaddress
6ahex). The nominal frequency of the crystal oscillator
must be written into D0:348. After an initialization
phase of 5 ms, the DSP data registers can be
accessed via I2C.
All analog outputs should be muted and the A/D and
the D/A converters must be switched off (register
00 10hex and 00 00hex at I2C subaddress 6chex). The
DSP and the audio codec must be disabled (clear
DSP_EN and CODEC_EN bits in the Control register,
I2C subaddress 6ahex). By clearing both DC/DC
enable flags in the Control register (I2C subaddress
6ahex), the microcontroller can power down the com-
plete system.
Input and output control is performed via memory loca-
tion D0:346 and D0:347. The serial input interface
SDIB is the default. The decoded audio can be routed
to either the SPDIF, the SDO and the analog outputs.
The output clock signal at pin CLKO is defined in
D0:349.
All changes in the D0-memory cells become effective
synchronously upon setting the LSB of Main I/O Con-
trol (see Table 3–7 on page 34). Therefore, this cell
should always be written at last.
The digital volume control (see Table 3–7 on page 34)
is applied to the output signal of the DSP. The
decoded audio data will be available at the SPDO out-
put interface in the next version.
The DSP does not have to be started if its functions
are not needed, e.g. for routing audio via the A/D and
the D/A converters through the codec part of the IC.
2.10.4.Start-up of the Audio Codec
Before enabling the audio codec, the controller should
check for a sufficient voltage supply (respective flag
PUPn at I2C subaddress 76hex).
The audio codec is enabled by setting the appropriate
bit at the Control register (I2C subaddress 6ahex). After
an initialization phase of 5 ms, the DSP data registers
can be accessed via I2C.The A/D and the D/A convert-
ers must be switched on explicitly (00 00hex at I2C sub-
address 6chex). The D/A converters may either accept
data from the A/D converters or the output of the DSP,
or a mix of both1) (register 00 06hex and 00 07hex at I2C
subaddress 6chex). Finally, an appropriate output vol-
ume (00 10hex at I2C subaddress 6chex) must be
selected.
1) mixer available in version A2 and later; in version A1
please use selector 00 0fhex
.
Micronas
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MAS 35X9F
ADVANCE INFORMATION
3. I2C Interface
Table 3–2: I2C subaddresses
3.1. General
Sub-
address Register
(hex) Name
I2C-
Function
3.1.1. Device Address
Controlling the MAS 35x9F is done via an I2C slave
interface. The device addresses are 3C/3Ehex (device
write) and 3D/3Fhex (device read) as shown in
Table 3–1. The device address pair 3C/3Dhex applies if
the DVS pin is connected to VSS, the device address
pair 3E/3Fhex applies if the DVS pin is connected to
VDD.
Direct Configuration
6A
CON-
TROL
Controller writes to
MAS 35x9F control register
76
DCCF
Controller writes to first
DC/DC configuration regis-
ter
Table 3–1: I2C device address
77
DCFR
Controller writes to
second DC/DC config reg.
A7
0
A6
0
A5
1
A4
1
A3
1
A2
1
A1
W/R
DSP Core Access
DVS 0/1
68
DATA
(WRITE)
Controller writes to
MAS 35x9F DSP
I2C clock synchronization is used to slow down the
interface if required.
69
DATA
(READ)
Controller reads from
MAS 35x9F DSP
3.1.2. I2C Registers and Subaddresses
Codec Access
6C
CODEC
(WRITE)
Controller writes to
MAS 35x9F codec register
The interface uses one level of subaddresses. The
MAS 35x9F interface has 7 subaddresses allocated for
the corresponding I2C registers. The registers can be
divided into three categories as shown in Table 3–2.
6D
CODEC
(READ)
Controller reads from
MAS 35x9F codec register
The address 6Ahex is used for basic control, i.e. reset
and task select. The other addresses are used for data
transfer from/to the MAS 35x9F.
The I2C registers of the MAS 35x9F are 16 bits wide,
the MSB is denoted as bit[15]. Transmissions via I2C
bus have to take place in 16-bit words (two byte trans-
fers, MSB sent first); thus, for each register access,
two 8-bit data words must be sent/received via I2C
bus.
18
Micronas
ADVANCE INFORMATION
MAS 35X9F
3.1.3. Naming Convention
codec_read 6Dhex
– Bus signals
The description of the various controller commands
uses the following formalism:
S
P
A
N
Start
Stop
– Abbreviations used in the following descriptions:
ACK = Acknowledge
NAK = Not acknowledge
a
d
n
o
r
address
data value
count value
offset value
register number
don’t care
W Wait = I2C Clockline is held low,
while the MAS 35x9F is processing the
I2C protocoll
– Symbols in the telegram examples
x
<
>
Start Condition
Stop
– A data value is split into 4-bit nibbles which are num-
bered beginning with 0 for the least significant nib-
ble.
dd
xx
data bytes
ignore
All telegram numbers are hexadecimal, data origi-
nating from the MAS 35x9F are greyed.
Example:
– Data values in nibbles are always shown in hexa-
decimal notation.
<DW 68 dd dd>
<DW 69 <DR dd dd> read data from DSP
write data to DSP
– A hexadecimal 20-bit number d is written, e.g. as
d = 17C63hex, its five nibbles are
and stop with NAK
d0 = 3hex, d1 = 6hex, d2 = Chex, d3 = 7hex, and
d4 = 1hex
.
Fig. 3–1 shows I2C bus protocols for write and read
operations of the interface; the read operations require
an extra start condition and repetition of the chip
address with the device read command (DR). Fields
with signals/data originating from the MAS 35x9F are
marked by a gray background. Note that in some
cases the data reading process must be concluded by
a NAK condition.
– Variables used in the following descriptions:
I2C address:
DW
DR
DSP core:
data_write 68hex
data_read 69hex
Codec:
3C/3Ehex
3D/3Fhex
codec_write 6Chex
Example: I2C write access
S
DW
A
subaddress
subaddress
A
A
high data word
A
low data word
A
P
Example: I2C read access
DW
S
A
S
DR
A
high data word
low data word
A
N
P
SDA
SCL
1
0
A
= 0 (ACK)
= 1 (NAK)
N
S
P
P
S
=
Start
Stop
=
Fig. 3–1: Example of an I2C bus protocol for the MAS 35x9F (MSB first; data must be stable while clock is high)
Micronas
19
MAS 35X9F
ADVANCE INFORMATION
3.2. Direct Configuration Registers
The task selection of the DSP and the DC/DC converters are controlled in the direct configuration registers Control,
DCCF, and DCFR.
3.2.1. Write Direct Configuration Registers
S
A
A
A
A
P
DW
subaddress
d3,d2
d1,d0
The write protocol for the direct configuration registers only consists of device address, subaddress and one 16-bit
data word.
3.2.2. Read Direct Configuration Register
1) send subaddress
S
A
A
A
P
S
DW
subaddress
subaddress
2) get register value
A
A
S
DW
DR
A
N
P
d3,d2
d1,d0
To check the PUP1 and PUP2 power-up flags, it is necessary to read back the content of the direct configuration reg-
isters.
20
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–3: Direct Configuration Registers
I2C Sub-
address
(hex)
Function
Name
6A
Control Register (reset value = 3000hex
)
CONTROL
bit[15:14]
Analog Supply Voltage Range
Code
00
01
10
11
AGNDC
1.1 V
1.3 V
1.6 V
reserved
recommended for voltage range of AVDD
2.0 ... 2.4 V (reset)
2.4 ... 3.0 V
3.0 ... 3.6 V
reserved
Higher voltage ranges permit higher output levels and thus a better signal-to-
noise ratio.
bit[13]
bit[12]
enable DC/DC 2 (reset=1)
enable DC/DC 1 (reset=1)
Both DC/DC converters are switched on by default.
bit[11]
bit[10]
enable and reset audio codec
enable and reset DSP core
For normal operation (MPEG-decoding and D/A conversion), both, the DSP
core and the audio codec have to be enabled after the power-up procedure.
The DSP can be left off if an audio signal is routed from the analog inputs to
the analog outputs (set bit[15] in codec register 00 0Fhex). The audio codec
can be left off if the DSP uses digital inputs and outputs only.
bit[9]
bit[8]
reset codec
reset DSP core
bit[7]
bit[6]
bit[5]
bit[4]
disable task 7 of DSP core
disable task 6 of DSP core
disable task 5 of DSP core
disable task 4 of DSP core
bit[3]
bit[2]
bit[1]
bit[0]
set task 3 of DSP core
set task 2 of DSP core
set task 1 of DSP core
set task 0 of DSP core
bit[7] 1)
enable XTAL input clock divider
(extended crystal range up to 28 MHz)
reserved, must be set to zero
bit[6:0] 1)
bit[15:8]
6B 1)
reserved, must be set to zero
DSP_TASK
bit[7]
bit[6]
bit[5]
bit[4]
disable task 7 of DSP core
disable task 6 of DSP core
disable task 5 of DSP core
disable task 4 of DSP core
bit[3]
bit[2]
bit[1]
bit[0]
set task 3 of DSP core
set task 2 of DSP core
set task 1 of DSP core
set task 0 of DSP core
Unless downloaded optional software is used, the bits 7...0 must be set to
zero.
1) available in the next version
Micronas
21
MAS 35X9F
ADVANCE INFORMATION
Table 3–3: Direct Configuration Registers
I2C Sub-
address
(hex)
Function
Name
76
DCCF Register (reset = 5050hex
)
DCCF
DC/DC Converter 2
bit[15]
PUP2: Voltage monitor 2 flag (readback)
Voltage between VSENS2 and DCSG2
bit[14:11]
Code
Nominal
output volt. of PUP2
set level
reset level
of PUP2
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V (reset)
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
2.0 V
1111
1110
3.5 V
3.4 V
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
3.4 V
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
1101
1100
1011
1010
1001
1000
0111
0110
0101
01001)
00111)
00101)
bit[10]
Mode
1
0
Pulse frequency modulation (PFM)
Pulse width modulation (PWM) (reset)
bit[9]
bit[8]
reserved, must be set to zero
Disable synchronized rectifier
1
0
disable synchronized recitifier
enable synchronized recitifier (reset)
The DC/DC converters are up-converters only. Thus, if the battery voltage is
higher than the selected nominal voltage, the output voltage will exceed the
nominal voltage.
1) refer to Section 4.6.2. on page 66
22
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–3: Direct Configuration Registers
I2C Sub-
address
(hex)
Function
Name
76
DC/DC Converter 1
(continued)
bit[7]
PUP1: Voltage monitor 1 flag (readback)
bit[6:3]
bit[2]
Voltage between VSENS1 and DCSG1 (see table above)
Mode
1
0
Pulse frequency modulation (PFM)
Pulse width modulation (PWM) (reset)
bit[1]
bit[0]
reserved, must be set to zero
Disable synchronized rectifier
1
0
disable synchronized recitifier
enable synchronized recitifier (reset)
Note, that the reference voltage for DC/DC converter 1 is derived from the
main reference source supplied via pin AVDD1. Therefore, if this DC/DC con-
verter is used, its output must be connected to the analog supply.
The DC/DC converters are up-converters only. Thus, if the battery voltage is
higher than the selected nominal voltage, the output voltage will exceed the
nominal voltage.
Micronas
23
MAS 35X9F
ADVANCE INFORMATION
Table 3–3: Direct Configuration Registers
I2C Sub-
address
(hex)
Function
Name
77
DCFR Register (reset = 00hex
)
DCFR
Battery Voltage Monitor
bit[15]
Comparison result (readback)
1
0
input voltage at pin VBAT above defined threshold
input voltage at pin VBAT below defined threshold
bit[14]
Number of battery cells
0
1
1 cell (range 0.8...1.5 V) (reset)
2 cells (range 1.6...3.0 V)
bit[13:10]
Voltage threshold level
1 cell
2 cells
3.0 V
2.9 V
1111
1110
...
1.5
1.45
0010
0001
0000
0.85
0.8
1.7 V
1.6 V
Battery voltage supervision off (reset)
bit[9:8]
Reserved, must be set to 0
The result is stable after 1 ms after enabling. The setup time for switching
between two thresholds is negligibly small.
For power management reasons, the battery voltage monitor should be
switched off by setting bit[13:10] to zero when the measurement is completed.
DC/DC Converter Frequency Control (PWM)
bit[7:4]
bit[3:0]
Reserved, must be set to 0
Frequency of DC/DC converter
Reference: 24.576 22.5792 18.432 MHz
0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000
315.1
323.4
332.1
341.3
351.1
361.4
372.4
384.0
396.4
409.6
423.7
438.9
455.1
472.6
491.5
512.0
289.5
297.1
305.1
313.6
322.6
332.0
342.1
352.8
364.2
376.3
389.3
403.2
418.1
434.2
451.6
470.4
297.3 kHz
307.2 kHz
317.8 kHz
329.1 kHz
341.3 kHz
354.5 kHz
368.6 kHz
384.0 kHz (reset)
400.7 kHz
418.9 kHz
438.9 kHz
460.8 kHz
485.1 kHz
512.0 kHz
542.1 kHz
576.0 kHz
If the audio codec is not enabled (bit 11 of the Control register at I2C-subad-
dress 6Ahex is zero), the clock for the DC/DC converters is directly derived
from the crystal frequency (nominal 18.432 MHz). Otherwise, the synthesizer
clock is used as the reference (please refer to the respective column in
Table 2–1 on page 11).
24
Micronas
ADVANCE INFORMATION
MAS 35X9F
3.3. DSP Core
also provides a download option for alternative soft-
ware modules.
The DSP Core of the MAS 35x9F has two RAM banks
denoted D0 and D1. The word size is 20 bits. All RAM
addresses can be accessed in a 20-bit or a 16-bit
mode via I2C bus. For fast access of internal DSP
states, the processor core also has an address space
of 256 data registers. All register and RAM addresses
are given in hexadecimal notation.
The MAS 35x9F firmware scans the I2C interface peri-
odically and checks for pending or new commands.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected. The theoretical worst case response time
does not exceed 4 ms. However, the typical response
time is less than 0.5 ms.
3.3.1. Access Protocol
Table 3–4 gives an overview over the different com-
mands which the DSP Core receives via the I2C data
register. The “Code” is always the first data nibble
transmitted after the “data_write” subaddress byte. A
second auxiliary code nibble is used for the short
memory (16-bit) access commands.
The access of the DSP Core in the MAS 35x9F uses a
special command syntax. The commands are exe-
cuted by the DSP during its normal operation without
any loss or interruption of the incoming data or outgo-
ing audio data stream. These I2C commands allow the
controller accessing the internal DSP registers and
RAM cells and thus, monitoring internal states and set-
ting the parameters for the DSP firmware. This access
Due to the 16-bit width of the I2C data register, all
actions transmit telegrams with multiples of 16 data
bits.
S
W
A
W
A
A
A
DW
$68
code , ...
... , ...
... , ...
Fig. 3–2: General core access protocol
Table 3–4: Basic controller command codes
Code Command
(hex)
Function
0...3
Run
Start execution of an internal program. Run with start address 0 means
freeze the operating system.
5
Read Ancillary Data
Fast Program Download
Read from Register
Write to Register
The controller reads a block of MPEG Ancillary Data from the MAS 35x9F
The controller downloads custom software via the PIO interface
The controller reads an internal register of the MAS 35x9F
The controller writes an internal register of the MAS 35x9F
The controller reads a block of the DSP memory
6
A
B
C
D
E
F
Read D0 Memory
Read D1 Memory
Write D0 Memory
Write D1 Memory
The controller reads a block of the DSP memory
The controller writes a block of the DSP memory
The controller writes a block of the DSP memory
Micronas
25
MAS 35X9F
ADVANCE INFORMATION
3.3.1.1. Run and Freeze
S
W
A
W
A
A
W
A
P
DW
$68
a3,a2
a1,a0
The Run command causes the start of a program part at address a = (a3,a2,a1,a0). Since nibble a3 is also the com-
mand code (see Table 3–4), it is restricted to values between 0 and 3.
If the start address is 1000hex ≤ a < 3FFFhex and the respective RAM area has been configured as program RAM
(see Table 3–5 on page 32), the MAS 35x9F continues execution with a custom program already downloaded to this
area.
Example 1: Start program execution at address 345hex
:
<DW 68 03 45>
Example 2: Start execution of a downloaded code at address 3000hex
:
<DW 68 30 00>
Freeze is a special run command with start address 0. It suspends all normal program execution. The operating sys-
tem will enter an idle loop so that all registers and memory cells can be watched. This state is useful for operations
like downloading code or contents of memory cells because the internal program cannot overwrite these values.
This freezing will be required if alternative software is downloaded into the internal RAM of the MAS 35x9F.
Freeze has the following I2C protocol:
<DW 68 00 00>
3.3.1.2. Read Register (Code Ahex
)
1) send command
S
W
A
W
A
A
A
W
A
A
P
DW
$68
a,r1
r0,0
2) get register value
S
W
A
W
A
A
S
W
A
DW
$68
x,x
DR
W
W
N
P
x,d4
d3,d2
d1,d0
Some registers (r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others control the
internal program flow. In contrast to memory cells, registers cannot be accessed as a block but must always be
addressed individually.
Example:
Read the content of the PIO data register (C8hex):
<DW 68 ac 80>
<DW 69 <DR xx xd dd dd>
define register
and read
26
Micronas
ADVANCE INFORMATION
MAS 35X9F
3.3.1.3. Write Register (Code Bhex
)
S
W
A
W
A
A
A
W
W
A
A
DW
$68
b,r1
r0,d4
d1,d0
P
d3,d2
The controller writes the 20-bit value (d = d4,d3,d2, d1,d0) into the MAS 35x9F register (r = r1,r0).
Example: Writing the value 81234hex into the register
with the number AAhex
:
<DW 68 ba a8 12 34>
In Table 3–5 on page 32 the registers of interest with respect to the firmware are described in detail.
3.3.1.4. Read D0 Memory (Code Chex
)
The MAS 35x9F has 2 memory areas of 2048 words called D0 and D1 memory. Both memory areas have different
read and write commands. All D0/D1 memory addresses are given in hexadecimal notation.
1) send command
S
W
A
W
A
A
A
A
W
W
W
A
A
A
DW
$68
c,0
0,0
n3,n2
a3,a2
n1,n0
a1,a0
P
2) get memory value
S
W
A
W
A
A
S
W
A
DW
$69
x,x
DR
W
A
A
A
A
W
W
A
N
x,d4
d3,d2
d1,d0
d1,d0
...repeat for n data values...
A
W
P
x,x
x,d4
d3,d2
The Read D0 Memory command gives the controller access to all 20 bits of D0 memory cells of the MAS 35x9F.
The telegram to read 3 words starting at location D0:100 is
<DW 68 c0 00 00 03 01 00>
<DW 69 <DR xx xd dd dd
xx xd dd dd xx xd dd dd>
Micronas
27
MAS 35X9F
ADVANCE INFORMATION
3.3.1.5. Short Read D0 Memory (Code C4hex
)
Because most cells in the user interface are only 16 bits wide, it is faster and more convenient to access the memory
locations with a special 16 bit mode for reading:
1) send command
S
W
A
W
A
A
A
A
W
W
W
A
A
A
DW
$68
$69
c,4
0,0
n3,n2
a3,a2
n1,n0
a1,a0
P
2) get memory value
S
W
A
W
A
S
W
A
DW
DR
A
W
A
N
d3,d2
d1,d0
...repeat for n data values...
A
W
P
d3,d2
d1,d0
This command is similar to the normal 20 bit read command and uses the same command code Chex, however it is
followed by a 4hex rather than a 0hex
.
3.3.1.6. Read D1 Memory (Code Dhex
)
1) send command
S
W
A
W
A
A
A
A
W
W
W
A
A
A
DW
$68
d,0
0,0
n3,n2
a3,a2
n1,n0
a1,a0
P
2) get memory value
S
W
A
W
A
A
S
W
A
DW
$69
x,x
DR
W
A
A
A
A
W
W
A
N
x,d4
d3,d2
d1,d0
d1,d0
...repeat for n data values...
A
W
P
x,x
x,d4
d3,d2
The Read D1 Memory command is provided to get information from D1 memory cells of the MAS 35x9F.
28
Micronas
ADVANCE INFORMATION
MAS 35X9F
3.3.1.7. Short Read D1 Memory (Code D4hex
)
1) send command
S
W
A
W
A
A
W
W
W
A
A
A
DW
$68
d,4
0,0
A
A
n3,n2
a3,a2
n1,n0
a1,a0
P
2) get memory value
S
W
A
W
A
S
W
A
DW
$69
DR
A
W
A
N
d3,d2
d1,d0
...repeat for n data values...
A
W
P
d3,d2
d1,d0
The Short Read D1 Memory command works similar to the Read D1 Memory command but with the code Dhex fol-
lowed by a 4hex
.
Example: Read 16 bits of D1:123 has the following I2C protocol:
<DW 68 d4 00
00 01
read 16 bits from D1
1 word to be read
start address
01 23
<DW 69 DR dd dd>
start reading
3.3.1.8. Write D0 Memory (Code Ehex
)
S
W
A
W
A
A
A
A
A
A
W
W
W
W
W
A
A
A
A
A
DW
$68
e,0
0,0
n3,n2
a3,a2
0,0
n1,n0
a1,a0
0,d4
d3,d2
d1,d0
...repeat for n data values...
A
A
W
W
A
A
0,0
0,d4
P
d3,d2
d1,d0
With the Write D0 Memory command n 20-bit memory cells in D0 can be initialized with new data.
Example: Write 80234hex to D0:456 has the following I2C protocol:
<DW 68 e0 00
00 01
write D1 memory
1 word to write
start address
04 56
00 08
value = 80234hex
02 34>
Micronas
29
MAS 35X9F
ADVANCE INFORMATION
3.3.1.9. Short Write D0 Memory (Code E4hex
)
S
W
A
W
A
A
W
W
W
W
A
A
A
A
DW
$68
e,4
0,0
A
A
A
n3,n2
a3,a2
d3,d2
n1,n0
a1,a0
d1,d0
...repeat for n data values...
A
W
A
P
d3,d2
d1,d0
For faster access only the lower 16 bits of each memory cell are accessed. The 4 MSBs of the cell are cleared.
3.3.1.10. Write D1 Memory (Code Fhex
)
S
W
A
W
A
A
A
A
A
A
W
W
W
W
W
A
A
A
A
A
DW
$68
f,0
0,0
n3,n2
a3,a2
0,0
n1,n0
a1,a0
0,d4
d3,d2
d1,d0
...repeat for n data values...
A
A
W
W
A
A
0,0
0,d4
P
d3,d2
d1,d0
For further details, see the Write D0 Memory command.
3.3.1.11. Short Write D1 Memory (Code F4hex
)
S
W
A
W
A
A
A
A
A
W
W
W
W
A
A
A
A
DW
$68
f,4
0,0
n3,n2
a3,a2
d3,d2
n1,n0
a1,a0
d1,d0
...repeat for n data values...
A
W
A
P
d3,d2
d1,d0
Only the 16 lower bits of each memory cell are written, the upper 4 bits are cleared.
3.3.1.12. Clear SYNC Signal (Code 5hex
)
S
W
A
W
A
A
W
A
P
DW
$68
5,0
0,0
After the successful decoding of an MPEG frame the signal at pin SYNC rises and thus generates an interrupt event
for the microcontroller. Issuing this command lets the signal at pin SYNC return to ’0’.
30
Micronas
ADVANCE INFORMATION
MAS 35X9F
3.3.1.13. Default Read
The Default Read command is the fastest way to get information from the MAS 35x9F. Executing the Default Read in
a polling loop can be used to detect a special state during decoding.
S
W
A
W
A
S
W
A
A
DW
$69
DR
W
N
P
d3,d2
d1,d0
The Default Read command immediately returns the lower 16 bit content of a specific RAM location as defined by
the pointer D0:ffb. The pointer must be loaded before the first Default Read action occurs. If the MSB of the pointer
is set, the pointer refers to a memory location in D1 rather than to one in D0.
Example: For watching D1:123 the pointer D0:ffb must be loaded with 8123hex
:
<DW 68 e0 00
00 01
write to D0 memory
1 word to write
start address ffb
value = 8...
0f fb
00 08
01 23>
...0123hex
Now Default Read commands can be issued as often as desired:
<DW 69 <DR
Default Read command
dd dd> 16 bit content of the
address as defined by the
pointer
<DW 69 <DR dd dd> ... and do it again
3.3.1.14. Serial Program Download
Program downloads may be performed via the I2C interface by using the Write D0/1 Memory commands.
The download must be initiated in the following sequence:
– Issue Freeze command
– Stop all DMA transfers
– Write D0/1 Memory commands to perform download
– Switch appropriate memory area to act as program RAM (register 6Bhex
)
– Issue Run command to start program execution at entry point of downloaded code
Micronas
31
MAS 35X9F
ADVANCE INFORMATION
3.3.2. List of DSP Registers
Table 3–5 lists the registers used in the standard
Layer 2/3 and AAC firmware (MPEG) and for the
download option (Download).
Note: Registers not given in the tables must not be
written.
Table 3–5: DSP Register Table
Address
(hex)
R/W Function
Mode
Default
(hex)
Name
6B
R/W Configuration of Variable RAM Areas
Download 0000
PSelect_Shadow
Affected RAM area
bit[19]
bit[18]
bit[17]
bit[16]
D0:800 ... D0:BFF
D0:C00 ... D0:FFF
D1:800 ... D1:BFF
D1:C00 ... D1:FFF
This register is used to switch four RAM areas from data
to program usage and thus enabling the DSP’s program
counter to access downloaded program code stored at
these locations. For normal operation (firmware in ROM)
this register must be kept to zero.
For details of program code download please refer to
Section 3.3.1.14.
aa
W
Soft Mute
MPEG
0000
SoftMute
%0 (reset) mute off
%1
mute on
Note: The location of the SoftMute register is to be
changed.
3.3.3. List of DSP Memory Cells
The meaning of the bits in both cells is given in Table
3–6.
Among the user interface control memory cells there
are some which have a global meaning and some
which control application specific parts of the DSP
core. In the tables below this is reflected by the key-
words All, MPEG, and G.729
3.3.3.2. Application Specific Control
The configuration of the MPEG Layer 2/3, AAC decod-
ing and the G.729 codec firmware is done via the con-
trol memory cells described in Table 3–7. The changes
applied to any of the control memory cells have to be
validated by setting bit[0] of memory cell Main I/O Con-
trol. This bit will be reset automatically after the
changes have been taken over by the DSP.
3.3.3.1. Application Select and Running
The AppSelect cell is a global user interface configura-
tion cell, which has to be written in order to start a spe-
cific application.
The status memory cells are used to read the decoder
status and to get additional MPEG bitstream informa-
tion.
The AppRunning cell is a global user interface status
cell, which indicates, which application loop is actually
running.
Note: Memory cells not given in the tables must not be
written.
32
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–6: Application Control and Status
Memory
Address
(hex)
Function
Name
D0:34b
Application Selection
All AppSelect
AppSelect is used for selecting an application. This is done by setting the
appropriate bit to one. It is principally allowed to set more than one bit to one,
e.g. setting AppSelect to 0x1c will select all MPEG audio decoders. The auto-
detection feature will automatically detect the Layer 2, Layer 3, or AAC data.
Setting bit[0] or bit[1] will make the DSP loop in the OS loop or the Top Level
loop respectively.
To add/remove MPEG layers while running in MPEG decoding mode (e.g.
Layer 2, Layer 3 (0x0c) to Layer 2, Layer 3, AAC (0x1c)), the application
selection has to be reset before writing the new value.
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
G.729 Codec
MPEG AAC Decoder
MPEG Layer 3 Decoder
MPEG Layer 2 Decoder
Top Level
Operating System
D0:34c
Application Running
All AppRunning
The AppRunning cell is a global user interface status cell, that indicates which
application loop is actually running. Prior to writing any of the configuration
registers or memory cells (except AppSelect), it has to be checked whether
the appropriate bit(s) in the AppRunning cell is set.
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
G.729 Codec
MPEG AAC Decoder
MPEG Layer 3 Decoder
MPEG Layer 2 Decoder
Top Level
Operating System
Micronas
33
MAS 35X9F
ADVANCE INFORMATION
Table 3–7: D0 Control Memory Cells
Memory
Address
(hex)
Function
Name
D0:346
Main I/O Control (reset = 24hex
)
MPEG
IOControlMain
IOControlMain is used for selecting/deselecting the appropriate data input
interface and for setting up the serial data output interface. In serial input
mode the coded audio data (Layer 2, Layer 3, AAC) is expected at the serial
input interface SDIB (default). In the 8-bit-parallel input mode the PIO pins
PI[19:12] are used.
bit[15]
bit[14]
Reserved, must be set to zero
Invert serial output clock (SOC)
0 (reset)
1
do not invert SOC
invert SOC
bit[13:12]
bit[11]
Reserved, must be set to zero
Serial data output delay
0 (reset)
1
no additional delay (reset)
additional delay of data related to word strobe
bit[10]
Reserved, must be set to zero
bit[9:8]
Input Select Main
00 (reset) serial input at interface B
01
10
11
parallel input at PIO pins PI[19...12]
S/PDIF input (not yet supported)
no main input
In the standard firmware the serial input interface A (SDI) cannot be selected.
bit[7:6]
bit[5]
Reserved, must be set to zero
SDO Word Strobe Invert
0
do not invert
1 (reset)
invert outgoing word strobe signal
bit[4]
Bits per Sample at SDO
0 (reset)
1
32 bits/sample
16 bits/sample
bit[3]
bit[2]
Reserved, must be set to zero
Serial data input interface B clock invert (pin SIBC)
0
not inverted (data latched at rising clock edge)
incoming clock signal is inverted (data latched at
falling clock edge)
1 (reset)
bit[1]
bit[0]
0 (reset)
1
DEMAND MODE (PLL off, MAS 35x9F is clock
master)
BROADCAST MODE (PLL on, clock of MAS 35x9F
locks on data stream)
Validate
0 (reset)
1
changes in control memory cell will be ignored
changes in control memory will become effective
Bit[0] is reset after the DSP has recognized the changes. The controller
should set this bit after the other D0 control memory cells have been initialized
with the desired values.
34
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–7: D0 Control Memory Cells
Memory
Address
(hex)
Function
Name
D0:347
Interface Status Control (reset = 04hex
)
MPEG
InterfaceControl
This control cell allows to enable/disable the data I/O interfaces. In addition,
the clock of the output data interface interfaces, S/PDIF and SDO, can be set
to a low-impedance mode.
bit[6]
S/PDIF input selection (not yet supported)
0 (reset)
1
select S/PDIF input 1
select S/PDIF input 2
bit[5]
Enable/disable S/PDIF output
(will be supported in the next version )
0 (reset)
1
enable S/PDIF output
S/PDIF output off (tristate)
bit[4]
bit[3]
Reserved, must be set to zero
Enable/disable serial data output SDO
0
SDO on
SDO off
1 (reset)
bit[2]
Output clock characteristic (SDO and S/PDIF outputs)
0
low impedance
high impedance
1 (reset)
bit [1:0]
reserved, must be set to zero
Both digital outputs, S/PDIF and I2S, and the D/A converters may use the
decoded audio independent of each other.
Changes at this memory address must be validated by setting bit [0] of
D0:346.
D0:348
Oscillator Frequency (reset = 18432dec
bit[19:0] oscillator frequency in kHz
)
All
OfreqControl
In order to achieve a correct internal operating frequency of the DSP, the nom-
inal crystal frequency has to be deposited into this memory cell.
Changes at this memory address must be validated by setting bit 0 of D0:346.
Micronas
35
MAS 35X9F
ADVANCE INFORMATION
Table 3–7: D0 Control Memory Cells
Memory
Address
(hex)
Function
Name
D0:349
Output Clock Configuration (pin CLKO) (reset = 80000hex
)
All
OutClkConfig
bit[19]
CLKO configuration
0
output clock signal at CLKO
CLKO is tristate
1 (reset)
The CLKO output pin of the MAS 35x9F can be disabled via bit [19].
bit[18]
bit[17]
Reserved, must be set to zero
Additional division by 2 if scaler is on (bit[8] cleared)
0 (reset)
1
oversampling factor 512/768
oversampling factor 256/384
bit[16:9]
bit[8]
Reserved, must be set to zero
Output clock scaler
0 (reset)
set output clock according to audio sample rate
(see Table 2–1)
1
output clock fixed at 24.576 or 22.5792 MHz
For a list of output frequencies at pin CLKO please refer to Table 2–1.
bit[7:0] reserved, must be set to zero
Changes at this memory address must be validated by setting bit[0] of
D0:346.
36
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–7: D0 Control Memory Cells
Memory
Address
(hex)
Function
Name
D0:34d
Operation Mode Selection (reset = 0hex
)
G.729
UserControl
The register is used to switch between basic G.729 operation modes.
bit[19:7]
bit[6]
Reserved, set to 0
Page headers
0
1
enable
disable
If the page headers bit is 0, a header frame is transfered before each page of
50 data frames. If the header bit is 1, all the frames are G.729 data frames.
Please refer to Section 3.3.6. on page 43.
bit[5:4]
Decoding speed
00
01
10
11
8 kHz (normal)
6 kHz (slow)
12 kHz (fast)
not allowed
The recording (encoding) is always done with a sampling rate of 8 kHz. During
decoding this control can be used to speed up or slow down the playback.
bit[3]
bit[2]
Reserved, set to 0
Pause encoder/decoder
0
1
normal operation
pause
If the pause bit is set, the processing continues until the current page is fin-
ished and then en-/decoding is paused. The pause mode lasts until the pause
bit is cleared again or the mode is set to 0.
bit[1:0]
Mode
00
idle
01
10
11
decode
not allowed
encode
To switch to encoder operation mode, UserControl has to be set to 3hex. Then
50 frames are encoded and sent via the PIO interface. This is repeated until
the UserControl register is changed. If the transmission of headers is enabled,
each page of 50 frames is preceeded by a header frame as shown in Fig. 3–5.
To switch to decoder operation mode, UserControl has to be set to 1hex. For
decoding with slow speed, UserControl must be 11hex, for decoding with fast
speed it must be 21hex. Then the decoder is requesting several frames via the
PIO interface to fill its internal buffer. If enough data is available, 50 frames are
decoded. This is repeated until the UserControl register is changed. If the
transmission of headers is enabled, a header frame (as shown in Fig. 3–5)
has to be sent before each page of 50 frames.
To switch off the encoder or decoder, UserControl has to be set to 0hex. Then
the encoding/decoding and sending/receiving of frames continues until the
end of the current page and the operation mode is set to stop.
Micronas
37
MAS 35X9F
ADVANCE INFORMATION
Table 3–7: D0 Control Memory Cells
Memory
Address
(hex)
Function
Name
D0:34e
The G.729 encoder is not working with the internal ADC and both, input
and output wordstrobe inverted (reset configuration). Therefore this
memory cell must be set to 0 to work with the integrated ADC.
SDISDOConfig
I2S Audio Input/Output Interface (reset = 60hex
)
G.729
bit[19:15]
bit[14]
Reserved, set to 0
Output clock signal
0
1
standard signal
inverted signal
bit[13]
bit[12]
Reserved, set to 0
Additional delay of input data related to
word strobe
0
1
no delay
1 bit delay
bit[11]
Additional delay of output data related to
word strobe
0
1
no delay
1 bit delay
bit[10:7]
bit[6]
Reserveded, set to 0
Input word strobe signal
0
1
standard signal
inverted signal
bit[5]
bit[4]
Output word strobe signal
0
1
standard signal
inverted signal
Wordlength
0
1
32 bits/sample
16 bits/sample
This setting affects the wordlength on the SDI and SDO interfaces.
bit[3]
Input clock signal
0
1
standard signal
inverted signal
bit[2:0]
Reserved, set to 0
Changes become effective when the codec is started or the mode is changed
by writing to the UserControl memory cell.
D0:34f
Interface Status Control (reset = 25hex
)
G.729
g729_InterfaceCont
rol
This control cell is used to enable/disable interfaces in G.729 mode. It con-
tains the same settings as memory cell D0:347 (InterfaceControl), but is ini-
tialized to a different default setting.
D0:352
D0:353
D0:354
D0:355
Volume input control: left gain
Volume input control: right gain
(reset=80000hex
(reset=0hex
)
G.729
G.729
All
in_L
)
in_R
Volume output control: left → left gain (reset=80000hex
Volume output control: left → right gain (reset=0hex
)
out_LL
out_LR
)
All
38
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–7: D0 Control Memory Cells
Memory
Address
(hex)
Function
Name
D0:356
D0:357
Volume output control: right → left gain(reset=0hex
)
All
All
out_RL
out_RR
Volume control: right → right gain (reset=80000hex
)
Table 3–8: D0 Status Memory Cells
Memory
Address
Function
Name
D0:FD0
MPEG Frame Counter
MPEGFrameCount
bit[19:0]
number of MPEG frames after synchronization
The counter will be incremented with every new frame that is decoded. With
an invalid MPEG bit stream at its input (e.g. an invalid header is detected), the
MAS 35x9F resets the MPEGFrameCount to ‘0’.
D0:FD1
MPEG Header and Status Information
MPEGStatus1
bit[15]
reserved, must be set to zero
bit[14:13]
MPEG ID, Bits 12, 11 of the MPEG header
00
01
10
11
MPEG 2.5
reserved
MPEG 2
MPEG 1
not valid in case of AAC decoding (bit[12:11] = 00)
bit[12:11]
bit[10]
Bits 14 and 13 of the MPEG header
00
01
10
11
AAC
Layer 3
Layer 2
Layer 1
CRC Protection
0
1
bitstream protected by CRC
bitstream not protected by CRC
bit[9:2]
bit[1]
Reserved
CRC error
0
1
no CRC error
CRC error
bit[0]
Invalid frame
0
1
no invalid frame´
invalid frame
This location contains bits 15...11 of the original MPEG header and other sta-
tus bits. It will be set each frame directly after the header has been decoded
from the bit stream.
Micronas
39
MAS 35X9F
ADVANCE INFORMATION
Table 3–8: D0 Status Memory Cells
Memory
Address
Function
Name
D0:FD2
MPEG Header Information
MPEGStatus2
bit[15:12]
MPEG Layer 2/3 Bitrate
MPEG1, L2
MPEG1, L3
MPEG2+2.5, L2/3
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
free
32
48
56
64
free
32
40
48
56
64
80
96
112
128
160
192
224
256
320
forbidden
free
8
16
24
32
40
48
56
64
80
96
112
128
160
192
224
256
320
384
forbidden
80
96
112
128
144
160
forbidden
bit[13:10]
Sampling frequency for MPEG2-AAC in Hz
0000..0010
0011
0100
0101
0110
0111
1000
1001
1010
reserved
48000
44100
32000
24000
22050
16000
12000
11025
8000
1011
1100..1111
reserved
...
40
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–8: D0 Status Memory Cells
Memory
Address
Function
Name
D0:FD2
MPEG Header Information, continued
MPEGStatus2
(continued)
bit[11:10]
Sampling frequencies in Hz
MPEG1
MPEG2
MPEG2.5
00
01
10
11
44100
48000
32000
reserved
22050
24000
16000
reserved
11025
12000
8000
reserved
bit[9]
Padding Bit
reserved
bit[8]
bit[7:6]
Mode
00
stereo
01
10
joint_stereo (intensity stereo / m/s stereo)
dual channel
11
single channel
bit[5:4]
Mode extension (applies to joint stereo only)
intensity stereo
m/s stereo
00
01
10
11
off
on
off
on
off
off
on
on
bit[3]
Copyright Protect Bit
0/1 not copyright protected/copyright protected
bit[2]
Copy/Original Bit
0/1
bitstream is a copy/bitstream is an original
bit[1:0]
Emphasis, indicates the type of emphasis
00
01
10
11
none
50/15 µs
reserved
CCITT J.17
This memory cell contains the 16 LSBs of the MPEG header. It will be set
directly after synchronizing to the bit stream.
Note that for AAC four bits are needed to define the sampling frequency while
for Layer2/Layer3 two bits are sufficient. This leads to an inconsistency in the
format of bits 13...10.
D0:FD3
D0:FD4
MPEG CRC Error Counter
CRCErrorCount
The counter will be increased by each CRC error detected in the MPEG bis-
stream. It will not be reset when losing the synchronization.
Number of Bits in Ancillary Data
NumberOfAncillary-
Bits
Number of valid ancillary bits in the current MPEG frame.
D0:FD5
...
D0:FF1
Ancillary Data
AncillaryData
Section 3.3.4. on page 42.
Micronas
41
MAS 35X9F
ADVANCE INFORMATION
3.3.4. Ancillary Data
left audio
+
−1
−1
−1
−1
LL
The memory fields D0:FD5...D0:ff1 contain the ancil-
lary data. It is organized in 28 words of 16 bit each.
The last ancillary bit of a frame is placed at bit 0 in
D0:FD5. The position of the first ancillary data bit
received can be located via the content of NumberO-
fAncillaryBits because
LR
RL
int[(NumberOfAncillaryBits-1)/16] + 1
of memory words are used.
Example:
First get the content of ’NumberOfAncillaryBits’
+
RR
<DW 68 c4 00 00 01 0f d4>
<DW 69 <DR dd dd>
right audio
Assume that the MAS 35x9F has received 19 ancillary
data bits. Therefore, it is necessary to read two 16-bit
words:
Fig. 3–3: Digital volume matrix
<DW 68 c4 00
Short Read from D0
00 02 0f d5> read 2 words starting at D0:fd5
<DW 69 <DR dd dd
Table 3–9: Settings for the digital volume matrix
dd dd>
Memory
Name
D0:354 D0:355 D0:356 D0:357
receive the 2 16-bit words
LL
LR
RL
RR
The first bit received from the MPEG source is at posi-
tion 2 of D0:FD6; the last bit received is at the LSB of
D0:fd5.
Stereo
(default)
−1.0
0
0
−1.0
Mono left
−1.0
−1.0
0
0
3.3.5. DSP Volume Control
Mono right
0
0
−1.0
−1.0
The digital baseband volume matrix is used for control-
ling the digital gain as shown in Fig. 3–3. This volume
control is effective on both, the digital audio output and
the data stream to the D/A converters. The values are
in 20-bit 2’s complement notation.
If channels are mixed, care must be taken to prevent
clipping at high amplitudes. Therefore the sum of the
absolute values of coefficients for one output channel
should be less than 1.0.
Table 3–9 shows the proposed settings for the 4 vol-
ume matrix coefficients for stereo, left and right mono.
The gain factors are given in fixed point notation
(−1.0×219 = 80000hex).
For normal operating conditions it is recommended to
use the main volume control of the audio codec
instead (register 00 10hex of the audio codec).
Table 3–10: Content of D0:fd5 after reception of 19 ancillary bits.
D0:fd5
MSB 14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Ancillary
Data
4th
bit
5th
bit
6th
bit
...
...
...
...
...
...
...
...
...
...
17th
bit
18th
bit
last
bit
Table 3–11: Content of D0:fd6 after reception of 19 ancillary bits.
D0:fd6
MSB 14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Ancillary
Data
x
x
x
x
x
x
x
x
x
x
x
x
x
first
bit
2nd
bit
3rd
bit
42
Micronas
ADVANCE INFORMATION
MAS 35X9F
3.3.6. Explanation of the G.729 Data Format
Table 3–12: Content of Page Header
Byte
The codec is working on a page basis where the
encoding and decoding is performed in blocks of 50
G.729 frames, whereas each frame consists of
10 bytes in byteswapped order (see Fig. 3–5 on
page 52). Therefore most changes to the UserControl
register become effective when processing of the cur-
rent page is finished. The pages are optionally pre-
ceeded by 10 byte header frames (see Table 3–12).
1
2
3
4
5
6
7
8
9
10
Value 64 6d 72 31 64 61 74 61 F4 01
(hex)
Switching directly from encoding to decoding mode or
vice versa is not allowed. Instead the controller has to
send a stop request to the MAS 35x9F (writing 0hex to
UserControl) and must keep on sending data in decod-
ing mode or receive data in encoding mode until the
current page of 50 frames is finished. After this run out
time, the encoding or decoding can be started again.
page frame frame frame
header
frame frame page frame frame
49 49 header 51 52
frame frame page frame frame
...
...
...
1
2
3
99
100 header 101
102
10 ms
10 ms
...
...
byte byte byte byte byte byte byte byte byte byte
10
64 6D 72 31 64 61 74 61 F4 01
2
1
4
3
6
5
8
7
9
Fig. 3–4: Schematic timing of the data transmission with preceeding header
Micronas
43
MAS 35X9F
ADVANCE INFORMATION
3.4. Audio Codec Access Protocol
The MAS 35x9F has 16-bit wide registers for the control of the audio codec. These registers are accessed via the
I2C subaddresses codec_write (6Chex) and codec_read (6Dhex).
3.4.1. Write Codec Register
S
W
A
A
A
A
A
A
DW
$6C
r3,r2
r1,r0
P
d3,d2
d1,d0
The controller writes the 16-bit value (d = d3,d2,d1,d0) into the MAS 35x9F codec register (r = r3,r2,r1,r0). A list of
registers is given in Table 3–13.
Example: Writing the value 1234hex into the codec register with the number 00 1Bhex
:
<DW 6c 00 1b 12 34>
3.4.2. Read Codec Register
1) send command
S
W
A
A
A
A
A
A
N
P
P
DW
$6C
$6D
r3,r2
r1,r0
2) get register value
S
W
A
S
W
A
DW
DR
d3,d2
d1,d0
Reading the codec registers also needs a set-up for the register address and an additional start condition during the
actual read cycle. A list of registers is given in Table 3–14.
44
Micronas
ADVANCE INFORMATION
MAS 35X9F
3.4.3. Codec Registers
Table 3–13: Codec control registers on I2C subaddress 6chex
Register
Address
(hex)
Function
Name
CONVERTER CONFIGURATION
00 00 Audio Codec Configuration
Please refer to Section 4.6.4. on page 80.
CONV_CONF
bit[15:12]
bit[11:8]
A/D converter left amplifier gain = n*1.5−3 [dB]
A/D converter right amplifier gain = n*1.5−3 [dB]
1111
1110
...
+19.5 dB
+18.0 dB
...
0011
0010
0001
0000
+1.5 dB
0.0 dB
−1.5 dB
− 3.0 dB
bit[7:4]
bit[3]
Microphone amplifier gain = n*1.5+21 [dB]
1111
1110
...
+43.5 dB
+42.0 dB
...
0001
0000
+22.5 dB
+21.0 dB
Input selection for left A/D converter channel
0
1
line-in
microphone
bit[2]
bit[1]
bit[0]
Enable left A/D converter1)
Enable right A/D converter1)
Enable D/A converter1)
1) The generation of the internal DC reference voltage for the D/A converter is
also controlled with this bit. In order to avoid click noise, the reference voltage
at pin AGNDC should have reached a near ground potential before repower-
ing the D/A converter after a short down phase.
Alternatively at least one of the A/D converters (bits [2] or [1]) should remain
set during short power-down phases of the D/A. Then the DC reference volt-
age generation for the D/A converter will not be interrupted.
INPUT MODE SELECT
00 08
Input Mode Setting
ADC_IN_MODE
bit[15]
Mono switch
0
1
stereo input mode
left channel is copied into the right channel
bit[14:2]
bit[1:0]
Reserved, must be set to 0
Deemphasis select
0
1
2
deemphasis off
deemphasis 50 µs
deemphasis 75 µs
Micronas
45
MAS 35X9F
ADVANCE INFORMATION
Table 3–13: Codec control registers on I2C subaddress 6chex
Register
Address
(hex)
Function
Name
OUTPUT MODE SELECT
00 0F 1)
D/A Converter Source
DAC_IN_SEL
bit[15]
D/A converter source select
0
1
DSP Core output
A/D converter output
bit[14:0]
reserved, must be set to 0
D/A Converter Source Mixer
MIX ADC scale
00 062)
00 072)
DAC_IN_ADC
DAC_IN_DSP
MIX DSP scale
bit[15:8]
Linear scaling factor (hex)
0
off
20
40
7f
50 % (−6 dB gain)
100 % (0 dB gain)
200 % (+6 dB gain)
In the sum of both mixing inputs exceeds 100 %, clipping may occur in the
successive audio processing.
00 0E
D/A Converter Output Mode
DAC_OUT_MODE
bit[15]
bit[14]
bit[1:0]
Mono switch
0
1
stereo through
mono matrix applied
Invert right channel
0
1
through
right channel is inverted
Reserved, must be set to 0
In order to achieve more output power a single loudspeaker can be connected
as a bridge between pins OUTL and OUTR. In this mode bit[15] and bit[14]
must be set.
1) Version A1 only
2) since version A2
46
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–13: Codec control registers on I2C subaddress 6chex
Register
Address
(hex)
Function
Name
BASEBAND FEATURES
00 14
Bass
BASS
bit[15:8]
Bass range
60hex
58hex
...
+12 dB
+11 dB
08hex
00hex
F8hex
...
+1 dB
0 dB
−1 dB
A8hex
A0hex
−11 dB
−12 dB
Higher resolution is possible, one LSB step results in a gain step of about
1/8 dB.
With positive bass settings clipping of the output signal may occur. Therefore,
it is not recommended to set bass to a value that, in conjunction with volume,
would result in an overall positive gain.
The settings require: max (bass, treble) + loudness + volume ≤ 0 dB
bit[7:0]
Not used, must be set to 0
00 15
Treble
TREBLE
bit[15:8]
Treble range
60hex
58hex
...
+12 dB
+11 dB
08hex
00hex
F8hex
...
+1 dB
0 dB
−1 dB
A8hex
A0hex
−11 dB
−12 dB
Higher resolution is possible, one LSB step results in a gain step of about
1/8 dB.
With positive treble settings, clipping of the output signal may occur. There-
fore, it is not recommended to set treble to a value that, in conjunction with
loudness and volume, would result in an overall positive gain.
The settings require: max (bass, treble) + loudness + volume ≤ 0 dB
bit[7:0]
Not used, must be set to 0
Micronas
47
MAS 35X9F
ADVANCE INFORMATION
Table 3–13: Codec control registers on I2C subaddress 6chex
Register
Address
(hex)
Function
Name
00 1E
Loudness
LDNESS
bit[15:8] Loudness Gain
44hex
40hex
...
+17 dB
+16 dB
04hex
00hex
+1 dB
0 dB
bit[7:0]
Loudness Mode
00hex
04hex
normal (constant volume at 1 kHz)
Super Bass (constant volume at 2 kHz)
Higher resolution of Loudness Gain is possible: An LSB step results in a gain
step of about 1/4 dB.
Loudness increases the volume of low- and high-frequency signals, while
keeping the amplitude of the 1-kHz reference frequency constant. The
intended loudness has to be set according to the actual volume setting.
Because loudness introduces gain, it is not recommended to set loudness to a
value that, in conjunction with volume, would result in an overall positive gain.
The settings should be: max (bass, treble) + loudness + volume ≤ 0 dB
The corner frequency for bass amplification can be set to two different values.
In Super Bass mode, the corner frequency is shifted up. The point of constant
volume is shifted from 1 kHz to 2 kHz.
48
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–13: Codec control registers on I2C subaddress 6chex
Register
Address
(hex)
Function
Name
Micronas Dynamic Bass (MDB)
00 22
MDB Effect Strength
MDB_STR
bit[15:8]
00hex
7Fhex
MDB off (default)
maximum MDB
The MDB effect strength can be adjusted in 1dB steps. A value of 40hex will
yield a medium MDB effect.
00 23
MDB Harmonics
MDB_HAR
bit[15:8]
00hex
64hex
7Fhex
no harmonics are added (default)
50% fundamentals + 50% harmonics
100% harmonics
The MDB exploits the psychoacoustic phenomenon of the ‘missing fundamen-
tal by creating harmonics of the frequencies below the center frequency of the
bandpass filter (MDB_FC). This enables a loudspeaker to display frequencies
that are below its cutoff frequency. The Variable MDB_HAR describes the ratio
of the harmonics towards the original signal.
00 24
MDB Center Frequency
MDB_FC
bit[15:8]
2
3
20 Hz
30 Hz
...
30
300 Hz
The MDB Center Frequency defines the center frequency of the MDB band-
pass filter (see Fig. 3–5 on page 52). The center frequency should approxi-
mately match the cutoff frequency of the loudspeakers. For high end
loudspeakers, this frequency is around 50 Hz, for low end speakers around
90 Hz
00 21
MDB Shape
MDB_SHAPE
bit[15:8]
5...30
corner frequency in 10-Hz steps
(range: 50...300 Hz)
With a second lowpass filter the steepness of the falling slope of the MDB
bandpass can be increased (see Fig. 3–5 on page 52). Choosing the corner
frequency of this filter close to the center frequency of the bandpass filter
(MDB_FC) results in a narrow MDB frequency range. The smaller this range,
the harder the bass sounds. The recommended value is around
1.5 × MDB_FC
MDB Switch
MDB_SWITCH
bit[7:2]
bit[1]
reserved, must be set to zero
MDB switch
MDB off
MDB on
0
1
bit [0]
reserved,must be set to zero
Micronas
49
MAS 35X9F
ADVANCE INFORMATION
Table 3–13: Codec control registers on I2C subaddress 6chex
Register
Address
(hex)
Function
Name
VOLUME
00 12
Automatic Volume Correction (AVC) Loudspeaker Channel
AVC
bit[15:12] 0hex
8hex
AVC off (and reset internal variables)
AVC on
bit[11:8] 8hex
8 s decay time
4 s decay time
2 s decay time
20 ms decay time (intended for quick adaptation to the
average volume level after track or source change)
4hex
2hex
1hex
Note: To reset the internal variables, the AVC should be switched off and then
on again during any track or source change. For standard applications, the
recommended decay time is 4 s.
00 11
Balance
BALANCE
bit[15:8] Balance range
7Fhex
7Ehex
...
left −127 dB, right 0 dB
left −126 dB, right 0 dB
01hex
00hex
FFhex
...
left −1 dB, right 0 dB
left 0 dB, right 0 dB
left 0 dB, right −1 dB
81hex
80hex
left 0 dB, right −127 dB
left 0 dB, right −128 dB
Positive balance settings reduce the left channel without affecting the right
channel; negative settings reduce the right channel leaving the left channel
unaffected.
00 10
Volume Control
VOLUME
bit[15:8] Volume table with 1 dB step size
7Fhex
7Ehex
...
+12 dB (maximum volume)
+11 dB
74hex
73hex
72hex
...
+1 dB
0 dB
−1 dB
02hex
01hex
00hex
−113 dB
−114 dB
mute (reset)
bit[7:0]
Not used, must be set to 0
This main volume control is applied to the analog outputs only. It is split
between a digital and an analog function. In order to avoid noise due to large
changes of the setting, the actual setting is internally low-pass filtered.
With large scale input signals, positive volume settings may lead to signal clip-
ping.
50
Micronas
ADVANCE INFORMATION
MAS 35X9F
Table 3–14: Codec status registers on I2C subaddress 6dhex
Register
Address
(hex)
Function
Name
INPUT QUASI-PEAK
00 0A
A/D Converter Quasi-Peak Detector Readout Left
QPEAK_L
bit[14:0]
positive 15-bit value, linear scale
0 %
25 % (−12 dBFS)
50 % (−6 dBFS)
100 % (0 dBFS)
0000
2000
4000
7FFF
00 0B
A/D Converter Quasi-Peak Detector Readout Right
QPEAK_R
bit[14:0]
positive 15-bit value, linear scale
0 %
25 % (−12 dBFS)
50 % (−6 dBFS)
100 % (0 dBFS)
0000
2000
4000
7FFF
OUTPUT QUASI-PEAK
00 0C
Audio Processing Input Quasi-Peak Detector Readout Left
bit[14..0] positive 15-bit value, linear scale
Audio Processing Input Quasi-Peak Detector Readout Right
bit[14..0] positive 15-bit value, linear scale
DQPEAK_L
DQPEAK_R
00 0D
Micronas
51
MAS 35X9F
ADVANCE INFORMATION
3.4.4. Basic MDB Configuration
(which results in a softer/harder bass sound), turn
on/off the MDB
With the parameters described in Table 3–13, the Mic-
ronas Dynamic Bass system (MDB) can be custom-
ized to create different bass effects as well as to fit the
MDB to various loudspeaker characteristics. The easi-
est way to find a good set of parameter is by selecting
one of the settings below, listening to music with strong
bass content and adjusting the MDB parameters:
– MDB_STR: Increase/decrease the strength of the
MDB effect
– MDB_HAR: Increase/decrease the content of low
Frequency
MDB_FC MDB_SHAPE
frequency harmonics
– MDB_FC: Shift the MDB effect to lower/higher fre-
quencies
Fig. 3–5: Micronas Dynamic Bass (MDB): Bass boost
in relation to input signal leve
– MDB_SHAPE: Widen/narrow MDB frequency range
Table 3–15: suggested MDB settings
Function
MDB_STR
(22hex
MDB_HAR
(23hex
MDB_FC
(24hex
MDB_SHAPE
(21hex
)
)
)
)
MDB off
xxxxhex
5000hex
xxxxhex
3000hex
xxxxhex
0600hex
xx00hex
0902hex
Low end headphones, medium
effect
52
Micronas
ADVANCE INFORMATION
MAS 35x9F
4. Specifications
4.1. Outline Dimensions
± 0.1
15 x 0.5 = 7.5
0.5
± 0.055
0.145
48
33
49
64
32
17
1
16
± 0.05
1.4
1.75
± 0.1
± 0.2
10
12
0.1
± 0.1
1.5
D0025/3E
Fig. 4–1:
64-Pin Plastic Low-Profile Quad Flat Pack
(PLQFP64)
Weight approximately 0.35 g
Dimensions in mm
Fig. 4–2:
64-Pin Plastic Metric Quad Flat Pack
(PMQFP64)
Weight approximately 0,4 g
Dimensions in mm
(available 2H-2001)
Micronas
53
MAS 35x9F
ADVANCE INFORMATION
1.4
A1 Ball Pad Corner
Laser marked pin 1
0.36
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
0.8
8 x 0.8 = 6.4
9
SPGS708000-1(P81)/1E
Fig. 4–3:
Plastic Ball Grid Array 81-Pin
(LFBGA81)
Weight approximately 0.19 g
Dimensions in mm
54
Micronas
ADVANCE INFORMATION
MAS 35x9F
4.2. Pin Connections and Short Descriptions
NC not connected, leave vacant
VDD connect to positive supply
VSS connect to ground
LV
X
If not used, leave vacant
obligatory, pin must be connected as described
in application information
(see Fig. 4–33 on page 87)
Pin
No.
Pin
No.
Pin Name
Type
Default
Connection
(if not used)
Short Description
PLQFP LFBG
64
A 81
H2
J2
1
AGNDC
MICIN
MICBI
INL
X
Analog reference voltage
Input for internal microphone amplifier
Bias for internal microphone
Left A/D input
2
IN
LV
LV
LV
LV
X
3
J3
IN
4
H3
H4
G4
J4
IN
5
INR
IN
Right A/D input
6
TE
IN
Test enable
7
XTI
IN
X
Crystal oscillator (ext. clock) input
Crystal oscillator output
Power on reset, active low
DSP supply ground
8
J5
XTO
OUT
LV
X
9
G5
H5
J6
POR
IN
10
11
12
13
14
15
16
VSS
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
IN/OUT
X
XVSS
VDD
X
Digital output supply ground
DSP supply
J7
X
H6
H7
G6
J8
XVDD
I2CVDD
DVS
X
Digital output supply
I2C supply
X
X
I2C device address selector
VSENS1
VDD
Sense input and power output
of DC/DC 1 converter
17
18
19
20
21
J9
DCSO1
DCSG1
DCSG2
DCSO2
VSENS2
SUPPLY
SUPPLY
SUPPLY
SUPPLY
IN/OUT
LV
DC/DC 1 switch output
DC/DC 1 switch ground
DC/DC 2 switch ground
DC/DC 2 switch output
H8
H9
G8
G9
VSS
VSS
LV
VDD
Sense input and power output
of DC/DC 2 converter
22
23
24
25
F8
F9
E8
E9
DCEN
CLKO
I2CC
IN
VSS
LV
X
DC/DC enable (both converters)
Clock output
OUT
IN/OUT
IN/OUT
I2C clock
I2CD
X
I2C data
Micronas
55
MAS 35x9F
ADVANCE INFORMATION
Pin
No.
Pin
No.
Pin Name
Type
Default
Connection
(if not used)
Short Description
PLQFP LFBG
64
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
A 81
E7
D9
D8
C9
C8
B9
B8
A9
A8
B7
A7
B6
A6
C6
A5
B5
C5
A4
B4
B3
A3
SYNC
VBAT
PUP
EOD
PRTR
PRTW
PR
OUT
LV
Sync output
IN
LV
Battery voltage monitor input
DC Converter Power-Up Signal
PIO end of DMA, active low
PIO ready to read, active low
PIO ready to write, active low
PIO DMA request, active high
PIO chip select, active low
PIO data bit 7 (MSB)
PIO data bit 6
OUT
LV
OUT
LV
OUT
LV
OUT
LV
IN
VDD
VSS
LV
PCS
PI19
PI18
PI17
PI16
PI15
PI14
PI13
PI12
SOD
SOI
IN
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
OUT
LV
LV
PIO data bit 5
LV
PIO data bit 4
LV
PIO data bit 3
LV
PIO data bit 2
LV
PIO data bit 1
LV
PIO data bit 0 (LSB)
Serial output data
LV
OUT
LV
Serial output frame identification
Serial output clock
SOC
SID
OUT
LV
IN
VSS
VSS
Serial input data, interface A
SII
IN
Serial input frame identification, inter-
face A
47
48
49
50
51
C4
E3
A1
A2
B2
SIC
IN
VSS
LV
Serial input clock, interface A
S/PDIF output interface
SPDO
SIBD
SIBC
SIBI
OUT
IN
VSS
VSS
VSS
Serial input data, interface B
Serial input clock, interface B
IN
IN
Serial input frame identification, inter-
face B
52
53
54
B1
C2
D2
SPDI2
SPDI1
SPDIR
IN
IN
IN
LV
LV
LV
Active differential S/PDIF input 2
Active differential S/PDIF input 1
Reference differential S/PDIF input 1
and 2
56
Micronas
ADVANCE INFORMATION
MAS 35x9F
Pin
No.
Pin
No.
Pin Name
Type
Default
Connection
(if not used)
Short Description
PLQFP LFBG
64
55
56
57
58
59
60
61
62
63
64
A 81
C1
E2
D1
E1
F2
FILTL
IN
X
Feedback input for left amplifier
Analog supply for output amplifiers
Left analog output
AVDD0
OUTL
OUTR
AVSS0
FILTR
AVSS1
VREF
PVDD
AVDD1
SUB
SUPPLY
OUT
X
LV
LV
X
OUT
Right analog output
SUPPLY
IN
Analog ground for output amplifiers
Feedback for right output amplifier
Analog ground
F1
X
G2
G1
H1
J1
SUPPLY
X
X
Analog reference ground
Internal power supply
SUPPLY
SUPPLY
X
X
Analog Supply
VSS
Substrate connection
In the 81-pin LFBGA housing, the pins C3, C7, D3, D4, D5, D6, D7, E4, E5, E6, F3, F4, F5, F6, F7, G3 and G7 are
common substrate contacts.
Micronas
57
MAS 35x9F
ADVANCE INFORMATION
4.3. Pin Descriptions
4.3.3. DC/DC Converters and Battery Voltage
Supervision
4.3.1. Power Supply Pins
DCSG1/DCSG2
SUPPLY
The use of all power supply pins is mandatory to
achieve correct function of the MAS 35x9F.
DC/DC converters switch ground. Connect using sep-
arate wide trace to negative pole of battery cell. Con-
nect also to AVSS0/1 and VSS/XVSS.
VDD, VSS
Digital supply pins.
SUPPLY
SUPPLY
SUPPLY
DCSO1/DCSO2
SUPPLY
DC/DC converter switch connection. If the respective
DC/DC converter is not used, this pin must be left
vacant.
XVDD, XVSS
Supply for digital output pins.
I2CVDD
VSENS1/VSENS2
IN
Supply for I2C interface circuitry. This net uses VSS or
XVSS as the ground return line.
Sense input and power output of DC/DC converters. If
the respective DC/DC converter is not used, this pin
should be connected to a supply.
PVDD
SUPPLY
Auxiliary pin for analog circuitry. This pin has to be
connected via a 3-nF capacitor to AVDD1. Extra care
should be taken to achieve a low inductance PCB line.
DCEN
IN
Enable signal for both DC/DC converters. If none of
the DC/DC converters is used, this pin must be con-
nected to VSS.
AVDD0/AVSS0
SUPPLY
Supply for analog output amplifier.
PUP
OUT
Power-up. This signal is set when the required volt-
ages are available at both DC/DC converter output
pins VSENS1 and VSENS2. The signal is cleared
when both voltages have dropped below the reset
level in the DCCF Register.
AVDD1/AVSS1
Supply for internal analog circuits (A/D, D/A convert-
ers, clock, PLL, S/PDIF input).
SUPPLY
AVDD0/AVSS0 and AVDD1/AVSS1 should receive the
same supply voltages.
VBAT
IN
Analog input for battery voltage supervision.
4.3.2. Analog Reference Pins
4.3.4. Oscillator Pins and Clocking
AGNDC
Internal analog reference voltage. This pin serves as
the internal ground connection for the analog circuitry.
XTI
XTO
IN
OUT
The XTI pin is connected to the input of the internal
crystal oscillator, the XTO pin to its output. Each pin
should be directly connected to the crystal and to a
ground-connected capacitor (see application diagram,
Fig. 4–33 on page 87).
VREF
Analog reference ground. All analog inputs and out-
puts should drive their return currents using separate
traces to a ground starpoint close to this pin. Connect
to AVSS1. This reference pin should be as noise free
as possible.
CLKO
OUT
The CLKO can drive an output clock line.
4.3.5. Control Lines
I2CC
I2CD
SCL
SDA
IN/OUT
IN/OUT
Standard I2C control lines.
DVS
IN
I2C device address selector. Connect this pin either to
VDD (I2C device address: 3E/3Fhex) or VSS (I2C
device address: 3C/3Dhex) to select a proper I2C
device address (see also Table 3–1 on page 18).
58
Micronas
ADVANCE INFORMATION
MAS 35x9F
4.3.6. Parallel Interface Lines
PI12..PI19
The PIO input pins PI12..PI19 are used as 8-bit I/O
interface to a microcontroller in order to transfer com-
pressed and uncompressed data. PI12 is the LSB,
PI19 the MSB.
4.3.10. S/PDIF Input Interface
IN/OUT
SPDI1
SPDI2
SPDIR
IN
IN
IN
SPDIF1 and SPDIF2 are alternative input pins for
S/PDIF sources according to the IEC 958 consumer
specification. A switch at D0:ff6 selects one of these
pins at a time. The SPDIR pin is a common reference
for both input lines (see Fig. 4–34 on page 88).
4.3.6.1. PIO Handshake Lines
PCS
IN
The PIO chip select PCS must be set to ‘0’ to activate
the PIO in operation mode.
4.3.11. S/PDIF Output Interface
PR
IN
SPDO
OUT
Pin PR must be set to ‘1’ to validate data output from
MAS 35x9F PIO pins.
The SPDO pin provides an digital output with standard
CMOS level that is compliant to the IEC 958 consumer
specification.
PRTR
OUT
Ready to read. This signal indicates that the
MAS 35x9F is able to receive data in PIO input mode.
4.3.12. Analog Input Interfaces
PRTW
OUT
In the standard MPEG-decoding DSP firmware the
analog inputs are not used. However, they can be
selected as a source for the D/A converters (set
bit [15] in audio codec register 00 0Fhex).
Ready to write. This pin indicates that MAS 35x9F has
data available for PIO output mode.
EOD
OUT
EOD indicates the end of an DMA cycle in the IC’s PIO
input mode. In ’serial’ input mode it is used as Demand
signal, that indicates that new input data are required.
MICIN
MICBI
IN
IN
The MICIN input may be directly used as electret
microphone input, which should be connected as
described in application information. The MICBI signal
provides the supply voltage for these microphones.
4.3.7. Serial Input Interface (SDI)
SID
SII
SIC
DATA
WORD STROBE
CLOCK
IN
IN
IN
INL
INR
IN
IN
INL and INR are analog line-in input lines. They are
connected to the embedded stereo A/D converter of
the MAS 35x9F. The sources should be AC coupled.
The reference ground for these analog input pins is the
VREF pin.
I2S compatible serial interface A for digital audio data.
In the standard firmware this interface is not used.
4.3.8. Serial Input Interface B (SDIB)
SIBD
SIBI
SIBC
DATA
WORD STROBE
CLOCK
IN
IN
IN
4.3.13. Analog Output Interfaces
OUTL
OUTR
OUT
OUT
The serial interface B is primarily used as bitstream
input interface. The SIBI line must be connected to
VSS in the standard application.
OUTL and OUTR are left and right analog outputs, that
may be directly connected to the headphones as
described in the application information (see Fig. 4–34
on page 88).
4.3.9. Serial Output Interface (SDO)
FILTL
FILTR
IN
IN
SOD
SOI
SOC
DATA
WORD STROBE
CLOCK
OUT
OUT
IN/OUT
Connection to input terminal of output amplifier.Can be
used to connect a capacitance from OUTL respectively
OUTR to FILTL respectively FILTR in parallel to feed-
back resistor and thus implement a low pass filter to
reduce the out-of-band noise of the DAC.
Data, Frame Indication, and Clock line of the serial
output interface. The SOI is reconfigurable and can be
adapted to several I2S compliant modes.
Micronas
59
MAS 35x9F
ADVANCE INFORMATION
4.3.14. Miscellaneous
SYNC
OUT
The SYNC signal indicates the detection of a frame
start in the input data of MAS 35x9F. Usually this sig-
nal generates an interrupt in the controller.
POR
IN
The Power-On Reset pin is used to reset the whole
MAS 35x9F, except for the DC/DC converter circuitry.
POR is an active-low signal.
TE
IN
The TE pin is for production test only and must be con-
nected with VSS in all applications.
SUB (LFBGA-81 ONLY)
Chip substrate connection. Must be connected to VSS
in all applications.
60
Micronas
ADVANCE INFORMATION
MAS 35x9F
4.4. Pin Configurations
PI12
PI13
PI14
PI15
PI16
PI17
PI18
PI19
SOD
SOI
SOC
SID
SII
SIC
SPDO
PCS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SIBD 49
SIBC 50
32 PR
31 PRTW
30 PRTR
29 EOD
SIBI 51
SPDI2 52
SPDI1 53
SPDIR 54
FILTL 55
AVDD0 56
OUTL 57
OUTR 58
AVSS0 59
FILTR 60
AVSS1 61
VREF 62
PVDD 63
AVDD1 64
28 PUP
27 VBAT
26 SYNC
25 I2CD
MAS 35x9F
24 I2CC
23 CLKO
22 DCEN
21 VSENS2
20 DCSO2
19 DCSG2
18 DCSG1
17 DCSO1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
AGNDC
VSENS1
MICIN
MICBI
DVS
I2CVDD
XVDD
VDD
XVSS
VSS
POR
INL
INR
TE
XTI
XTO
Fig. 4–4: PLQFP64 package
Micronas
61
MAS 35x9F
ADVANCE INFORMATION
9
8
7
6
5
4
3
2
1
MAS 35x9F
PCS
PI19
PR
PI17
PI18
PI15
PI16
PI14
SUB
SUB
SUB
DVS
XVDD
XVSS
PI13
PI12
SOD
SUB
SUB
SUB
POR
VSS
XTO
SOI
SOC
SIC
SII
SIBC
SIBI
SIBD
SPDI2
FILTL
OUTL
OUTR
FILTR
VREF
PVDD
AVDD1
A
A
PRTW
SID
SUB
SUB
SPDO
SUB
SUB
INL
B
B
C
D
E
F
EOD
PRTR
PUP
SUB
SPDI1
SPDIR
AVDD0
AVSS0
AVSS1
AGNDC
MICIN
C
VBAT
SUB
SUB
SUB
SUB
TE
D
I2CD
I2CC
SYNC
SUB
E
CLKO
DCEN
DCSO2
DCSG1
F
VSENS2
SUB
G
G
H
J
DCSG2
I2CVDD
VDD
INR
XTI
H
DCSO1
VSENS1
MICBI
J
9
8
7
6
5
4
3
2
1
Fig. 4–5: LFBGA81 package
62
Micronas
ADVANCE INFORMATION
MAS 35x9F
4.5. Internal Pin Circuits
TTLIN
VDD
N
Fig. 4–6: Input pins PCS, PR
VSS
Fig. 4–11: Input/output pins I2CC, I2CD
Fig. 4–7: Input pin TE, DVS, POR
VSENS
P
DCSO
N
DCSG
Fig. 4–12: Input/output pins DCSO1/2, DCSG1/2,
VSENS1/2
Fig. 4–8: Input pin DCEN
XVDD
P
XVDD
P
N
N
XVSS
XVSS
Fig. 4–9: Input/output pins SOC, SOI, SOD,
PI12...PI19, SPDO
Fig. 4–13: Output pins PRTW, EOD, PRTR, CLKO,
SYNC, PUP
XVDD
P
AVDD
P
XTI
P
N
XVSS
P
N
XTO
N
Fig. 4–10: Input pins SI(B)C, SI(B)I, SI(B)D
Enable
N
AVSS
Fig. 4–14: Clock oscillator XTI, XTO
Micronas
63
MAS 35x9F
ADVANCE INFORMATION
MICIN
INL
INR
XVDD
A
−
+
SPDI1,
SPDI2
−
D
+
SPDIR
AGNDC
XVDD
Fig. 4–15: Analog input pins MICIN, INL, INR
Bias
Fig. 4–19: S/PDIF inputs
+
−
AGNDC
MICBI
VBAT
+
VREF
−
programmable
=
Fig. 4–16: Microphone bias pin (MICBI)
VSS
VSS
Fig. 4–20: Battery voltage monitor VBAT
FILTL(R)
D
I
−
+
A
OUTL(R)
AGNDC
Fig. 4–17: Analog outputs OUTL(R) and connections
for filter capacitors FILTL(R)
+
AGNDC
−
1.25 V
VREF
Fig. 4–18: Analog ground generation with pin to
connect external capacitor
64
Micronas
ADVANCE INFORMATION
MAS 35x9F
4.6. Electrical Characteristics
4.6.1. Absolute Maximum Ratings
Symbol
TA
Parameter
Pin Name
Min.
−40
−40
Max.
Unit
°C
Ambient operating temperature
Storage Temperature
Power dissipation
85
TS
125
650
°C
PTOT
VDD, XVDD,
AVDD0/1,
I2CVDD
mW
VSUPA
VSUP
Analog supply voltages1)
Digital supply voltage
AVDD0/1
−0.3
−0.3
6
6
V
V
VDD, XVDD,
I2CVDD
VIdig
IIdig
VIana
IIana
IOaudio
IOdig
Input voltage, all digital inputs
Input current, all digital inputs
Input voltage, all analog inputs
Input current, all analog inputs
Output current, audio output2)
Output current, all digital outputs3)
Output current DCDC converter 1
Output current DCDC converter 2
−0.3
−20
−0.3
−5
VSUP +0.3
+20
V
mA
V
VSUP + 0.3
+5
mA
A
OUTL/R
−0.2
−50
0.2
+50
mA
A
IOdcdc1
DCSO1
DCSO2
1.5
IOdcdc2
1.5
A
1)
Both AVDD0 and AVDD1 have to be connected together!
These pins are not short-circuit proof!
Total chip power dissipation must not exceed absolute maximum rating
2)
3)
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
Micronas
65
MAS 35x9F
ADVANCE INFORMATION
4.6.2. Recommended Operating Conditions
Symbol
VSUPD1
VSUPD2
Parameter
Pin Name
Min.
2.5
Typ.
2.7
Max.
3.6
Unit
Digital supply voltage (decoder)
VDD, XVDD
V
Digital supply voltage
(G.729 A encoder)
2.7
2.9
3.6
I2C bus supply voltage
I2CVDD
VSUPDn
at VDD
3.9
V
1)
VSUPI2C
VSUPA
Analog audio supply voltage
AVDD0/1
2.2
2.7
3.6
1.6
V
Analog audio supply voltage in
relation to the digital supply volt-
age
0.62
VSUPD
VSUPx
PIN supply voltage in relation to
digital supply voltage
XVDD
0.62
1.6
VSUPD
1) n = 1,2
Table 4–1: Reference Frequency Generation and Crystal Recommendation
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
External Clock Input Recommendations
fCLK
Clock frequency
XTI, XTO
13.00
0.7
18.432
20.00
1.05
MHz
VPP
VCLKI
Clockamplitude of external clock XTI
fed into XTI at VAVDD = 2.2 V
Clockamplitude of external clock
fed into XTI at VAVDD = 2.7 V
0.55
0.45
1.25
0.75
0.55
45
1.5
1.75
2.2
2.7
3.3
55
Clockamplitude of external clock
fed into XTI at VAVDD = 3.3 V
Clockamplitude of external clock XTO
fed into XTO at VAVDD = 2.2 V
Clockamplitude of external clock
fed into XTO at VAVDD = 2.7 V
Clockamplitude of external clock
fed into XTO at VAVDD = 3.3 V
Duty cycle
XTI, XTO
50
%
66
Micronas
ADVANCE INFORMATION
MAS 35x9F
Table 4–1: Reference Frequency Generation and Crystal Recommendation
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Crystal Recommendations
fP
Load resonance frequency at
CI = 20 pF
XTI, XTO
18.432
MHz
ppm
ppm
∆f/fS
∆f/fS
Accuracy of frequency adjust-
ment
−50
−50
50
50
Frequency variation vs. temper-
ature
REQ
C0
Equivalent series resistance
Shunt (parallel) capacitance
12
3
30
5
Ω
pF
Table 4–2: Input Levels
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
IIL
Input low voltage
at VDD = 2.5...3.6 V
I2CC,
I2CD
0.3
V
IIH
IIL
IIH
Input high voltage
at VDD = 2.5...3.6 V
1.4
V
V
V
Input low voltage
at VDD = 2.5...3.6 V
POR,
DCEN
0.2
0.3
Input high voltage
at VDD = 2.5...3.6 V
0.9
IILD
IIHD
Input low voltage
Input high voltage
PI<I>,
SI(B)I,
SI(B)C,
SI(B)D, PR,
PCS,
V
V
VSUP
−0.5
TE, DVS
Micronas
67
MAS 35x9F
ADVANCE INFORMATION
Table 4–3: Analog Input and Output Recommendations
Symbol
Parameter
Pin Name
AGNDC
PVDD
Min.
1.0
3
Typ.
Max.
Unit
Analog Reference
CAGNDC1
CAGNDC2
CPVDD
Analog filter capacitor
3.3
10
µF
nF
nF
Ceramic capacitor in parallel
Capacitor for analog circuitry
Analog Audio Inputs
CinAD DC-decoupling capacitor at A/D- INL/R
390
390
nF
nF
nF
converter inputs
CinMI
DC-decoupling capacitor at
microphone-input
MICIN
CLMICBI
Minimum-Capacitance at micro- MICBI
phone bias
3.3
Analog Audio Filter Outputs
CFILT Filter capacitor for headphone
FILTL/R
OUTL/R
−20 %
470
+20 %
pF
amplifier
high-Q type,
NP0 or C0G material
Analog Audio Output
ZAOL_HP Analog output load with stereo
OUTL/R
16
Ω
headphones
100
pF
DC/DC-Converter External Circuitry (please refer to application example)
C1
VTH
L
VSENS blocking
(<100 mΩ ESR)
VSENS1/2
330
0.35
22
µF
V
Schottky diode threshold voltage DCSO1/2
VSENS1/2
Ferrite ring core coil inductance
DCSO1/2
µH
S/PDIF Interface Analog Input
CSPI S/PDIF coupling capacitor
SPDI1/2
SPDIR
100
nF
68
Micronas
ADVANCE INFORMATION
MAS 35x9F
4.6.3. Digital Characteristics
at TA = TA, VSUPD, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 °C
Symbol
Parameter
Pin Name
Min.
Typ.
Max. Unit
Test Conditions
Digital Supply Voltage
ISUPD
ISUPD
ISUPD
Current consumption
VDD,
XVDD,
I2CVDD
39
24
15
mA
mA
mA
2.5 V, sampling fre-
quency ≥ 32 kHz
Current consumption
Current consumption
2.5 V, sampling fre-
quency ≤ 24 kHz
2.5 V, sampling fre-
quency
≤ 12 kHz
Digital Outputs and Inputs
ODigL
ODigH
Output low voltage
Output low voltage
PI<I>,
SOI,
SOC,
SOD,
0.3
V
V
Iload = 2 mA
VSUPD
−0.3
Iload = −2 mA
EOD,
PRTR,
PRTW,
CLKO,
SYNC, PUP,
SPDO
ZDigI
Input impedance
ALLDIGITAL
INPUTS
7
1
pF
µA
IDLeak
Digital input leakage cur-
rent
−1
0 V < Vpin < VSUPD
ISTANDBY
Total current at stand-by
10
µA
DSP off, Codec off,
DC/DC off, AD and
DAC off, no I2C access
Micronas
69
MAS 35x9F
ADVANCE INFORMATION
4.6.3.1. I2C Characteristics
at TA = 25°C, VSUPI2C = 2.5...3.6 V
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
I2C Input Specifications
fI2C
Upper limit I2C bus frequency I2CC
operation
400
300
300
kHz
ns
tI2C1
I2C START condition setup
time
I2CC,
I2CD
tI2C2
I2C STOP condition setup
time
I2CC,
I2CD
ns
tI2C3
tI2C4
tI2C5
I2C clock low pulse time
I2C clock high pulse time
I2CC
I2CC
I2CC
1250
1250
80
ns
ns
ns
I2C data setup time before
rising edge of clock
tI2C6
I2C data hold time after falling I2CC
edge of clock
80
ns
V
VI2COL
II2COH
tI2COL1
tI2COL2
VI2CIL
VI2CIH
tW
I2C output low voltage
I2CC,
I2CD
0.4
1
Iload = 3 mA
I2C output high leakage
current
I2CC,
I2CD
µA
ns
ns
I2C data output hold time after I2CC,
20
falling edge of clock
I2CD
I2C data output setup time
before rising edge of clock
I2CC,
I2CD
250
fI2C = 400 kHz
I2C input low voltage
I2C input high voltage
Wait time
I2CC;
I2CD
0.3
4
VSUPI2C
VSUPI2C
ms
I2CC,
I2CD
0.6
0
I2CC,
I2CD
0.5
70
Micronas
ADVANCE INFORMATION
MAS 35x9F
1/fI2C
tI2C4
tI2C3
H
I2CC
L
tI2C1
tI2C5
tI2C6
tI2C2
H
I2CD as input
L
tIC2OL1
tI2COL2
H
I2CD as output
L
Fig. 4–21: I2C timing diagram
Micronas
71
MAS 35x9F
ADVANCE INFORMATION
4.6.3.2. Serial (I2S) Input Interface Characteristics (SDI, SDIB)
at TA = TA, VSUPD, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 °C
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
tSICLK
I2S clock input clock period
SI(B)C
325
ns
fS = 48 kHz Stereo,
32 bits per sample
(for demand mode see
Table 4–4)
tSIDS
I2S data setup time before
rising edge of clock (for
continuous data stream:
falling edge)
SI(B)C,
SI(B)D
50
ns
tSIDH
tSIIS
I2S data hold time
SI(B)D
50
50
ns
ns
I2S ident setup time before
rising edge of clock (for
continuous data stream:
falling edge)
SI(B)C,
SI(B)I
tSIIH
tbw
I2S ident hold time
Burst wait time
SI(B)I
50
ns
SI(B)C,
SI(B)D
480
Table 4–4: Maximum demand clock frequency
fSample (kHz)
48, 32
44.1
fC (MHz)
6.144
5.6448
3.072
24, 16
22.05
2.8224
1.536
12, 8
11.025
1.4112
72
Micronas
ADVANCE INFORMATION
MAS 35x9F
TSICLK
H
SI(B)C
L
H
SI(B)I
L
SI(B)D H
L
TSIDH
TSIDS
Fig. 4–22: Continuous data stream at serial input A or B. In this mode, the word strobe SI(B)I is not used and the
data are read at the falling edge of the clock (bit 2 in D0:346 is set).
TSICLK
H
SI(B)C
L
H
SI(B)I
L
TSIIS
TSIIH
H
L
SI(B)D
TSIDH
TSIDS
Fig. 4–23: Serial input of I2S signal
Micronas
73
MAS 35x9F
ADVANCE INFORMATION
4.6.3.3. Serial Output Interface Characteristics (SDO)
at TA = TA, VSUPD, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 °C
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
tSOCLK
I2S clock output frequency
SOC
325
ns
fS=48 kHz Stereo
32 bits per sample
tSOISS
I2S word strobe delay time
after falling edge of clock
SOC,
SOI
0
0
tSOCLK ns
/4
C
load = t.b.d.
Rload = t.b.d.
tSOODC
I2S data delay time after
falling edge of clock
SOC,
SOD
tSOCLK ns
/4
Cload = t.b.d.
Rload = t.b.d.
TSOCLK
H
SOC
L
H
L
SOI
TSOISS
TSOISS
H
L
SOD
TSOODC
Fig. 4–24: Serial output interface timing.
V
V
h
l
SOC
V
V
h
l
7
6 5 4 3 2 1 0
15 14 13 12 11 10
14
15
13 12 11 10
8
9
9
8
7 6 5 4 3 2 1 0
SOD
SOI
V
V
h
l
right 16-bit audio sample
left 16-bit audio sample
Fig. 4–25: Sample timing of the SDO interface in 16 bit/sample mode. D0:346 settings are: Bit 14 = 0 (SOC not
inverted), bit 11 = 1 (SOI delay), bit 5 = 0 (word strobe not inverted), bit 4 = 1 (16 bits/sample).
74
Micronas
ADVANCE INFORMATION
MAS 35x9F
V
V
h
...
...
SOC
l
V
V
h
SOD
SOI
...
31
30 29 28 27 26 25 ...
0
31 30 29 28 27 26 25
7
6
5
4
3
2
1
7 6 5 4 3 2 1 0
l
V
V
h
right 32-bit audio sample
left 32-bit audio sample
l
Fig. 4–26: Sample timing of the SDO interface in 32 bit/sample mode. D0:346 settings are: Bit 14 = 0 (SOC not
inverted), bit 11 = 0 (no SOI delay), bit 5 = 1 (word strobe inverted), bit 4 = 0 (32 bits/sample).
Micronas
75
MAS 35x9F
ADVANCE INFORMATION
4.6.3.4. S/PDIF Input Characteristics
at TA = TA, VSUPD, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 °C.
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VS
Signal amplitude
SPDI1, SPDI2, 200
SPDIR
500
1000
mVpp
fs1
fs2
fs3
tP
Bi-phase frequency
Bi-phase frequency
Bi-phase frequency
Bi-phase period
Rise time
SPDI1, SPDI2,
SPDIR
2.048
2.822
3.072
326
MHz
MHz
MHz
ns
±1000 ppm, fs = 48 kHz
SPDI1, SPDI2,
SPDIR
±1000 ppm,
fs = 44.1 kHz
SPDI1, SPDI2,
SPDIR
±1000 ppm, fs = 32 kHz
SPDI1, SPDI2,
SPDIR
at fs = 48 kHz, (highest
sampling rate)
tR
SPDI1, SPDI2,
SPDIR
0
65
ns
at fs = 48 kHz, (highest
sampling rate)
tF
Fall time
SPDI1, SPDI2,
SPDIR
0
65
ns
at fs = 48 kHz, (highest
sampling rate)
Duty cycle
SPDI
40
81
50
60
%
at bit value=1 and
fs = 48 kHz
tH1,L1
SPDI
163
ns
minimum/maximum pulse
duration with a level above
90 % or below 10 % and
at fs = 48 kHz
tH0,L0
SPDI
163
244
ns
minimum/maximum pulse
duration with a level above
90 % or below 10 % and
at fs = 48 kHz
tR
tF
tH1
tL1
Bit value = 1
Bit value = 0
tH0
tL0
tP
Fig. 4–27: Timing of the S/PDIF input
76
Micronas
ADVANCE INFORMATION
MAS 35x9F
4.6.3.5. S/PDIF Output Characteristics
at TA = TA, VSUPD, VSUPA = 2.5 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 °C.
Symbol
Parameter
Pin Name
SPDO
Min.
Typ.
Max.
Unit
MHz
MHz
MHz
ns
Test Conditions
fs = 48 kHz
fs1
fs2
fs3
tP
Bi-phase frequency
Bi-phase frequency
Bi-phase frequency
Bi-phase period
3.072
2.822
2.048
326
SPDO
fs = 44.1 kHz
fs = 32 kHz
SPDO
SPDO
at fs = 48 kHz, (highest
sampling rate)
tR
Rise time
Fall time
SPDO
SPDO
0
0
2
2
ns
ns
Cload = 10 pF
Rload = t.b.d.
tF
Cload = 10 pF
Rload = t.b.d.
Duty cycle
SPDO
SPDO
50
%
tH1,L1
tH0,L0
VS
163
ns
minimum/maximum pulse
duration with a level above
90 % or below 10 % and
at fs = 48 kHz
SPDO
SPDO
326
ns
minimum/maximum pulse
duration with a level above
90 % or below 10 % and
at fs = 48 kHz
Signal amplitude
VSUPD
tR
tF
tH1
tL1
Bit value = 1
Bit value = 0
tH0
tL0
tP
Fig. 4–28: Timing of the S/PDIF output
Micronas
77
MAS 35x9F
ADVANCE INFORMATION
4.6.3.6. PIO as Parallel Input Interface: DMA Mode
Symbol Pin
Name
Min.
Max.
Unit
In decoding mode, the data transfer can be started
after the EOD pin of the MAS 35x9F is set to “high”.
After verifying this, the controller signalizes the send-
ing of data by activating the PR line. The MAS 35x9F
responds by setting the RTR line to the “low” level. The
MAS 35x9F reads the data PI[19:12] and sets RTR to
low after rising edge of PR. After RTR is set to high,
the mC sets PR to low. The next data word write oper-
ation will be initialized again by setting the PR line via
the controller. Please refer to Figure 4–29 for the exact
timing
tst
tr
PR, EOD
PR, RTR
0.010
40
2000
160
µs
ns
ns
tpd
PR,
120
480
PI[19:12]
tset
th
trtrq
tpr
PI[19:12]
PI[19:12]
RTR
160
160
200
480
160
40
ns
ns
ns
ns
ns
ns
µs
30000
The procedure above will be repeated until the
MAS 35x9F sets the EOD signal to “0” which indicates
that the transfer of one data block has been executed.
Subsequently, the controller should set PR to “0”, wait
until EOD rises again and then repeat the procedure to
send the next block of data. The DMA buffer is
15 bytes long.
PR
trpr
teod
teodq
PR, RTR
PR, EOD
EOD
160
500
2.5
The buffer size is subject to change in the next version.
.
teod
trpr
teodq
tst
tr trtrq
tpd
high
low
EOD
PR
high
tpr
low
high
low
RTR
tset
th
high
low
PI[19:12]
Byte 1
Byte 15
MAS 35x9F latches the PIO DATA
Fig. 4–29: Handshake protocol for writing MPEG data to the PIO-DMA
78
Micronas
ADVANCE INFORMATION
MAS 35x9F
4.6.3.7. PIO as Parallel Output Interface
Some downloadable software may use the PIO inter-
face (lines PI19...PI12) as output. The data transfer
rate and conditions are defines by the software func-
tion.
7DEOHꢀꢁ±ꢂꢃ PIO output mode timing
Symbol Pin
Min.
RTW, PCS 0.010
PCS 0.330
PCS, RTW 0.010
Max.
Unit
µs
Handshaking for PIO output mode is accomplished
through the RTW, PCS, and PI12..PI19 signal lines
(see Fig. 4–30). The PR line has to be set to high level.
t0
t1
t2
t3
t4
t5
1800
µs
RTW will go low as soon as a byte is available in the
output buffer and will stay low until a byte has been
read. Reading of a byte is performed with a PCS
pulse. Data is latched out from the MAS on the falling
edge of PCS and removed from the bus on the rising
edge of PCS.
µs
RTW
PI
0.330
0.330
0.081
10000
µs
µs
PI
µs
t0
t1 t2
t3
RTW
PIxx
PCS
t4
t5
Fig. 4–30: Output Timing
Micronas
79
MAS 35x9F
ADVANCE INFORMATION
4.6.4. Analog Characteristics
at TA = TA, VSUPD = 2.5...3.6 V, VSUPA = 2.2 ... 3.6 V, fCrystal = 13...20 MHz,
typical values at TA = 25 °C and fCRYSTAL = 18.432 MHz
Symbol
Analog Supply
IAVDD Current consumption analog
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
AVDD0/1
AVDD0/1
5
mA
VSUPA = 2.2 V, Mute
audio
IQOSC
Current consumption crystal
oscillator
200
µA
Codec = off
DSP = off
DC/DC = on
ISTANDBY
10
Codec = off
DSP = off
DC/DC = off
Crystal Oscillator
VDCCLK
VACLK
DC voltage at oscillator pins
XTI, XTO
0.5
VSUPA
Clock amplitude
0.5
VSUPA VPP
if crystal is used
VSUPA = 2.2 V
−0.5
CIN
Input capacitance
Output resistance
3
pF
ROUT
XTO
220
125
94
Ω
V
V
SUPA = 2.7 V
SUPA = 3.3 V
Analog Audio
VAI
Analog line input clipping
level (at minimum analog
input gain,i.e. −3 dB)
INL/R
Vpp
VSUPA
Bits 15, 14
in Reg. 6Ahex
2.2
2.6
3.2
>2.2 V
>2.4 V
>3.0 V
VSUPA
00
01
10
VMI
Microphone input clipping
level (at minimum analog
input gain, i.e. +21 dB)
MICIN
mVpp
Bits 15,14
in Reg. 6Ahex
141
167
282
>2.2 V
>2.4 V
>3.0 V
00
01
10
80
Micronas
ADVANCE INFORMATION
MAS 35x9F
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VAO1
Analog Output Voltage AC
OUTL/R
RL≥1 kΩ
Input=0 dBFS digital
VSUPA
Bits 15, 14
in Reg 6Ahex
at 0 dB output gain
at +3 dB output gain
1.56
1.84
2.27
2.20
2.60
3.20
Vpp
Vpp
mV
>2.2 V
>2.4 V
>3.0 V
>2.2 V
>2.6 V
>3.2 V
00
01
10
00
01
10
dVAO1
Deviation of DC-Level at
Analog Output for AGNDC-
Voltage
OUTL/R
OUTL/R
−20
20
VAO2
Analog Output Voltage AC
RLis 16 Ω Headphone and
22 Ω seriesresistor
Input=0 dBFS digital
(see Fig. 4–34 on
page 88)
VSUPA
Bits 15, 14
in Reg 6Ahex
at 0 dB output gain
1.56
1.84
2.27
2.00
2.40
3.00
97
Vpp
Vpp
kΩ
>2.2 V
>2.4 V
>3.0 V
>2.2 V
>2.6 V
>3.2 V
00
01
10
00
01
10
at +3 dB output gain
Analog line input resistance
RinAI
INL/R
at minimum analog input
gain, i.e. −3 dB
20
at maximum analog input
gain, i.e. +19.5 dB
67
94
not selected
RinMI
Microphone input resistance
MICIN
kΩ
at minimum analog input
gain, i.e. −21 dB
8
at maximum analog input
gain, i.e. +43.5 dB
94
not selected
RinAO
Analog output resistance
OUTL/R
INL/R
6
Ω
analog gain=+3 dB,
Input=0 dBFS digital
SNRAI
Signal-to-noise ratio of line
input
74
dB(A) BW = 20 Hz...20 kHz,
analog gain=0 dB, input
1 kHz at VAI−20 dB
Micronas
81
MAS 35x9F
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
SNRMI
Signal-to-noise ratio of
microphone input
MICIN
73
dB(A) BW = 20 Hz...20 kHz,
analog gain=+21 dB, input
1 kHz at VMI−20 dB
THDAI
Total harmonic distortion of
analog inputs
INL/R
MICIN
0,01
0.02
%
BW = 20 Hz...20 kHz,
analog gain = 0 dB,
resp. 24 dB,
input 1 kHz at
−3 dBFS=VAI−6 dB
resp. VMI-6 dB
XTALKAI
PSRRAI
Crosstalk attenuation
left/right channel
INL/R
MICIN
80
dB
f = 1 kHz, sine wave,
analog gain = 0 dB,
input = −3 dBFS
(analog inputs)
Power supply rejection ratio
for analog audio inputs
AVDD0/1,
INL/R
MICIN
45
20
dB
dB
1 kHz sine at 100 mVrms
≤100 kHz sine at
100 mVrms
Audio Output
SNRAO
Signal-to-noise ratio of analog OUTL/R
output
94
dB(A) RL≥16 Ω
BW = 20 Hz...20 kHz,
analog gain = 0 dB
input = -20 dBFS
THDAO
Total harmonic distortion
(headphone)
OUTL/R
for RL≥16Ω plus 22Ω series
resistor
0.03
0.05
%
(see Fig. 4–34 on page 88)
for RL≥1kΩ
0.003 0.01
%
LevMuteAO
Mute level
OUTL/R
−113
dBV
A-weighted
BW=20 Hz...22kHz , no
digital input signal,
analog gain=mute
XTALKAO
Crosstalk attenuation left/right OUTLR
channel (headphone)
80
dB
f=1 kHz, sine wave,
OUTL/R: RL≥16 Ω
(see Fig. 4–34 on
page 88)
analog gain=0 dB
input=-3 dBFS
PSRRAO
Power supply rejection ratio
for analog audio outputs
AVDD0/1
OUTL/R
70
35
dB
dB
1 kHz sine at 100 mVrms
≤100 kHz sine at
100mVrms
VAGNDC
Analog Reference Voltage
AGNDC
V
RL >> 10 MΩ,
referred to VREF
VSUPA
Bits 15, 14 in
Reg. 6Ahex
1.1
1.3
1.6
>2.2 V
>2.4 V
>3.0 V
00
01
10
82
Micronas
ADVANCE INFORMATION
MAS 35x9F
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VMICBI
Bias voltage for microphone
MICBI
VSUPA
Bits 15, 14 in
Reg. 6Ahex
1.8
>2.2 V
>2.4 V
>3.0 V
00
01
10
2.13
2.62
180
RMICBI
IMAX
Source resistance
MICBI
Ω
Maximum current microphone MICBI
bias
µA
VSUPA
>2.2 V
Bits 15, 14 in
Reg. 6Ahex
300
00
Micronas
83
MAS 35x9F
ADVANCE INFORMATION
4.6.5. DC/DC Converter Characteristics
at TA = TA, Vin = 1.2 V (unless otherwise noted), Voutn = 3.0 V, fclk = 18.432 MHz, fsw = 384 kHz,
Typ. values for TA = 25 °C
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VIN
Minimum start-up input
voltage
*
0.9
V
I
LOAD ≤ 1 mA,
DCCF = 5050hex (reset)
VIN
Minimum operating input
voltage
DC1*
DC2*
0.7
0.8
V
V
V
I
LOAD = 50 mA,
DCCF = 5050hex (reset)
DC1*
DC2*
1.1
1.2
ILOAD = 200 mA,
DCCF = 5050hex (reset)
VOUT
Programmable output voltage VSENSN
range
2.0
3.5
Voltage settings in DCCF
register (I2C subaddress
76hex
)
VOTOL
ILOAD1
ILOAD2
Output voltage tolerance
VSENSN
VSENSN
2.88
3.12
200
600
V
ILOAD = 20 mA
TA = 25 °C
Output current
1 battery cell
mA
mA
%/V
VIN = 0.9...1.5 V, 330 µF
Output current
2 battery cells
VIN = 1.8...3.0 V, 330 µF
dVOUT
/
Line regulation
VSENSN
0.8
dVIN/VOUT
dVOUT
VOUT
/
Load regulation
DC1
VSENS1
VSENS2
−1.7
−1.8
%
ILOAD = 20...200 mA,
DC2
hmax
Maximum efficiency
Switching frequency
−
95
%
VIN = 2.4 V, VOUT = 3.5 V
fswitch
DCSOn
297
384
250
576
kHz
(see Table 2–1 on
page 11)
fstartup
Switching frequency during
start-up
DCSOn
kHz
µA
VSENSn < 1.9 V
1)
IsupPFM1
IsupPFM2
IsupPWM1
IsupPWM2
Ilnmax
Supply current in PFM mode
VSENS1
VSENS2
75
135
265
325
1
Supply current in PWM mode VSENS1
VSENS2
µA
VSENSn
1)
2)
NMOS switch current limit
(low side switch)
DCSOn,
DCSGn
A
Ilptoff
PMOS switch turnoff current
(rectifier switch)
DCSOn,
VSENSn
70
mA
µA
ILEAK
leakage current
DCSOn,
DCSGn
0.1
Tj = 25 °C, converter off,
ILOAD = 0 µA
1) Current into VSENSn. VIN > VOUT+∆V; (∆V≈0.4 V); no DC/DC-Converter regulation switching action present
2) Add. current of oscillator at PIN AVDD0/1, (see Section 4.6.4. on page 80)
84
Micronas
ADVANCE INFORMATION
MAS 35x9F
4.6.6. Typical Performance Characteristics
Efficiency vs. Load Current
Efficiency vs. Load Current
DCDC1 (VOUT = 3.5 V)
DCDC2 (VOUT = 3.5 V)
100
100
80
60
40
20
0
3.0 V
3.0 V
80
1.8 V
1.8 V
60
VIN:
3.0 V
2.4 V
VIN:
3.0 V
2.4 V
1.8 V
40
1.8 V
PFM
PWM
PFM
PWM
20
0
10−4
1
10−4
1
10−3
10−2
10−1
10−3
10−2
10−1
Load Current (A)
Load Current (A)
Efficiency vs. Load Current
Efficiency vs. Load Current
DCDC1 (VOUT = 3.0 V)
DCDC2 (VOUT = 3.0 V)
100
80
60
40
20
0
100
80
60
40
20
0
2.4 V
2.4 V
0.9 V
0.9 V
VIN:
VIN:
2.4 V
1.5 V
1.2 V
0.9 V
2.4 V
1.5 V
1.2 V
0.9 V
PFM
PFM
PWM
PWM
10−4
1
10−4
1
10−3
10−2
10−1
10−3
10−2
10−1
Load Current (A)
Load Current (A)
Fig. 4–31: Efficiency vs. Load Current
Micronas
85
MAS 35x9F
ADVANCE INFORMATION
Efficiency vs. Load Current
Efficiency vs. Load Current
DCDC1 (VOUT = 2.2 V)
DCDC2 (VOUT = 2.2 V)
100
80
60
40
20
0
100
80
60
40
20
0
1.5 V
1.5 V
0.9 V
0.9 V
VIN:
VIN:
1.5 V
1.2 V
0.9 V
1.5 V
1.2 V
0.9 V
PFM
PFM
PWM
PWM
10−4
1
10−4
1
10−3
10−2
10−1
10−3
10−2
10−1
Load Current (A)
Load Current (A)
Maximum Load Current
vs. Input Voltage
Maximum Load Current
vs. Input Voltage
0.8
0.6
0.4
0.8
0.6
0.4
DCDC1
DCDC2
Vout
:
Vout:
2.2 V
3.0 V
3.5 V
2.2 V
3.0 V
3.5 V
PFM
PFM
PWM
PWM
0.2
0
0.2
0
0.0
0.0
1.0
2.0
3.0
1.0
2.0
3.0
Input Voltage (V)
Input Voltage (V)
Fig. 4–32: Maximum Load Current vs. Input Voltage
Note: Efficiency is measured as VSENSn × ILOAD / (Vin × Iin).
IAVDD is not included (Oscillator current)
86
Micronas
VDC2
VDC2
Portable radio
telephone
Serial memory device
e.g. SDI-Card
Parallel memory device
e.g. SmartMediaCard
3
D
3
MPEG, SC4
D
DigiAmp
MD-recorder
MPEG, CELP, SC4
8
IEC 60958
Reference
clock
VDC2
2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SIBD 49
SIBC 50
SIBI 51
32 PR
5
D
10k
31 PRTWQ
30 PRTRQ
29 EODQ
28 PUP
PIO-control
100n
100n
75
75
DAB-receiver
DVD-player
SPDI2 52
SPDI1 53
MPEG (IEC 61937)
ADR-receiver
SPDIR 54
FILTL 55
AVDD0 56
OUTL 57
OUTR 58
AVSS0 59
FILTR 60
AVSS1 61
VREF 62
PVDD 63
AVDD1 64
27 VBAT
26 SYNC
25 I2CD
100n
470p
22
220u
220u
MAS 35x9F
24 I2CC
23 CLKO
22 DCEN
21 VSENS2
20 DCSO2
19 DCSG2
18 DCSG1
17 DCSO1
22
4k7
L
R
4k7
100
VDC2
100
470p
3n
µC
Headphone
> 16
1.5k
1.5k
Ω
6.8n
6.8n
22u
10n
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
See figure caption
3u3
10n
Place all cermic capacitors
as close as possible to IC pins
220p
VDC1
1n
1n
A
470p capacitorss should be
high-Q (NP0 or C0G)
1.5u
18p
1.5u
18p
Option for
I2C-address
D
A
D
4u7
390 n
connect to
VSS or I2CVDD
A
D
390n
Star point
ground connection
very close to pins
DCSG1 and DCSG2
VDC2
18.432 MHz
390n
VDC1
10k
3.6...5.6 k
MIC
3.3 n
390p
390p
Place VDD / XVDD -filter
capacitors above ground plane
A
separate trace
Tape recorder
FM radio
MAS 35x9F
ADVANCE INFORMATION
4.8. Recommended DC/DC Converter Application Circuit
(Power optimized szenario, (see Fig. 2–5 on page 13))
VBAT
L1 = 22 µH
DCSO1
D1, Schottky
+
AVDD0/1
VSENS1
C3 = 330 µF
V
(Input Voltage)
in
(0.9..1.5 V)
VDC1
e.g. 2.2 V
C1 = 330 µF
(low ESR)
+
DCSG1
VSS, XVSS
D
DCEN
Power-On Push Button
L2 = 22 µH
DCSO2
D2, Schottky
VSENS2
VDC2
e.g. 3.0 V
for µC,
Storage Media
C2 = 330 µF
(low ESR)
+
Star Point
Ground Connection
very close to Pins
DCSG2
DCSG1 and DCSG2
V
REF
D
AVSS0/1
A
A
Fig. 4–34: External circuitry for the DC/DC converters
88
Micronas
ADVANCE INFORMATION
MAS 35x9F
Micronas
89
MAS 35X9F
ADVANCE INFORMATION
5. Data Sheet History
1. Advance Information: “MAS 3509F,
MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A
Codec”, August 04, 2000, 6251-505-1AI.
First release of the advance information.
2. Advance Information: “MAS 35x9F,
MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A
Codec”, October 31, 2000, 6251-505-2AI.
Second release of the advance information.
Major changes:
This data sheet applies to MAS 35x9F version A2.
3. Advance Information: “MAS 35x9F,
MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A
Codec”, April xx, 2001, 6251-505-3AI.
Third release of the advance information.
Major changes:
New supply voltages
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com
Printed in Germany
Order No. 6251-505-3AI
90
Micronas
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