U3550BM-AFLG3 [TEMIC]
Low-Power FM Transmitter / Synthesizer System 26 to 50 MHz; 低功耗FM发射器/合成器系统26至50兆赫
| 型号： | U3550BM-AFLG3 |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Low-Power FM Transmitter / Synthesizer System 26 to 50 MHz |
| 文件： | 总25页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U3550BM
Low-Power FM Transmitter / Synthesizer System 26 to 50 MHz
Description
The U3550BM is a radio-frequency IC for analog The receive part is designed for a double-conversion
cordless telephone applications in the 26/50-MHz band architecture. The incoming radio-frequency signal will
(CTO standard). The IC performs full duplex communi- be filtered and amplified before reaching the first mixer.
cation. The transmitting and receiving frequency depends At this stage, the RF signal will be converted down to the
on whether the IC is used in the handset or in the base first intermediate frequency (10.7 MHz) by using a local
station.
adjustable oscillator (VCO3). The frequency of this
oscillator is controlled by the PLL.
The U3550BM’s frequency converter consists of an FM
transmitter with switchable output power and receiver
Mixer 1 in the same unit. A two-wire bus interface can be
used for frequency control as well as for switching the
transmitter’s power amplifier and the receiver. Fine
frequency adjustment of the reference crystal oscillator is
programmable.
The transmitter part contains two PLL-controlled VCOs.
The frequency modulation is accomplished by
superposing the incoming audio signal on the first PLL
control voltage. In this system, the frequency is a product
of mixing VCO1 with local oscillator (VCO3). The FM-
modulated carrier is amplified by external power
amplifier before entering the output filter and the antenna
connector.
Features
Application
All PLLs and most of the oscillators are integrated
CT0 (USA, France, Spain, Netherlands, Portugal,
Korea, Taiwan, New Zealand, China)
All functions and channel selection controllable by
serial bus
Narrowband voice and data transmitting / receiving
systems
Receiver Mixer 1 with integrated image rejection
Up to 25 channels selectable depending on CT0
standard
Integrated oscillator circuit with external crystal
(11.15 MHz)
Programmable carrier-modulation frequency
Block Diagram
VBAT DELVB DELGND MIXO LOGND PCLO
OSCVDD MCKA OSCGND
Mixer 1
11.15 MHz
20
XCK
Oscillator
interface
VCC
+ 45
MCKO
MIXIN
10.7 MHz
– 45
sin
MIXVB
K
cos
cos
LO1
LO2
C
D
Phase
comparator
Serial BUS
interface
VCO 3
2
N
557.5 KHz
sin
Mixer 2
+ 45
D 1
D 2
VCO 1
2
D 3
P
GREF
VTX
– 45
RFOVB
RFO
Loop
filter
Phase
comparator
Phase
VCO 2
LFGND
13280
comparator
RFOGND
AGND
VSS
MODIN
MLF
Figure 1. Block diagram
Rev. A2, 10-Sep-98
1 (25)
Preliminary Information
U3550BM
Pin Description
Pin
1
2
3
4
5
6
7
Symbol
Function
1
2
3
4
5
6
7
8
9
28
MCKO
VCC
MCKO Clock output for peripherals
D
C
Data input of serial bus
Clock line of serial bus
27
26
D
C
VSS
OSCGND Oscillator ground
XCK
OSCVDD Oscillator supply input
DELVB Phase correction VCO3 supply
input
MCKA
Oscillator input (11.15 MHz)
25
24
OSCGND
MODIN
LFGND
MLF
XCK
OSCVDD
DELVB
8
9
DELGND Phase correction VCO3 ground
GREF
23
22
Voltage reference for internal
current sources
10
11
12
13
14
15
16
17
18
19
MIXIN Mixer input
MIXVB Mixer-supply input
MIXO
LO1
LO2
VBAT
AGND
VTX
21
20
19
18
17
DELGND
GREF
Mixer output
Tank elements for LO are
connected to these pins
PCLO
Phase comparator PLL3 output
10
11
12
13
14
RFOVB
RFO
MIXIN
LOGND VCO3 ground
RFOGND RF transmit output ground
MIXVB
RFO
RF transmit output
RFOVB Power-supply input of RF
transmit output buffer
VTX
MIXO
LO1
RFOGND
LOGND
PCLO
16
15
20
Power-supply output of RF
external power amplifier
LO2
21
22
23
24
25
26
AGND Analog ground
VBAT
MLF
LFGND Modulator loop-filter ground
MODIN Modulator input signal
MCKA Peripheral-clock output
adjustment
Power supply of analog part
Modulator loop filter
11623
Figure 2. Pinning
27
28
VSS
VCC
Digital ground
Power supply of digital part
Order Information
Extended Type Number
U3550BM-AFL
U3550BM-AFLG3
Package
SO28
SO28
Remarks
Taped and reeled
2 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
VCO Adjustments
Duration Adjustment of the
Anti-Backlash Signals
To be able to use a wide VCO frequency range
(i.e., VCO2 = 26.3 to 49.9 MHz), VCO1 and VCO2 have
a rough adjust and a fine adjust to increase the frequency
range given by the phase comparator.
The phase comparators of the modulator- and the mixer-
loop have a 2-bit adjustment for the duration of the up-
and down pulses when the loop is locked (anti-backlash).
The 4 rough adjusts for VCO1 and VCO2 (3 used in
VCO1) are correlated to the country setting. For each
country, there are two sets of VCO rough adjust settings,
one for the base and one for the handset (see tables
Channel Frequencies, Dividers and Country Settings).
Best results can be achieved by setting all the bits
(AMOD[2:1], AMIX[2:1]) to 0.
Adjustment of the Modulator Gain
To achieve the adaption to the various country standards,
there is a fine adjust with 32 steps for VCO1 and VCO2.
These fine adjusts can be set manually (for test purposes)
or by the automatically mode. Theoretically, the indicator
of the change (increase/ decrease when the voltage of the
phase comparator is too high) is selectable. The program-
ming value ‘1’, however, is necessary.
To fulfill all requirements of the various countries, three
conversion gains of the modulator are selectable by the
bits GMOD[1:0].
For country settings, see tables Channel Frequencies,
Dividers and Country Settings. For the ranges, see tabel
Electrical Characteristics (RF transmitter).
Setting normal conditions VCO1:
EAFA1 = 1, automatic fine adjust VCO1 enabled
SAFA1 = 1, sign of auto fine adjustment VCO1 = 1.
Clock-Output Divider Adjustment
Setting for VCO2 is identical.
For VCO3, there is no internal adjustment.
The MCKO pin is a clock output derived from the crystal
oscillator. It can be used to drive a microprocessor or
other remote components and thereby reduces the number
of crystals required.
Speed-up of the Modulator Loop Filter
To obtain a fast locking time for the modulator loop, there
is a precharge and a speed-up mode for the external loop
filter.
The crystal oscillator frequency can be divided by an
integer value: 1, 2, 3, 4, 6 or switched off.
During receive mode (VCO3 enabled, VCO1 disabled),
the modulator loop filter is precharged to 1.25 V.
The divider value is adjusted by an analog level on the
MCKA pin.
During the first 30 ms after enabling VCO1, the modu-
lator phase comparator is in speed-up mode. In this mode,
the current of the phase comparator which charges the
loop filter is much larger than in normal mode. The
duration of the speed-up mode depends on the number of
oscillator clock cycles.
Table 1 shows the clock-output value on MCKO for
different divider values and the corresponding level
required on MCKA.
Crystal oscillator = 11.15 MHz.
Table 1. Clock-output values
Level on MCKA 0 to 7% VCC 13% to 27% VCC 33% to 47% VCC 53% to 67% VCC 73% to 87% VCC 93% to VCC
Level on MCKA
for VCC = 3.6 V
0 to 0.25
0.47 to 0.97
1.19 to 1.69
1.91 to 2.41
2.63 to 3.13
3.35 to 3.6
Corresponding
divider
X
6
4
3
2
1
Corresponding
clock on MCKO
(MHz)
No output
1.858
2.7875
3.716
5.575
11.15
Rev. A2, 10-Sep-98
3 (25)
Preliminary Information
U3550BM
Frequency Synthesis
Loop
96 11627
filter
3)
fRef3
fLO
Phase
comparator
11.15 MHz
K
VCO 3
2
N
D1
D2
2)
fRef
Loop
filter
Phase
comparator
VCO 2
VCO 1
2
D3
fmod
P+
Loop
filter
Q
223
1)
Phase
comparator
1)
Modulator loop
Mixer loop
Local oscillator (LO) loop
2)
3)
fRef1
=
557.5 kHz
Figure 3.
Modulator Loop and Mixer Loop Dividers
D1
4
D2
8
D3
2
fRef2 (MHz)
1.075
0.9
fmod (MHz)
France
Spain
4.3
1.8
2
8
4
Netherlands
Portugal
2
8
4
0.9
1.8
2
8
4
0.625
0.955
0.943
0.9625
0.5875
0.955
1.25
7.64
5.66
7.70
4.70
7.64
USA (channels 1 to 10)
USA (new channels)
Taiwan
8
8
1
6
6
1
8
8
1
New Zealand
Korea
4
8
2
8
8
1
For France, Spain, Netherlands, Portugal, Taiwan and New Zealand, fRef2 and fmod do not change when the channel changes. For USA
and Korea is valid: fRef2 and fmod are varying according to the channel number. For all countries, fRef2 and fmod are identical for base
set and handset.
Reference Frequency Dividers for Local Oscillator
K0 = 4460
K1 = 2230
K2 = 1784
K3 = 1115
K4 = 892
K5 = 446
fRef3 = 2.5 kHz
fRef3 = 5 kHz
fRef3 = 6.25 kHz
fRef3 = 10 kHz
fRef3 = 12.5 kHz
fRef3 = 25 kHz
4 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
Modulator PLL
Local Oscillator PLL
fLO
N
The fractional divider has been chosen to increase
reference the frequency of the modulator PLL.
fRef3
Serial Bus Interface
Q
223
557.5 kHz
fmod
P
The circuit is remoted by an external microcontroller
through the serial bus.
P: integer part of the fractional divider
Q: fractional part of the fractional divider
The data is a 12-bit word:
A0 – A3: address of the destination register (0 to 15)
D0 – D7: contents of register
fmod
557.5 kHz
Q
223
–P
The data line must be stable when the clock is high and
data must be shifted serially.
557.7 kHz
2.5 kHz
223
After a 12-clock period, the transfer to the destination
register is generated (internally) by a low-to-high
The frequency step 2.5 kHz is a fraction of the reference transition of the data line when the clock is high.
frequency 557.5 kHz
Qx (P 1) (223–Q)P
223
Q
223
P
Data
D
C
For each comparison cycle (fRef1 = 557.5 kHz), the accu-
mulator content is incremented by the Q value and the
divider divides by the P value. When the accumulator
value reaches or exceeds 223, the divider divides by the
value (P + 1). Then, the accumulator holds the excess
value (accumulator value – 223). After 223 cycles, the
correct division is executed.
Micro-
processor
Clock
96 11787
Figure 4.
Data
(D)
D0
D1
D2
A0
A1
A2
A3
Clock
(C)
1st word
2nd word
13279
Word transmission
Figure 5. Serial bus transmission
Transfer condition
Rev. A2, 10-Sep-98
5 (25)
Preliminary Information
U3550BM
Data
8
4
Clock
0
128
Address
Decoder
Latches
15
96 11653
Commands
Figure 6.
Data
(D)
A1
A2
A3
D0
Clock
(C)
tsud
thd
tch
tcl
teon
teh
teoff
96 11654
Figure 7.
6 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
Content of Internal Registers
The registers have the following structure
D7
D6
D5
D4
D3
D2
D1
D0
R0 – R4: reserved for U3500BM
R5: Gain VCO2
free
free
KV23
KV22
KV21
M12
reserved U3500
KV2[3:1]: Gain VCO2
M12: Frequency of phase-comparator in Mixer loop
R6: Country setting bits
ETXO
M1CP
UDM1
IMIXI
GMOD1
GMOD0
free
free
ETXO: Enable HF-transmit output
M1CP: Changes 1 dB compression point of Mixer 1
UDM1: Up-/down-mixing of Mixer 1
IMIXI: Inverse inputs of phase comparator in mixer loop
GMOD[1:0]: Modulation gain of VCO1
R7: VCO1 setting
AMOD2
AMOD1
RA11
RA10
DV1I3
DV1I2
DVlI1
DVlI0
AMOD[2:1]: Lengthening anti-backlash signal modulator loop
RA1[1:0]: Rough adjustment VCO1
DVlI[3:0]: Divider setting VCO1 integer part
R8: Divider VCO1 fractional part
DV1F7
DV1F6
DV1F5
DV1F4
DV1F3
DV3I3
DV3I11
DV1F2
DV3I2
DVlF1
DV3I1
DV3I9
DVlF0
DV3I0
DV3I8
DV1F [7:0]: Divider setting VCO1 fractional part
R9: Divider VCO3 integer part LSB
DV3I7
DV3I6
DV3I5
DV3I4
DV3I [7:0]: Divider setting VCO3 integer part LSB
R10: Divider VCO3 integer part MSB
free
DV3I14
DV3I13
DV3I12
DV3I10
DV3I[14:8]: Divider setting VCO3 integer part MSB
Rev. A2, 10-Sep-98
7 (25)
Preliminary Information
U3550BM
R11: Setting VCO2 and VCO3
free
free
FRMT
free
AMIX2
AMIX1
RA21
RA20
FRMT: Output frequency range of Mixer T
AMIX[2:1]: Lengthening anti-backlash signal mixer loop
RA2[1:0]: Rough adjustment VCO2
R12: Divider for country setting, fine adjust oscillator
FAOS2
FAOS1
FAOS0
D31
D30
D20
D11
D10
FAOS[2:0]: Oscillator fine adjust
D3[1:0]: Setting divider D3
D20: Setting divider D2
D1[1:0]: Setting divider D1
R13: VCO1 enable and fine adjust
EVCO1
SAFA1
EAFA1
FA14
FA13
FA12
FA11
FA10
EVCO1: Enable VCO1
SAFA1: Sign for automatic fine adjust VCO1
EAFA1: Enable automatic fine adjust VCO1
FA1[4:0]: Fine adjust VCO1 for manual adjustment
R14: VCO2 enable and fine adjust
EVCO2
SAFA2
EAFA2
FA24
FA23
FA22
FA21
FA20
EVCO2: Enable VCO2 and Mixer T
SAFA2: Sign for automatic fine adjust VCO2
EAFA2: Enable automatic fine adjust VCO2
FA2 [4:0]: Fine adjust VCO2 for manual adjustment
R15: VCO3 enable, oscillator enable, selection of phase comparator VCO3 and speed-up phase comparator for VCO3
EVCO3 EOSC SU3 E25K E12K5 E10K E6K25 E5K
EVCO3: Enable VCO3 and Mixer 1
EOSC: Enable oscillator
SU3: Speed-up phase-comparator for VCO3
E25K: Selection phase-comparator frequency VCO3: fRef3 = 25 kHz
E12K5: Selection phase-comparator frequency VCO3: fRef3 = 12.5 kHz
E10K: Selection phase-comparator frequency VCO3: fRef3 = 10 kHz
E6K25: Selection phase-comparator frequency VCO3: fRef3 = 6.25 kHz
E5K: Selection phase-comparator frequency VCO3: fRef3 = 5 kHz
E5K, E6K25, El0K, El2K5, E25K = 0
Selection phase-comparator frequency VCO3: fRef3 = 2.5 kHz
8 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
Absolute Maximum Ratings
Parameters
Symbol
VS
Min.
Max.
5.5
Unit
V
Supply voltage
Junction temperature
Ambient temperature
Storage temperature
Power dissipation Tamb = 60°C
Tj
Tamb
Tstg
+125
+75
+125
520
°C
°C
°C
mW
–25
–50
SO28
Ptot
Thermal Resistance
Parameters
Symbol
RthJA
Value
120
Unit
K/W
Junction ambient
SO28
Electrical Characteristics
Tamb = +25°C; VS = VBAT = MIXVB = RFOVB = DELVB = VCC = OSCVDD; VS = 3.6 V; fMIXIN = 26.40 MHz, fdev = 2.5 kHz;
VMIXIN = 2.24 mVrms; fRFO = 41.4 MHz; (Fh8) fMODIN = 1.0 kHz; VMODIN = 0.5 Vrms; Voffset = 1.5 V; VMCKA = VCC
all blocks disabled (ETXO = EVCO1 = EVCO2 = EVCO3 = 0); unless otherwise specified. Test circuit see figure 8.
;
Parameters
Power supply
Test Conditions / Pins
Symbol
Min.
3.1
Typ.
3.6
Max.
Unit
Operating voltage range
5.2
5
V
A
Operating current
in active mode (1)
VBAT = MIXVB = RFOVB = DELVB =
2.9 V
OSCVDD = VCC = 0 V
Operating current
in standby mode,
oscillator off (1)
VBAT = MIXVB = RFOVB = DELVB =
VCC = OSCVDD = 3.6 V,
200
700
6
A
A
V
= 0 V, EOSC = 0
MCKA
Operating current
in standby mode,
oscillator on
VBAT = MIXVB = RFOVB = DELVB =
VCC = OSCVDD = 3.6 V,
V
= 3.6 V, EOSC = 1
MCKA
Operating current in RX mode
EVCO3 = 1
5
mA
mA
Operating current in active mode
without TX output
EVCO1 = EVCO2 = 1
12
Operating current in active mode
RF transmitter
ETXO = 1, no load at RFO
14
16
mA
k
MODIN input impedance
RFO output impedance
70
100
300
130
390
0.3
Load = 200
RFO output-voltage level
Lowest operating frequency
Highest operation frequency
ETXO = 0; no load
V
France base channel 1 (Fb1) (2)
USA base channel 9 (US1b9) (2)
26.3125
49.9900
MHz
MHz
TX conversion gain
RFO – MODIN
Eb1: f
US1h9: f
= 31.025 MHz
5.7
3.42
2.85
kHz/V
kHz/V
kHz/V
RFO
= 49.99 MHz
RFO
Fh6: f
= 41.4375 MHz
RFO
for V = 3.1 to 5.2 V
S
Demodulated distortion THD
Eb1: f = 5.0 kHz
Fh9: f = 1.5 kHz
2
%
for V = 3.1 to 5.2 V
S
Residual modulation (4) on
demodulated signal
THD measurement with psophometric
filter
dB
Rev. A2, 10-Sep-98
9 (25)
Preliminary Information
U3550BM
Parameters
Test Conditions / Pins
Symbol
Min.
60
Typ.
Max.
Unit
dBc
Spurious at RFO output
(delta versus carrier)
a/ Fb6: f
= 26.375 MHz
RFO
b/ US1h9: F
= 49.99 MHz (3)
RFO
f = 2.5 kHz
f = 12.5 kHz
f = 557.5 kHz
f = 1/2 f
mod
f =
f
mod
for V = 3.1 to 5.2 V
S
VTX output capability
I
= 3 mA
0.5
1
V
A
LOAD
V with and without load
VTX output leakage current
PLLs
ETXO = 0; current to GND
V = 3.1 to 5.2 V
S
Charge-pump output voltage
EVCO1 =1, output high
2.38
1.15
2.5
1.4
2.63
1.65
V
V
Precharge voltage at the loop
filter
EVCO3 = 1
EVCO1 = 0
Charge-pump output current in
speed-up mode
EVCO1 = 1
–400
–300
–200
A
V
= 1.25 V, output high
= 1.25 V, output low
= 1.25 V, output high
MLF
Charge-pump output current
V
4.3
–8
6.2
8
A
A
MLF
V
–6.2
–4.3
+100
156
MLF
Charge-pump leakage current
VCO1 gain
V
= 1.25 V, output tristate
–100
121
nA
MLF
V
= 0 V, then 2.5 V
140
kHz/V
MLF
Receiver input mixer (Mixer 1)
Input frequency range
Output frequency
EVCO3 = 1
20
50
MHz
MHz
k
10.7
3.0
Input resistance
2.4
3
3.6
4
Input capacitor
3.5
pF
Output impedance
M1CP = 0
M1CP = 1
210
50
330
80
390
110
Voltage gain on MIXO
M1CP = 0
M1CP = 1
for:
9.5
14
12.5
17
15.5
20
dB
dB
Fb8: f = 30.7 MHz
LO
FRF11 = 20 MHz
UDM1 = 1
Fb8: f = 30.7 MHz
LO
FRF21 = 41.4 MHz
UDM1 = 0
US1h10: f = 57.67 MHz
LO
FRF31 = 46.97 MHz
UDM1 = 1
for V = 3.1 to 5.2 V
S
Noise figure
BW = 1 MHz
14
18
dB
50- input impedance
Input compression point
M1CP = 0
M1CP = 1
–19
–16
–17.7
–14.3
dBm
dBm
50- input impedance
10 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Third order input intercept point
M1CP = 0
M1CP = 1
–7
–4
–5
–2
dBm
dBm
50- input impedance
FRF1 = 41.4 MHz
FRF2 = 41.4125 MHz
Input level 1 = –30 dBm
Input level 2 = –30 dBm
Image-frequency rejection
Fb8: f = 30.7 MHz
20
dB
LO
UDM1 = 0
FRF11 = 41.4 MHz
FRF12 = 20 MHz (image)
Fb8: f = 30.7 MHz
LO
UDM1 = 0
FRF21 = 20 MHz
FRF22 = 41.4 MHz (image)
Fb8: f = 57.67 MHz
LO
UDM1 = 1
FRF31 = 46.97 MHz
FRF32 = 68.37
LO to RF MIXIN input isolation
LO to IF MIXO output isolation
Fb8: measuring, f = 30.7 MHz
0.2
1.2
mV
mV
LO
rms
Fb8: measuring, f = 30.7 MHz
LO
rms
Isolation transmit path to receive
path (crosstalk)
Synthesizer programming
as ‘Taiwan channel 5’ (see page 21),
transmitter modulation (Pin 25) for
28
dB
f = 3 kHz, f
= 300 to 3400 kHz,
mod
M1CP = 1,
f
(Pin 10) = 45.35 or 48.35 MHz
RF
unmodulated, –25 dBm (50 ) measuring
frequency modulation of the 10.7 MHz
signal at MIXO (Pin 12)
Logical part
Inputs: C, D
Low-voltage input
High-voltage input
Inputs: C, D, MCKA
Input leakage current
(0 < VI < VCC)
V
V
ih
0.2 V
CC
il
0.8 V
CC
V
–1
1
A
A
i
Input leakage current Pin XCK
(0 < VI < VCC)
–5
5
Output impedance at MCKO
0.5
1.0
k
Serial bus (figure 8)
Data set-up rime
Data hold time
t
t
t
t
0.1
0
2
2
0.1
s
s
s
s
s
sud
hd
Clock low time
cl
ch
Clock high time
Hold time before transfer
condition
t
eon
Data low pulse on transfer
condition
Data high pulse on transfer
condition
t
0.2
0.2
s
s
eh
t
eoff
(1)
(2)
IS = IVBAT + IVCC + IMIXVB + IRFOVB
+ ODELVB + I1OSCVDD
1-measure 11.15 MHz at MCKO pin
2-measure FRFO at RFO pin
(3)
(4)
See country channels
Ratio between demodulated audio level with and
without 1-kHz modulation
Rev. A2, 10-Sep-98
11 (25)
Preliminary Information
U3550BM
Fine Adjustment of the Oscillator Frequency
To set the oscillator’s frequency exactly to 11.5 MHz, the frequency is adjustable in 8 steps. By adding 3 different
internal capacities, the frequency can be reduced. The values of these capacitors are designed to be 0.7 pF (FAO0),
1.4 pF (FAO1) and 2.8 pF (FAO2).
Parameters
Oscillator frequency without
reduction
Test Conditions / Pins
FAOS (0:2) = 0
Min.
Typ.
11.15
Max.
Unit
MHz
Changing the oscillator’s
FAO2 FAO1 FAO0
frequency with FOSC reduction
0
0
1
1
0
1
0
1
1
0
0
1
100
200
400
700
Hz
Hz
Hz
Hz
Test Circuit
f = 1 kHz
= 500 mV
sin
V
rms
C6
56 nF
C7
C9
1 µF
V
offset
= 1.5 V
+
0.1 µF
V
V
V
V
R3
Batt
CC
MCKA
RFOVB
R5
R4
200
24 k
C8
5.6 kΩ
DC
+
+
+
+
DC
DC
26
DC
4.7 nF
16 15
28
24
23
21
20
19
18
17
27
25
22
U3550BM
1
2
3
4
5
7
8
6
9
10
11
12
13
14
V
V
V
MIX
OSC
110 nH
C2
V
+
+
+
DD
B
R1
10 nF
L1
C5
330
D
C
V
Batt
C4
C3
DC
DC
V
DC
DELVB
1 nF
10 nF
) BPY51 or
BZT55C51
*
12 pF
)
)
*
Inputs serial bus
11.15
*
+
D1
D2
C1
4.7 pF
f = f
RF
= 50
= 2.24 mV
MHz
R
out
R3
56 k
V
rms
sin
13281
Figure 8. Test circuit
12 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
Channel Frequencies, Dividers and Country Settings
To meet all requirements of various countries France (F), Spain (E), Netherlands (NL), USA and Portugal (P), Korea,
Taiwan, New Zealand and modes base (b), handset (h) several bits have to be set which do not change for
the different channels. These settings are called country settings.
The country-setting bits are followed by further bits enabling the adjustments given below.
Rough adjustments for 2 VCOs
Modulator gain
Setting three integer dividers mixer and
modulator loop
Up-/down-mixing Mixer 1 and Mixer T
Output-frequency range of Mixer T
Gain adjustment of the VCO2
Name Register
Function
Notes
RA1[0:1]
RA2[0:1]
D1[0:1]
D20
Rough adjust VCO1
Rough adjust VCO2
Integer divider D1
Integer divider D2
Integer divider D3
Gain VCO2
00: is the highest frequency
00: is the highest frequency
Division by 2, 4, 6, 8
Division by 6, 8
3
4
4
2
3
6
3
2
D3[0:1]
KV[1:3]
GMOD[0:1]
IMIXI
Division by 1, 2, 4
Modulator gain
00: gain minimal
Up-/down-mixing
Mixer T
0: if fVCO2 lower than fLO
UDM1
FRMT
Up-/down-mixing
Mixer 1
1: supra band active (handset)
0: for fVCO2 – fLO < 6 MHz
2
2
Output-frequency range
Mixer T
Note: Setting the fractional dividers:
For Q, send the binary equivalent of the numbers given below.
For P (integer part), send the D2 complement (16 – P)
i.e. Fb1 (P = 7, Q = 159 => integer: send 16 – P = 9, fractional: send 159)
Rev. A2, 10-Sep-98
13 (25)
Preliminary Information
U3550BM
France CT0 Base Set
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
00
11
11
4
1
8
01
2
100
01
0
0
0
Setting
max
min
mid
supra
infra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
41.3125
1st LO Frequency (MHz)
30.6125
N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
4898
4900
4902
4904
4906
4908
4910
4912
4914
4916
4918
4920
4922
4924
4926
41.3250
41.3375
41.3500
41.3625
41.3750
41.3875
41.4000
41.4125
41.4250
41.4375
41.4500
41.4625
41.4750
41.4875
30.6250
30.6375
30.6500
30.6625
30.6750
30.6875
30.7000
30.7125
30.7250
30.7375
30.7500
30.7625
30.7750
30.7875
France CT0 Handset
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
00
01
11
4
1
8
01
2
101
01
1
1
0
Setting
max
high
mid
infra
supra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
26.3125
1st LO Frequency (MHz)
37.0125
N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5922
5924
5926
5928
5930
5932
5934
5936
5938
5940
5942
5944
5946
5948
5950
26.3250
26.3375
26.3500
26.3625
26.3750
26.3875
26.4000
26.4125
26.4250
26.4375
26.4500
26.4625
26.4750
26.4875
37.0250
37.0375
37.0500
37.0625
37.0750
37.0875
37.1000
37.1125
37.1250
37.1375
37.1500
37.1625
37.1750
37.1875
14 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
France CT0 Modulation Loop Frequency and Divider
fmod = 4.3 MHz, P = 7, Q = 159
Spain CT0 Base Set
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
10
00
2
1
8
11
4
100
10
1
0
0
Setting
mid
low
high
infra
infra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
1st LO Frequency (MHz)
29.225
N
1
2
3
4
5
6
7
8
9
39.925
39.950
39.975
40.000
40.025
40.050
40.075
40.100
40.150
40.175
40.200
40.225
4676
4680
4684
4688
4692
4696
4700
4704
4712
4716
4720
4724
29.250
29.275
29.300
29.325
29.350
29.375
29.400
29.450
10
11
12
29.475
29.500
29.525
Spain CT0 Handset
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
01
00
2
1
8
11
4
100
10
0
1
0
Setting
mid
high
high
supra
supra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
1st LO Frequency (MHz)
41.725
N
1
2
3
4
5
6
7
8
9
31.025
31.050
31.075
31.100
31.125
31.150
31.175
31.200
31.250
31.275
31.300
31.325
6676
6680
6684
6688
6692
6696
6700
6704
6712
6716
6720
6724
41.750
41.775
41.800
41.825
41.850
41.875
41.900
41.950
10
11
12
41.975
42.000
42.025
Spain CT0 Modulation Loop Frequency and Divider
fmod = 1.8 MHz, P = 3, Q = 51
Rev. A2, 10-Sep-98
15 (25)
Preliminary Information
U3550BM
Netherlands CT0 Base Set
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
10
00
2
1
8
11
4
100
10
1
0
0
Setting
mid
low
high
infra
infra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
39.9375
1st LO Frequency (MHz)
29.2375
N
1
2
3
4
5
6
7
8
9
4678
4682
4686
4690
4694
4698
4702
4706
4710
4714
4718
4722
39.9625
39.9875
40.0125
40.0375
40.0625
40.0875
40.1125
40.1375
29.2625
29.2875
29.3125
29.3375
29.3625
29.3875
29.4125
29.4375
10
11
12
40.1625
40.1875
40.2125
29.4625
29.4875
29.5125
Netherlands CT0 Handset
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
01
00
2
1
8
11
4
001
10
0
1
0
Setting
mid
high
high
supra
supra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
31.0375
1st LO Frequency (MHz)
41.7375
N
1
2
3
4
5
6
7
8
9
6678
6682
6686
6690
6694
6698
6702
6706
6710
6714
6718
6722
31.0625
31.0875
31.1125
31.1375
31.1625
31.1875
31.2125
31.2375
41.7625
41.7875
41.8125
41.8375
41.8625
41.8875
41.9125
41.9375
10
11
12
31.2625
31.2875
31.3125
41.9625
41.9875
42.0125
Netherlands CT0 Modulation Loop Frequency and Divider
fmod = 1.8 MHz, P = 3, Q = 51
16 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
USA CT0 Base Set
Country setting channel 1 – 10 (USA1):
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
00
01
8
1
8
00
1
100
00
1
0
1
Setting
mid
max
low
infra
infra
high
Country setting new channels (channel 11 – 25, USA2):
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
01
01
10
6
0
6
00
1
110
01
1
0
0
Setting
mid
high
mid
infra
infra
low
Channel frequencies and 1st LO divider, fRef3 = 5 kHz
Channel Number
RX Channel Frequency (MHz)
1st LO Frequency (MHz)
38.970
N
1
2
3
4
5
6
7
8
9
49.670
49.845
49.860
49.770
49.875
49.830
49.890
49.930
49.990
49.970
7794
7829
7832
7814
7835
7826
7838
7846
7858
7854
39.145
39.160
39.070
39.175
39.130
39.190
39.230
39.290
10
39.270
New channels
Channel Number
RX Channel Frequency (MHz)
1st LO Frequency (MHz)
N
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
48.760
48.840
48.860
48.920
49.020
49.080
49.100
49.160
49.200
49.240
49.280
49.360
49.400
49.460
49.500
38.06
38.14
38.16
38.22
38.32
38.38
38.40
38.46
38.50
38.54
38.58
38.66
38.70
38.76
38.80
7612
7628
7632
7644
7664
7676
7680
7692
7700
7708
7716
7732
7740
7752
7760
Rev. A2, 10-Sep-98
17 (25)
Preliminary Information
U3550BM
USA CT0 Handset
Country setting channel 1 – 10 (USA1):
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
00
01
8
1
8
00
1
100
00
0
1
1
Setting
mid
max
low
supra
supra
high
Country setting new channels (channel 11 – 25 USA2):
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
01
00
10
6
0
6
00
1
110
01
0
1
0
Setting
mid
max
mid
supra
supra
low
Channel frequencies and 1st LO divider, fRef3 = 5 kHz
Channel Number
RX Channel Frequency (MHz)
1st LO Frequency (MHz)
N
1
2
3
4
5
6
7
8
9
46.610
46.630
46.670
46.710
46.730
46.770
46.830
46.870
46.930
46.970
57.31
57.33
57.37
57.41
57.43
57.47
57.53
57.57
57.63
57.67
11462
11466
11474
11482
11486
11494
11506
11514
11526
11534
10
New channels
Channel Number
RX Channel Frequency (MHz)
1st LO Frequency (MHz)
N
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
43.720
43.740
43.820
43.840
43.920
43.960
44.120
44.160
44.180
44.200
44.320
44.360
44.400
44.460
44.480
54.42
54.44
54.52
54.54
54.62
54.66
54.82
54.86
54.88
54.90
55.02
55.06
55.10
55.16
55.18
10884
10888
10904
10908
10924
10932
10964
10972
10976
10980
11004
11012
11020
11032
11036
18 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
USA CT Modulation Loop Frequencies and Dividers
N Channel
P
Q
157
95
fmod (MHz)
7.640
1
2
3
4
5
6
7
8
9
13
13
13
13
13
13
13
13
13
13
7.485
7.510
7.640
7.555
7.640
7.640
7.640
7.640
105
157
123
157
157
157
157
181
10
7.700
New channels
N Channel
P
Q
fmod (MHz)
5.66
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
34
10
34
18
10
2
58
50
42
34
66
50
50
50
42
5.60
5.66
5.62
5.60
5.58
5.72
5.70
5.68
5.66
5.74
5.70
5.70
5.70
5.68
Rev. A2, 10-Sep-98
19 (25)
Preliminary Information
U3550BM
Portugal CT0 Base Set
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
01
10
00
2
1
8
11
4
010
10
1
0
0
Setting
min
low
high
infra
infra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
1st LO Frequency (MHz)
26.300
N
1
2
3
4
5
6
7
8
9
37.000
37.025
37.050
37.075
37.100
37.125
37.150
37.175
37.200
37.225
37.250
37.275
4208
4212
4216
4220
4224
4228
4232
4236
4240
4244
4248
4252
26.325
26.350
26.375
26.400
26.425
26.450
26.475
26.500
10
11
12
26.525
26.550
26.575
Portugal CT0 Handset
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
01
01
00
2
1
8
11
4
001
10
0
1
0
Setting
min
high
high
supra
supra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
1st LO Frequency (MHz)
38.250
N
1
2
3
4
5
6
7
8
9
27.550
27.575
27.600
27.625
27.650
27.675
27.700
27.725
27.750
27.775
27.800
27.825
6120
6124
6128
6132
6136
6140
6144
6148
6152
6156
6160
6164
38.275
38.300
38.325
38.350
38.375
38.400
38.425
38.450
10
11
12
38.475
38.500
38.525
Portugal CT0 Modulation Loop Frequency and Divider
fmod = 1.25 MHz, P = 2, Q = 54
20 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
Taiwan CT0 Base Set
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
00
01
8
1
8
00
1
110
01
1
0
1
Setting
mid
max
low
infra
supra
higher
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
48.2500
1st LO Frequency (MHz)
37.5500
N
1
2
3
4
5
6
7
8
9
6008
6012
6016
6020
6024
6028
6032
6036
6040
6044
48.2750
48.3000
48.3250
48.3500
48.3750
48.4000
48.4250
48.4500
37.5750
37.6000
37.6250
37.6500
37.6750
37.7000
37.7250
37.7500
10
48.4750
37.7750
Taiwan CT0 Handset
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
00
01
8
1
8
00
1
110
00
0
1
1
Setting
mid
max
low
supra
supra
high
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
45.2500
1st LO Frequency (MHz)
55.9500
N
1
2
3
4
5
6
7
8
9
8952
8956
8960
8964
8968
8972
8976
8980
8984
8988
45.2750
45.3000
45.3250
45.3500
45.3750
45.4000
45.4250
45.4500
55.9750
56.0000
56.0250
56.0500
56.0750
56.1000
56.1250
56.1500
10
45.4750
56.1750
Taiwan CT0 Modulation Loop Frequency and Divider
fmod = 7.70 MHz, P = 13, Q = 181
Rev. A2, 10-Sep-98
21 (25)
Preliminary Information
U3550BM
New Zealand CT0 Base Set
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
00
01
11
4
1
8
01
2
110
01
1
0
0
Setting
max
high
mid
infra
infra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
40.2500
1st LO Frequency (MHz)
29.5500
N
11
12
13
14
15
16
17
18
19
20
4728
4732
4736
4740
4744
4748
4752
4756
4760
4764
40.2750
40.3000
40.3250
40.3500
40.3750
40.4000
40.4250
40.4500
29.5750
29.6000
29.6250
29.6500
29.6750
29.7000
29.7250
29.7500
40.4750
29.7750
New Zealand CT0 Handset
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
00
11
11
4
1
8
01
2
101
01
0
0
0
Setting
max
min
mid
supra
supra
low
Channel frequencies and 1st LO divider, fRef3 = 6.25 kHz
Channel Number
RX Channel Frequency (MHz)
34.2500
1st LO Frequency (MHz)
44.9500
N
11
12
13
14
15
16
17
18
19
20
7192
7196
7200
7204
7208
7212
7216
7220
7224
7228
34.2750
34.3000
34.3250
34.3500
34.3750
34.4000
34.4250
34.4500
44.9750
45.0000
45.0250
45.0500
45.0750
45.1000
45.1250
45.1500
34.4750
45.1750
New Zealand CT0 Modulation Loop Frequency and Divider
fmod = 4.70 MHz, P = 8, Q = 96
22 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
Korea CT0 Base Set
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
00
01
8
1
8
00
1
100
00
1
0
1
Setting
mid
max
low
infra
infra
high
Channel frequencies and 1st LO divider, fRef3 = 5 kHz
Channel Number
RX Channel Frequency (MHz)
49.6700
1st LO Frequency (MHz)
38.9700
N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
7794
7829
7832
7814
7835
7826
7838
7846
7858
7854
7799
7802
7805
7808
7811
49.8450
49.8600
49.7700
49.8750
49.8300
49.8900
49.9300
49.9900
49.9700
49.6950
49.7100
49.7250
49.7400
49.7550
39.1450
39.1600
39.0700
39.1750
39.1300
39.1900
39.2300
39.2900
39.2700
39.9950
39.0100
39.0250
39.0400
39.0550
Korea CT0 Handset
Country setting:
Name RA1[1:0] RA2[1:0] D1B[1:0]
D2B0
D3B[1:0] KV2[3:1] GMOD[1:0] IMIXI
UDM1 FRMT
Value
10
00
01
8
1
8
00
1
100
00
0
1
1
Setting
mid
max
low
supra
supra
high
Channel frequencies and 1st LO divider, fRef3 = 5 kHz
Channel Number
RX Channel Frequency (MHz)
46.6100
1st LO Frequency (MHz)
57.3100
N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
11462
11466
11474
11482
11486
11494
11506
11514
11526
11534
11442
11446
11450
11454
11458
46.6300
46.6700
46.7100
46.7300
46.7700
46.8300
46.8700
46.9300
46.9700
46.5100
46.5300
46.5500
46.5700
46.5900
57.3300
57.3700
57.4100
57.4300
57.4700
57.5300
57.5700
57.6300
57.6700
57.2100
57.2300
57.2500
57.2700
57.2900
Rev. A2, 10-Sep-98
23 (25)
Preliminary Information
U3550BM
Korea CT Modulation Loop Frequencies and Dividers
N Channel
P
Q
157
95
fmod (MHz)
7.640
7.485
7.510
7.640
7.555
7.640
7.640
7.640
7.640
7.700
7.515
7.520
7.525
7.530
7.535
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
105
157
123
157
157
157
157
181
107
109
111
113
115
Package Information
9.15
8.65
Package SO28
Dimensions in mm
18.05
17.80
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
16.51
28
15
technical drawings
according to DIN
specifications
13033
1
14
24 (25)
Rev. A2, 10-Sep-98
Preliminary Information
U3550BM
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.
TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of
continuous improvements to eliminate the use of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain
such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or
unauthorized use.
TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
Rev. A2, 10-Sep-98
25 (25)
Preliminary Information
相关型号：
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