74FCT16823CTPVCTG4 [TI]
18-Bit Registers;
| 型号： | 74FCT16823CTPVCTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-Bit Registers |
| 文件： | 总8页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16823T
CY74FCT162823T
SCCS062 - August 1994 - Revised March 2000
18-Bit Registers
CY74FCT162823T Features:
Features
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
• FCT-E speed at 4.4 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
Functional Description
• Typical output skew < 250 ps
• ESD > 2000V
The CY74FCT16823T and the CY74FCT162823T 18-bit bus
interface registers are designed for use in high-speed,
low-power systems needing wide registers and parity. 18-bit
operation is achieved by connecting the control lines of the two
9-bit registers. Flow-through pinout and small shrink
packaging aids in simplifying board layout. The outputs are
designed with a power-off disable feature to allow live insertion
of boards.
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
• VCC = 5V ± 10%
CY74FCT16823T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
The CY74FCT16823T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162823T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162823T is ideal for driving transmission lines.
Logic Block Diagrams
Pin Configuration
SSOP/TSSOP
OE
1
Top View
CLR
1
CLK
56
55
54
53
52
51
50
1
1
CLR
1
2
3
4
5
6
1
CLKEN
D
OE
1
CLK
1
Q
1
1
1
1
GND
Q
GND
D
CLKEN
1
1
1
2
3
1
1
2
3
Q
D
V
CC
V
CC
7
R
C
D
Q
D
1
1
1
4
5
1
1
4
49
48
47
46
8
Q
1
1
D
5
Q
9
D
Q
1
6
6
D
10
11
12
1
1
GND
GND
Q
D
D
1
7
1
1
1
7
8
45
44
43
42
41
Q
Q
1
1
8
9
13
14
FCT16823-1
D
9
TO 8 OTHER CHANNELS
D
D
Q
Q
Q
2
2
1
2
2
2
1
15
16
17
OE
2
2
2
3
D
2
3
40
39
38
CLR
2
GND
Q
GND
D
18
19
20
21
22
23
2
2
2
4
5
6
2
2
4
5
6
CLK
2
D
D
Q
Q
37
36
35
34
2
CLKEN
2
V
CC
V
CC
7
Q
Q
D
2
2
7
2
2
33
32
31
30
29
D
8
8
24
25
R
C
D
GND
Q
GND
D
Q
1
2
9
26
27
28
2
2
9
OE
CLKEN
CLK
2
2
2
D
2
2
CLR
2
FCT16823-3
FCT16823-2
TO 8 OTHER CHANNELS
Copyright © 2000, Texas Instruments Incorporated
CY74FCT16823T
CY74FCT162823T
Function Table[1]
Pin Description
Inputs
OE CLR CLKEN CLK
Outputs
Name
Description
D
X
X
X
L
Q
Z
Function
High Z
Clear
D
Data Inputs
Clock Inputs
H
L
X
L
X
X
H
L
X
X
X
CLK
L
Q[2]
CLKEN Clock Enable Inputs (Active LOW)
L
H
H
H
H
H
Hold
CLR
OE
Q
Asynchronous Clear Inputs (Active LOW)
Output Enable Inputs (Active LOW)
Three-State Outputs
H
H
L
Z
Load
L
H
L
Z
L
L
L
L
H
H
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .....................................−55°C to +125°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Operating Range
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
Ambient
Range
Industrial
Temperature
VCC
−40°C to +85°C
5V ± 10%
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
Notes:
1. H = HIGH Voltage Level.
L = LOW Voltage Level.
X = Don’t Care.
Z = HIGH Impedance.
=LOW-to-HIGH transition.
2. Output level before indicated steady-state input conditions were established.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
2
CY74FCT16823T
CY74FCT162823T
Electrical Characteristics Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Input Hysteresis[6]
Test Conditions
Min.
Typ.[5]
Max.
Unit
V
VIH
VIL
VH
VIK
IIH
2.0
0.8
V
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
VCC=Min., IIN=−18 mA
−0.7
−1.2
±1
VCC=Max., VI=VCC
VCC=Max., VI=GND
µA
µA
µA
IIL
±1
IOZH
High Impedance Output Current VCC=Max., VOUT=2.7V
(Three-State Output pins)
±1
IOZL
High Impedance Output Current VCC=Max., VOUT=0.5V
(Three-State Output pins)
±1
µA
IOS
IO
Short Circuit Current[7]
Output Drive Current[7]
Power-Off Disable
VCC=Max., VOUT=GND
VCC=Max., VOUT=2.5V
VCC=0V, VOUT≤4.5V[8]
−80
−50
−140
−200
−180
1
mA
mA
µA
IOFF
Output Drive Characteristics for CY74FCT16823T
Parameter
Description
Test Conditions
VCC=Min., IOH=−3 mA
Min.
2.5
Typ.[5]
3.5
Max.
Unit
VOH
Output HIGH Voltage
V
VCC=Min., IOH=−15 mA
VCC=Min., IOH=−32 mA
VCC=Min., IOL=64 mA
2.4
3.5
2.0
3.0
VOL
Output LOW Voltage
0.2
0.55
V
Output Drive Characteristics for CY74FCT162823T
Parameter
IODL
Description
Output LOW Voltage[7]
Output HIGH Voltage[7]
Output HIGH Voltage
Output LOW Voltage
Test Conditions
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
VCC=Min., IOH=−24 mA
Min.
60
Typ.[5]
115
Max.
150
Unit
mA
mA
V
IODH
−60
2.4
−115
3.3
−150
VOH
VOL
VCC=Min., IOL=24 mA
0.3
0.55
V
Capacitance[9] (TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 0V
Typ.[5] Max.
Unit
pF
CIN
4.5
5.5
6.0
8.0
COUT
VOUT = 0V
pF
Notes:
5. Typical values are at VCC= 5.0V, TA= +25˚C ambient.
6. This input is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
8. Tested at +25˚C.
9. This parameter is specified but not tested.
3
CY74FCT16823T
CY74FCT162823T
Power Supply Characteristics
Parameter
Description
Test Conditions[10]
VIN<0.2V
Min.
Typ.[5]
Max.
Unit
ICC
Quiescent Power Supply
Current
VCC=Max.
VCC=Max.
—
5
500
µA
VIN>VCC−0.2V
VIN=3.4V[11]
∆ICC
Quiescent Power Supply
Current (TTL inputs HIGH)
—
—
0.5
75
1.5
mA
ICCD
Dynamic Power Supply
Current[12]
VCC=Max.,
VIN=VCC or
VIN=GND
120
µA/
MHz
One Input Toggling,
50% Duty Cycle,
Outputs Open,
OE=CLKEN=GND
IC
Total Power Supply Current[13] VCC=Max.,
f0=10 MHz,
VIN=VCC or
VIN=GND
—
—
0.8
1.3
1.7
3.2
mA
50% Duty Cycle,
VIN=3.4V or
VIN=GND
Outputs Open,
One Bit Toggling,
OE=CLKEN=GND
at f1=5 MHz
VCC=Max.,
VIN=VCC or
VIN=GND
—
—
4.2
9.2
7.1[14]
at f1=2.5 MHz,
50% Duty Cycle,
Outputs Open,
Eighteen Bits Toggling,
OE=CLKEN=GND
f0=10 MHz
VIN=3.4V or
VIN=GND
22.1[14]
Notes:
10. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
13. IC
IC
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
ICCD
f0
f1
N1
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Input signal frequency
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
14. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
4
CY74FCT16823T
CY74FCT162823T
Switching Characteristics Over the Operating Range[15]
CY74FCT16823AT
CY74FCT162823AT
Parameter
Description
Condition[16]
Min.
Max.
Unit
Fig.No.[16]
tPLH
tPHL
Propagation Delay CLK to Q
CL=50 pF
RL=500Ω
1.5
10.0
ns
1, 5
CL=300 pF[17]
RL=500Ω
1.5
1.5
1.5
1.5
1.5
1.5
20.0
14.0
12.0
23.0
7.0
tPHL
Propagation Delay CLR to Q
Output Enable Time OE to Q
CL=50 pF
RL=500Ω
ns
ns
1, 5
tPZH
tPZL
CL=50 pF
RL=500Ω
CL=300 pF[17]
RL=500Ω
CL=5 pF[17]
RL=500Ω
1, 7, 8
tPHZ
tPLZ
Output Disable Time OE to Q
ns
1, 7, 8
CL=50 pF
8.0
RL=500Ω
tSU
tH
tSU
tH
Set-Up Time HIGH or LOW, D to CLK
Hold Time HIGH or LOW, D to CLK
Set-Up Time HIGH or LOW, CLKEN to CLK
Hold Time HIGH or LOW CLKEN to CLK
CLK Pulse Width HIGH or LOW
CLR Pulse Width LOW
CL=50 pF
RL=500Ω
3.0
1.5
3.0
0.0
6.0
6.0
6.0
—
—
—
—
—
—
—
—
0.5
ns
ns
ns
ns
ns
ns
ns
ns
4
4
9
9
tW
5
tW
5
tREM
tSK(O)
Recovery Time CLR to CLK
Output Skew[18]
6
—
Switching Characteristics Over the Operating Range[15]
CY74FCT16823CT CY74FCT16823ET
CY74FCT162823CT CY74FCT162823ET
Parameter
Description
Condition[16]
Min.
Max.
Min.
Max.
Unit Fig.No.[16]
tPLH
tPHL
Propagation Delay
CLK to Q
CL=50 pF
RL=500Ω
1.5
6.0
1.5
4.4
ns
1, 5
CL=300 pF[17]
RL=500Ω
1.5
1.5
1.5
1.5
1.5
1.5
12.5
6.1
1.5
1.5
1.5
1.5
1.5
1.5
8.0
4.4
4.4
9.0
3.6
3.6
tPHL
Propagation Delay
CLR to Q
CL=50 pF
RL=500Ω
ns
ns
1, 5
tPZH
tPZL
Output Enable Time
OE to Q
CL=50 pF
RL=500Ω
CL=300 pF[17]
RL=500Ω
CL=5 pF[17]
RL=500Ω
5.5
1, 7, 8
12.5
5.2
tPHZ
tPLZ
Output Disable Time
OE to Q
ns
1, 7, 8
CL=50 pF
6.5
RL=500Ω
5
CY74FCT16823T
CY74FCT162823T
Switching Characteristics Over the Operating Range[15] (continued)
CY74FCT16823CT CY74FCT16823ET
CY74FCT162823CT CY74FCT162823ET
Parameter
Description
Set-Up Time
HIGH or LOW, D to CLK
Condition[16]
Min.
Max.
Min.
Max.
Unit Fig.No.[16]
tSU
CL=50 pF
RL=500Ω
2.0
—
1.5
—
ns
ns
ns
ns
ns
4
4
9
9
5
tH
Hold Time
HIGH or LOW, D to CLK
1.5
3.0
0.0
3.3
—
—
—
—
0.0
2.5
0.0
3.3
—
—
—
—
tSU
tH
Set-Up Time
HIGH or LOW, CLKEN to CLK
Hold Time HIGH or LOW
CLKEN to CLK
tW
CLK Pulse Width
HIGH or LOW
tW
CLR Pulse Width LOW
3.3
6.0
—
—
3.0
3.0
—
—
ns
ns
5
6
tREM
Recovery Time
CLR to CLK
tSK(O)
Output Skew[18]
—
0.5
—
0.5
ns
—
Notes:
15. Minimum limits are specified but not tested on Propagation Delays.
16. See “Parameter Measurement Information” in the General Information section.
17. These limits are specified but not tested.
18. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
Ordering Information CY74FCT16823
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY74FCT16823ETPACT
CY74FCT16823ETPVC/PVCT
CY74FCT16823CTPACT
CY74FCT16823CTPVC/PVCT
CY74FCT16823ATPACT
Package Type
56-Lead (240-Mil) TSSOP
4.4
Z56
O56
Z56
O56
Z56
Industrial
Industrial
Industrial
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
6.0
10.0
Ordering Information CY74FCT162823
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
74FCT162823ETPACT
CY74FCT162823ETPVC
74FCT162823ETPVCT
74FCT162823CTPACT
CY74FCT162823CTPVC
74FCT162823CTPVCT
74FCT162823ATPACT
Package Type
4.4
Z56
O56
O56
Z56
O56
O56
Z56
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
Industrial
Industrial
Industrial
6.0
10.0
6
CY74FCT16823T
CY74FCT162823T
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
7
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Copyright 2000, Texas Instruments Incorporated
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