ADS1601IPFBT [TI]

16 位 1.25MSPS 高速和高精密 Δ-Σ ADC | PFB | 48 | -40 to 85;


型号：	ADS1601IPFBT
厂家：	TEXAS INSTRUMENTS
描述：	16 位 1.25MSPS 高速和高精密 Δ-Σ ADC \| PFB \| 48 \| -40 to 85 转换器
文件：	总30页 (文件大小：914K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

16-Bit, 1.25MSPS Analog-to-Digital Converter

Check for Samples: ADS1601

FEATURES

DESCRIPTION

The ADS1601 is

delta-sigma analog-to-digital

high-speed, high-precision,

converter (ADC)

•

High Speed:

–

Data Rate: 1.25MSPS

Bandwidth: 615kHz

manufactured on an advanced CMOS process. The

ADS1601 oversampling topology reduces clock jitter

sensitivity during the sampling of high-frequency,

large amplitude signals by a factor of four over that

achieved by Nyquist-rate ADCs. Consequently,

signal-to-noise ratio (SNR) is particularly improved.

Total harmonic distortion (THD) is –103dB, and the

spurious-free dynamic range (SFDR) is 105dB

•

Outstanding Performance:

–

SNR: 92dB at f_IN= 100kHz, –1dBFS

THD: –103dB at f_IN= 100kHz, –6dBFS

SFDR: 105dB at f_IN= 100kHz, –6dBFS

•

Ease-of-Use:

Optimized for power and performance, the ADS1601

dissipates only 330mW while providing a full-scale

differential input range of ±0.94V_REF. Having such a

wide input range makes out-of-range signals

uncommon. The OTR pin indicates if an analog input

out-of-range condition does occur. The differential

input signal is measured against the differential

reference, which can be generated internally on the

ADS1601 or supplied externally.

–

High-Speed 3-Wire Serial Interface

Directly Connects to TMS320 DSPs

On-Chip Digital Filter Simplifies Anti-Alias

Requirements

–

Simple Pin-Driven Control—No On-Chip

Registers to Program

–

Selectable On-Chip Voltage Reference

Simultaneous Sampling with Multiple

ADS1601s

The ADS1601 uses an inherently stable advanced

modulator with an on-chip decimation filter. The filter

stop band extends to 19.3MHz, which greatly

simplifies the anti-aliasing circuitry. The modulator

samples the input signal up to 20MSPS, depending

on f_CLK, while the 16x decimation filter uses a series

of four half-band FIR filter stages to provide 75dB of

stop band attenuation and 0.001dB of passband

ripple.

•

Low Power:

–

330mW at 1.25MSPS

145mW at 625kSPS

Power-Down Mode

APPLICATIONS

•

Sonar

Output data is provided over a simple 3-wire serial

interface at rates up to 1.25MSPS, with a –3dB

bandwidth of 615kHz. The output data or its

complementary format directly connects to DSPs

such as TI’s TMS320 family, FPGAs, or ASICs. A

dedicated synchronization pin enables simultaneous

sampling with multiple ADS1601s in multi-channel

systems. Power dissipation is set by an external

resistor that allows a reduction in dissipation when

operating at slower speeds. All of the ADS1601

features are controlled by dedicated I/O pins, which

simplify operation by eliminating the need for on-chip

registers.

Vibration Analysis

Data Acquisition

VREFP VREFN VMID RBIAS VCAP AVDD

DVDD

IOVDD

CLK

SYNC

FSO

Reference and Bias Circuits

SCLK

Serial

AINP

AINN

Linear Phase

Interface

Modulator

FIR Digital Filter

DOUT

OTR

ADS1601

The high performing, easy-to-use ADS1601 is

especially suitable for demanding measurement

applications in sonar, vibration analysis, and data

acquisition. The ADS1601 is offered in a small, 7mm

REFEN

AGND

DGND

7mm TQFP-48 package and is specified

from –40°C to +85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or visit the device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

ADS1601

–0.3 to +6

UNIT

AVDD to AGND

DVDD to DGND

–0.3 to +3.6

IOVDD to DGND

–0.3 to +6

AGND to DGND

–0.3 to +0.3

Input current

100, momentary

10, continuous

–0.3 to AVDD + 0.3

–0.3 to IOVDD + 0.3

+150

Input current

Analog I/O to AGND

Digital I/O to DGND

Maximum junction temperature

Operating temperature range

Storage temperature range

°C

–40 to +105

–60 to +150

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS

All specifications at T_A= –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 20MHz, V_REF= +3V, V_CM= +2.7V, and

R_BIAS= 60kΩ, unless otherwise noted.

ADS1601

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog Input

Differential input voltage (V_IN) (AINP – AINN)

0dBFS

±0.94V_REF

Common-mode input voltage (V_CM) (AINP + AINN) / 2

2.7

Differential input voltage (V_IN

(AINP or AINN with respect to AGND)

)

0dBFS

–0.1

4.6

Dynamic Specifications

f_CLK

1.25

Data rate

MSPS

(

)

20MHZ

f_IN= 10kHz, –1dBFS

f_IN= 10kHz, –3dBFS

f_IN= 10kHz, –6dBFS

f_IN= 100kHz, –1dBFS

f_IN= 100kHz, –3dBFS

f_IN= 100kHz, –6dBFS

f_IN= 500kHz, –1dBFS

f_IN= 500kHz, –3dBFS

f_IN= 500kHz, –6dBFS

f_IN= 10kHz, –1dBFS

f_IN= 10kHz, –3dBFS

f_IN= 10kHz, –6dBFS

f_IN= 100kHz, –1dBFS

f_IN= 100kHz, –3dBFS

f_IN= 100kHz, –6dBFS

f_IN= 500kHz, –1dBFS

f_IN= 500kHz, –3dBFS

f_IN= 500kHz, –6dBFS

f_IN= 10kHz, –1dBFS

f_IN= 10kHz, –3dBFS

f_IN= 10kHz, –6dBFS

f_IN= 100kHz, –1dBFS

f_IN= 100kHz, –3dBFS

f_IN= 100kHz, –6dBFS

f_IN= 500kHz, –1dBFS

f_IN= 500kHz, –3dBFS

f_IN= 500kHz, –6dBFS

f_IN= 10kHz, –1dBFS

f_IN= 10kHz, –3dBFS

f_IN= 10kHz, –6dBFS

f_IN= 100kHz, –1dBFS

f_IN= 100kHz, –3dBFS

f_IN= 100kHz, –6dBFS

f_IN= 500kHz, –1dBFS

f_IN= 500kHz, –3dBFS

f_IN= 500kHz, –6dBFS

Signal-to-noise ratio (SNR)

–91

–100

–104

–88

–96

–103

–115

–112

–110

–90

–97

Total harmonic distortion (THD)

–90

–96

Signal-to-noise + distortion (SINAD)

100

109

Spurious-free dynamic range (SFDR)

105

120

118

115

f₁= 499kHz, –6dBFS

f₂= 501kHz, –6dBFS

Intermodulation distortion (IMD)

Aperture delay

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 20MHz, V_REF= +3V, V_CM= +2.7V, and

R_BIAS= 60kΩ, unless otherwise noted.

ADS1601

PARAMETER

Digital Filter Characteristics

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_CLK

550

Passband

kHz

(

)

20MHZ

Passband ripple

±0.001

f_CLK

575

–0.1dB attenuation

–3.0dB attentuation

kHz

(

)

20MHZ

Passband transition

f_CLK

615

kHz

(

)

20MHZ

f_CLK

0.7

19.3

Stop band

MHz

(

)

(

)

20MHZ

Stop band attenuation

Group delay

20MHz

f_CLK

20.8

μs

(

)

20MHz

f_CLK

40.8

Settling time

Complete settling

μs

(

)

Static Specifications

Resolution

Bits

No missing codes

Input-referred noise

Integral nonlinearity

Differential nonlinearity

Offset error

0.5

0.75

0.25

–0.05

0.5

0.75

LSB, rms

LSB

–0.5dBFS signal

LSB

%FSR

ppmFSR/°C

Offset error drift

Gain error

0.25⁽¹⁾

Gain error drift

Excluding reference drift

At DC

ppm/°C

Common-mode rejection

Power-supply rejection

Internal Voltage Reference

V_REF= (VREFP – VREFN)

VREFP

At DC

REFEN = low

2.75

3.5

0.5

2.3

3.25

4.1

1.1

2.6

3.8

0.8

2.4

VREFN

VMID

V_REFdrift

ppm/°C

Startup time

External Voltage Reference

V_REF= (VREFP – VREFN)

VREFP

REFEN = high

2.0

3.5

0.5

2.3

3.25

4.25

1.5

VREFN

VMID

2.5

2.6

(1) There is a constant gain error of 2.5% in addition to the variable gain error of ±0.25%. Therefore, the gain error is 2.5 ± 0.25%.

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 20MHz, V_REF= +3V, V_CM= +2.7V, and

R_BIAS= 60kΩ, unless otherwise noted.

ADS1601

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Clock Input

Frequency (f_CLK

Duty cycle

)

MHz

f_CLK= 20MHz

Digital Input/Output

V_IH

0.7 × IOVDD

DGND

IOVDD

V_IL

0.3 × IOVDD

V_OH

I_OH= 50μA

I_OL= 50μA

IOVDD – 0.5

V_OL

DGND + 0.5

Input leakage

DGND < V_DIGIN< IOVDD

±10

μA

Power-Supply Requirements

AVDD

DVDD

IOVDD

4.75

2.7

5.25

3.3

5.25

I_OH= 50μA

REFEN = low

REFEN = high

IOVDD = 3V

2.7

AVDD current (I_AVDD

)

DVDD current (I_DVDD

)

IOVDD current (I_IOVDD

)

AVDD = 5V, DVDD = 3V, IOVDD = 3V,

REFEN = high

330

380

Power dissipation

PD = low, CLK disabled

Temperature Range

Specified

–40

–60

+85

+105

+150

°C

Operating

Storage

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

DEFINITIONS

Intermodulation Distortion (IMD)

Absolute Input Voltage

Absolute input voltage, given in volts, is the voltage of

each analog input (AINN or AINP) with respect to

AGND.

IMD, given in dB, is measured while applying two

input signals of the same magnitude, but with slightly

different frequencies. It is calculated as the difference

between the rms amplitude of the input signal to the

rms amplitude of the peak spurious signal.

Aperture Delay

Aperture delay is the delay between the rising edge

of CLK and the sampling of the input signal.

Offset Error

Offset Error, given in % of FSR, is the output reading

when the differential input is zero.

Common-Mode Input Voltage

Common-mode input voltage (V_CM) is the average

voltage of the analog inputs:

Offset Error Drift

Offset error drift, given in ppm of FSR/°C, is the drift

over temperature of the offset error. The offset error

is specified as the larger of the drift from ambient

(T = +25°C) to the minimum or maximum operating

temperatures.

(AINP + AINN)

Differential Input Voltage

Differential input voltage (V_IN) is the voltage

difference between the analog inputs (AINP−AINN).

Signal-to-Noise Ratio (SNR)

SNR, given in dB, is the ratio of the rms value of the

input signal to the sum of all the frequency

components below f_CLK/2 (the Nyquist frequency)

excluding the first six harmonics of the input signal

and the dc component.

Differential Nonlinearity (DNL)

DNL, given in least-significant bits of the output code

(LSB), is the maximum deviation of the output code

step sizes from the ideal value of 1LSB.

Signal-to-Noise and Distortion (SINAD)

Full-Scale Range (FSR)

SINAD, given in dB, is the ratio of the rms value of

the input signal to the sum of all the frequency

components below fCLK/2 (the Nyquist frequency)

including the harmonics of the input signal but

excluding the dc component.

FSR is the difference between the maximum and

minimum measurable input signals (FSR = 1.88V_REF).

Gain Error

Gain error, given in %, is the error of the full-scale

input signal with respect to the ideal value.

Spurious-Free Dynamic Range (SFDR)

SFDR, given in dB, is the difference between the rms

amplitude of the input signal to the rms amplitude of

the peak spurious signal.

Gain Error Drift

Gain error drift, given in ppm/°C, is the drift over

temperature of the gain error. The gain error is

specified as the larger of the drift from ambient

(T = 25°C) to the minimum or maximum operating

temperatures.

Total Harmonic Distortion (THD)

THD, given in dB, is the ratio of the sum of the rms

value of the first six harmonics of the input signal to

the rms value of the input signal.

Integral Nonlinearity (INL)

INL, given in least-significant bits of the output code

(LSB), is the maximum deviation of the output codes

from a best fit line.

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

PIN ASSIGNMENTS

48 47 46 45 44 43 42 41 40 39 38 37

AGND

36 DGND

35 NC

AVDD

AGND

AINN

34 DVDD

33 DGND

32 FSO

31 FSO

30 DOUT

29 DOUT

28 SCLK

27 SCLK

26 NC

AINP

AGND

AVDD

RBIAS

AGND

TQFP PACKAGE

(TOP VIEW)

ADS1601

AVDD 10

AGND 11

AVDD 12

25 NC

13 14 15 16 17 18 19 20 21 22 23 24

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

AGND

AVDD

AINN

NO.

1, 3, 6, 9, 11, 39, 41

Analog

Analog ground

Analog supply

2, 7, 10, 12, 42

Analog input

Analog

Negative analog input

Positive analog input

AINP

RBIAS

REFEN

Terminal for external analog bias setting resistor.

Internal reference enable. Internal pull-down resistor of 170kΩ to DGND.

These terminals must be left unconnected.

Pull-up to DVDD with 10kΩ resistor (see Figure 50).

Power-down all circuitry. Internal pull-up resistor of 170kΩ to DGND.

Digital supply

Digital input: active low

Do not connect

Digital Input

Digital input: active low

Digital

14, 16, 24–26, 35

RPULLUP

DVDD

DGND

SYNC

OTR

18, 23, 34

19, 22, 33, 36, 38

Digital

Digital ground

Digital input

Digital output

Digital

Synchronization control input

Indicates analog input signal is out of range.

Serial clock output

SCLK

DOUT

FSO

Serial clock output, complementary signal.

Data output

Data output, complementary signal.

Frame synchronization output

FSO

Frame synchronization output, complementary signal.

Digital I/O supply

IOVDD

CLK

Digital output

Analog

Clock input supply

VCAP

VREFN

VMID

VREFP

Terminal for external bypass capacitor connection to internal bias voltage.

Negative reference voltage

44, 45

Analog

Midpoint voltage

47, 48

Analog

Positive reference voltage

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

TIMING DIAGRAMS

t_C

CLK

t_HSC

t_SSC

SYNC

FSO

t_SYPW

t_STL

Figure 1. Initialization Timing

TIMING REQUIREMENTS

For T_A= –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V.

SYMBOL

t_SYPW

t_C

DESCRIPTION

MIN

TYP

MAX

UNIT

CLK period

SYNC positive pulse width

Clock period (CLK)

t_SSC

Setup time; SYNC rising edge to CLK rising edge

Hold time; CLK rising edge to SYNC falling edge

0.5

CLK period

t_HSC

Settling time of the ADS1601; FSO falling edge to next

FSO rising edge

t_STL

833

CLK periods

t_CPW

CLK

t_CS

t_CPW

SCLK

t_CF

t_FPW

t_DH

FSO

t_DS

BIT

DOUT

MSB

LSB

New Data

Figure 2. Data Retrieval Timing

TIMING REQUIREMENTS

For T_A= –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V.

SYMBOL

t_CS

DESCRIPTION

MIN

TYP

MAX

UNIT

Rising edge of CLK to rising edge of SCLK

Rising edge of SCLK to rising edge of FSO

CLK positive or negative pulse width

Frame sync output high pulse width

SCLK rising edge to new DOUT valid

SCLK falling edge to DOUT invalid

t_CF

t_CPW

t_FPW

t_DS

CLK period

t_DH

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 20MHz, V_REF= +3V, V_CM= +2.7V, and

R_BIAS= 60kΩ, unless otherwise noted.

SPECTRAL RESPONSE

-20

f_IN= 10kHz, -1dBFS

f_IN= 10kHz, -6dBFS

SNR = 92dB

THD = -91dB

SFDR = 92dB

SNR = 87dB

THD = -108dB

SFDR = 111dB

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

100

200

300

400

500

600

100

200

300

400

500

600

Frequency (kHz)

Figure 3.

Figure 4.

SPECTRAL RESPONSE

-20

f_IN= 10kHz, -10dBFS

SNR = 83dB

f_IN= 100kHz, -1dBFS

SNR = 92dB

THD = -106dB

SFDR = 111dB

THD = -88dB

-40

SFDR = 88dB

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

100

200

300

400

500

600

200

300

400

500

600

Frequency (kHz)

Figure 5.

Figure 6.

SPECTRAL RESPONSE

-20

f_IN= 100kHz, -10dBFS

SNR = 83dB

f_IN= 100kHz, -6dBFS

SNR = 87dB

THD = -103dB

SFDR = 105dB

-40

SFDR = 105dB

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

100

200

300

400

500

600

200

300

400

500

600

Frequency (kHz)

Figure 7.

Figure 8.

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 20MHz, V_REF= +3V, V_CM= +2.7V, and

R_BIAS= 60kΩ, unless otherwise noted.

SPECTRAL RESPONSE

-20

f_IN= 504kHz, -6dBFS

f_IN= 504kHz, -1dBFS

SNR = 86dB

SNR = 91dB

THD = -110dB

SFDR = 115dB

THD = -117dB

SFDR = 122dB

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

100

200

300

400

500

600

100

200

300

400

500

600

Frequency (kHz)

Figure 9.

Figure 10.

SNR, THD, AND SFDR

SPECTRAL RESPONSE

vs INPUT SIGNAL AMPLITUDE

-20

140

f_IN= 504kHz, -10dBFS

SNR = 83dB

120

100

THD = -110dB

-40

SFDR = 117dB

-60

SFDR

THD

-80

SNR

-100

-120

-140

-160

f_IN= 10kHz

100

200

300

400

500

600

-80

-70

-60

-50

-40

-30

-20

-10

Frequency (kHz)

Input Signal Amplitude, V_IN(dB)

Figure 11.

Figure 12.

SNR, THD, AND SFDR

vs INPUT SIGNAL AMPLITUDE

140

120

100

120

100

SFDR

THD

SFDR

SNR

THD

SNR

f_IN= 100kHz

f_IN= 500kHz

-80

-70

-60

-50

-40

-30

-20

-10

-80

-70

-60

-50

-40

-30

-20

-10

Input Signal Amplitude, V_IN(dB)

Figure 13.

Figure 14.

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 20MHz, V_REF= +3V, V_CM= +2.7V, and

R_BIAS= 60kΩ, unless otherwise noted.

SIGNAL-TO-NOISE RATIO

vs INPUT FREQUENCY

TOTAL HARMONIC DISTORTION

vs INPUT FREQUENCY

100

-80

-90

V_IN= -1dB

V_IN= -6dB

-100

-110

-120

V_IN= -10dB

V_IN= -6dB

V_IN= -10dB

10k

100k

10k

100k

Input Frequency, f_IN(Hz)

Figure 15.

Figure 16.

SPURIOUS-FREE DYNAMIC RANGE

vs INPUT FREQUENCY

SIGNAL-TO-NOISE RATIO

vs INPUT COMMON-MODE VOLTAGE

120

110

100

f_IN= 10kHz, V_IN= -1dB

f_IN= 100kHz, V_IN= -1dB

V_IN= -10dB

V_IN= -6dB

f_IN= 10kHz, V_IN= -6dB

f_IN= 100kHz, V_IN= -6dB

V_IN= -1dB

10k

100k

1.0

1.4

1.8

2.2

2.6

3.0

3.4

Input Frequency, f_IN(Hz)

Input Common-Mode Voltage, V_CM(V)

Figure 17.

Figure 18.

TOTAL HARMONIC DISTORTION

vs INPUT COMMON-MODE VOLTAGE

SPURIOUS-FREE DYNAMIC RANGE

vs INPUT COMMON-MODE VOLTAGE

-80

-90

120

110

100

f_IN= 100kHz, V_IN= -1dB

f_IN= 10kHz, V_IN= -6dB

f_IN= 10kHz, V_IN= -1dB

-100

-110

-120

f_IN= 100kHz, V_IN= -6dB

f_IN= 10kHz, V_IN= -1dB

f_IN= 10kHz, V_IN= -6dB

f_IN= 100kHz, V_IN= -6dB

f_IN= 100kHz, V_IN= -1dB

1.0

1.4

1.8

2.2

2.6

3.0

3.4

1.0

1.4

1.8

2.2

2.6

3.0

3.4

Input Common-Mode Voltage, V_CM(V)

Figure 19.

Figure 20.

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 20MHz, V_REF= +3V, V_CM= +2.7V, and

R_BIAS= 60kΩ, unless otherwise noted.

SIGNAL-TO-NOISE RATIO

vs CLOCK FREQUENCY

TOTAL HARMONIC DISTORTION

vs CLOCK FREQUENCY

-80

-90

100

V_IN= -6dBFS, f_IN= 10kHz

R_BIAS= 210kW

R_BIAS= 60kW

R_BIAS= 267kW

-100

-110

-120

R_BIAS= 140kW

R_BIAS= 210kW

R_BIAS= 267kW

R_BIAS= 140kW

R_BIAS= 60kW

VIN = -6dBFS, fIN = 10kHz

Clock Frequency, f_CLK(MHz)

Figure 21.

Figure 22.

SPURIOUS-FREE DYNAMIC RANGE

vs CLOCK FREQUENCY

NOISE

vs DC INPUT VOLTAGE

120

110

100

1000

100

R_BIAS= 140kW

R_BIAS= 60kW

R_BIAS= 210kW

R_BIAS= 267kW

V_IN= -6dBFS, f_IN= 10kHz

0.1

-3

-2

-1

Input DC Voltage (V)

Clock Frequency, f_CLK(MHz)

Figure 23.

Figure 24.

NOISE HISTOGRAM

OFFSET DRIFT OVER TIME

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

V_IN= 0V

-1

-2

-3

-4

-3

-2

-1

100 200 300 400 500 600 700 800 900 1000

Time Interval (s)

Output Code (LSB)

Figure 25.

Figure 26.

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 20MHz, V_REF= +3V, V_CM= +2.7V, and

R_BIAS= 60kΩ, unless otherwise noted.

POWER-SUPPLY CURRENT vs TEMPERATURE

SUPPLY CURRENT vs CLOCK FREQUENCY

I_AVDD(REFEN = low)

I_AVDD(REFEN = high)

I_DVDD+ I_IOVDD

I_IOVDD+ I_DVDD

R_BIAS= 60kW, f_CLK= 20MHz

R_BIAS= 60kW

-40

-15

Temperature (°C)

Clock Frequency, f_CLK(MHz)

Figure 27.

Figure 28.

ANALOG SUPPLY CURRENT vs R_BIAS

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

100

V_IN= -1dB

V_IN= -6dB

I_AVDD(REFEN = low)

V_IN= -10dB

I_AVDD(REFEN = high)

f_IN= 100kHz

f_CLK= 20MHz

250

-40

-15

100

150

200

300

Temperature (°C)

R_BIAS(kW)

Figure 29.

Figure 30.

TOTAL HARMONIC DISTORTION vs TEMPERATURE

SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE

120

-80

V_IN= -1dB

V_IN= -6dB

V_IN= -10dB

110

-90

-100

-110

-120

V_IN= -6dB

100

V_IN= -10dB

V_IN= -1dB

f_IN= 100kHz

60 85

f_IN= 100kHz

-40

-15

-40

-15

Temperature (°C)

Figure 31.

Figure 32.

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 20MHz, V_REF= +3V, V_CM= +2.7V, and

R_BIAS= 60kΩ, unless otherwise noted.

V_REFvs TEMPERATURE

INTERMODULATION RESPONSE

3.00

2.99

2.98

2.97

2.96

2.95

2.94

2.93

2.92

2.91

2.90

-20

f_IN1= 499kHz

f_IN2= 501kHz

IMD = -94dB

-40

-60

-80

-100

-120

-140

-40

-15

480

485

490

495

500

505

510

515

520

Temperature (°C)

Frequency (kHz)

Figure 33.

Figure 34.

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

OVERVIEW

The ADS1601 is a high-performance delta-sigma

ADC. The modulator uses an inherently stable 2-1-1

multi-stage architecture incorporating proprietary

circuitry that allows for very linear high-speed

operation. The modulator samples the input signal at

20MSPS (when f_CLK= 20MHz). A low-ripple linear

phase digital filter decimates the modulator output by

16 to provide high resolution 16-bit output data.

The ADS1601 supports a very wide range of input

signals. For V_REF= 3V, the full-scale input voltage is

±2.82V. Having such a wide input range makes

out-of-range signals unlikely. However, if an

out-of-range signal occurs, the digital output OTR

goes high.

The analog inputs must be driven with a differential

signal to achieve optimum performance. For the input

signal:

Conceptually, the modulator and digital filter measure

the differential input signal, V_IN= (AINP – AINN),

AINP + AINN

V_CM

against

the

scaled

differential

reference,

V_REF= (VREFP – VREFN), as shown in Figure 35.

The voltage reference can either be generated

internally or supplied externally. A three-wire serial

interface, designed for direct connection to DSPs,

outputs the data. A separate power supply for the I/O

allows flexibility for interfacing to different logic

families. Out-of-range conditions are indicated with a

dedicated digital output pin. Analog power dissipation

is controlled using an external resistor. This control

allows reduced dissipation when operating at slower

speeds. When not in use, power consumption can be

dramatically reduced by setting the PD pin low to

enter Power-Down mode.

the recommended common-mode voltage is 2.7V. In

addition to the differential and common-mode input

voltages, the absolute input voltage is also important.

This is the voltage on either input (AINP or AINN)

with respect to AGND. The range for this voltage is:

–0.1V < (AINN or AINP) < 4.6V

If either input is taken below –0.1V, ESD protection

diodes on the inputs will turn on. Exceeding 4.6V on

either input results in degradation in the linearity

performance. ESD protection diodes will also turn on

if the inputs are taken above AVDD (+5V).

The recommended absolute input voltage is:

ANALOG INPUTS (AINP, AINN)

–0.1V < (AINN or AINP) < 4.2V

The ADS1601 measures the differential signal,

V_IN

reference, V_REF= (VREFP – VREFN). The most

positive measurable differential input is 0.94V_REF

= (AINP – AINN), against the differential

Keeping the inputs within this range provides for

optimum performance.

which produces the most positive digital output code

of 7FFFh. Likewise, the most negative measurable

differential input is –0.94V_REF, which produces the

most negative digital output code of 8000h.

VREFP VREFN

IOVDD

CLK

V_REF

FSO

V_IN

AINP

AINN

Modulator

SCLK

DOUT

Digital

Filter

Serial

1.06

Interface

Figure 35. Conceptual Block Diagram

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

INPUT CIRCUITRY

drivers close to the inputs and use good capacitor

bypass techniques on their supplies, such as a

smaller high-quality ceramic capacitor in parallel with

a larger capacitor. Keep the resistances used in the

driver circuits low—thermal noise in the driver circuits

degrades the overall noise performance. When the

signal can be ac-coupled to the ADS1601 inputs, a

simple RC filter can set the input common-mode

The ADS1601 uses switched-capacitor circuitry to

measure the input voltage. Internal capacitors are

charged by the inputs and then discharged internally

with this cycle repeating at the frequency of CLK.

Figure 36 shows a conceptual diagram of these

circuits. Switches S₂represent the net effect of the

modulator circuitry in discharging the sampling

capacitors; the actual implementation is different. The

timing for switches S₁and S₂is shown in Figure 37.

voltage.

The

ADS1601

high-speed,

high-performance ADC. Special care must be taken

when selecting the test equipment and setup used

with this device. Pay particular attention to the signal

sources to ensure they do not limit performance when

measuring the ADS1601.

ADS1601

S₁

AINP

S₂

392W

10pF

8pF

40pF

392W

V_IN

+ V_CM

VMID

0.01mF

49.9W

S₁

AINP

OPA2822

392W

(2)

(1)

AINN

V_CM

100pF

S₂

1kW

1mF

10pF

8pF

(2)

392W

(1)

(3)

V_CM

100pF

ADS1601

(2)

VMID

40pF

392W

V_IN

AGND

1kW

+ V_CM

0.01mF

49.9W

AINN

OPA2822

392W

(2)

(1)

Figure 36. Conceptual Diagram of Internal

Circuitry Connected to the Analog Inputs

V_CM

100pF

1mF

AGND

t_SAMPLE= 1/f_CLK

(1) Recommended V_CM= 2.7V.

(2) Optional ac-coupling circuit provides common-mode input

voltage.

Off

S₁

(3) Increase to 390pF when f_IN≤ 100kHz for improved SNR and

THD.

Off

S₂

Figure 38. Recommended Driver Circuit Using

the OPA2822

Figure 37. Timing for the Switches in Figure 36

22pF

24.9W

DRIVING THE INPUTS

AINP

392W

The external circuits driving the ADS1601 inputs must

be able to handle the load presented by the switching

capacitors within the ADS1601. The input switches S₁

in Figure 36 are closed for approximately one-half of

the sampling period, t_SAMPLE, allowing only ≉ 24ns for

the internal capacitors to be charged by the inputs

when f_CLK= 20MHz.

100pF

392W

-V_IN

V_CM

THS4503

ADS1601

100pF

+V_IN

392W

24.9W

AINN

100pF

22pF

Figure 38 and Figure 39 show the recommended

circuits when using single-ended or differential op

amps, respectively. The analog inputs must be driven

differentially to achieve optimum performance. The

external capacitors, between the inputs and from

each input to AGND, improve linearity and should be

placed as close to the pins as possible. Place the

Figure 39. Recommended Driver Circuit Using

the THS4503 Differential Amplifier

ADS1601

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SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

REFERENCE INPUTS (VREFN, VREFP, VMID)

EXTERNAL REFERENCE (REFEN = HIGH)

The ADS1601 can operate from an internal or

external voltage reference. In either case, the

reference voltage V_REFis set by the differential

To use an external reference, set the REFEN pin

high. This deactivates the internal generators for

VREFP,

VREFN,

and

VMID,

and

saves

voltage between VREFN and VREFP: V_REF

approximately 25mA of current on the analog supply

(AVDD). The voltages applied to these pins must be

within the values specified in the Electrical

Characteristics table. Typically, VREFP = 4V, VMID =

2.5V, and VREFN = 1V. The external circuitry must

be capable of providing both a dc and a transient

current. Figure 41 shows a simplified diagram of the

internal circuitry of the reference when the internal

reference is disabled. As with the input circuitry,

switches S₁and S₂open and close as shown by the

timing in Figure 37.

(VREFP – VREFN). VREFP and VREFN each use

two pins, which should be shorted together. VMID

equals approximately 2.5V and is used by the

modulator. VCAP connects to an internal node and

must also be bypassed with an external capacitor.

INTERNAL REFERENCE (REFEN = LOW)

To use the internal reference, set the REFEN pin low.

This activates the internal circuitry that generates the

reference voltages. The internal reference voltages

are applied to the pins. Good bypassing of the

reference pins is critical to achieve optimum

performance and is done by placing the bypass

capacitors as close to the pins as possible. Figure 40

shows the recommended bypass capacitor values.

Use high-quality ceramic capacitors for the smaller

values. Avoid loading the internal reference with

external circuitry. If the ADS1601 internal reference is

to be used by other circuitry, buffer the reference

voltages to prevent directly loading the reference

pins.

ADS1601

S₁

VREFP

S₂

300W

50pF

VREFN

S₁

Figure 41. Conceptual Internal Circuitry for the

Reference When REFEN = High

ADS1601

Figure 42 shows the recommended circuitry for

driving these reference inputs. Keep the resistances

used in the buffer circuits low to prevent excessive

thermal noise from degrading performance. Layout of

these circuits is critical; be sure to follow good

high-speed layout practices. Place the buffers, and

especially the bypass capacitors, as close to the pins

as possible. VCAP is unaffected by the setting on

REFEN and must be bypassed when using the

internal or an external reference.

VREFP

10mF

0.1mF

VMID

0.1mF

10mF

0.1mF

VREFN

10mF

0.1mF

VCAP

AGND

Figure 40. Reference Bypassing When Using the

Internal Reference

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

Table 1. Maximum Allowable Clock Source Jitter

for Different Input Signal Frequencies and

Amplitude

392W

0.001mF

ADS1601

INPUT SIGNAL

VREFP

OPA2822

MAXIMUM

FREQUENCY AMPLITUDE

MAXIMUM

MAXIMUM ALLOWABLE

CLOCK SOURCE JITTER

10mF

2.5V

0.1mF

392W

500kHz

100kHz

–0.5dB

–20dB

–0.5dB

–20dB

6ps

60ps

30ps

300ps

0.1mF

0.001mF

VMID

OPA2822

10mF

0.1mF

392W

DATA FORMAT

0.001mF

The 16-bit output data are in binary two’s

complement format as shown in Table 2. When the

input is positive out-of-range, exceeding the positive

full-scale value of +0.94V_REF, the output clips to all

7FFFh and the OTR output goes high.

VREFN

OPA2822

10mF

0.1mF

VCAP

Likewise, when the input is negative out-of-range by

going below the negative full-scale value

of –0.94V_REF, the output clips to 8000h and the OTR

output goes high. The OTR remains high while the

input signal is out-of-range.

AGND

Figure 42. Recommended Buffer Circuit When

Using an External Reference

Table 2. Output Code versus Input Signal

INPUT SIGNAL (INP –

IDEAL OUTPUT

CODE⁽¹⁾

CLOCK INPUT (CLK)

INN)

OTR

≥ +0.94V_REF(> 0dB)

–0.94V_REF(0dB)

7FFFh

The ADS1601 requires an external clock signal to be

applied to the CLK input pin. The sampling of the

modulator is controlled by this clock signal. As with

any high-speed data converter, a high quality clock is

essential for optimum performance. Crystal clock

oscillators are the recommended CLK source; other

sources, such as frequency synthesizers, are usually

inadequate. Make sure to avoid excess ringing on the

CLK input; keeping the trace as short as possible

helps.

+0.94V_REF

001h

0000h

FFFFh

- 1

-0.94V_REF

- 1

-0.94V_REF

8000h

(

)

- 1

Measuring high-frequency, large amplitude signals

requires tight control of clock jitter. The uncertainty

during sampling of the input from clock jitter limits the

maximum achievable SNR. This effect becomes more

pronounced with higher frequency and larger

magnitude inputs. Fortunately, the ADS1601

oversampling topology reduces clock jitter sensitivity

over that of Nyquist rate converters such as pipeline

and successive approximation converters by a factor

of √16.

-0.94V_REF

(

)

- 1

(1) Excludes effects of noise, INL, offset and gain errors.

OUT-OF-RANGE INDICATION (OTR)

If the output code exceeds the positive or negative

full-scale, the out-of-range digital output OTR will go

high on the falling edge of SCLK. When the output

code returns within the full-scale range, OTR returns

low on the falling edge of SCLK.

In order to not limit the ADS1601 SNR performance,

keep the jitter on the clock source below the values

shown in Table 1. When measuring lower frequency

and lower amplitude inputs, more CLK jitter can be

tolerated. In determining the allowable clock source

jitter, select the worst-case input (highest frequency,

largest amplitude) that will be seen in the application.

ADS1601

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SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

DATA RETRIEVAL

STEP RESPONSE

Data retrieval is controlled through a simple serial

interface. The interface operates in a master fashion

by outputting both a frame sync indicator (FSO) and a

serial clock (SCLK). Complementary outputs are

provided for the frame sync output (FSO), serial clock

(SCLK), and data output (DOUT). When not needed,

leave the complementary outputs unconnected.

Figure 44 plots the normalized step response for an

input applied at t = 0. The x-axis units of time are

conversions cycles. It takes 51 cycles to fully settle;

for f_CLK= 20MHz, this corresponds to 40.8μs.

1.2

1.0

0.8

0.6

0.4

0.2

INITIALIZING THE ADS1601

After the power supplies have stabilized, you must

initialize the ADS1601 by issuing a SYNC pulse as

shown in Figure 1. This operation needs only to be

done once after power-up and does not need to be

performed when exiting the Power-Down mode. Note

that the ADS1601 silicon was revised in June 2006.

The digital interface timing specifications were

modified slightly from the previous revision. This data

sheet reflects behavior of the latest revision. Contact

the factory for more information on the previous

revision.

-0.2

Time (Conversion Cycles)

Figure 44. Step Response

SYNCHRONIZING MULTIPLE ADS1601s

The SYNC input can be used to synchronize multiple

ADS1601s to provide simultaneous sampling. All

devices to be synchronized must use a common CLK

input. With the CLK inputs running, pulse SYNC on

the falling edge of CLK, as shown in Figure 43.

Afterwards, the converters will be converting

synchronously with the FSO outputs updating

simultaneously. After synchronization, FSO is held

low until the digital filter has fully settled.

FREQUENCY RESPONSE

The linear phase FIR digital filter sets the overall

frequency response. Figure 45 shows the frequency

response from dc to 10MHz for f_CLK= 20MHz. The

frequency response of the ADS1601 filter scales

directly with CLK frequency. For example, if the CLK

frequency is decreased by half (to 10MHz), the

values on the X-axis in Figure 45 would need to be

scaled by half, with the span becoming dc to 5MHz.

Figure 46 shows the passband ripple from dc to

600kHz (f_CLK= 20MHz). Figure 47 shows a closer

view of the passband transition by plotting the

response from 400kHz to 650kHz (f_CLK= 20MHz).

ADS1601₁

SYNC

CLK

SYNC

CLK

FSO

FSO₁

DOUT

DOUT₁

f_CLK= 20MHz

ADS1601₂

-20

FSO₂

SYNC

CLK

FSO

DOUT₂

DOUT

-40

-60

-80

CLK

-100

-120

-140

SYNC

t_STL

FSO₁

FSO₂

Frequency (MHz)

Figure 45. Frequency Response

Figure 43. Synchronizing Multiple Converters

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

0.001

0.0008

0.0006

0.0004

0.0002

f_CLK= 20MHz

-20

-40

-60

-80

-100

-120

-140

-0.0002

-0.0004

-0.0006

-0.0008

f_CLK= 20MHz

400 500

-0.001

100

200

300

600

Frequency (kHz)

Frequency (MHz)

Figure 46. Passband Ripple

Figure 48. Frequency Response Out to 120MHz

ANALOG POWER DISSIPATION

0.5

f_CLK= 20MHz

An external resistor connected between the RBIAS

pin and the analog ground sets the analog current

level, as shown in Figure 49. The current is inversely

proportional to the resistor value. Table 3 shows the

recommended values of R_BIASfor different CLK

frequencies. Notice that the analog current can be

reduced when using a slower frequency CLK input

because the modulator has more time to settle. Avoid

adding any capacitance in parallel to R_BIASbecause

this interferes with the internal circuitry used to set

the biasing. Please note that changing R_BIASchanges

internally-generated voltages, including the internal

reference; therefore, it should be understood that the

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

400

450

500

550

600

650

Frequency (kHz)

recommendations of Table

reference only.

3 are for external

Figure 47. Passband Transition

ADS1601

ANTI-ALIAS REQUIREMENTS

Higher frequency, out-of-band signals must be

eliminated to prevent aliasing with ADCs. Fortunately,

the ADS1601 on-chip digital filter greatly simplifies

this filtering requirement. Figure 48 shows the

ADS1601 response out to 60MHz (f_CLK= 20MHz).

Since the stop band extends out to 19.3MHz, the

anti-alias filter in front of the ADS1601 only needs to

be designed to remove higher frequency signals than

this, which can usually be accomplished with a simple

RC circuit on the input driver.

RBIAS

R_BIAS

AGND

Figure 49. External Resistor Used to Set Analog

Power Dissipation

Table 3. Recommended R_BIASResistor Values for

Different CLK Frequencies

TYPICAL POWER

DATA

RATE

DISSIPATION

WITH REFEN HIGH

f_CLK

R_BIAS

267k

210k

140k

60k

5MHz

315kSPS

625kSPS

940kSPS

1.25MSPS

100mW

145mW

200mW

325mW

10MHz

15MHz

20MHz

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

POWER DOWN (PD)

POWER SUPPLIES

When not in use, the ADS1601 can be powered down

by taking the PD pin low. All circuitry is shut down,

including the voltage reference. To minimize the

digital current during power down, stop the clock

signal supplied to the CLK input. There is an internal

pull-up resistor of 170kΩ on the PD pin, but it is

recommended that this pin be connected to IOVDD if

not used. Make sure to allow time for the reference to

start up after exiting power-down mode. The internal

reference typically requires 15ms. After the reference

has stabilized, allow at least 100 conversions for the

modulator and digital filter to settle before retrieving

data.

Three supplies are used on the ADS1601: analog

(AVDD), digital (DVDD) and digital I/O (IOVDD). Each

supply must be suitably bypassed to achieve the best

performance. It is recommended that a 1μF and

0.1μF ceramic capacitor be placed as close to each

supply pin as possible. Connect each supply-pin

bypass capacitor to the associated ground, as shown

in Figure 50. Each main supply bus should also be

bypassed with a bank of capacitors from 47μF to

0.1μF, as shown. The I/O and digital supplies (IOVDD

and DVDD) can be connected together when using

the same voltage. In this case, only one bank of 47μF

to 0.1μF capacitors is needed on the main supply

bus, though each supply pin must still be bypassed

with a 1μF and 0.1μF ceramic capacitor.

DVDD

47mF

4.7mF

1mF

0.1mF

IOVDD

AVDD

4.7mF

0.1mF

C_P

AGND

AVDD

DGND 36

C_P

If using separate analog and

digital ground planes, connect

together on the ADS1601 PCB.

AGND

C_P

AVDD

AGND

ADS1601

DGND

AGND

NOTE: C_P= 1mF úú 0.1mF

C_P

10 AVDD

11 AGND

C_P

12 AVDD

10kW

C_P

Figure 50. Recommended Power-Supply Bypassing

ADS1601

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

LAYOUT ISSUES AND COMPONENT

SELECTION

The McBSP provides a host of functions including:

•

Full-duplex communication

Double-buffered data registers

Independent framing and clocking for reception

and transmission of data

The ADS1601 is a very high-speed, high-resolution

data converter. In order to achieve maximum

performance, the user must give very careful

consideration to both the layout of the printed circuit

board (PCB) in addition to the routing of the traces.

Capacitors that are critical to achieve the best

performance from the device should be placed as

close to the pins of the device as possible. These

include capacitors related to the analog inputs, the

reference, and the power supplies.

The sequence begins with a one-time synchronization

of the serial port by the microprocessor. The

ADS1601 recognizes the SYNC signal if it is high for

at least one CLK period. Transfers are initiated by the

ADS1601 after the SYNC signal is de-asserted by the

microprocessor.

The FSO signal from the ADS1601 indicates that

data is available to be read, and is connected to the

frame sync receive (FSR) pin of the DSP. The clock

receiver (CLKR) is derived directly from the ADS1601

For critical capacitors, it is recommended that Class II

dielectrics such as Z5U be avoided. These dielectrics

have

a narrow operating temperature, a large

tolerance on the capacitance, and lose up to 20% of

the rated capacitance over 10,000 hours. Rather,

select capacitors with a Class I dielectric. C0G (also

known as NP0), for example, has a tight tolerance

less than ±30ppm/°C and is very stable over time.

Should Class II capacitors be chosen because of the

size constraints, select an X7R or X5R dielectric to

minimize the variations of the capacitor’s critical

characteristics.

serial

clock

output

ensure

continued

synchronization of data with the clock.

ADS1601

FSO

TMS320

FSR

CLKR

SCLK

DOUT

SYNC

The resistors used in the circuits to drive the input

and reference should be kept as low as possible to

prevent excess thermal noise from degrading the

system performance.

FSX

The digital outputs from the device should always be

buffered. This will have a number of benefits: it

reduces the loading of the internal digital buffers,

which decreases noise generated within the device,

and it also reduces device power consumption.

Figure 51. ADS1601—TMS320 Interface

Connection

An evaluation module (EVM) is available from Texas

Instruments. The module consists of the ADS1601

and supporting circuits, allowing users to quickly

assess the performance and characteristics of the

ADS1601. The EVM easily connects to various

microcontrollers and DSP systems. For more details,

or to download a copy of the ADS1601EVM User’s

Guide, visit the Texas Instruments web site at

www.ti.com.

APPLICATIONS INFORMATION

Interfacing the ADS1601 to the TMS320 DSP

family.

Since the ADS1601 communicates with the host via a

serial interface, the most suitable method to connect

to any of the TMS320 DSPs is via the multi-channel

buffered serial port (McBSP). A typical connection to

the TMS320 DSP is shown in Figure 51.

ADS1601

www.ti.com

SBAS322D –DECEMBER 2004–REVISED OCTOBER 2011

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (September 2010) to Revision D

Page

•

Added footnote 1 to Electrical Characteristics table ............................................................................................................. 4

Changes from Revision B (September 2008) to Revision C

Page

•

Changed the Timing Diagrams section ................................................................................................................................. 8

Added note to Initializing the ADS1601 section .................................................................................................................. 19

Updated Figure 43 .............................................................................................................................................................. 19

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADS1601IPFBR

ADS1601IPFBT

ACTIVE

TQFP

PFB

1000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

ADS1601I

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Feb-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS1601IPFBR

TQFP

PFB

1000

330.0

16.4

9.6

1.5

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Feb-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TQFP PFB 48

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

ADS1601IPFBR

1000

Pack Materials-Page 2

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

0,08

0,13 NOM

5,50 TYP

7,20

Gage Plane

6,80

9,20

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ADS1601IPFBT [TI]

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