ADS1602IPFBR_技术文档

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

16-Bit, 2.5MSPS Analog-to-Digital Converter

Check for Samples: ADS1602

1

FEATURES

DESCRIPTION

The ADS1602 is

a high-speed, high-precision,

2

•

High Speed:

delta-sigma (ΔΣ) analog-to-digital converter (ADC)

manufactured on an advanced CMOS process. The

ADS1602 oversampling topology reduces clock jitter

sensitivity during the sampling of high-frequency,

large amplitude signals by a factor of four over that

achieved by Nyquist-rate ADCs. Consequently,

signal-to-noise ratio (SNR) is particularly improved.

Total harmonic distortion (THD) is –101dB, and the

spurious-free dynamic range (SFDR) is 103dB.

–

Data Rate: 2.5MSPS

Bandwidth: 1.23MHz

•

Outstanding Performance:

–

SNR: 91dB at f_IN= 100kHz, –1dBFS

THD: –101dB at f_IN= 100kHz, –6dBFS

SFDR: 103dB at f_IN= 100kHz, –6dBFS

•

Ease-of-Use:

Optimized for power and performance, the ADS1602

dissipates only 530mW while providing a full-scale

differential input range of ±3V. Having such a wide

input range makes out-of-range signals unlikely. The

OTR pin indicates if an analog input out-of-range

condition does occur. The differential input signal is

measured against the differential reference, which

can be generated internally or supplied externally on

the ADS1602.

–

High-Speed 3-Wire Serial Interface

Directly Connects to TMS320 DSPs

On-Chip Digital Filter Simplifies Antialias

Requirements

–

Simple Pin-Driven Control—No On-Chip

Registers to Program

–

Selectable On-Chip Voltage Reference

Simultaneous Sampling with Multiple

ADS1602s

The ADS1602 uses an inherently stable advanced

modulator with an on-chip decimation filter. The filter

stop band extends to 38.6MHz, which greatly

simplifies the antialiasing circuitry. The modulator

samples the input signal up to 40MSPS, depending

on f_CLK, while the 16x decimation filter uses a series

of four half-band FIR filter stages to provide 75dB of

stop band attenuation and 0.001dB of passband

ripple.

•

Low Power:

–

530mW at 2.5MSPS

Power-Down Mode

APPLICATIONS

•

Sonar

Vibration Analysis

Data Acquisition

VREFP VREFN VMID RBIAS VCAP AVDD

Output data is provided over a simple 3-wire serial

interface at rates up to 2.5MSPS, with a –3dB

bandwidth of 1.23MHz. The output data or its

complementary format directly connects to DSPs

such as TI’s TMS320 family, FPGAs, or ASICs. A

dedicated synchronization pin enables simultaneous

sampling with multiple ADS1602s in multi-channel

systems. Power dissipation is set by an external

resistor that allows a reduction in dissipation when

operating at slower speeds. All of the ADS1602

features are controlled by dedicated I/O pins, which

simplify operation by eliminating the need for on-chip

registers.

DVDD

IOVDD

CLK

SYNC

FSO

Reference and Bias Circuits

SCLK

Serial

AINP

AINN

DS

Linear Phase

Interface

Modulator

FIR Digital Filter

DOUT

OTR

PD

ADS1602

REFEN

The high performing, easy-to-use ADS1602 is

especially suitable for demanding measurement

applications in sonar, vibration analysis, and data

acquisition. The ADS1602 is offered in a small, 7mm

AGND

DGND

×

7mm TQFP-48 package and is specified

from –40°C to +85°C.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or visit the device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

ADS1602

–0.3 to +6

UNIT

V

AVDD to AGND

DVDD to DGND

–0.3 to +3.6

V

IOVDD to DGND

–0.3 to +6

V

AGND to DGND

–0.3 to +0.3

V

Input current

100, momentary

10, continuous

–0.3 to AVDD + 0.3

–0.3 to IOVDD + 0.3

+150

mA

V

Input current

Analog I/O to AGND

Digital I/O to DGND

Maximum junction temperature

Operating temperature range

Storage temperature range

V

°C

–40 to +105

–60 to +150

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

2

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS

All specifications at T_A= –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 40MHz, external V_REF= +3V, V_CM

=

+1.45V, and R_BIAS= 37kΩ, unless otherwise noted.

ADS1602

TYP

PARAMETER

Analog Input

TEST CONDITIONS

MIN

MAX

UNIT

Differential input voltage (V_IN) (AINP – AINN)

Common-mode input voltage (V_CM) (AINP + AINN) / 2

0dBFS

±V_REF

V

1.45

Absolute input voltage

(AINP or AINN with respect to AGND)

–0.1

4.6

V

Dynamic Specifications

f_CLK

2.5

Data rate

MSPS

(

)

40MHz

f_IN= 10kHz, –1dBFS

f_IN= 10kHz, –3dBFS

f_IN= 10kHz, –6dBFS

f_IN= 100kHz, –1dBFS

f_IN= 100kHz, –3dBFS

f_IN= 100kHz, –6dBFS

f_IN= 800kHz, –1dBFS

f_IN= 800kHz, –3dBFS

f_IN= 800kHz, –6dBFS

f_IN= 10kHz, –1dBFS

f_IN= 10kHz, –3dBFS

f_IN= 10kHz, –6dBFS

f_IN= 100kHz, –1dBFS

f_IN= 100kHz, –3dBFS

f_IN= 100kHz, –6dBFS

f_IN= 800kHz, –1dBFS

f_IN= 800kHz, –3dBFS

f_IN= 800kHz, –6dBFS

f_IN= 10kHz, –1dBFS

f_IN= 10kHz, –3dBFS

f_IN= 10kHz, –6dBFS

f_IN= 100kHz, –1dBFS

f_IN= 100kHz, –3dBFS

f_IN= 100kHz, –6dBFS

f_IN= 800kHz, –1dBFS

f_IN= 800kHz, –3dBFS

f_IN= 800kHz, –6dBFS

f_IN= 10kHz, –1dBFS

f_IN= 10kHz, –3dBFS

f_IN= 10kHz, –6dBFS

f_IN= 100kHz, –1dBFS

f_IN= 100kHz, –3dBFS

f_IN= 100kHz, –6dBFS

f_IN= 800kHz, –1dBFS

f_IN= 800kHz, –3dBFS

f_IN= 800kHz, –6dBFS

92

dB

87

84

90

87

91

Signal-to-noise ratio (SNR)

87

84

89

86

91

89

86

–94

–106

–108

–90

–96

–101

–116

–114

–110

89

–92

–93

Total harmonic distortion (THD)

Signal-to-noise + distortion (SINAD)

Spurious-free dynamic range (SFDR)

–90

–92

85

82

90

87

85

82

88

86

91

89

86

95

90

93

107

112

91

90

93

96

103

120

119

114

f₁= 995kHz, –6dBFS

f₂= 1005kHz, –6dBFS

Intermodulation distortion (IMD)

Aperture delay

94

4

dB

ns

3

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 40MHz, external V_REF= +3V, V_CM

=

+1.45V, and R_BIAS= 37kΩ, unless otherwise noted.

ADS1602

PARAMETER

Digital Filter Characteristics

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_CLK

1.1

Passband

0

MHz

dB

(

)

40MHz

Passband ripple

±0.001

f_CLK

1.15

–0.1dB attenuation

–3dB attentuation

MHz

(

)

40MHz

Passband transition

f_CLK

1.23

MHz

(

)

40MHz

f_CLK

38.6

1.4

(

)

Stop band

(

)

MHz

dB

40MHz

Stop band attenuation

75

40MHz

f_CLK

10.4

Group delay

Settling time

μs

(

)

40MHz

f_CLK

20.4

Complete settling

(

)

Static Specifications

Resolution

16

Bits

No missing codes

Input-referred noise

Integral nonlinearity

Differential nonlinearity

Offset error

16

0.5

0.85

LSB, rms

LSB

–1dBFS signal

0.75

0.25

–0.1

LSB

%FSR

ppmFSR/°C

%

Offset error drift

Gain error

0.25⁽¹⁾

Gain error drift

Excluding reference drift

10

ppm/°C

dB

Common-mode rejection

Power-supply rejection

Internal Voltage Reference

V_REF= (VREFP – VREFN)

VREFP

At dc

75

65

dB

REFEN = low

2.75

3.5

0.5

2.3

3

4

3.25

4.3

1.3

2.7

V

VREFN

1

VMID

2.5

50

15

V

V_REFdrift

ppm/°C

ms

Startup time

External Voltage Reference

V_REF= (VREFP – VREFN)

VREFP

REFEN = high

2

3

4

3.25

4.25

1.5

V

3.5

0.5

2.3

VREFN

1

VMID

2.5

2.6

(1) There is a constant gain error of 2.5% in addition to the variable gain error of ±0.25%. Therefore, the gain error is 2.5 ± 0.25%.

4

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 40MHz, external V_REF= +3V, V_CM

=

+1.45V, and R_BIAS= 37kΩ, unless otherwise noted.

ADS1602

TYP

PARAMETER

Clock Input

TEST CONDITIONS

MIN

MAX

UNIT

Frequency (f_CLK

)

40

55

MHz

%

Duty cycle

f_CLK= 40MHz

45

Digital Input/Output

V_IH

0.7 × IOVDD

DGND

IOVDD

V

V_IL

0.3 × IOVDD

V_OH

I_OH= 50μA

I_OL= 50μA

IOVDD – 0.5

V

V_OL

DGND + 0.5

V

Input leakage

DGND < V_DIGIN< IOVDD

±10

μA

Power-Supply Requirements

AVDD

DVDD

IOVDD

4.75

2.7

5.25

3.3

5.25

125

98

V

I_OH= 50μA

REFEN = low

REFEN = high

IOVDD = 3V

2.7

V

110

88

25

8

mA

AVDD current (I_AVDD

)

DVDD current (I_DVDD

)

30

IOVDD current (I_IOVDD

)

10

AVDD = 5V, DVDD = 3V, IOVDD = 3V,

REFEN = high

530

10

610

mW

Power dissipation

PD = low, CLK disabled

Temperature Range

Specified

–40

–60

+85

+105

+150

°C

Operating

Storage

5

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

DEFINITIONS

Intermodulation Distortion (IMD)

Absolute Input Voltage

Absolute input voltage, given in volts, is the voltage of

each analog input (AINN or AINP) with respect to

AGND.

IMD, given in dB, is measured while applying two

input signals of the same magnitude, but with slightly

different frequencies. It is calculated as the difference

between the rms amplitude of the input signal to the

rms amplitude of the peak spurious signal.

Aperture Delay

Aperture delay is the delay between the rising edge

of CLK and the sampling of the input signal.

Offset Error

Offset Error, given in % of FSR, is the output reading

when the differential input is zero.

Common-Mode Input Voltage

Common-mode input voltage (V_CM) is the average

voltage of the analog inputs:

Offset Error Drift

Offset error drift, given in ppm of FSR/°C, is the drift

over temperature of the offset error. The offset error

is specified as the larger of the drift from ambient

(T = +25°C) to the minimum or maximum operating

temperatures.

(AINP + AINN)

2

Differential Input Voltage

Differential input voltage (V_IN) is the voltage

difference between the analog inputs (AINP − AINN).

Signal-to-Noise Ratio (SNR)

SNR, given in dB, is the ratio of the rms value of the

input signal to the sum of all the frequency

components below f_CLK/2 (the Nyquist frequency)

excluding the first six harmonics of the input signal

and the dc component.

Differential Nonlinearity (DNL)

DNL, given in least-significant bits of the output code

(LSB), is the maximum deviation of the output code

step sizes from the ideal value of 1LSB.

Signal-to-Noise and Distortion (SINAD)

Full-Scale Range (FSR)

SINAD, given in dB, is the ratio of the rms value of

the input signal to the sum of all the frequency

components below f_CLK/2 (the Nyquist frequency)

including the harmonics of the input signal but

excluding the dc component.

FSR is the difference between the maximum and

minimum measurable input signals (FSR = 2V_REF).

Gain Error

Gain error, given in %, is the error of the full-scale

input signal with respect to the ideal value.

Spurious-Free Dynamic Range (SFDR)

SFDR, given in dB, is the difference between the rms

amplitude of the input signal to the rms amplitude of

the peak spurious signal.

Gain Error Drift

Gain error drift, given in ppm/°C, is the drift over

temperature of the gain error. The gain error is

specified as the larger of the drift from ambient

(T = +25°C) to the minimum or maximum operating

temperatures.

Total Harmonic Distortion (THD)

THD, given in dB, is the ratio of the sum of the rms

value of the first six harmonics of the input signal to

the rms value of the input signal.

Integral Nonlinearity (INL)

INL, given in least-significant bits of the output code

(LSB), is the maximum deviation of the output codes

from a best fit line.

6

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

PIN ASSIGNMENTS

48 47 46 45 44 43 42 41 40 39 38 37

AGND

1

2

3

4

5

6

7

8

9

36 DGND

35 NC

AVDD

AGND

AINN

34 DVDD

33 DGND

32 FSO

31 FSO

30 DOUT

29 DOUT

28 SCLK

27 SCLK

26 NC

AINP

AGND

AVDD

RBIAS

AGND

TQFP PACKAGE

(TOP VIEW)

ADS1602

AVDD 10

AGND 11

AVDD 12

25 NC

13 14 15 16 17 18 19 20 21 22 23 24

TERMINAL FUNCTIONS

TERMINAL

FUNCTION

DESCRIPTION

NAME

AGND

AVDD

AINN

NO.

1, 3, 6, 9, 11, 39, 41

Analog

Analog ground

2, 7, 10, 12, 42

Analog supply

4

Analog input

Analog

Negative analog input

Positive analog input

AINP

5

RBIAS

REFEN

NC

8

Terminal for external analog bias setting resistor.

Internal reference enable. Internal pull-down resistor of 170kΩ to DGND.

These terminals must be left unconnected.

Pull-up to DVDD with 10kΩ resistor (see Figure 53).

Power-down all circuitry. Internal pull-up resistor of 170kΩ to DGND.

Digital supply

13

Digital input: active low

Do not connect

Digital input

Digital input: active low

Digital

14, 16, 24–26, 35

RPULLUP

PD

15

17

DVDD

DGND

SYNC

OTR

18, 23, 34

19, 22, 33, 36, 38

Digital

Digital ground

20

21

Digital input

Digital output

Digital

Synchronization control input

Indicates analog input signal is out of range.

Serial clock output

SCLK

DOUT

FSO

28

27

Serial clock output, complementary signal.

Data output

30

29

Data output, complementary signal.

Frame synchronization output

32

FSO

31

Frame synchronization output, complementary signal.

Digital I/O supply

IOVDD

CLK

37

40

Digital input

Analog

Clock input

VCAP

VREFN

VMID

VREFP

43

Terminal for external bypass capacitor connection to internal bias voltage.

Negative reference voltage

44, 45

46

Analog

Midpoint voltage

47, 48

Analog

Positive reference voltage

7

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

TIMING DIAGRAMS

t_C

CLK

t_HSC

t_SSC

SYNC

FSO

t_SYPW

t_STL

Figure 1. Initialization Timing

TIMING REQUIREMENTS

For T_A= –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V.

SYMBOL

t_SYPW

t_C

DESCRIPTION

MIN

1

TYP

MAX

UNIT

CLK period

ns

SYNC positive pulse width

Clock period (CLK)

25

t_SSC

Setup time; SYNC rising edge to CLK rising edge

Hold time; CLK rising edge to SYNC falling edge

0.5

CLK period

t_HSC

Settling time of the ADS1602; FSO falling edge to next

FSO rising edge

t_STL

833

CLK periods

t_CPW

CLK

t_CS

t_CPW

SCLK

t_CF

t_FPW

t_DH

FSO

t_DS

BIT

14

BIT

DOUT

MSB

LSB

1

New Data

Figure 2. Data Retrieval Timing

TIMING REQUIREMENTS

For T_A= –40°C to +85°C, DVDD = 2.7V to 3.6V, and IOVDD = 2.7V to 5.25V.

SYMBOL

t_CS

DESCRIPTION

MIN

11.25

6

TYP

MAX

15

UNIT

Rising edge of CLK to rising edge of SCLK

Rising edge of SCLK to rising edge of FSO

CLK positive or negative pulse width

Frame sync output high pulse width

SCLK rising edge to new DOUT valid

SCLK falling edge to DOUT invalid

ns

t_CF

5

ns

t_CPW

t_FPW

t_DS

ns

CLK period

ns

1

5

t_DH

ns

8

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 40MHz, External V_REF= +3V, V_CM= +1.45V, and

R_BIAS= 37kΩ, unless otherwise noted.

SPECTRAL RESPONSE

0

-20

0

-20

f_IN= 10kHz, -1dBFS

f_IN= 10kHz, -6dBFS

SNR = 92dB

THD = -94dB

SFDR = 95dB

SNR = 87dB

THD = -108dB

SFDR = 112dB

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

Frequency (kHz)

Figure 3.

Figure 4.

SPECTRAL RESPONSE

0

-20

0

f_IN= 10kHz, -10dBFS

f_IN= 100kHz, -1dBFS

-20

-40

SNR = 83dB

THD = -105dB

SFDR = 110dB

SNR = 90dB

THD = -90dB

SFDR = 91dB

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

400

600

800

1000

1200

0

400

600

800

1000

1200

Frequency (kHz)

Figure 5.

Figure 6.

SPECTRAL RESPONSE

0

-20

0

-20

f_IN= 100kHz, -6dBFS

f_IN= 100kHz, -10dBFS

SNR = 86dB

THD = -101dB

SFDR = 103dB

SNR = 82dB

THD = -100dB

SFDR = 102dB

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

400

600

800

1000

1200

0

400

600

800

1000

1200

Frequency (kHz)

Figure 7.

Figure 8.

9

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 40MHz, External V_REF= +3V, V_CM= +1.45V, and

R_BIAS= 37kΩ, unless otherwise noted.

SPECTRAL RESPONSE

0

-20

0

-20

f_IN= 504kHz, -1dBFS

f_IN= 504kHz, -6dBFS

SNR = 91dB

THD = -119dB

SFDR = 119dB

SNR = 86dB

THD = -103dB

SFDR = 103dB

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

Frequency (kHz)

Figure 9.

Figure 10.

SPECTRAL RESPONSE

0

-20

0

-20

f_IN= 504kHz, -10dBFS

f_IN= 799kHz, -1dBFS

SNR = 82dB

THD = -96dB

SFDR = 96dB

SNR = 91dB

THD = -116dB

SFDR = 120dB

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

200

400

600

800

1000

1200

200

400

600

800

1200

Frequency (kHz)

Figure 11.

Figure 12.

SPECTRAL RESPONSE

0

-20

0

-20

f_IN= 799kHz, -6dBFS

f_IN= 799kHz, -10dBFS

SNR = 86dB

THD = -110dB

SFDR = 114dB

SNR = 82dB

THD = -107dB

SFDR = 112dB

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

200

400

600

800

1000

1200

200

400

600

800

1200

Frequency (kHz)

Figure 13.

Figure 14.

10

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 40MHz, External V_REF= +3V, V_CM= +1.45V, and

R_BIAS= 37kΩ, unless otherwise noted.

SNR, THD, AND SFDR

vs INPUT SIGNAL AMPLITUDE

140

120

100

80

120

110

100

90

SFDR

THD

SFDR

THD

80

SNR

70

SNR

60

50

40

30

f_IN= 10kHz

f_IN= 50kHz

20

-80

-70

-60

-50

-40

-30

-20

-10

0

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Signal Amplitude, V_IN(dB)

Figure 15.

Figure 16.

SNR, THD, AND SFDR

vs INPUT SIGNAL AMPLITUDE

140

120

100

80

140

120

100

80

SFDR

THD

SFDR

THD

SNR

60

SNR

40

f_IN= 100kHz

f_IN= 500kHz

20

-70

-60

-50

-40

-30

-20

-10

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Signal Amplitude, V_IN(dB)

Figure 17.

Figure 18.

SNR, THD, AND SFDR

vs INPUT SIGNAL AMPLITUDE

SNR vs INPUT FREQUENCY

140

120

100

80

95

V_IN= -1dB

90

85

80

75

70

V_IN= -6dB

SFDR

THD

V_IN= -10dB

60

SNR

40

f_IN= 800kHz

20

-70

-60

-50

-40

-30

-20

-10

10k

100k

1M

Input Signal Amplitude, V_IN(dB)

Input Frequency, f_IN(Hz)

Figure 19.

Figure 20.

11

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 40MHz, External V_REF= +3V, V_CM= +1.45V, and

R_BIAS= 37kΩ, unless otherwise noted.

THD vs INPUT FREQUENCY

SFDR vs INPUT FREQUENCY

130

120

110

100

90

-80

-85

V_IN= -10dB

-90

V_IN= -10dB

-95

V_IN= -6dB

-100

-105

-110

-115

-120

V_IN= -1dB

V_IN= -6dB

80

V_IN= -1dB

70

10k

100k

1M

10k

100k

1M

Input Frequency, f_IN(Hz)

Figure 21.

Figure 22.

SNR vs INPUT COMMON-MODE VOLTAGE

THD vs INPUT COMMON-MODE VOLTAGE

93

92

91

90

89

88

87

86

85

-70

-80

f_IN= 10kHz, V_IN= -1dB

f_IN= 100kHz, V_IN= -1dB

f_IN= 10kHz, V_IN= -1dB

-90

-100

-110

f_IN= 100kHz, V_IN= -6dB

f_IN= 10kHz, V_IN= -6dB

f_IN= 100kHz, V_IN= -6dB

1.4 1.8

f_IN= 10kHz, V_IN= -6dB

2.6 3.4

1

1.4

1.8

2.2

2.6

3

3.4

1

2.2

3

Input Common-Mode Voltage, V_CM(V)

Figure 23.

Figure 24.

SFDR vs INPUT COMMON-MODE VOLTAGE

f_IN= 10kHz, V_IN= -6dB

OFFSET DRIFT OVER TIME

110

105

100

95

3

2

f_IN= 100kHz, V_IN= -6dB

1

f_IN= 10kHz

0

V_IN= -1dB

90

-1

-2

-3

85

f_IN= 100kHz, V_IN= -1dB

80

0

100 200 300 400 500 600 700 800 900 1000

Time Interval (s)

1

1.4

1.8

2.2

2.6

3

3.4

Input Common-Mode Voltage, V_CM(V)

Figure 25.

Figure 26.

12

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 40MHz, External V_REF= +3V, V_CM= +1.45V, and

R_BIAS= 37kΩ, unless otherwise noted.

SNR vs CLOCK FREQUENCY

THD vs CLOCK FREQUENCY

110

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

R_BIAS= 37kW

V_IN= -6dBFS, f_IN= 10kHz

R_BIAS= 30kW

R_BIAS= 37kW

R_BIAS

= 60kW

= 30kW

R_BIAS= 267kW

R_BIAS

R_BIAS= 210kW

= 60kW

R_BIAS

R_BIAS= 210kW

= 140kW = 100kW

= 100kW

R_BIAS= 140kW

R_BIAS= 267kW

V_IN= -6dBFS, f_IN= 10kHz

5

10

15

20

25

30

35

40

45

50

5

10

15

20

25

30

35

40

45

50

Clock Frequency, f_CLK(MHz)

Figure 27.

Figure 28.

SFDR vs CLOCK FREQUENCY

NOISE vs DC INPUT VOLTAGE

110

100

90

80

70

60

50

40

30

20

1000

100

10

R_BIAS= 37kW

R_BIAS

= 60kW

R_BIAS

R_BIAS= 267kW

R_BIAS= 210kW

= 30kW

R_BIAS

= 100kW

R_BIAS= 140kW

1

V_IN= -6dBFS, f_IN= 10kHz

0.1

-3

-2

-1

0

1

2

3

5

10

15

20

25

30

35

40

45

50

Clock Frequency, f_CLK(MHz)

Input DC Voltage (V)

Figure 29.

Figure 30.

NOISE HISTOGRAM

POWER-SUPPLY CURRENT vs TEMPERATURE

120

100

80

60

40

20

0

1540

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

V_IN= 0

I_AVDD(REFEN = low)

I_AVDD(REFEN = high)

I_DVDD+ I_IOVDD

R_BIAS= 37kW, f_CLK= 40MHz

-4

-3

-2

-1

0

1

2

3

4

-40

-15

10

35

60

85

Output Code (LSB)

Temperature (°C)

Figure 31.

Figure 32.

13

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at T_A= +25°C, AVDD = 5V, DVDD = IOVDD = 3V, f_CLK= 40MHz, External V_REF= +3V, V_CM= +1.45V, and

R_BIAS= 37kΩ, unless otherwise noted.

SUPPLY CURRENT vs CLOCK FREQUENCY

ANALOG SUPPLY CURRENT vs R_BIAS

140

120

100

80

130

110

90

V_IN= -6dBFS

f_IN= 10kHz

I_AVDD(REFEN = low)

R_BIAS= 37kW

f_CLK= 40MHz

70

I_AVDD(REFEN = high)

60

I_AVDD(REFEN = low)

I_AVDD(REFEN = high)

50

40

I_IOVDD+ I_DVDD

30

20

0

10

0

5

10

15

20

25

30

35

40

0

50

100

150

200

250

300

Clock Frequency, f_CLK(MHz)

R_BIAS(kW)

Figure 33.

Figure 34.

SNR vs TEMPERATURE

THD vs TEMPERATURE

100

-80

-85

95

90

85

80

75

70

V_IN= -1dB

V_IN= -6dB

V_IN= -1dB

V_IN= -6dB

-90

V_IN= -10dB

-95

V_IN= -10dB

-100

-105

f_IN= 100kHz

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

Figure 35.

Figure 36.

SFDR vs TEMPERATURE

120

115

110

105

100

95

V_IN= -10dB

V_IN= -6dB

90

V_IN= -1dB

85

80

-40

-15

10

35

60

85

Temperature (°C)

Figure 37.

14

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

OVERVIEW

The ADS1602 is a high-performance delta-sigma

(ΔΣ) analog-to-digital converter (ADC). The modulator

uses an inherently stable 2-1-1 multi-stage

architecture incorporating proprietary circuitry that

allows for very linear high-speed operation. The

modulator samples the input signal at 40MSPS (when

f_CLK= 40MHz). A low-ripple linear phase digital filter

decimates the modulator output by 16 to provide high

resolution 16-bit output data.

The ADS1602 supports a very wide range of input

signals. For V_REF= 3V, the full-scale input voltages

are ±3V. Having such a wide input range makes

out-of-range signals unlikely. However, should an

out-of-range signal occur, the digital output OTR goes

high.

The analog inputs must be driven with a differential

signal to achieve optimum performance. For the input

signal:

Conceptually, the modulator and digital filter measure

the differential input signal, V_IN= (AINP – AINN),

AINP + AINN

2

V_CM

=

against

the

scaled

differential

reference,

V_REF= (VREFP – VREFN), as shown in Figure 38.

The voltage reference can either be generated

internally or supplied externally. A three-wire serial

interface, designed for direct connection to DSPs,

outputs the data. A separate power supply for the I/O

allows flexibility for interfacing to different logic

families. Out-of-range conditions are indicated with a

dedicated digital output pin. Analog power dissipation

is controlled using an external resistor. This control

allows reduced dissipation when operating at slower

speeds. When not in use, power consumption can be

dramatically reduced by setting the PD pin low to

enter Power-Down mode.

the recommended common-mode voltage is 1.5V. In

addition to the differential and common-mode input

voltages, the absolute input voltage is also important.

This is the voltage on either input (AINP or AINN)

with respect to AGND. The range for this voltage is:

–0.1V < (AINN or AINP) < 4.6V

If either input is taken below –0.1V, ESD protection

diodes on the inputs will turn on. Exceeding 4.6V on

either input results in degradation in the linearity

performance. ESD protection diodes will also turn on

if the inputs are taken above AVDD (+5V).

The recommended absolute input voltage is:

ANALOG INPUTS (AINP, AINN)

–0.1V < (AINN or AINP) < 4.2V

The ADS1602 measures the differential signal,

Keeping the inputs within this range provides for

optimum performance.

V_IN

= (AINP – AINN), against the differential

reference, V_REF= (VREFP – VREFN). The most

positive measurable differential input is V_REF, which

produces the most positive digital output code of

7FFFh. Likewise, the most negative measurable

differential input is –V_REF, which produces the most

negative digital output code of 8000h.

VREFP VREFN

IOVDD

CLK

S

V_REF

FSO

SCLK

V_IN

AINP

SD

Digital

Filter

Serial

Interface

S

Modulator

AINN

SCLK

DOUT

Figure 38. Conceptual Block Diagram

15

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

INPUT CIRCUITRY

drivers close to the inputs and use good capacitor

bypass techniques on the supplies, such as a smaller

high-quality ceramic capacitor in parallel with a larger

capacitor. Keep the resistances used in the driver

circuits low—thermal noise in the driver circuits

degrades the overall noise performance. When the

signal can be ac-coupled to the ADS1602 inputs, a

simple RC filter can set the input common-mode

The ADS1602 uses switched-capacitor circuitry to

measure the input voltage. Internal capacitors are

charged by the inputs and then discharged internally

with this cycle repeating at the frequency of CLK.

Figure 39 shows a conceptual diagram of these

circuits. Switches S₂represent the net effect of the

modulator circuitry in discharging the sampling

capacitors; the actual implementation is different. The

timing for switches S₁and S₂is shown in Figure 40.

voltage.

The

ADS1602

is

a

high-speed,

high-performance ADC. Special care must be taken

when selecting the test equipment and setup used

with this device. Pay particular attention to the signal

sources to ensure they do not limit performance when

measuring the ADS1602.

ADS1602

S₁

AINP

S₂

392W

10pF

8pF

40pF

392W

V_IN

2

-

VMID

0.01mF

S₁

49.9W

AINP

AINN

OPA2822

392W

(2)

(1)

V_CM

S₂

100pF

10pF

8pF

1kW

1mF

(2)

392W

(1)

V_CM

100pF⁽³⁾

ADS1602

VMID

AGND

(2)

40pF

392W

V_IN

1kW

2

0.01mF

49.9W

Figure 39. Conceptual Diagram of Internal

Circuitry Connected to the Analog Inputs

AINN

OPA2822

392W

(2)

(1)

V_CM

100pF

1mF

AGND

t_SAMPLE= 1/f_CLK

(1) Recommended V_CM= 1.5V.

On

Off

S₁

(2) Optional ac-coupling circuit provides common-mode input

voltage.

(3) Increase to 390pF when f_IN≤ 100kHz for improved SNR and

THD.

On

Off

S₂

Figure 41. Recommended Driver Circuit Using

the OPA2822

Figure 40. Timing for the Switches in Figure 39

DRIVING THE INPUTS

22pF

24.9W

The external circuits driving the ADS1602 inputs must

be able to handle the load presented by the switching

capacitors within the ADS1602. The input switches S₁

in Figure 39 are closed for approximately one-half of

the sampling period, t_SAMPLE, allowing only ≉ 11ns for

the internal capacitors to be charged by the inputs

when f_CLK= 40MHz.

AINP

392W

100pF

392W

-V_IN

V_CM

THS4503

ADS1602

+V_IN

392W

24.9W

AINN

Figure 41 and Figure 42 show the recommended

circuits when using single-ended or differential op

amps, respectively. The analog inputs must be driven

differentially to achieve optimum performance. The

external capacitors, between the inputs and from

each input to AGND, improve linearity and should be

placed as close to the pins as possible. Place the

100pF

22pF

Figure 42. Recommended Driver Circuit Using

the THS4503 Differential Amplifier

16

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

REFERENCE INPUTS (VREFN, VREFP, VMID)

EXTERNAL REFERENCE (REFEN = HIGH)

The ADS1602 can operate from an internal or

external voltage reference. In either case, the

reference voltage V_REFis set by the differential

To use an external reference, set the REFEN pin

high. This deactivates the internal generators for

VREFP,

VREFN,

and

VMID,

and

saves

voltage between VREFN and VREFP: V_REF

=

approximately 25mA of current on the analog supply

(AVDD). The voltages applied to these pins must be

within the values specified in the Electrical

Characteristics table. Typically, VREFP = 4V, VMID =

2.5V, and VREFN = 1V. The external circuitry must

be capable of providing both a dc and a transient

current. Figure 44 shows a simplified diagram of the

internal circuitry of the reference when the internal

reference is disabled. As with the input circuitry,

switches S₁and S₂open and close as shown by the

timing in Figure 40.

(VREFP – VREFN). VREFP and VREFN each use

two pins, which should be shorted together. VMID

equals approximately 2.5V and is used by the

modulator. VCAP connects to an internal node and

must also be bypassed with an external capacitor.

INTERNAL REFERENCE (REFEN = LOW)

To use the internal reference, set the REFEN pin low.

This activates the internal circuitry that generates the

reference voltages. The internal reference voltages

are applied to the pins. Good bypassing of the

reference pins is critical to achieve optimum

performance and is done by placing the bypass

capacitors as close to the pins as possible. Figure 43

shows the recommended bypass capacitor values.

Use high-quality ceramic capacitors for the smaller

values. Avoid loading the internal reference with

external circuitry. If the ADS1602 internal reference is

to be used by other circuitry, buffer the reference

voltages to prevent directly loading the reference

pins.

ADS1602

S₁

VREFP

S₂

300W

50pF

VREFN

S₁

Figure 44. Conceptual Internal Circuitry for the

Reference When REFEN = High

ADS1602

Figure 45 shows the recommended circuitry for

driving these reference inputs. Keep the resistances

used in the buffer circuits low to prevent excessive

thermal noise from degrading performance. Layout of

these circuits is critical; be sure to follow good

high-speed layout practices. Place the buffers, and

especially the bypass capacitors, as close to the pins

as possible. VCAP is unaffected by the setting on

REFEN and must be bypassed when using the

internal or an external reference.

VREFP

10mF

0.1mF

VMID

0.1mF

10mF

0.1mF

VREFN

10mF

0.1mF

VCAP

AGND

Figure 43. Reference Bypassing When Using the

Internal Reference

17

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

Table 1. Maximum Allowable Clock Source Jitter

for Different Input Signal Frequencies and

Amplitude

392W

0.001mF

ADS1602

INPUT SIGNAL

MAXIMUM

FREQUENCY AMPLITUDE

MAXIMUM

MAXIMUM ALLOWABLE

CLOCK SOURCE JITTER

VREFP

OPA2822

10mF

4V

2.5V

1V

0.1mF

1MHz

–2dB

–20dB

–2dB

3.8ps

28ps

7.6ps

57ps

38ps

285ps

392W

0.1mF

0.001mF

500kHz

100kHz

–20dB

–2dB

VMID

OPA2822

10mF

0.1mF

–20dB

392W

DATA FORMAT

0.001mF

The 16-bit output data are in binary two’s

complement format as shown in Table 2. When the

input is positive out-of-range, exceeding the positive

full-scale value of V_REF, the output clips to all 7FFFh

and the OTR output goes high.

VREFN

OPA2822

10mF

0.1mF

VCAP

Likewise, when the input is negative out-of-range by

going below the negative full-scale value of –V_REF

,

AGND

the output clips to 8000h and the OTR output goes

high. The OTR remains high while the input signal is

out-of-range.

Figure 45. Recommended Buffer Circuit When

Using an External Reference

Table 2. Output Code versus Input Signal

INPUT SIGNAL (INP –

IDEAL OUTPUT

CODE⁽¹⁾

CLOCK INPUT (CLK)

INN)

OTR

The ADS1602 requires an external clock signal to be

applied to the CLK input pin. The sampling of the

modulator is controlled by this clock signal. As with

any high-speed data converter, a high quality clock is

essential for optimum performance. Crystal clock

oscillators are the recommended CLK source; other

sources, such as frequency synthesizers, are usually

inadequate. Make sure to avoid excess ringing on the

CLK input; keeping the trace as short as possible

helps.

≥ +V_REF(> 0dB)

–V_REF(0dB)

7FFFh

1

0

+V_REF

0001h

0000h

FFFFh

0

15

2

- 1

0

-V_REF

15

2

- 1

15

2

15

-V_REF

(

)

8000h

0

1

Measuring high-frequency, large amplitude signals

requires tight control of clock jitter. The uncertainty

during sampling of the input from clock jitter limits the

maximum achievable SNR. This effect becomes more

pronounced with higher frequency and larger

magnitude inputs. Fortunately, the ADS1602

oversampling topology reduces clock jitter sensitivity

over that of Nyquist rate converters such as pipeline

and successive approximation converters by a factor

of √16.

2

- 1

15

2

15

-V_REF

(

)

2

- 1

(1) Excludes effects of noise, INL, offset, and gain errors.

OUT-OF-RANGE INDICATION (OTR)

If the output code exceeds the positive or negative

full-scale, the out-of-range digital output OTR will go

high on the falling edge of SCLK. When the output

code returns within the full-scale range, OTR returns

low on the falling edge of SCLK.

In order to not limit the ADS1602 SNR performance,

keep the jitter on the clock source below the values

shown in Table 1. When measuring lower frequency

and lower amplitude inputs, more CLK jitter can be

tolerated. In determining the allowable clock source

jitter, select the worst-case input (highest frequency,

largest amplitude) that will be seen in the application.

18

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

DATA RETRIEVAL

STEP RESPONSE

Data retrieval is controlled through a simple serial

interface. The interface operates in a master fashion

by outputting both a frame sync indicator (FSO) and a

serial clock (SCLK). Complementary outputs are

provided for the frame sync output (FSO), serial clock

(SCLK), and data output (DOUT). When not needed,

leave the complementary outputs unconnected.

Figure 47 plots the normalized step response for an

input applied at t = 0. The x-axis units of time are

conversion cycles. It takes 51 cycles to fully settle; for

f_CLK= 40MHz, this corresponds to 20.4μs.

1.2

1.0

0.8

0.6

0.4

0.2

0

INITIALIZING THE ADS1602

After the power supplies have stabilized, you must

initialize the ADS1602 by issuing a SYNC pulse as

shown in Figure 1. This operation needs only to be

done once after power-up and does not need to be

performed when exiting the Power-Down mode. Note

that the ADS1602 silicon was revised in June 2006.

The digital interface timing specifications were

modified slightly from the previous revision. This data

sheet reflects behavior of the latest revision. Contact

the factory for more information on the previous

revision.

-0.2

0

10

20

30

40

50

Time (Conversion Cycles)

Figure 47. Step Response

SYNCHRONIZING MULTIPLE ADS1602s

The SYNC input can be used to synchronize multiple

ADS1602s to provide simultaneous sampling. All

devices to be synchronized must use a common CLK

input. With the CLK inputs running, pulse SYNC on

the falling edge of CLK, as shown in Figure 46.

Afterwards, the converters will be converting

synchronously with the FSO outputs updating

simultaneously. After synchronization, FSO is held

low until the digital filter has fully settled.

FREQUENCY RESPONSE

The linear phase FIR digital filter sets the overall

frequency response. Figure 48 shows the frequency

response from dc to 20MHz for f_CLK= 40MHz. The

frequency response of the ADS1602 filter scales

directly with CLK frequency. For example, if the CLK

frequency is decreased by half (to 20MHz), the

values on the x-axis in Figure 48 would need to be

scaled by half, with the span becoming dc to 10MHz.

ADS1602₁

Figure 49 shows the passband ripple from dc to

1200kHz (f_CLK= 40MHz). Figure 50 shows a closer

view of the passband transition by plotting the

response from 900kHz to 1300kHz (f_CLK= 40MHz).

FSO₁

SYNC

CLK

SYNC

CLK

FSO

DOUT₁

DOUT

20

ADS1602₂

f_CLK= 40MHz

0

-20

FSO₂

SYNC

CLK

FSO

DOUT₂

DOUT

-40

-60

-80

CLK

-100

-120

-140

SYNC

t_STL

0

2

4

6

8

10 12

14

16

18

20

FSO₁

FSO₂

Frequency (MHz)

Figure 48. Frequency Response

Figure 46. Synchronizing Multiple Converters

19

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

0.001

0.0008

0.0006

0.0004

0.0002

0

20

0

f_CLK= 40MHz

-20

-40

-60

-80

-100

-120

-140

-0.0002

-0.0004

-0.0006

-0.0008

f_CLK= 40MHz

800 1000

-0.001

0

200

400

600

1200

0

20

40

60

80

100

120

Frequency (kHz)

Frequency (MHz)

Figure 49. Passband Ripple

Figure 51. Frequency Response Out to 120MHz

ANALOG POWER DISSIPATION

0.5

0

f_CLK= 40MHz

An external resistor connected between the RBIAS

pin and the analog ground sets the analog current

level, as shown in Figure 52. The current is inversely

proportional to the resistor value. Table 3 shows the

recommended values of R_BIASfor different CLK

frequencies. Notice that the analog current can be

reduced when using a slower frequency CLK input

because the modulator has more time to settle. Avoid

adding any capacitance in parallel to R_BIASbecause

this interferes with the internal circuitry used to set

the biasing. Please note that changing the R_BIAS

resistor value changes all internally-generated bias

voltages, including the internal reference; therefore,

the recommendations in Table 3 are only for when

using an external reference.

-0.5

-1

-1.5

-2

-2.5

-3

-3.5

800

900

1000

1100

1200

1300

Frequency (kHz)

Figure 50. Passband Transition

ADS1602

ANTIALIAS REQUIREMENTS

Higher frequency, out-of-band signals must be

eliminated to prevent aliasing with ADCs. Fortunately,

the ADS1602 on-chip digital filter greatly simplifies

this filtering requirement. Figure 51 shows the

ADS1602 response out to 120MHz (f_CLK= 40MHz).

Since the stop band extends out to 38.6MHz, the

antialias filter in front of the ADS1602 only needs to

be designed to remove higher frequency signals than

this, which can usually be accomplished with a simple

RC circuit on the input driver.

RBIAS

R_BIAS

AGND

Figure 52. External Resistor Used to Set Analog

Power Dissipation

Table 3. Recommended R_BIASResistor Values for

Different CLK Frequencies

TYPICAL POWER

DATA

RATE

DISSIPATION

WITH REFEN HIGH

f_CLK

R_BIAS

140kΩ

100kΩ

60kΩ

16MHz

24MHz

32MHz

40MHz

1MSPS

1.5MSPS

2MSPS

200mW

270mW

390mW

530mW

2.5MSPS

37kΩ

20

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

POWER DOWN (PD)

POWER SUPPLIES

When not in use, the ADS1602 can be powered down

by taking the PD pin low. All circuitry is shut down,

including the voltage reference. To minimize the

digital current during power down, stop the clock

signal supplied to the CLK input. There is an internal

pull-up resistor of 170kΩ on the PD pin, but it is

recommended that this pin be connected to IOVDD if

not used. Make sure to allow time for the reference to

start up after exiting power-down mode. The internal

reference typically requires 15ms. After the reference

has stabilized, allow at least 100 conversions for the

modulator and digital filter to settle before retrieving

data.

Three supplies are used on the ADS1602: analog

(AVDD), digital (DVDD), and digital I/O (IOVDD).

Each supply must be suitably bypassed to achieve

the best performance. It is recommended that a 1μF

and 0.1μF ceramic capacitor be placed as close to

each supply pin as possible. Connect each supply-pin

bypass capacitor to the associated ground, as shown

in Figure 53. Each main supply bus should also be

bypassed with a bank of capacitors from 47μF to

0.1μF, as shown. The I/O and digital supplies (IOVDD

and DVDD) can be connected together when using

the same voltage. In this case, only one bank of 47μF

to 0.1μF capacitors is needed on the main supply

bus, though each supply pin must still be bypassed

with a 1μF and 0.1μF ceramic capacitor.

DVDD

47mF

4.7mF

1mF

0.1mF

IOVDD

AVDD

4.7mF

0.1mF

C_P

42

41

55

38

37

34

33

1

DGND 36

AGND

AVDD

C_P

2

If using separate analog and

digital ground planes, connect

together on the ADS1602 PCB.

3

6

AGND

C_P

AVDD

AGND

7

9

ADS1602

DGND

AGND

C_P

AVDD

AGND

10

11

C_P

12

AVDD

15

18

19

22

23

C_P

10kW

NOTE: C_P= 1µF || 0.1µF.

Figure 53. Recommended Power-Supply Bypassing

21

ADS1602

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

www.ti.com

LAYOUT ISSUES AND COMPONENT

SELECTION

The McBSP provides a host of functions including:

•

Full-duplex communication

Double-buffered data registers

Independent framing and clocking for reception

and transmission of data

The ADS1602 is a very high-speed, high-resolution

data converter. In order to achieve maximum

performance, the user must give very careful

consideration to both the layout of the printed circuit

board (PCB) in addition to the routing of the traces.

Capacitors that are critical to achieve the best

performance from the device should be placed as

close to the pins of the device as possible. These

include capacitors related to the analog inputs, the

reference, and the power supplies.

The sequence begins with a one-time synchronization

of the serial port by the microprocessor. The

ADS1602 recognizes the SYNC signal if it is high for

at least one CLK period. Transfers are initiated by the

ADS1602 after the SYNC signal is de-asserted by the

microprocessor.

The FSO signal from the ADS1602 indicates that

data is available to be read, and is connected to the

frame sync receive (FSR) pin of the DSP. The clock

receiver (CLKR) is derived directly from the ADS1602

For critical capacitors, it is recommended that Class II

dielectrics such as Z5U be avoided. These dielectrics

have

a narrow operating temperature, a large

tolerance on the capacitance, and lose up to 20% of

the rated capacitance over 10,000 hours. Rather,

select capacitors with a Class I dielectric. C0G (also

known as NP0), for example, has a tight tolerance

less than ±30ppm/°C and is very stable over time.

Should Class II capacitors be chosen because of the

size constraints, select an X7R or X5R dielectric to

minimize the variations of the capacitor’s critical

characteristics.

serial

clock

output

to

ensure

continued

synchronization of data with the clock.

ADS1602

FSO

TMS320

FSR

CLKR

DR

SCLK

DOUT

SYNC

The resistors used in the circuits to drive the input

and reference should be kept as low as possible to

prevent excess thermal noise from degrading the

system performance.

FSX

The digital outputs from the device should always be

buffered. This has a number of benefits: it reduces

the loading of the internal digital buffers, which

decreases noise generated within the device, and it

also reduces device power consumption.

Figure 54. ADS1602—TMS320 Interface

Connection

An evaluation module (EVM) is available from Texas

Instruments. The module consists of the ADS1602

and supporting circuits, allowing users to quickly

assess the performance and characteristics of the

ADS1602. The EVM easily connects to various

microcontrollers and DSP systems. For more details,

or to download a copy of the ADS1602EVM User’s

Guide, visit the Texas Instruments web site at

www.ti.com.

APPLICATIONS INFORMATION

Interfacing the ADS1602 to the TMS320 DSP

family

Since the ADS1602 communicates with the host via a

serial interface, the most suitable method to connect

to any of the TMS320 DSPs is via the multi-channel

buffered serial port (McBSP). A typical connection to

the TMS320 DSP is shown in Figure 54.

22

ADS1602

www.ti.com

SBAS341E –DECEMBER 2004–REVISED OCTOBER 2011

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (November 2010) to Revision E

Page

•

Added footnote to Electrical Characteristics table ................................................................................................................ 4

Changes from Revision C (September 2010) to Revision D

Page

•

Changed t_Cminimum specification in Timing Requirements table for Figure 1 ................................................................... 8

Changed t_CPWminimum specification in Timing Requirements table for Figure 2 ............................................................... 8

Changed t_DHminimum specification in Timing Requirements table for Figure 2 .................................................................. 8

23

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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型号：	ADS1602IPFBR
厂家：	TEXAS INSTRUMENTS
描述：	16 位 2.5MSPS 模数转换器 \| PFB \| 48 \| -40 to 85 转换器模数转换器
文件：	总30页 (文件大小：898K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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