ADS9110IRGET [TI]
具有增强型串行外设接口 (SPI) 的 18 位、2MSPS、单通道 SAR ADC | RGE | 24 | -40 to 85;
| 型号： | ADS9110IRGET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有增强型串行外设接口 (SPI) 的 18 位、2MSPS、单通道 SAR ADC | RGE | 24 | -40 to 85 |
| 文件： | 总64页 (文件大小：2805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS9110
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
ADS9110 18 位、2MSPS、15mW SAR ADC，具有 multiSPI™ 接口
1 特性
3 说明
1
•
采样率：2MSPS
无延迟输出
ADS9110 是一款 18 位、2MSPS、逐次逼近寄存器
(SAR) 模数转换器 (ADC)，在典型工作条件下具有
±0.5 LSB INL 和 100dB SNR 规范值。 高吞吐量使得
开发者能够对输入信号进行过采样，从而提高测量的动
态范围和精度。
•
•
出色的直流和交流性能：
–
积分非线性 (INL)：±0.5 最低有效位 (LSB)（典
型值），±1.5 LSB（最大值）
–
微分非线性 (DNL)：±0.75 LSB（最大值），18
位无丢码 (NMC)
该器件支持单极全差分模拟输入信号，并采用 2.5V 至
5V 的外部基准电压，能够提供宽输入选择范围，无需
额外进行输入调节。
–
–
信噪比 (SNR)：100dB
总谐波失真 (THD)：-118dB
该器件以 2MSPS 全吞吐量运行时的功耗仅为
15mW。 吞吐量较低时，可灵活使用低功耗模式
（NAP 和 PD）来降低功耗。
•
•
宽输入范围：
–
–
单极差分输入范围：±VREF
VREF 输入范围：2.5V 至 5V，
与 AVDD 无关
集成的 multiSPI 串行接口向后兼容传统 SPI™ 协议。
此外，该器件的可配置功能还能够简化电路板布局、时
序和固件，并且以低时钟速度运行时能够获得高吞吐
量，因此可轻松连接各种微控制器、数字信号处理器
(DSP) 以及现场可编程门阵列 (FPGA)。
低功耗：
–
–
–
2MSPS 时为 9mW（仅限 AVDD）
2MSPS 时为 15mW（总功耗）
灵活的低功耗模式，可根据吞吐量调节功率
•
•
•
multiSPI：增强型串行接口
该器件采用节省空间的 4mm × 4mm VQFN 封装，支
持符合 JESD8-7A 标准的 I/O 和标准工业温度范围。
符合 JESD8-7A 标准的数字 I/O（1.8V DVDD 时）
在 -40°C 至 +85°C 的工业温度范围内完全额定运
行
器件信息
•
小型封装：4mm × 4mm 超薄四方扁平无引线
(VQFN) 封装
部件号
ADS9110
封装
VQFN (24)
封装尺寸（标称值）
4.00mm x 4.00mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
•
•
•
测试和测量
医疗成像
高精度、高速工业领域
典型应用图以及积分非线性度与代码间的关系图
DVDD
AVDD
REFP
REFM
ADS9110
CONVST
CS
multiSPITM
Serial
AIN_P
VIN+
SCLK
+
SPI
Mode
multiSPITM
Mode
OPA625
Interface
SDI
18-Bit SAR ADC,
2 MSPS
VBIAS
SDO œ 0
SDO œ 1
SDO œ 2
SDO œ 3
RVS
4X
DDR
OPA625
SDO
+
VIN-
AIN_M
AGND
DGND
RST
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS629
ADS9110
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
www.ti.com.cn
目录
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 22
7.5 Programming........................................................... 24
7.6 Register Maps......................................................... 44
Application and Implementation ........................ 47
8.1 Application Information............................................ 47
8.2 Typical Application .................................................. 50
Power-Supply Recommendations...................... 52
9.1 Power-Supply Decoupling....................................... 52
9.2 Power Saving.......................................................... 52
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements: Conversion Cycle.................. 7
8
9
10 Layout................................................................... 54
10.1 Layout Guidelines ................................................. 54
10.2 Layout Example .................................................... 55
11 器件和文档支持 ..................................................... 56
11.1 文档支持................................................................ 56
11.2 社区资源................................................................ 56
11.3 商标....................................................................... 56
11.4 静电放电警告......................................................... 56
11.5 Glossary................................................................ 56
12 机械封装和可订购信息 .......................................... 56
6.7 Timing Requirements: Asynchronous Reset, NAP,
and PD....................................................................... 7
6.8 Timing Requirements: SPI-Compatible Serial
Interface ..................................................................... 7
6.9 Timing Requirements: Source-Synchronous Serial
Interface (External Clock) .......................................... 8
6.10 Timing Requirements: Source-Synchronous Serial
Interface (Internal Clock)............................................ 8
6.11 Typical Characteristics.......................................... 12
7
Detailed Description ............................................ 17
4 修订历史记录
Changes from Original (October 2015) to Revision A
Page
•
已发布为量产数据................................................................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
ADS9110
www.ti.com.cn
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
5 Pin Configuration and Functions
RGE Package
VQFN-24
Top View
1
18
17
16
15
14
13
CONVST
SDO-2
SDO-3
DVDD
GND
2
RST
3
NC
Thermal
Pad
4
REFM
5
REFP
AVDD
AVDD
6
NC
Pin Functions
PIN
NAME
AINM
NO.
10
FUNCTION
Analog input
Analog input
Power supply
DESCRIPTION
Negative analog input
AINP
9
Positive analog input
AVDD
13, 14
Analog power supply for the device
Conversion start input pin for the device.
A CONVST rising edge brings the device from ACQ state to CNV state.
CONVST
1
Digital input
Chip-select input pin for the device; active low
The device takes control of the data bus when CS is low.
The SDO-x pins go to tri-state when CS is high.
CS
24
Digital input
DVDD
GND
NC
16
11, 15
3, 6, 12
4, 8
Power supply
Power supply
No connection
Analog input
Analog input
Interface supply
Ground
These pins must be left floating with no external connection
Reference ground potential
Reference voltage input
REFM
REFP
5, 7
Asynchronous reset input pin for the device.
A low pulse on the RST pin resets the device and all register bits return to their default state.
RST
2
Digital input
Multi-function output pin for the device.
RVS
21
Digital output
With CS held high, RVS reflects the status of the internal ADCST signal.
With CS low, the status of RVS depends on the output protocol selection.
Clock input pin for the serial interface.
All system-synchronous data transfer protocols are timed with respect to the SCLK signal.
SCLK
SDI
23
22
Digital input
Digital input
Serial data input pin for the device.
This pin is used to feed the data or command into the device.
SDO-0
20
19
18
17
Digital output
Digital output
Digital output
Digital output
Supply
Serial communication: data output 0
SDO-1
Serial communication: data output 1
SDO-2
Serial communication: data output 2
SDO-3
Serial communication: data output 3
Thermal pad
Exposed thermal pad; connecting this pin to GND is recommended
Copyright © 2015, Texas Instruments Incorporated
3
ADS9110
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.1
–0.3
–0.3
–0.3
–40
MAX
2.1
UNIT
V
AVDD to GND
DVDD to GND
2.1
V
REFP to REFM
5.5
V
REFM to GND
0.1
V
Analog (AINP, AINM) to GND
Digital input (RST, CONVST, CS, SCLK, SDI) to GND
Digital output (RVS, SDO-0, SDO-1, SDO-2, SDO-3) to GND
Operating temperature, TA
Storage temperature, Tstg
REFP + 0.3
DVDD + 0.3
DVDD + 0.3
85
V
V
V
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
1.8
1.8
5
MAX
UNIT
AVDD
DVDD
REFP
Analog supply voltage
Digital supply voltage
Positive reference
V
V
V
6.4 Thermal Information
ADS9110
THERMAL METRIC(1)
RGE (VQFN)
24 PINS
31.9
UNITS
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
29.9
8.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
8.9
RθJC(bot)
2.0
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
ADS9110
www.ti.com.cn
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
6.5 Electrical Characteristics
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C.
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Full-scale input range
(AINP – AINM)(1)
FSR
VIN
–VREF
–0.1
VREF
V
V
V
Absolute input voltage
(AINP and AINM to REFGND)
VREF + 0.1
Common-mode voltage range
(AINP + AINM) / 2
VCM
(VREF / 2) – 0.1 VREF / 2 (VREF / 2) + 0.1
In sample mode
60
4
CIN
IIL
Input capacitance
pF
µA
In hold mode
Input leakage current
±1
VOLTAGE REFERENCE INPUT
VREF Reference input voltage range
2.5
5
V
Average current, VREF = 5 V,
2-kHz, full-scale input,
throughput = 2 MSPS
IREF
Reference input current
1.25
18
mA
DC ACCURACY
Resolution
Bits
Bits
1.5 LSB(3)
5.7 ppm
0.75 LSB(3)
NMC
No missing codes
18
–1.5
–5.7
–0.75
–1
In LSBs
In ppm
±0.5(2)
±2
±0.4(2)
±0.05(2)
1
INL
Integral nonlinearity
DNL
E(IO)
Differential nonlinearity
Input offset error
1
mV
μV/°C
%FS
dVOS/dT Input offset thermal drift
GE
Gain error
–0.01 ±0.005(2)
0.01
GE/dT
Gain error thermal drift
Transition noise
0.25
0.9
80
ppm/°C
LSB(3)
dB
CMRR
Common-mode rejection ratio
At dc to 20 kHz
AC ACCURACY(4)
fIN = 2 kHz
98
99.9
95.4
89
SINAD
SNR
Signal-to-noise + distortion
fIN = 100 kHz
fIN = 500 kHz
fIN = 2 kHz
dB
dB
dB
dB
98.1
100
Signal-to-noise ratio
fIN = 100 kHz
fIN = 500 kHz
fIN = 2 kHz
95.5
89.3
–118
–111
–101
123
THD
Total harmonic distortion(5)
Spurious-free dynamic range
fIN = 100 kHz
fIN = 500 kHz
fIN = 2 kHz
SFDR
fIN = 100 kHz
fIN = 500 kHz
116
106
(1) Ideal input span, does not include gain or offset errors.
(2) See Figure 9, Figure 10, Figure 25, and Figure 26 for statistical distribution data for INL, DNL, offset, and gain error parameters.
(3) LSB = least-significant bit. 1 LSB at 18 bits is approximately 3.8 ppm.
(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.1 dB below full-scale,
unless otherwise specified.
(5) Calculated on the first nine harmonics of the input frequency.
Copyright © 2015, Texas Instruments Incorporated
5
ADS9110
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
www.ti.com.cn
Electrical Characteristics (continued)
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C.
PARAMETER
DIGITAL INPUTS(6)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
High-level input voltage
0.65 DVDD
–0.3
DVDD + 0.3
0.35 DVDD
V
V
VIL
Low-level input voltage
DIGITAL OUTPUTS(6)
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = 2-mA source
DVDD – 0.45
V
V
IOH = 2-mA sink
0.45
POWER SUPPLY
AVDD
DVDD
Analog supply voltage
1.65
1.65
1.8
1.8
5
1.95
1.95
6.25
V
V
Digital supply voltage
Active, fastest throughput
Static, ACQ state
mA
µA
3.7
500
1
AVDD supply current
(AVDD = 1.8 V)
IDD
PD
Low-power, NAP mode
Power-down, PD state
Active, fastest throughput
Static, ACQ state
9
11.25
mW
µW
6.6
900
1.8
AVDD power dissipation
(AVDD = 1.8 V)
Low-power, NAP mode
Power-down, PD state
TEMPERATURE RANGE
TA Operating free-air temperature
(6) As per the JESD8-7A standard. Specified by design; not production tested.
–40
85
°C
6
Copyright © 2015, Texas Instruments Incorporated
ADS9110
www.ti.com.cn
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
6.6 Timing Requirements: Conversion Cycle
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 1.
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
fcycle
Sampling frequency
2
MHz
ns
tcycle
ADC cycle time period
Pulse duration: CONVST high
Pulse duration: CONVST low
Acquisition time
Quiet acquisition time(1)
Quiet aperture time(1)
500
30
twh_CONVST
twl_CONVST
tacq
ns
30
ns
150
25
ns
tqt_acq
ns
td_cnvcap
10
ns
TIMING SPECIFICATIONS
tconv
Conversion time
300
340
ns
(1) See Figure 48.
6.7 Timing Requirements: Asynchronous Reset, NAP, and PD
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 2 and
Figure 3.
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
twl_RST
Pulse duration: RST low
100
ns
TIMING SPECIFICATIONS
td_rst
Delay time: RST rising to RVS rising
1250
300
µs
ns
µs
tnap_wkup
tPWRUP
Wake-up time: NAP mode
Power-up time: PD mode
250
6.8 Timing Requirements: SPI-Compatible Serial Interface
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 4.
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
fCLK
Serial clock frequency
75
MHz
ns
tCLK
Serial clock time period
13.33
0.45
0.45
5
tph_CK
tpl_CK
SCLK high time
0.55
0.55
tCLK
tCLK
ns
SCLK low time
tsu_CSCK
tsu_CKDI
tht_CKDI
tht_CKCS
Setup time: CS falling to the first SCLK capture edge
Setup time: SDI data valid to the SCLK capture edge
Hold time: SCLK capture edge to (previous) data valid on SDI
Delay time: last SCLK falling to CS rising
1.2
ns
0.65
5
ns
ns
TIMING SPECIFICATIONS
tden_CSDO
tdz_CSDO
td_CKDO
Delay time: CS falling to data enable
4.5
10
6.5
5
ns
ns
ns
ns
Delay time: CS rising to SDO going to 3-state
Delay time: SCLK launch edge to (next) data valid on SDO
Delay time: CS falling to RVS falling
td_CSRDY_f
After NOP operation
10
70
Delay time:
CS rising to RVS rising
td_CSRDY_r
ns
After WR or RD operation
Copyright © 2015, Texas Instruments Incorporated
7
ADS9110
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
www.ti.com.cn
6.9 Timing Requirements: Source-Synchronous Serial Interface (External Clock)
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 5.
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
fCLK Serial clock frequency
tCLK Serial clock time period
TIMING SPECIFICATIONS(1)
100
MHz
ns
10
td_CKSTR_r
td_CKSTR_f
toff_STRDO_f
toff_STRDO_r
Delay time: SCLK launch edge to RVS rising
8.5
8.5
0.5
0.5
ns
ns
ns
ns
Delay time: SCLK launch edge to RVS falling
Time offset: RVS rising to (next) data valid on SDO
Time offset: RVS falling to (next) data valid on SDO
–0.5
–0.5
(1) Other parameters are the same as the Timing Requirements: SPI-Compatible Serial Interface table.
6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 6.
MIN
TYP
MAX
UNIT
TIMING SPECIFICATIONS(1)
td_CSSTR
Delay time: CS falling to RVS rising
12
–0.5
–0.5
9.9
40
0.5
ns
ns
ns
toff_STRDO_f
toff_STRDO_r
Time offset: RVS rising to (next) data valid on SDO
Time offset: RVS falling to (next) data valid on SDO
INTCLK option
0.5
11.1
22.2
44.4
0.55
0.55
tSTR
Strobe output time period
INTCLK / 2 option
INTCLK / 4 option
19.8
39.6
0.45
0.45
ns
tph_STR
tpl_STR
Strobe output high time
Strobe output low time
tSTR
tSTR
(1) Other parameters are the same as the Timing Requirements: SPI-Compatible Serial Interface table.
8
Copyright © 2015, Texas Instruments Incorporated
ADS9110
www.ti.com.cn
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
Sample
S
Sample
S+1
twh_CONVST
twl_CONVST
CONVST
tcycle
tconv_max
tconv
tconv_min
tacq
ADCST (Internal)
CNV (C)
ACQ (C+1)
CS
RVS
Figure 1. Conversion Cycle Timing Diagram
trst
twl_RST
RST
CONVST
CS
td_rst
SCLK
RVS
SDO-x
Figure 2. Asynchronous Reset Timing Diagram
Copyright © 2015, Texas Instruments Incorporated
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ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
www.ti.com.cn
Sample
S
Sample
S+1
twh_CONVST
twl_CONVST
CONVST
tcycle
tnap
tconv
tnap_wkup
tacq
tconv_max
tconv_min
ADCST
(Internal)
CNV C
NAP + ACQ C+1
ACQ C+1
CS
RVS
t = 0
Figure 3. NAP Mode Timing Diagram
tCLK
tph_CK
tpl_CK
CS
SCLK(1)
SDO-x
SCLK(1)
tsu_CKDI
tht_CKDI
tsu_CSCK
tht_CKCS
SDI
tden_CSDO
tdz_CSDO
td_CKDO
SDO-x
(1) The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
Figure 4. SPI-Compatible Serial Interface Timing Diagram
10
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ADS9110
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ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
tCLK
tph_CK
tpl_CK
CS
SCLK
td_CKSTR_f
tsu_CSCK
tht_CKCS
td_CKSTR_r
SCLK
RVS
tden_CSDO
tdz_CSDO
toff_STRDO_r
toff_STRDO_f
SDO-x
(DDR)
SDO-x
td_CSRDY_f
td_CSRDY_r
toff_STRDO_r
SDO-x
(SDR)
RVS
Figure 5. Source-Synchronous Serial Interface Timing Diagram (External Clock)
CS
SDO-x
RVS
CS
tSTR
tden_CSDO
tdz_CSDO
tph_STR
tpl_STR
td_CSSTR
RVS
td_CSRDY_f
td_CSRDY_r
toff_STRDO_r
toff_STRDO_f
SDO-x
(DDR)
toff_STRDO_r
SDO-x
(SDR)
Figure 6. Source-Synchronous Serial Interface Timing Diagram (Internal Clock)
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6.11 Typical Characteristics
At TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
1.5
1
0.75
0.5
0.5
0
0.25
0
-0.5
-1
-0.25
-0.5
-0.75
-1.5
131071
C002
-131072
131071
œ131072
C001
ADC Output Code
ADC Output Code
Typical INL = ±0.5 LSB
Typical DNL = ±0.4 LSB
Figure 7. Typical INL
Figure 8. Typical DNL
600
480
360
240
120
0
600
480
360
240
120
0
Max
Min
Min
Max
-1.5 -1.2 -0.9 -0.6 -0.3
0
0.3 0.6 0.9 1.2 1.5
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
C009
C009
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
600 devices
600 devices
Figure 9. Typical INL Distribution
Figure 10. Typical DNL Distribution
1.5
1
0.75
0.5
Maximum
Maximum
0.5
0
0.25
0
-0.5
-1
-0.25
-0.5
-0.75
Minimum
Minimum
-1.5
-40
-15
10
35
60
85
10
35
60
85
œ40
œ15
C004
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C003
VREF = 5 V
VREF = 5 V
Figure 11. INL vs Temperature
Figure 12. DNL vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
1.5
0.75
Maximum
1
0.5
Maximum
Minimum
0.5
0
0.25
0
-0.5
-1
-0.25
-0.5
-0.75
Minimum
-1.5
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
C006
C005
Reference Voltage (V)
Reference Voltage (V)
TA = 25°C
TA = 25°C
Figure 13. INL vs Reference Voltage
Figure 14. DNL vs Reference Voltage
32768
24576
16384
8192
0
32768
24576
16384
8192
0
131069 131070 131071 131072 131073 131074 131075
131069 131070 131071 131072 131073 131074
C009
C010
ADC Output Code
ADC Output Code
Standard deviation = 0.9 LSB
Standard deviation = 0.9 LSB
Figure 15. DC Input Histogram, Code Ceter
Figure 16. DC Input Histogram, Code Transition
0
œ40
0
œ40
œ80
œ80
œ120
œ160
œ200
œ120
œ160
œ200
0
200
400
600
800
1000
0
200
400
600
800
1000
C011
C012
fIN, Input Frequency ( kHz)
fIN, Input Frequency ( kHz)
fIN = 2 kHz, SNR = 100 dB, THD = –120 dB
fIN = 100 kHz, SNR = 97.5 dB, THD = –113 dB
Figure 17. Typical FFT
Figure 18. Typical FFT
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
œ114
126
125
124
123
122
121
120
119
102
101
100
99
16.6
16.5
16.4
16.3
16.2
œ115
œ116
œ117
œ118
œ119
œ120
œ121
œ122
SFDR
SNR
SINAD
THD
ENOB
118
85
98
-40
-15
10
35
60
10
35
60
85
œ40
œ15
C014
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C013
fIN = 2 kHz, VREF = 5 V
Figure 20. Distortion Performance vs Temperature
fIN = 2 kHz, VREF = 5 V
Figure 19. Noise Performance vs Temperature
101
100
99
18
œ113
124
123
122
121
120
119
118
117
œ114
œ115
œ116
œ117
œ118
œ119
œ120
17.5
17
THD
SINAD
98
16.5
SNR
97
16
ENOB
SFDR
96
15.5
95
15
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
C016
C015
Reference Voltage (V)
Reference Voltage (V)
fIN = 2 kHz, TA = 25°C
fIN = 2 kHz, TA = 25°C
Figure 22. Distortion Performance vs Reference Voltage
Figure 21. Noise Performance vs Reference Voltage
100
98
96
94
92
90
88
17
œ100
œ104
œ108
œ112
œ116
œ120
œ124
124
120
116
112
108
104
100
16.5
16
THD
SINAD
SFDR
SNR
15.5
15
ENOB
14.5
14
0
100
200
300
400
500
C017
0
100
200
300
400
500
C018
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
VREF = 5 V, TA = 25°C
Figure 23. Noise Performance vs Input Frequency
VREF = 5 V, TA = 25°C
Figure 24. Distortion Performance vs Input Frequency
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
600
480
360
240
120
0
500
400
300
200
100
0
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
C009
-0.01
-0.006
-0.002
0.002
0.006
0.01
C009
Offset (mV)
Gain Error (%FS)
600 devices
Figure 25. Offset Typical Distribution
600 devices
Figure 26. Gain Error Typical Distribution
1
0.5
0
0.01
0.005
0
-0.5
-1
-0.005
-0.01
10
35
60
85
C019
-40
-15
10
35
60
85
C020
œ40
œ15
Free-Air Temperature (oC)
Free-Air Temperature (oC)
VREF = 5 V
VREF = 5 V
Figure 27. Offset vs Temperature
Figure 28. Gain Error vs Temperature
1
0.5
0
0.01
0.005
0
-0.5
-1
-0.005
-0.01
2.5
3
3.5
4
4.5
5
C021
2.5
3
3.5
4
4.5
5
C022
Reference Voltage (V)
Reference Voltage (V)
TA = 25°C
TA = 25°C
Figure 29. Offset vs Reference Voltage
Figure 30. Gain Error vs Reference Voltage
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
10
8
6
4
2
0
8
Without
NAP
6
4
2
With
NAP
0
-40
-15
10
35
60
85
C026
2000
1600
1200
800
400
0
C027
Free-Air Temperature (oC)
fS, Throughput (kSPS)
2 MSPS
TA = 25°C
Figure 31. Supply Current vs Temperature
Figure 32. Supply Current vs Throughput
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-40
-15
10
35
60
85
2000
1600
1200
800
400
0
C028
Free-Air Temperature (oC)
fS, Throughput (kSPS)
C02
2 MSPS
TA = 25°C
Figure 33. Reference Current vs Temperature
Figure 34. Reference Current vs Throughput
œ86
œ87
œ88
œ89
œ90
œ91
œ92
œ93
0
150
300
fIN, Input Frequency (kHz)
450
600
C025
Figure 35. CMRR vs Input Frequency
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7 Detailed Description
7.1 Overview
The ADS9110 is a high-speed, successive approximation register (SAR), analog-to-digital converter (ADC) based
on the charge redistribution architecture. This compact device features high performance at a high throughput
rate and at low power consumption.
The ADS9110 supports unipolar, fully-differential analog input signals and operates with a 2.5-V to 5-V external
reference, offering a wide selection of input ranges without additional input scaling.
When a conversion is initiated, the differential input between the AINP and AINM pins is sampled on the internal
capacitor array. The ADS9110 uses an internal clock to perform conversions. During the conversion process,
both analog inputs are disconnected from the internal circuit. At the end of conversion process, the device
reconnects the sampling capacitors to the AINP and AINM pins and enters acquisition phase.
The device consumes only 15 mW of power when operating at the full 2-MSPS throughput. Power consumption
at lower throughputs can be reduced by using the flexible low-power modes (NAP and PD).
The new multiSPI interface simplifies board layout, timing, and firmware, and achieves high throughput at lower
clock speeds, thus allowing easy interface to a variety of microprocessors, digital signal processors (DSPs), and
field-programmable gate arrays (FPGAs).
7.2 Functional Block Diagram
From a functional perspective, the device comprises of two modules: the converter module and the interface
module, as shown in Figure 36.
The converter module samples and converts the analog input into an equivalent digital output code whereas the
interface module facilitates communication and data transfer with the host controller.
REFP AVDD
DVDD
RST
CONVST
CS
SCLK
SDI
AINP
AINM
Interface Module
SDO-0
SDO-1
SDO-2
SDO-3
RVS
Converter Module
REFM
GND
Figure 36. Functional Block Diagram
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7.3 Feature Description
7.3.1 Converter Module
As shown in Figure 37, the converter module samples the analog input signal (provided between the AINP and
AINM pins), compares this signal with the reference voltage (provided between the pair of REFP and REFM
pins), and generates an equivalent digital output code.
The converter module receives RST and CONVST inputs from the interface module and outputs the ADCST
signal and the conversion result back to the interface module.
REFP
DVDD
AVDD
RST
CONVST
CS
SCLK
SDI
SDO-0
SDO-1
SDO-2
SDO-3
RVS
OSC
RST
CONVST
ADCST
AINP
AINM
Sample-
and-Hold
Circuit
Interface
Module
ADC
Conversion
Result
AGND
Converter Module
DGND
REFM
GND
Figure 37. Converter Module
7.3.1.1 Sample-and-Hold Circuit
The device supports unipolar, fully-differential analog input signals. Figure 38 shows a small-signal equivalent
circuit of the sample-and-hold circuit. Each sampling switch is represented by a resistance (Rs1 and Rs2, typically
30 Ω) in series with an ideal switch (sw1 and sw2). The sampling capacitors, Cs1 and Cs2, are typically 60 pF.
Rs1
Device in Hold Mode
4 pF
sw1
AINP
AINN
Cs1
REFP
4 pF
GND
Cs2
GND
sw2
Figure 38. Input Sampling Stage Equivalent Circuit
Rs2
During the acquisition process (in ACQ state), both positive and negative inputs are individually sampled on Cs1
and Cs2, respectively. During the conversion process (in CNV state), the device converts for the voltage
difference between the two sampled values: VAINP – VAINM
.
Each analog input pin has electrostatic discharge (ESD) protection diodes to REFP and GND. Keep the analog
inputs within the specified range to avoid turning the diodes on.
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Feature Description (continued)
Equation 1 and Equation 2 show the full-scale voltage range (FSR) and common-mode voltage range (VCM
)
supported at the analog inputs for any external reference voltage (VREF).
FSR = êVREF
(1)
V
≈
’
REF
VCM
=
ê 0.1 V
∆
«
÷
◊
2
(2)
7.3.1.2 External Reference Source
The input range for the device is set by the external voltage applied at the two REFP pins. The REFM pins
function as the reference ground and must be connected to each reference capacitor.
The device takes very little static current from the reference pins in the RST and ACQ states. During the
conversion process (in CNV state), binary-weighted capacitors are switched onto the reference pins. The
switching frequency is proportional to the conversion clock frequency, but the dynamic charge requirements are
a function of the absolute values of the input voltage and the reference voltage. Reference capacitors decouple
the dynamic reference loads and a low-impedance reference driver is required to keep the voltage regulated to
within 1 LSB.
Most reference sources have very high broadband noise. TI recommends filtering the voltage reference source
with a 160-Hz filter before being connected to the reference driver, as shown in Figure 39. See the ADC
Reference Driver section for reference capacitor and driver selection. Also, the reference inputs are sensitive to
board layout; thus, the layout guidelines described in the Layout section must be followed.
4
5
6
REFM
REFP
Device
CREF
10 µF
RREF_FLT
1 kW
Voltage
Reference
Buffer
CREF_FLT
1 µF
CREF
10 µF
CREF
10 µF
Figure 39. Reference Driver Schematic
7.3.1.3 Internal Oscillator
The device features an internal oscillator (OSC) that provides the conversion clock; see Figure 37. Conversion
duration can vary but is bounded by the minimum and maximum value of tconv, as specified in the Timing
Requirements: Conversion Cycle table.
The interface module can use this internal clock (OSC) or an external clock (provided by the host controller on
the SCLK pin) or a combination of the internal and external clocks for executing the data transfer operations
between the device and host controller; see the Interface Module section for more details.
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Feature Description (continued)
7.3.1.4 ADC Transfer Function
The ADS9110 supports unipolar, fully-differential analog inputs. The device output is in twos compliment format.
Figure 40 and Table 1 show the ideal transfer characteristics for the device.
The LSB for the ADC is given by Equation 3:
FSR
218
VREF
218
1 LSB =
= 2ì
(3)
1FFFF
00000
3FFFF
20001
20000
VIN
VREF
œ 1 LSB
œVREF
+ 1 LSB
œ1 LSB
0
Differential Analog Input
(AINP - AINN)
Figure 40. Differential Transfer Characteristics
Table 1. Transfer Characteristics
DIFFERENTIAL ANALOG INPUT VOLTAGE
(AINP – AINM)
OUTPUT CODE
(Hex)
< –VREF
–VREF + 1 LSB
–1 LSB
20000
20001
3FFFF
00000
00001
1FFFF
0
1 LSB
> VREF – 1 LSB
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7.3.2 Interface Module
The interface module facilitates the communication and data transfer between the device and the host controller.
As shown in Figure 41, the module comprises of shift registers (both input and output), configuration registers,
and a protocol unit.
Interface Module
Shift Registers
RST
Output Shift Register (OSR)
CONVST
D19
B19
D18
D1
D0
CS
20 Bits
20 Bits
SCLK
SDI
B18
B1
B0
Converter Module
SDO-0
SDO-1
SDO-2
SDO-3
RVS
Input Shift Register (ISR)
Command Processor
Configuration Registers
SCLK
Counter
Figure 41. Interface Module
The Pin Configuration and Functions section provides descriptions of the interface pins; the Data Transfer Frame
section details the functions of shift registers, the SCLK counter, and the command processor; the Data Transfer
Protocols section details supported protocols; and the Register Maps section explains the configuration registers
and bit settings.
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7.4 Device Functional Modes
As shown in Figure 42, the device supports three functional states: RST, ACQ, and CNV. The device state is
determined by the status of the CONVST and RST control signals provided by the host controller.
Power Up
ACQ
CONVST Rising Edge
RST Rising Edge
End of Conversion
CNV
RST
RST Falling Edge
Figure 42. Device Functional States
7.4.1 RST State
In the ADS9110, the RST pin is an asynchronous digital input. To enter RST state, the host controller must pull
the RST pin low and keep it low for the twl_RST duration (as specified in the Timing Requirements: Asynchronous
Reset, NAP, and PD table).
In RST state, all configuration registers (see the Register Maps section) are reset to their default values, the RVS
pins remain low, and the SDO-x pins are tri-stated.
To exit RST state, the host controller must pull the RST pin high with CONVST and SCLK held low and CS held
high, as shown in Figure 43. After a delay of td_rst, the device enters ACQ state and the RVS pin goes high.
trst
twl_RST
RST
td_rst
CONVST
CS
SCLK
RVS
SDO-x
Figure 43. Asynchronous Reset
To operate the device in any of the other two states (ACQ or CNV), RST must be held high. With RST held high,
transitions on the CONVST pin determine the functional state of the device.
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Device Functional Modes (continued)
Figure 44 shows a typical conversion process. An internal signal, ADCST, goes low during conversion and goes
high at the end of conversion. With CS held high, RVS reflects the status of ADCST.
Sample
S
Sample
S+1
twh_CONVST
twl_CONVST
CONVST
tcycle
tconv_max
tconv
tconv_min
tacq
ADCST (Internal)
CNV (C)
ACQ (C+1)
CS
RVS
Figure 44. Typical Conversion Process
7.4.2 ACQ State
In ACQ state, the device acquires the analog input signal. The device enters ACQ state on power-up, after any
asynchronous reset, or after end of every conversion.
An RST falling edge takes the device from an ACQ state to a RST state. A CONVST rising edge takes the
device from an ACQ state to a CNV state.
The device offers a low-power NAP mode to reduce power consumption in the ACQ state; see the NAP Mode
section for more details on NAP mode.
7.4.3 CNV State
The device moves from ACQ state to CNV state on a rising edge of the CONVST pin. The conversion process
uses an internal clock and the device ignores any further transitions on the CONVST signal until the ongoing
conversion is complete (that is, during the time interval of tconv).
At the end of conversion, the device enters ACQ state. The cycle time for the device is given by Equation 4:
tcycle-min = tconv + tacq-min
(4)
NOTE
The conversion time, tconv, can vary within the specified limits of tconv_min and tconv_max (as
specified in the Timing Requirements: Conversion Cycle table). After initiating a
conversion, the host controller must monitor for a low-to-high transition on the RVS pin or
wait for the tconv_max duration to elapse before initiating a new operation (data transfer or
conversion). If RVS is not monitored, substitute tconv in Equation 4 with tconv_max
.
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7.5 Programming
The device features four configuration registers (as described in the Register Maps section) and supports two
types of data transfer operations: data write (the host configures the device), and data read (the host reads data
from the device).
To access the internal configuration registers, the device supports the commands listed in Table 2.
Table 2. Supported Commands
OPCODE B[19:0]
COMMAND ACRONYM
COMMAND DESCRIPTION
0000_0000_0000_0000_0000
1001_<8-bit address>_0000_0000
1010_<8-bit address>_<8-bit data>
1111_1111_1111_1111_1111
NOP
RD_REG
WR_REG
NOP
No operation
Read contents from the <8-bit address>
Write <8-bit data> to the <8-bit address>
No operation
These commands are reserved and treated by the
device as no operation
Remaining combinations
Reserved
In the ADS9110, any data write to the device is always synchronous to the external clock provided on the SCLK
pin. The data read from the device can be synchronized to the same external clock or to an internal clock of the
device by programming the configuration registers (see the Data Transfer Protocols section for details).
In any data transfer frame, the contents of an internal, 20-bit, output data word are shifted out on the SDO pins.
The D[19:2] bits of the 20-bit output data word for any frame (F+1), are determined by the:
•
•
Settings of the DATA_PATN[2:0] bits applicable to frame F+1 (see the DATA_CNTL register) and
Command issued in frame F
If a valid RD_REG command is executed in frame F, then the D[19:12] bits in frame F+1 reflect the contents of
the selected register and the D[11:0] bits are 0s.
If the DATA_PATN[2:0] bits for frame F+1 are set to 1xxb, then the D[19:2] bits in frame F+1 are the fixed data
pattern shown in Figure 45.
For all other combinations, the D[19:2] bits for frame F+1 are the latest conversion result.
Output
Data Word
D[19:0]
A valid RG_READ command is
received in the previous frame.
D19
D18
Register Data
RR000h
000
001
Conversion
Result
D[19:2]
010
011
100
00000h
3FFFFh
15555h
03333h
101
110
111
D3
D2
D1
D0
Parity Computation Unit
DATA_PATN [2:0]
Figure 45. Output Data Word (D[19:0])
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Figure 46 shows further details of the parity computation unit illustrated in Figure 45.
Output Data Word
D[19:0]
Parity Computation Unit
D19
D18
XOR
D17
D16
XOR
D15
D14
XOR
D13
D12
XOR
D11
D10
XOR
D9
D8
XOR
D7
D6
D5
D4
D3
D2
D1
D0
XOR
FLPAR
FTPAR
XOR
)
)
11
10
01
00
16 MSBs
12 MSBs
8 MSBs
4 MSBs
MUX
PAR_EN
FPAR_LOC[1:0]
Figure 46. Parity Bits Computation
With the PAR_EN bit set to 0, the D[1] and D[0] bits of the output data word are set to 0 (default configuration).
When the PAR_EN bit is set to 1, the device calculates the parity bits (FLPAR and FTPAR) and appends them
as bits D[1] and D[0].
•
•
FLPAR is the even parity calculated on bits D[19:2].
FTPAR is the even parity calculated on the bits defined by FPAR_LOC[1:0].
See the DATA_CNTL register for more details on the FPAR_LOC[1:0] bit settings.
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7.5.1 Data Transfer Frame
A data transfer frame between the device and the host controller is bounded between a CS falling edge and the
subsequent CS rising edge. The host controller can initiate a data transfer frame (as shown in Figure 47) at any
time irrespective of the status of the CONVST signal; however, the data read during such a data transfer frame is
a function of relative timing between the CONVST and CS signals.
Frame F
CONVST
CS
RVS
As per output protocol selection.
td_RVS
SCLK
N SCLKs
Valid Command
SDI
SDO-x
OSR Contents
SCLK Counter
SCLK Counter
0
b
Output Data Word
Input Shift Register (ISR)
D19
D0
B19
B0
D19
D0
D19
D0
Output Shift Register (OSR)
Command Processor
Figure 47. Data Transfer Frame
For this discussion, assume that the CONVST signal remains low.
For a typical data transfer frame F:
1. The host controller pulls CS low to initiate a data transfer frame. On the CS falling edge:
–
–
–
RVS goes low, indicating the beginning of the data transfer frame.
The SCLK counter is reset to 0.
The device takes control of the data bus. As shown in Figure 47, the 20-bit contents of the output data
word (see Figure 45) are loaded in to the 20-bit OSR (see Figure 41).
–
The 20-bit ISR (see Figure 41) is reset to 00000h, corresponding to a NOP command.
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2. During the frame, the host controller provides clocks on the SCLK pin:
–
–
–
On each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin
is shifted in to the ISR.
On each launch edge of the output clock (SCLK in this case), OSR data are shifted out on the selected
SDO-x pins.
The status of the RVS pin depends on the output protocol selection (see the Protocols for Reading From
the Device section).
3. The host controller pulls CS high to end the data transfer frame. On the CS rising edge:
–
–
–
The SDO-x pins go to tri-state.
RVS goes high (after a delay of td_RVS).
As illustrated in Figure 47, the 20-bit contents of the ISR are transferred to the command processor (see
Figure 41) for decoding and further action.
After pulling CS high, the host controller must monitor for a low-to-high transition on the RVS pin or wait for the
td_RVS time (see the Timing Requirements: SPI-Compatible Serial Interface table) to elapse before initiating a new
operation (data transfer or conversion). The delay, td_RVS, for any data transfer frame F varies based on the data
transfer operation executed in the frame F.
At the end of the data transfer frame F:
•
If the SCLK counter is < 20, then the device treats the frame F as a short data transfer frame. The output
data bits transferred during such a short data transfer frame are still valid data; however, the device ignores
the data received over the SDI pin (similar to a no operation command). The host controller can use these
short data transfer frames to read only the required number of MSB bits from the 20-bit output data word.
•
•
If the SCLK counter = 20, then the device treats the frame F as a optimal data transfer frame. At the end of
an optimal data transfer frame, the command processor treats the 20-bit contents of the ISR as a valid
command word.
If the SCLK counter > 20, then the device treats the frame F as a long data transfer frame. At the end of a
long data transfer frame, the command processor treats the 20-bit contents of the ISR as a valid command
word. There is no restriction on the maximum number of clocks that can be provided within any data transfer
frame F. However, when the host controller provides a long data transfer frame, the last 20 bits shifted into
the device prior to the CS rising edge must constitute the desired command.
NOTE
This example shows a data transfer synchronous to the external clock provided on the
SCLK pin. The device also supports data transfer operations that are synchronous to the
internal clock; see the Protocols for Reading From the Device section for more details.
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7.5.2 Interleaving Conversion Cycles and Data Transfer Frames
The host controller can operate the ADS9110 at the desired throughput by interleaving the conversion cycles and
the data transfer frames.
The cycle time of the device, tcycle, is the time difference between two consecutive CONVST rising edges
provided by the host controller. The response time of the device, tresp, is the time difference between the host
controller initiating a conversion C and the host controller receiving the complete result for conversion C.
Figure 48 shows three conversion cycles, C, C+1, and C+2. Conversion C is initiated by a CONVST rising edge
at the t = 0 time and the conversion result becomes available for data transfer at the tconv time. However, this
result is loaded into the OSR only on the subsequent CS falling edge. This CS falling edge must be provided
before the completion of the conversion C+1 (that is, before the tcycle + tconv time).
To achieve the rated performance specifications, the host controller must ensure that no digital signals toggle
during the quiet acquisition time (tqt_acq) and quiet aperture time (td_cnvcap). Any noise during td_cnvcap can
negatively affect the result of the ongoing conversion whereas any noise during tqt_acq can negatively affect the
result of the subsequent conversion.
Sample
S
Sample
S+1
Sample
S+2
tcycle
td_cnvcap
tqt_acq
tconv
tacq
CONVST
ADCST
(Internal)
Zone1
Zone2
Conversion
C
Conversion
C+1
Conversion
C+2
t = 0
Figure 48. Data Transfer Zones
This architecture allows for two distinct time zones (zone1 and zone2) to transfer data for each conversion.
Zone1 and zone2 for conversion C are defined in Table 3.
Table 3. Data Transfer Zones Timing
ZONE
STARTING TIME
ENDING TIME
tcycle - tqt_acq
tconv
Zone1 for conversion C
tcycle + td_cnvcap
tcycle + tcycle - tqt_acq
Zone2 for conversion C
The response time includes the conversion time and the data transfer time, and is thus a function of the data
transfer zone selected.
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Figure 49 and Figure 50 illustrate interleaving of three conversion cycles (C, C+1, and C+2) with three data
transfer frames (F, F+1, and F+2) in zone1 and in zone2, respectively.
Sample
S
Sample
S+1
Sample
S+2
tcycle
td_cnvcap
tqt_acq
tconv
tacq
CONVST
ADCST
(Internal)
Zone1
C
Zone1
C+1
Zone1
C+2
Conversion
C
Conversion
C+1
Conversion
C+2
Frame
F
Frame
F+1
Frame
F+2
CS
SDO
tread-Z1
tresp-Z1
C
C+1
C+2
SCLK
t = 0
Figure 49. Zone1 Data Transfer
Sample
S
Sample
S+1
Sample
S+2
tcycle
td_cnvcap
tqt_acq
tconv
tacq
CONVST
ADCST
(Internal)
Zone2
C
Zone2
C+1
Zone2
C+2
Conversion
Conversion
C+1
Conversion
C+2
C
Frame
F
Frame
F+1
Frame
F+2
CS
SDO
tread-Z2
tresp-Z2
C-1
C
C+1
SCLK
t = 0
Figure 50. Zone2 Data Transfer
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To achieve cycle time, tcycle, the read time in zone1 is given by Equation 5:
tread-Z1 Ç tcycle - tconv - tqt_acq
(5)
For an optimal data transfer frame, Equation 5 results in an SCLK frequency given by Equation 6:
20
fSCLK
í
tread-Z1
(6)
(7)
Then, the zone1 data transfer achieves a response time defined by Equation 7:
tresp-Z1-min = tconv + tread-Z1
As an example, while operating the ADS9110 at its full throughput of 2 MSPS, the host controller can achieve a
response time of 1 µs provided that the data transfer in zone1 is completed within 135 ns. However, to achieve
this response time, the SCLK frequency must be greater than 148 MHz.
Note that the device does not support such high SCLK speeds. At lower SCLK speeds, tread-Z1 increases,
resulting in slower response times and higher cycle times.
To achieve the same cycle time, tcycle, the read time in zone2 is given by Equation 8:
tread-Z2 Ç tcycle - td_cnvcap - tqt_acq
(8)
For an optimal data transfer frame, Equation 8 results in an SCLK frequency given by Equation 9:
20
fSCLK
í
tread_Z2
(9)
Then, the zone2 data transfer achieves a response time defined by Equation 10:
tresp-Z2-min = tcycle + td_cnvcap + tread-Z2
(10)
As an example, the host controller can operate the ADS9110 at its full throughput of 2 MSPS using zone2 data
transfer with a 43 MHz SCLK (and a read time of 465 ns). However, zone2 data transfer will result in response
time of nearly 2 µs.
Any increase in tread-Z2 increases response time and can increase cycle time.
For a given cycle time, the zone1 data transfer clearly achieves faster response time but also requires a higher
SCLK speed (as evident from Equation 5, Equation 6, and Equation 7), whereas the zone2 data transfer clearly
requires a lower SCLK speed but supports slower response time (as evident from Equation 8, Equation 9, and
Equation 10).
NOTE
In zone2, the data transfer is active when the device is converting for the next analog
sample. This digital activity can interfere with the ongoing conversion and cause some
degradation in SNR performance.
Additionally, a data transfer frame can begin in zone1 and then extend into zone2;
however, the host controller must ensure that no digital transitions occur during the tqt_acq
and td_cnvcap time intervals.
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7.5.3 Data Transfer Protocols
The device features a multiSPI interface that allows the host controller to operate at slower SCLK speeds and
still achieve the required cycle time with a faster response time. The multiSPI interface module offers two options
to reduce the SCLK speed required for data transfer:
1. An option to increase the width of the output data bus
2. An option to enable double data rate (DDR) transfer
These two options can be combined to achieve further reduction in SCLK speed.
Figure 51 shows the delays between the host controller and the device in a typical serial communication.
Digital Isolator
Device
Host Controller
(Optional)
tpcb_CK
SCLK
SCLK
td_ckdo
td_ISO
tsu_h
SDI
SDO-0
td_ISO
tpcb_SDO
Figure 51. Delays in Serial Communication
The total delay in the path is given by Equation 11:
td_total_serial = tpcb_CK + td_iso + td_ckdo + td_iso + tpcb_SDO + tsu_h
(11)
In a standard SPI protocol, the host controller and the device launch and capture data bits on alternate SCLK
edges. Therefore, the td_total_serial delay must be kept less than half of the SCLK duration. Equation 12 shows the
fastest clock allowed by the SPI protocol.
1
fclk-SPI
Ç
2ìtd_total-serial
(12)
Larger values of the td_total_serial delay restrict the maximum SCLK speed for the SPI protocol, resulting in higher
read and response times, and can increase cycle times. To remove this restriction on the SCLK speed, the
multiSPI interface module supports an ADC-master or source-synchronous mode of operation.
Digital Isolator
(Optional)
Device
Host Controller
tpcb_CK
SCLK
SCLK
td_ISO
td_ckdo
SDO-0
td_ckstr
SDI
tsu_h
td_ISO
toff_strdo
tpcb_SDO
RVS
td_ISO
tpcb_RVS
Figure 52. Delays in Source-Synchronous Communication
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As illustrated in Figure 52, in ADC-master or source-synchronous mode, the device provides a synchronous
output clock (on the RVS pin) along with the output data (on the SDO-x pins).
For a source-synchronous data transfer, the total delay in the path is given by Equation 13:
td_total_srcsync = tpcb_RVS -tpcb_SDO + tsu_h
(13)
As illustrated in Equation 11 and Equation 13, the ADC-master or source-synchronous mode completely
eliminates the affect of isolator delays and the clock-to-data delays, which are typically the largest contributors in
the overall delay computation.
Furthermore, the actual values of tpcb_RVS and tpcb_SDO do not matter. In most cases, the td_total_srcsync delay can be
kept at a minimum by routing the RVS and SDO lines together on the PCB. Therefore, the ADC-master or
source-synchronous mode allows the host controller and device to operate at much higher SCLK speeds.
7.5.3.1 Protocols for Configuring the Device
As shown in Table 4, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S,
SPI-01-S, SPI-10-S, or SPI-11-S) to write data in to the device.
Table 4. SPI Protocols for Configuring the Device
SCLK POLARITY
(At CS Falling Edge)
SCLK PHASE
(Capture Edge)
PROTOCOL
SDI_CNTL
SDO_CNTL
DIAGRAM
SPI-00-S
SPI-01-S
SPI-10-S
SPI-11-S
Low
Low
High
High
Rising
Falling
Falling
Rising
00h
01h
02h
03h
00h
00h
00h
00h
Figure 53
Figure 54
Figure 55
Figure 56
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data
read and data write operations.
To select a different SPI-compatible protocol, program the SDI_MODE[1:0] bits in the SDI_CNTL register. This
first write operation must adhere to the SPI-00-S protocol. Any subsequent data transfer frames must adhere to
the newly selected protocol.
Figure 53, Figure 54, Figure 55, and Figure 56 detail the four protocols using an optimal, 20-SCLK frame; see
the Timing Requirements: SPI-Compatible Serial Interface section for associated timing parameters.
NOTE
As explained in the Data Transfer Frame section, a valid write operation to the device
requires a minimum of 20 SCLKs to be provided within a data transfer frame.
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CS
SCLK
SDI
CS
SCLK
SDI
B19
B18
B1
B0
B19
B18
B17
B1
B0
RVS
RVS
Figure 54. SPI-01-S Protocol, 20 SCLKs
Figure 53. SPI-00-S Protocol, 20 SCLKs
CS
SCLK
SDI
CS
SCLK
SDI
B19
B18
B17
B1
B0
B19
B18
B2
B1
B0
RVS
RVS
Figure 55. SPI-10-S Protocol, 20 SCLKs
Figure 56. SPI-11-S Protocol, 20 SCLKs
7.5.3.2 Protocols for Reading From the Device
The protocols for the data read operation can be broadly classified into three categories:
1. Legacy, SPI-compatible (SPI-xy-S) protocols,
2. SPI-compatible protocols with bus width options (SPI-xy-D and SPI-xy-Q), and
3. Source-synchronous (SRC) protocols
7.5.3.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
As shown in Table 5, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI-
01-S, SPI-10-S, or SPI-11-S) to read data from the device.
Table 5. SPI Protocols for Reading From the Device
SCLK POLARITY
(At CS Falling
Edge)
SCLK PHASE
(Capture Edge)
MSB BIT
LAUNCH EDGE
PROTOCOL
SDI_CNTL
SDO_CNTL
DIAGRAM
SPI-00-S
SPI-01-S
SPI-10-S
SPI-11-S
Low
Low
High
High
Rising
Falling
Falling
Rising
CS falling
1st SCLK rising
CS falling
00h
01h
02h
03h
00h
00h
00h
00h
Figure 57
Figure 58
Figure 59
Figure 60
1st SCLK falling
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data
read and data write operations. To select a different SPI-compatible protocol for both the data transfer
operations:
1. Program the SDI_MODE[1:0] bits in the SDI_CNTL register. This first write operation must adhere to the SPI-
00-S protocol. Any subsequent data transfer frames must adhere to the newly selected protocol.
2. Set the SDO_MODE[1:0] bits = 00b in the SDO_CNTL register.
When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer frame;
see the Timing Requirements: SPI-Compatible Serial Interface table for associated timing parameters.
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Figure 57, Figure 58, Figure 59, and Figure 60 explain the details of the four protocols using an optimal, 20-
SCLK frame. As explained in the Data Transfer Frame section, the host controller can use a short data transfer
frame to read only the required number of MSB bits from the 20-bit output data word.
With SDO_CNTL[7:0] = 00h, if the host controller uses a long data transfer frame, the device exhibits daisy-chain
operation (see the Multiple Devices: Daisy-Chain Topology section).
D19
CS
SCLK
SDO-0
RVS
CS
SCLK
SDO-0
RVS
D19
D18
D1
D0
D18
D17
D1
D0
D19
D18
D17
D0
D19
D19
D18
D18
D17
D1
D0
D1
D0
0
D19
D18
D1
D0
Figure 57. SPI-00-S Protocol, 20 SCLKs
Figure 58. SPI-01-S Protocol, 20 SCLKs
D19
CS
SCLK
SDO-0
RVS
CS
SCLK
SDO-0
RVS
D19
D18
D17
D1
D0
D19
D18
D17
D1
D0
D19
D19
D18
D18
D2
D1
D0
D18
D17
D1
D0
0
D2
D1
D0
D19
D18
D1
D0
Figure 60. SPI-11-S Protocol, 20 SCLKs
Figure 59. SPI-10-S Protocol, 20 SCLKs
7.5.3.2.2 SPI-Compatible Protocols with Bus Width Options
The device provides an option to increase the SDO bus width from one bit (default, single SDO) to two bits (dual
SDO) or to four bits (quad SDO) when operating with any of the four legacy, SPI-compatible protocols.
Set the SDO_WIDTH[1:0] bits in the SDO_CNTL register to select the SDO bus width.
In dual SDO mode (SDO_WIDTH[1:0] = 10b), two bits of data are launched on the two SDO pins (SDO-0 and
SDO-1) on every SCLK launch edge.
In quad SDO mode (SDO_WIDTH[1:0] = 11b), four bits of data are launched on the four SDO pins (SDO-0,
SDO-1, SDO-2, and SDO-3) on every SCLK launch edge.
The SCLK launch edge depends upon the SPI protocol selection (as shown in Table 6).
Table 6. SPI-Compatible Protocols with Bus Width Options
SCLK POLARITY
(At CS Falling
Edge)
SCLK PHASE
(Capture Edge)
MSB BIT
LAUNCH EDGE
PROTOCOL
SDI_CNTL
SDO_CNTL
DIAGRAM
SPI-00-D
SPI-01-D
SPI-10-D
SPI-11-D
SPI-00-Q
SPI-01-Q
SPI-10-Q
SPI-11-Q
Low
Low
High
High
Low
Low
High
High
Rising
Falling
Falling
Rising
Rising
Falling
Falling
Rising
CS falling
First SCLK rising
CS falling
00h
01h
02h
03h
00h
01h
02h
03h
08h
08h
08h
08h
0Ch
0Ch
0Ch
0Ch
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
First SCLK falling
CS falling
First SCLK rising
CS falling
First SCLK falling
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When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer frame.
Figure 61 to Figure 68 illustrate how the wider data bus allows the host controller to read all 20 bits of the output
data word using short data transfer frames; see the Timing Requirements: SPI-Compatible Serial Interface table
for associated timing parameters.
NOTE
With SDO_CNTL[7:0] ≠ 00h, a long data transfer frame does not result in daisy-chain
operation.
CS
SCLK
SDO-1
SDO-0
RVS
CS
SCLK
SDO-1
SDO-0
RVS
D19
D18
D17
D16
D3
D2
D1
D0
0
0
D19
D18
D17
D16
D3
D2
D1
D0
Figure 61. SPI-00-D Protocol
Figure 62. SPI-01-D Protocol
CS
SCLK
SDO-1
SDO-0
RVS
CS
SCLK
SDO-1
SDO-0
RVS
D19
D18
D17
D16
D3
D2
D1
D0
0
0
D19
D18
D17
D16
D5
D4
D3
D1
D0
D2
Figure 64. SPI-11-D Protocol
Figure 63. SPI-10-D Protocol
CS
SCLK
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D19
D18
D17
D16
D15
D14
D13
D12
D3
D2
D1
D0
SDO-3
SDO-2
SDO-1
SDO-0
RVS
0
0
0
0
D19
D18
D17
D16
D15 D7
D14 D6
D13 D5
D12 D4
D3
D2
D1
D0
Figure 65. SPI-00-Q Protocol
Figure 66. SPI-01-Q Protocol
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CS
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D19
D18
D17
D16
D15
D14
D13
D12
D1
D0
D1
D0
0
0
0
0
D19
D18
D17
D16
D15
D14
D13
D12
D7
D6
D5
D4
D3
D2
D1
D0
Figure 68. SPI-11-Q Protocol
Figure 67. SPI-10-Q Protocol
7.5.3.2.3 Source-Synchronous (SRC) Protocols
As described in the Data Transfer Protocols section, the multiSPI interface supports an ADC-master or source-
synchronous mode of data transfer between the device and host controller. In this mode, the device provides an
output clock that is synchronous with the output data. Furthermore, the host controller can also select the output
clock source, data bus width, and data transfer rate.
7.5.3.2.3.1 Output Clock Source Options with SRC Protocols
In all SRC protocols, the RVS pin provides the output clock. The device allows this output clock to be
synchronous to either the external clock provided on the SCLK pin or to the internal clock of the device.
Furthermore, this internal clock can be divided by a factor of two or four to lower the data rates.
As shown in Figure 69, set the SSYNC_CLK_SEL[1:0] bits in the SDO_CNTL register to select the output clock
source.
SCLK
OSC
00
INTCLK
01
Output Clock
RVS
INTCLK / 2
INTCLK / 4
10
11
/ 2
/ 4
SSYNC_CLK_SEL [1:0]
Figure 69. Output Clock Source options with SRC Protocols
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7.5.3.2.3.2 Bus Width Options with SRC Protocols
The device provides an option to increase the SDO bus width from one bit (default, single SDO) to two bits (dual
SDO) or to four bits (quad SDO) when operating with any of the SRC protocols. Set the SDO_WIDTH[1:0] bits in
the SDO_CNTL register to select the SDO bus width.
In dual SDO mode (SDO_WIDTH[1:0] = 10b), two bits of data are launched on the two SDO pins (SDO-0 and
SDO-1) on every SCLK rising edge.
In quad SDO mode (SDO_WIDTH[1:0] = 11b), four bits of data are launched on the four SDO pins (SDO-0,
SDO-1, SDO-2, and SDO-3) on every SCLK rising edge.
7.5.3.2.3.3 Output Data Rate Options with SRC Protocols
The device provides an option to transfer the data to the host controller at single data rate (default, SDR) or at
double data rate (DDR). Set the DATA_RATE bit in the SDO_CNTL register to select the data transfer rate.
In SDR mode (DATA_RATE = 0b), the RVS pin toggles from low to high and the output data bits are launched
on the SDO pins on the output clock rising edge.
In DDR mode (DTA_RATE = 1b), the RVS pin toggles and the output data bits are launched on the SDO pins on
every output clock edge, starting with the first rising edge.
The device supports all 24 combinations of output clock source, bus width, and output data rate, as shown in
Table 7.
Table 7. SRC Protocol Combinations
OUTPUT CLOCK
SOURCE
OUTPUT DATA
RATE
PROTOCOL
BUS WIDTH
SDI_CNTL
SDO_CNTL
DIAGRAM
SRC-EXT-SS
SRC-INT-SS
SRC-IB2-SS
SRC-IB4-SS
SRC-EXT-DS
SRC-INT-DS
SRC-IB2-DS
SRC-IB4-DS
SRC-EXT-QS
SRC-INT-QS
SRC-IB2-QS
SRC-IB4-QS
SRC-EXT-SD
SRC-INT-SD
SRC-IB2-SD
SRC-IB4-SD
SRC-EXT-DD
SRC-INT-DD
SRC-IB2-DD
SRC-IB4-DD
SRC-EXT-QD
SRC-INT-QD
SRC-IB2-QD
SRC-IB4-QD
SCLK
INTCLK
Single
Single
Single
Single
Dual
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
03h
43h
83h
C3h
0Bh
4Bh
8Bh
CBh
0Fh
4Fh
8Fh
CFh
13h
53h
93h
D3h
1Bh
5Bh
9Bh
DBh
1Fh
5Fh
9Fh
DFh
Figure 70
INTCLK / 2
INTCLK / 4
SCLK
Figure 71
Figure 74
Figure 75
Figure 78
Figure 79
Figure 72
Figure 73
Figure 76
Figure 77
Figure 80
Figure 81
INTCLK
Dual
INTCLK / 2
INTCLK / 4
SCLK
Dual
Dual
Quad
Quad
Quad
Quad
Single
Single
Single
Single
Dual
INTCLK
INTCLK / 2
INTCLK / 4
SCLK
00h, 01h,
02h, or 03h
INTCLK
INTCLK / 2
INTCLK / 4
SCLK
INTCLK
Dual
INTCLK / 2
INTCLK / 4
SCLK
Dual
Dual
Quad
Quad
Quad
Quad
INTCLK
INTCLK / 2
INTCLK / 4
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CS
CS
SCLK
SDO-0
RVS
SCLK
D19
D18
D17
D1
D0
D19
D18
D2
D1
D0
D19
D18
D2
D1
D0
SDO-0
RVS
Figure 70. SRC-EXT-SS: SRC, SCLK, Single SDO, SDR
Figure 71. SRC-INT-SS: SRC, INTCLK, Single SDO, SDR
CS
SCLK
SDO-0
RVS
CS
SCLK
SDO-0
RVS
D18
D2
D0
D19
D17
D19 D18
D1
D3
D2
D1
D0
D19 D18
D3
D2
D1
D0
Figure 72. SRC-EXT-SD: SRC, SCLK, Single SDO, DDR
Figure 73. SRC-INT-SD: SRC, INTCLK, Single SDO, DDR
CS
SCLK
SDO-1
SDO-0
RVS
CS
SCLK
SDO-1
SDO-0
RVS
D19
D18
D17
D16
D5
D4
D3
D2
D1
D0
D19
D18
D17
D16
D5
D4
D3
D2
D1
D0
Figure 75. SRC-INT-DS: SRC, INTCLK, Dual SDO, SDR
Figure 74. SRC-EXT-DS: SRC, SCLK, Dual SDO, SDR
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CS
CS
SCLK
SDO-1
SDO-0
RVS
SCLK
SDO-1
SDO-0
RVS
D19 D17
D18 D16
D7
D6
D5
D4
D3
D2
D1
D0
D19 D17
D18 D16
D7
D6
D5
D4
D3
D2
D1
D0
Figure 76. SRC-EXT-DD: SRC, SCLK, Dual SDO, DDR
Figure 77. SRC-INT-DD: SRC, INTCLK, Dual SDO, DDR
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D7
D6
D5
D4
D3
D2
D1
D0
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D7
D6
D5
D4
D3
D2
D1
D0
D8
D8
Figure 78. SRC-EXT-QS: SRC, SCLK, Quad SDO, SDR
Figure 79. SRC-INT-QS: SRC, INTCLK, Quad SDO, SDR
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D19 D15 D11 D7
D18 D14 D10 D6
D3
D2
D1
D0
D19 D15 D11 D7
D18 D14 D10 D6
D3
D2
D1
D0
D17 D13 D9
D16 D12 D8
D5
D4
D17 D13 D9
D16 D12 D8
D5
D4
Figure 80. SRC-EXT-QD: SRC, SCLK, Quad SDO, DDR
Figure 81. SRC-INT-QD: SRC, INTCLK, Quad SDO, DDR
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7.5.4 Device Setup
The multiSPI interface and the device configuration registers offer multiple operation modes. This section
describes how to select the hardware connection topology to meet different system requirements.
7.5.4.1 Single Device: All multiSPI Options
Figure 82 shows the connections between a host controller and a stand-alone device to exercise all options
provided by the multiSPI interface.
DVDD
Isolation
(Optional)
RST
CONVST
CS
SCLK
SDI
Host
Controller
Device
SDO-0
SDO-1
SDO-2
SDO-3
RVS
Figure 82. MultiSPI Interface, All Pins
7.5.4.2 Single Device: Minimum Pins for a Standard SPI Interface
Figure 83 shows the minimum-pin interface for applications using a standard SPI protocol.
DVDD
Isolation
(Optional)
(Optional)
RST
(Optional)
CONVST
CS
SCLK
SDI
Host
Controller
Device
SDO-0
SDO-1
SDO-2
SDO-3
RVS
(Optional)
Figure 83. SPI Interface, Minimum Pins
The CS, SCLK, SDI, and SDO-0 pins constitute a standard SPI port of the host controller. The CONVST pin can
be tied to CS, or can be controlled independently for additional timing flexibility. The RST pin can be tied to
DVDD. The RVS pin can be monitored for timing benefits. The SDO-1, SDO-2, and SDO-3 pins have no external
connections.
40
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7.5.4.3 Multiple Devices: Daisy-Chain Topology
A typical connection diagram showing multiple devices in a daisy-chain topology is shown in Figure 84.
Host Controller
CS SCLK
CONVST
SDO
SDI
c
c
c
c
c
c
Device-1
Device-2
Device-N
Figure 84. Daisy-Chain Connection Schematic
The CONVST, CS, and SCLK inputs of all devices are connected together and controlled by a single CONVST,
CS, and SCLK pin of the host controller, respectively. The SDI input pin of the first device in the chain (Device-1)
is connected to the SDO pin of the host controller, the SDO-0 output pin of Device-1 is connected to the SDI
input pin of Device-2, and so forth. The SDO-0 output pin of the last device in the chain (Device-N) is connected
to the SDI pin of the host controller.
To operate multiple devices in a daisy-chain topology, the host controller must program the configuration
registers in each device with identical values and must operate with any of the legacy, SPI-compatible protocols
for data read and data write operations (SDO_CNT[7:0] = 00h). With these configurations settings, the 20-bit
OSR and 20-bit ISR registers collapse to form a single, 20-bit unified shift register (USR), as shown in Figure 85.
CS
20 Bits
SDI
Host Controller
DB19
DB18
DB1
DB0
Unified Shift Register
Interface Module
SCLK
SDO-0
Figure 85. Unified Shift Register Schematic
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All devices in the daisy-chain topology sample their analog input signals on the CONVST rising edge. The data
transfer frame starts with a CS falling edge. On each SCLK launch edge, every device in the chain shifts out the
MSB of its USR on to its SDO-0 pin. On every SCLK capture edge, each device in the chain shifts in data
received on its SDI pin as the LSB bit of its USR. Therefore, in a daisy-chain configuration, the host controller
receives the data of Device-N, followed by the data of Device-N-1, and so forth (in MSB-first fashion). On the CS
rising edge, each device decodes the contents in its USR and takes appropriate action.
A typical timing diagram for three devices connected in daisy-chain topology and using the SPI-00-S protocol is
shown in Figure 86.
CS
1
2
19
20
21
22
39
40
41
42
Configuration Data Device -1
B18 B1
Configuration Data Device -2
B38 B21
Configuration Data Device -3
B58 B41
Output Data œ Device 1
{D18}1 {D1}1
59
60
SCLK
{SDO}HOST
{SDI}1
B59
B58
B41
B40
B39
B38
B21
B20
B19
B0
{SDO-0}1
{SDI}2
{D19}1
{D19}2
{D19}3
{D18}1
{D18}2
{D1}1
{D1}2
{D0}1
{D0}2
{D0}3
B59
B58
B41
B40
{D0}1
{D0}2
B39
B59
B20
B40
{SDO-0}2
{SDI}3
{D19}1
{D19}2
{D18}1
{D1}1
Output Data œ Device 3
{D18}3 {D1}3
Output Data œ Device 2
{D18}2 {D1}2
{SDO-0}3
{SDI}HOST
{D19}1
{D0}1
Figure 86. Three Devices in Daisy-Chain Mode Timing Diagram
For N devices connected in daisy-chain topology, an optimal data transfer frame must contain 20 × N SCLK
capture edges. For a longer data transfer frame, the host controller must appropriately align the configuration
data for each device before bringing CS high. A shorter data transfer frame can result in an erroneous device
configuration, and must be avoided.
Note that the overall throughput of the system is proportionally reduced with the number of devices connected in
a daisy-chain topology.
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7.5.4.4 Multiple Devices: Star Topology
A typical connection diagram showing multiple devices in the star topology is shown in Figure 87. The CONVST,
SDI, and SCLK inputs of all devices are connected together and are controlled by a single CONVST, SDO, and
SCLK pin of the host controller, respectively. Similarly, the SDO output pin of all devices are tied together and
connected to the a single SDI input pin of the host controller. The CS input pin of each device is individually
controlled by separate CS control lines from the host controller.
Host Controller
Device N
Device 2
Device 1
Figure 87. Star Topology Connection Schematic
The timing diagram for N devices connected in the star topology is shown in Figure 88. In order to avoid any
conflict related to multiple devices driving the SDO line at the same time, ensure that the host controller pulls
down the CS signal for only one device at any particular time.
1
2
19
20
21
22
39
40
41
42
59
60
SCLK
{CS}1
{CS}2
{CS}3
Configuration Data Device -1
{B18}1 {B1}1
Output Data œ Device 1
{D18}1 {D1}1
Configuration Data Device -2
{B18}2 {B1}2
Output Data œ Device 2
{D18}2 {D1}2
Configuration Data Device -3
{B18}3 {B1}3
Output Data œ Device 3
{D18}3 {D1}3
{SDO}HOST
{SDI}1,2,3
{B19}1
{D19}1
{B0}1
{B19}2
{B0}2
{B19}3
{B0}3
{SDO-0}1,2,3
{SDI}HOST
{D0}1
{D19}2
{D0}2
{D19}3
{D0}3
Figure 88. Three Devices Connected in Star Connection Timing Diagram
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7.6 Register Maps
7.6.1 Device Configuration and Register Maps
The device features four configuration registers, mapped as described in Table 8.
Table 8. Configuration Registers Mapping
REGISTER
NAME
ADDRESS
REGISTER FUNCTION
SECTION
010h
014h
018h
01Ch
PD_CNTL
SDI_CNTL
SDO_CNTL
DATA_CNTL
Low-power modes control register
SDI input protocol selection register
SDO output protocol selection register
Output data word configuration register
PD Control
SDI Control
SDO Control
DATA Control
7.6.1.1 PD_CNTL Register (address = 010h)
This register controls the low-power modes offered by the device and is protected using a key.
Any writes to the PD_CNTL register must be preceded by a write operation with the register address set to 011h
and the register data set to 69h.
Figure 89. PD_CNTL Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
NAP_EN
R/W-0b
PDWN
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. PD_CNTL Register Field Descriptions
Bit
7-2
1
Field
0
Type
R
Reset
000000b
0b
Description
Reserved bits. Reads return 000000b.
NAP_EN
R/W
This bit enables NAP mode for the device.
0b = NAP mode is disabled
1b = NAP mode is enabled
0
PDWN
R/W
0b
This bit outputs the device in power-down mode.
0b = Device is powered up
1b = Device is powered down
7.6.1.2 SDI_CNTL Register (address = 014h)
This register configures the protocol used for writing data into the device.
Figure 90. SDI_CNTL Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SDI_MODE[1:0]
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. SDI_CNTL Register Field Descriptions
Bit
7-2
1-0
Field
Type
R
Reset
Description
0
000000b Reserved bits. Reads return 000000b.
SDI_MODE[1:0]
R/W
00b
These bits select the protocol for writing data into the device.
00b = Standard SPI with CPOL = 0 and CPHASE = 0
01b = Standard SPI with CPOL = 0 and CPHASE = 1
10b = Standard SPI with CPOL = 1 and CPHASE = 0
11b = Standard SPI with CPOL = 1 and CPHASE = 1
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7.6.1.3 SDO_CNTL Register (address = 018h)
This register configures the protocol for reading data from the device.
Figure 91. SDO_CNTL Register
7
6
5
0
4
3
2
1
0
SSYNC_CLK_SEL[1:0]
R/W-00b
DATA_RATE
R/W-0b
SDO_WIDTH[1:0]
R/W-00b
SDO_MODE[1:0]
R/W-00b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. SDO_CNTL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
SSYNC_CLK_SEL[1:0]
R/W
00b
These bits select the source and frequency of the clock for the source-
synchronous data transmission and are valid only if SDO_MODE[1:0] =
11b.
00b = External SCLK echo
01b = Internal clock (INTCLK)
10b = Internal clock / 2 (INTCLK / 2)
11b = Internal clock / 4 (INTCLK / 4)
5
4
0
R
0b
0b
This bit must be always set to 0.
DATA_RATE
R/W
This bit is ignored if SDO_MODE[1:0] = 00b. When SDO_MODE[1:0] =
11b:
0b = SDOs are updated at single data rate (SDR) with respect to the
output clock
1b = SDOs are updated at double data rate (DDR) with respect to the
output clock
3-2
1-0
SDO_WIDTH[1:0]
SDO_MODE[1:0]
R/W
R/W
00b
00b
These bits set the width of the output bus.
0xb = Data are output only on SDO-0
10b = Data are output only on SDO-0 and SDO-1
11b = Data are output on SDO-0, SDO-1, SDO-2, and SDO-3
These bits select the protocol for reading data from the device.
00b = SDO follows the same SPI protocol as SDI; see the SDI_CNTL
register
01b = Invalid configuration, not supported by the device
10b = Invalid configuration, not supported by the device
11b = SDO follows the source-synchronous protocol
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7.6.1.4 DATA_CNTL Register (address = 01Ch)
This register configures the contents of the 20-bit output data word (D[19:0]).
Figure 92. DATA_CNTL Register
7
0
6
0
5
4
3
2
1
0
FPAR_LOC 0
R/W-00b
PAR_EN
R/W-0b
DATA_PATN[2:0]
R/W-000b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. DATA_CNTL Register Field Descriptions
Bit
7-6
5-4
Field
Type
R
Reset
00b
Description
0
Reserved bits. Reads return 00b.
FPAR_LOC[1:0]
R/W
00b
These bits control the data span for calculating the FTPAR bit (bit D[0] in
the output data word).
00b = D[0] reflects even parity calculated for 4 MSB bits
01b = D[0] reflects even parity calculated for 8 MSB bits
10b = D[0] reflects even parity calculated for 12 MSB bits
11b = D[0] reflects even parity calculated for 16 MSB bits
3
PAR_EN
R/W
R/W
0b
0b = Output data does not contain any parity information
spaceD[1] = 0
spaceD[0] = 0
1b = Parity information is appended to the LSB of the output data
spaceD[1] = Even parity calculated on bits D[19:2]
spaceD[0] = Even parity computed on the selected number of MSB bits of
D[19:2] as per the FPAR_LOC[1:0] setting
See Figure 46 for further details of parity computation.
2-0
DATA_PATN[2:0]
000b
These bits control bits D[19:2] of the output data word.
0xxb = 18-bit conversion output
100b = All 0s
101b = All 1s
110b = Alternating 0s and 1s (that is, 15555h)
111b = Alternating 00s and 11s (that is, 03333h)
See Figure 47 for more details.
46
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, followed by an application circuit designed
using the ADS9110.
8.1.1 ADC Input Driver
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input signal and its low output impedance provides a
buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate the
sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing
filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is
critical to meet the linearity and noise performance of the ADS9110.
8.1.2 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance
goals of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate
amplifier to drive the inputs of the ADC are:
•
Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter (see the
Antialiasing Filter section) at the inputs of the ADC. Higher bandwidth also minimizes the harmonic distortion
at higher input frequencies. In order to maintain the overall stability of the input driver circuit, select the
amplifier with Unity Gain Bandwidth (UGB) as described in Equation 14:
≈
’
1
∆
∆
÷
÷
UGB í 4 ì
2p
ì RFLT ìCFLT
«
◊
(14)
•
Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in
SNR performance of the system. Generally, to ensure that the noise performance of the data acquisition
system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be
kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-limited by
designing a low cutoff frequency RC filter, as explained in Equation 15.
2
SNR
(
dB
)
≈
∆
’
÷
V
≈
∆
’
÷
-
1
_ AMP_PP
p
2
1
5
VREF
2
20
+ en2_RMS
ì
ì f-3dB
Ç
ì
ì10
f
«
◊
NG ì 2 ì
∆
∆
÷
÷
6.6
«
◊
where:
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µV,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit that is equal to 1 in a buffer configuration.
(15)
•
Distortion. Both the ADC and the input driver introduce distortion in a data acquisition block. To ensure that
the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of
the input driver must be at least 10 dB lower than the distortion of the ADC, as shown in Equation 16.
THDAMP Ç THDADC - 10
dB
(16)
47
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Application Information (continued)
•
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle within an 18-bit accuracy at the device inputs during the acquisition time window. This condition is
critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify
the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 18-bit
accuracy. Therefore, always verify the settling behavior of the input driver by TINA™-SPICE simulations
before selecting the amplifier.
8.1.3 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher-frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the
harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a
low-pass, RC filter, where the 3-dB bandwidth is optimized based on specific application requirements. For dc
signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow
accurately settling the signal at the inputs of the ADC during the small acquisition time window. For ac signals,
keep the filter bandwidth low to band-limit the noise fed into the input of the ADC, thereby increasing the signal-
to-noise ratio (SNR) of the system.
Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling
charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected from
each input pin of the ADC to the ground (as shown in Figure 93). This capacitor helps reduce the sampling
charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during
the acquisition process. Generally, the value of this capacitor must be at least 15 times the specified value of the
ADC sampling capacitance. For the ADS9110, the input sampling capacitance is equal to 60 pF, thus it is
recommeded to keep CFLT greater than 900 pF. The capacitor must be a COG- or NPO-type because these
capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying
voltages, frequency, and time.
RFLT ≤ 10 ꢀ
AINP
CFLT ≥ 900 pF
1
f-3dB
=
Device
2
p
ì RFLT ì CFLT
AINM
CFLT ≥ 900 pF
RFLT ≤ 10 ꢀ
GND
Figure 93. Antialiasing Filter Configuration
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For the ADS9110, limiting the value of RFLT to a maximum of 10-Ω is recommended
in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors must
be kept less than 1% to keep the inputs balanced.
The driver amplifier must be selected such that its closed-loop output impedance is at least 5X lesser than the
RFLT
.
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Application Information (continued)
8.1.4 ADC Reference Driver
The external reference source to the ADS9110 must provide low-drift and very accurate voltage for the ADC
reference input and support the dynamic charge requirements without affecting the noise and linearity
performance of the device. The output broadband noise of most references can be in the order of a few hundred
μVRMS. Therefore, to prevent any degradation in the noise performance of the ADC, the output of the voltage
reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few hundred hertz.
After band-limiting the noise of the reference circuit, the next important step is to design a reference buffer that
can drive the dynamic load posed by the reference input of the ADC. The reference buffer must regulate the
voltage at the reference pin such that the value of VREF stays within the 1-LSB error at the start of each
conversion. This condition necessitates the use of a large capacitor, CBUF_FLT (see Figure 39), between each
pair of REFP and REFM pins for regulating the voltage at the reference input of the ADC. The effective
capacitance of any large capacitor reduces with the applied voltage based on the voltage rating and type. Using
X7R-type capacitors is strongly recommended.
The amplifier selected as the reference driver must have an extremely low offset and temperature drift with a low
output impedance to drive the capacitor at the ADC reference pins without any stability issues.
Copyright © 2015, Texas Instruments Incorporated
49
ADS9110
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
www.ti.com.cn
8.2 Typical Application
30 kꢀ
Reference Drive Circuit
10 pF
0.1 µF
499 ꢀ
1 kꢀ
-
4.7 ꢀ
OPA+
-
OPA625
+
2.49 kꢀ
4.99 kꢀ
+
OPA378
+
1 kꢀ
REF5045
+
220 nF
OPA+
(See Reference Datasheet
for Detailed Pin Configuration)
OPA+
0.1 µF
1 µF
1 nF
10 µF
1 kꢀ
10 µF
10 µF
1 kꢀ
1.18 VDC
1 µF
-
10 nF
-VDIFF/2
REFM REFP REFP REFM
OPA625
2.2 ꢀ
AINP
+
CONVST
VINCM = 0 V
Device
CONVST
AINM
+
2.2 ꢀ
OPA625
GND
AVDD
DVDD
10 nF
+VDIFF/2
-
1 kꢀ
AVDD DVDD
GND
1 kꢀ
Input Driver
SAR ADC
1 nF
Figure 94. Differential Input DAQ Circuit for Lowest Distortion and Noise at 2 MSPS
8.2.1 Design Requirements
Design an application circuit optimized for using the ADS9110 to achieve:
•
•
•
> 98.5-dB SNR, < –118-dB THD,
±1-LSB linearity, and
Maximum-specified throughput of 2 MSPS
50
Copyright © 2015, Texas Instruments Incorporated
ADS9110
www.ti.com.cn
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
Typical Application (continued)
8.2.2 Detailed Design Procedure
The application circuits are illustrated in Figure 94. For simplicity, power-supply decoupling capacitors are not
shown in these circuit diagrams; see the Power-Supply Recommendations section for suggested guidelines.
The input signal is processed through the OPA625 (a high-bandwidth, low-distortion, high-precision amplifier in
an inverting gain configuration) and a low-pass RC filter before being fed into the ADC. Generally, the distortion
from the input driver must be at least 10 dB less than the ADC distortion. The distortion resulting from variation in
the common-mode signal is eliminated by using the OPA625 in an inverting gain configuration. The low-power
OPA625 as an input driver provides exceptional ac performance because of its extremely low-distortion and high-
bandwidth specifications. To exercise the complete dynamic range of the ADS9110, the common-mode voltage
at the ADS9110 inputs is established at a value of 2.25 V (4.5 V / 2) by using the noninverting pins of the
OPA625 amplifiers.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal.
The reference driver circuit, illustrated in Figure 94, generates a voltage of 4.5 VDC using a single 5-V supply.
This circuit is suitable to drive the reference of the ADS9110 at higher sampling rates up to 2 MSPS. The
reference voltage of 4.5 V in this design is generated by the high-precision, low-noise REF5045 circuit. The
output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160
Hz.
The reference buffer is designed with the OPA625 and OPA378 in a composite architecture to achieve superior
dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier.
The OPA625 is a high-bandwidth amplifier with a very low open-loop output impedance of 1 Ω up to a frequency
of 1 MHz. The low open-loop output impedance makes the OPA625 a good choice for driving a high capacitive
load to regulate the voltage at the reference input of the ADC. The relatively higher offset and drift specifications
of the OPA625 are corrected by using a dc-correcting amplifier (the OPA378) inside the feedback loop. The
composite scheme inherits the extremely low offset and temperature drift specifications of the OPA378.
8.2.3 Application Curves
1
0.75
0.5
0
œ40
0.25
0
œ80
œ120
œ160
œ200
-0.25
-0.5
-0.75
-1
0
200
400
600
800
1000
œ131072
C031
C030
fIN, Input Frequency (kHz)
ADC Output Code
Typical INL of ±0.5 LSB
fIN = 2 kHz, SNR = 99 dB, THD = –120 dB
Figure 96. Typical INL
Figure 95. FFT with a 2-kHz Input Signal
Copyright © 2015, Texas Instruments Incorporated
51
ADS9110
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
www.ti.com.cn
9 Power-Supply Recommendations
The device has two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on
AVDD; DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the
permissible range.
9.1 Power-Supply Decoupling
The AVDD and DVDD supply pins cannot share the same decoupling capacitor. As shown in Figure 97, separate
1-μF ceramic capacitors are recommended. These capacitors avoid digital and analog supply crosstalk resulting
from dynamic currents during conversion and data transfer.
Digital
Supply
16
DVDD
15
GND
AVDD
AVDD
1 µF
1 µF
14
13
Analog
Supply
Figure 97. Supply Decoupling
9.2 Power Saving
In normal mode of operation, the device does not power down between conversions, and therefore achieves a
high throughput of 2 MSPS. However, the device offers two programmable low-power modes (NAP and PD) to
reduce power consumption when the device is operated at lower throughput rates. Figure 98 shows comparative
power consumption between the different modes of the device.
tconv
CNV
tacq
tnap
tpd
Device Phase
ACQ
NAP
PD
~1.5X
~10X
~5000X
IAVDD
~1800X
IREF
Figure 98. Power Consumption in Different Operating Modes
52
Copyright © 2015, Texas Instruments Incorporated
ADS9110
www.ti.com.cn
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
Power Saving (continued)
9.2.1 NAP Mode
In NAP mode, some of the internal blocks of the device power down to reduce power consumption in the ACQ
state.
To enable NAP mode, set the NAP_EN bit in the PD_CNTL register. To exercise NAP mode, keep the CONVST
pin high at the end of conversion process. The device then enters NAP mode at the end of conversion and
continues in NAP mode until the CONVST pin is held high.
A CONVST falling edge brings the device out of NAP mode; however, the host controller can initiate a new
conversion (CONVST rising edge) only after the tnap_wkup time has elapsed.
Figure 99 shows a typical conversion cycle with NAP mode enabled (NAP_EN = 1b).
Sample
S
Sample
S+1
twh_CONVST
twl_CONVST
CONVST
tcycle
tnap
tconv
tnap_wkup
tacq
tconv_max
tconv_min
ADCST
(Internal)
CNV C
NAP + ACQ C+1
ACQ C+1
CS
RVS
t = 0
Figure 99. NAP Enabled Conversion Cycle
The cycle time is given by Equation 17.
tcycle = tconv + tnap + tnap_wkup
(17)
At lower throughputs, cycle time (tcycle) increases but the conversion time (tconv) remains constant, and therefore
the device spends more time in NAP mode, thus giving power scaling with throughput as shown in Figure 100.
8
6
Without
NAP
4
2
With
NAP
0
2000
1600
1200
800
400
0
C027
fS, Throughput (kSPS)
Figure 100. Power Scaling with Throughput with NAP Mode
Copyright © 2015, Texas Instruments Incorporated
53
ADS9110
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
www.ti.com.cn
Power Saving (continued)
9.2.2 PD Mode
The device also features a deep power-down mode (PD) to reduce the power consumption at very low
throughput rates.
To enter PD mode:
1. Write 069h to address 011h to unlock the PD_CNTL register.
2. Set the PDWN bit in the PD_CNTL register. The device enters PD mode on the CS rising edge.
In PD mode, all analog blocks within the device are powered down; however, the interface remains active and
the register contents are also retained. The RVS pin is high, indicating that the device is ready to receive the
next command.
To exit PD mode:
1. Reset the PDWN bit in the PD_CNTL register.
2. The RVS pin goes high, indicating that the device has started coming out of PD mode. However, the host
controller must wait for the tPWRUP time to elapse before initiating a new conversion.
10 Layout
10.1 Layout Guidelines
This section provides some recommended layout guidelines for achieving optimum performance with the
ADS9110 device.
10.1.1 Signal Path
As illustrated in Figure 101, the analog input and reference signals are routed in opposite directions to the digital
connections. This arrangement prevents noise generated by digital switching activity from coupling to sensitive
analog signals.
10.1.2 Grounding and PCB Stack-Up
Low inductance grounding is critical for achieving optimum performance. Grounding inductance is kept below 1
nH with 15-mil grounding vias and a printed circuit board (PCB) layout design that has at least four layers. Place
all critical components of the signal chain on the top layer with a solid analog ground from subsequent inner
layers to minimize via length to ground.
Pins 11 and 15 of the ADS9110 can be easily grounded with very low inductance by placing at least four 8-mil
grounding vias at the ADS9110 thermal pad. Afterwards, pins 11 and 15 can be connected directly to the
grounded thermal path.
10.1.3 Decoupling of Power Supplies
Place the AVDD and DVDD supply decoupling capacitors within 20 mil from the supply pins and use a 15-mil via
to ground from each capacitor. Avoid placing vias between any supply pin and its decoupling capacitor.
10.1.4 Reference Decoupling
Dynamic currents are also present at the REFP and REFM pins during the conversion phase and excellent
decoupling is required to achieve optimum performance. Three 10-μF, X7R-grade, ceramic capacitors with 10-V
rating are recommended, placed as illustrated in Figure 101. Select 0603- or 0805-size capacitors to keep ESL
low. The REFM pin of each pair must be connected to the decoupling capacitor before a ground via.
10.1.5 Differential Input Decoupling
Dynamic currents are also present at the differential analog inputs of the ADS9110. C0G- or NPO-type
capacitors are required to decouple these inputs because their capacitance stays almost constant over the full
input voltage range. Lower quality capacitors (such as X5R and X7R) have large capacitance changes over the
full input voltage range that can cause degradation in the performance of the ADS9110.
54
Copyright © 2015, Texas Instruments Incorporated
ADS9110
www.ti.com.cn
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
10.2 Layout Example
GND
10 mF
Digital Inputs
and Outputs
REFP
REFM
Reset
Convert Start
5 4
1
7
8
Chip Select
Serial Clock
Data In
REFM
REFM
GND
GND
AINP
Multi Function
Data Out 0
Data Out 1
GND
AINN
Data Out 2
Data Out 3
+
AVDD
Differential
Analog Input
DVDD
-
GND
GND
GND
Figure 101. Recommended Layout
版权 © 2015, Texas Instruments Incorporated
55
ADS9110
ZHCSE95A –OCTOBER 2015–REVISED OCTOBER 2015
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
《OPA378 数据表》，SBOS417
《OPA625 数据表》，SBOS688
《REF5045 数据表》（文献编号 SBOS410）
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
multiSPI, TINA, E2E are trademarks of Texas Instruments.
SPI is a trademark of Motorola Mobility LLC.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
56
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IMPORTANT NOTICE
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Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS9110IRGER
ADS9110IRGET
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
ADS9110
ADS9110
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
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