AFE1302Y/2K [TI]
ADSL ANALOG FRONT-END; ADSL模拟前端型号: | AFE1302Y/2K |
厂家: | TEXAS INSTRUMENTS |
描述: | ADSL ANALOG FRONT-END |
文件: | 总13页 (文件大小:221K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AFE1302
A
F
E
1
3
0
2
www.ti.com
ADSL ANALOG FRONT-END
● 8.8M TO 1.1MWords/s WORD RATE
FEATURES
● FIVE GENERAL-PURPOSE OUTPUTS
● 570mW POWER DISSIPATION
● TQFP-48 PACKAGE
● NOISE FLOOR: –144dBm/Hz
● MULTIRATE COMPATIBLE
● VCXO CIRCUITRY AND DAC
DESCRIPTION
This IC operates on a single 5V supply. The digital
circuitry in the unit can be connected to a supply voltage
ranging from 3.3V to 5V. The chip uses only 570mW.
Burr-Brown’s Analog Front-End from Texas Instru-
ments reduces the size and cost of an ADSL-compliant
system by providing the active analog circuitry needed
to connect an ADSL Digital Signal Processor (DSP) to
an external line driver, receiver, TX/RX filters, hy-
brid, transformer, and POTS filter. The AFE1302 is
designed for downstream data rates of 4Mbps and
higher, and operation at a clock rate of 35.328MHz,
with an output word rate of up to 8.832MWords/s.
The AFE1302 is designed to be used with external
amplifiers and filters for noise reduction and dynamic-
range improvement.
The RX channel consists of a low-noise PGA, a switched
capacitor low-pass filter, and fourth-order delta-sigma
Analog-to-Digital Converter (ADC). The delta-sigma
modulator operating at a 32X oversampling ratio pro-
duces a 16-bit output at word rates up to 8832kHz.
Functionally, this unit consists of a transmit (TX) chan-
nel, a receive (RX) channel, a VCXO (Voltage Con-
trolled Crystal Oscillator) control Digital-to-Analog
Converter (DAC), and VCXO active circuitry. The TX
section converts, filters, and buffers outgoing Discrete
Multi Tone (DMT) data from the ADSL DSP.
The receive section amplifies, filters, and digitizes the
DMT data received on the twisted pair line.
The TX channel consists of a fourth-order delta-sigma
DAC, switched-capacitor low-pass filter, program-
mable attenuator, and buffer. The buffer drives off-
chip into a low-noise line driver configured as a 3-pole
active filter to produce an overall low-noise high-drive
TX output signal on a twisted pair line.
Patents Pending
AFE1302
Interpolation
Filter
16-Bit
DAC
LP
Filter
Buffer
Atten
TX Output
Digital
Loopback
Decimation
Filter
16-Bit
ADC
LP
Filter
Analog
Loop Back
PGA
RX Input
5
General Purpose
Digital Output
Digital
Interface
VCXO
DAC
VCXO
Active Ckts
From DSP
Copyright © 2000, Texas Instruments Incorporated
SBWS014
Printed in U.S.A. December, 2000
SPECIFICATIONS
Typical at 25°C, AVDD = +5V, DVDD = +3.3V, fCLK = 35.328MHz, TX output and RX input measured differentially, unless otherwise specified.
AFE1302Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RECEIVE CHANNEL
Input Signal (CMV = AVDD/2)
Common-Mode Voltage
Input Impedance
Differential, G = –6dB
Pin-to-AVDD
9.0
9.6
AVDD/2
2.8
Vp-p
V
kΩ
Input Capacitance
30
pF
Programmable Amplifier Range
Gain Step Size
Input Noise
–6
40
dB
dB
Monotonicity Guaranteed
PGA = +40dB(1)
1
–148
–144
8.832
16
dBm/Hz
MWords/s
Bits
MSamples/s
MHz
dB
Output Word Rate
1.104
Output Word Resolution
ADC Sampling Rate
Low-Pass Frequency Corner
Passband Droop
(15 Bits + 1 Sign Bit) or (14 Bits + 2 Sign Bits)
35.328
One Pole Analog Filter
At 550kHz
1.1
1
SINAD
PGA Gain = 40dB, Input Referred
PGA Gain = 0dB
100
dB
dB
dB
dB
68
75
THD
Single Tone, PGA = 0dB
84
75
MTPR (MultiTone Power Ratio)
TRANSMIT CHANNEL
Input Word Rate
Input Word Resolution
Peak Signal Amplitude
Common-Mode Voltage
Load Resistance
1.104
4.4
8.832
16
MWords/s
Bits
Vp-p
(15 Bits + 1 Sign Bit) or (14 Bits + 2 Sign Bits)
Differential, G = 0dB
4.8
AVDD/2
400
Differential
Differential
Ω
pF
Load Capacitance
10
Programmable Attenuator Range
Attenuator Step Size
Attenuator Step Accuracy
Low-Pass Filter Corner Frequency
Passband Ripple
–31
0
dB
dB
dB
kHz
dB
Monotonicity Guaranteed
1.0
0.5
127
–0.1
Fourth-Order, 0.1dB Programmable
Group Delay Variation
Output Noise
10
µs
Measured at 50kHz
Measured at 200kHz
FS Output 0dB
FS Output –6dB
See Note (2)
–110
–116
65
73
–98
70
dBm/Hz
dBm/Hz
dBc
dBc
dBVrms
dB
THD Distortion
SFDR in RX Band (20 Tone Test)
MTPR
VCXO WITH EXTERNAL CIRCUITRY
Frequency
Tuning Range
Sensitive to PCB Layout
Monotonicity Guaranteed
35.328
±100
10
MHz
ppm
Bits
DAC Resolution
DIGITAL INTERFACE
Logic Levels
VIH
VIL
VOH
VOL
|IIH| < 10µA
|IIL| < 10µA
IOH = –20µA
IOL = 20µA
DVDD – 1
–0.3
DVDD – 0.5
DVDD
0
DVDD + 0.3
0.8
V
V
V
V
0.4
CONTROL INTERFACE (GC0, GC1, GP0, GP1, GP2)
Logic Levels
VOH
VOL
IOH = 1mA
IOL = 1mA
DVDD – 0.5
V
V
0.4
POWER
Analog Power Supply Voltage
Analog Dissipated Power
Digital Power Supply Voltage
Digital Dissipated Power
AVDD
4.75
3.0
5
5.25
5.5
V
mW
V
470
3.3
100
DVDD
VDD = 3.3V
mW
TEMPERATURE RANGE
Operation
0
70
°C
Thermal Resistance, θJA
56.5
°C/W
NOTES: (1) With TX in operation, no RX data, referred to 100Ω. (2) With TX reverb multitone signal (25.875kHz to 138kHz at a 4.3125kHz step), measured signal
level beyond 150kHz at TXP, TXN.
2
AFE1302
SBWS014
PIN CONFIGURATION
Top View
TQFP
48 47 46 45 44 43 42 41 40 39 38 37
CLWD
1
2
3
4
5
6
7
8
9
36 AVSS
35 TXP
4
CTRLIN
DVDD
1
1
34 AVDD
33 TXN
4
DVSS
TX3
TX2
TX1
TX0
RX3
32 AVSS
31 CMI
6
AFE1302
30 CMO
29 VREF1
28 VRNTX
27 VRPTX
26 VRNRX
25 VRPRX
RX2 10
RX1 11
RX0 12
13 14 15 16 17 18 19 20 21 22 23 24
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Analog Inputs: Current ............................................. ±100mA, Momentary
±10mA, Continuous
Voltage................................. AGND –0.3V to AVDD +0.3V
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Analog Outputs Short Circuit to Ground (+25°C) ................... Continuous
AVDD to AGND ....................................................................... –0.3V to 6V
DVDD to DGND ....................................................................... –0.3V to 6V
Digital Input Voltage to DGND ................................ –0.3V to DVDD +0.3V
Digital Output Voltage to DGND ............................. –0.3V to DVDD +0.3V
AGND, DGND, Differential Voltage.................................................... 0.3V
Junction Temperature (TJ) ............................................................ +150°C
Storage Temperature Range .........................................–40°C to +125°C
Lead Temperature (soldering, 3s) ................................................. +260°C
Power Dissipation .......................................................................... 700mW
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
AFE1302Y
TQFP-48
355
0°C to +70°C
AFE1302Y
AFE1302Y/250
AFE1302Y/2K
Tape and Reel
Tape and Reel
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “AFE1302Y/2K” will get a single 2000-piece Tape and Reel.
3
AFE1302
SBWS014
PIN DESCRIPTIONS
Number
Type
Pin Name
Description
External Connection
Analog Interface
23
24
19
20
25
26
30
27
28
29
31
35
33
40
41
43
44
Output
Output
Input
GC0
GC1
External Gain Control Output LSB
External Gain Control Output MSB
Analog Receive Negative Input
Analog Receive Positive Input
RX Reference Positive Output
RX Reference Negative Output
Output Common-Mode voltage
TX Reference Positive Output
TX Reference Negative Output
Unbuffered Bandgap Reference
Unbuffered Common-Mode Voltage
TX Positive Output
Optional Swap Amp
Optional Swap Amp
Line Interface
RXN
Input
RXP
Line Interface
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
—
VRPRX
VRNRX
CMO
0.1uF,1µF to AVSS
0.1uF,1µF to AVSS
0.1uF,1µF to AVSS
0.1uF,1µF to AVSS
0.1uF,1µF to AVSS
0.1uF,1µF to AVSS
0.1uF,1µF to AVSS
Line Interface
3
3
3
3
3
3
3
VRPTX
VRNTX
VREF1
CMI
TXP
TXN
TX Negative Output
Line Interface
VREF2
VCXO
XTALI
XTALO
DAC Reference Voltage
XTAL Interface
XTAL Interface
XTAL
VXCO Control Voltage DAC Output
XTAL Oscillator Input
—
XTAL Oscillator Output
XTAL
Digital Interface
48
47
1
Output
CLKM
CLKNIB
CLWD
CTRLIN
TX3
Master Clock Output, f = 35.328MHz
Nibble Clock Output
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
—
Output
Output
Input
Word Clock Output
2
Serial Data Input
5
Input
Digital Transmit Input
6
Input
TX2
Digital Transmit Input
7
Input
TX1
Digital Transmit Input
8
Input
TX0
Digital Transmit Input
9
Output
Output
Output
Output
Output
Input
RX3
Digital Receive Output
Digital Receive Output
Digital Receive Output
Digital Receive Output
Clipping Detection Output
Power-Down Select, “1” = Power Down
Reset Pin (Active LOW)
General-Purpose Output 2
General-Purpose Output 1
General-Purpose Output 0
10
11
12
13
14
15
16
17
18
RX2
RX1
RX0
CLIP
PDOWN
RESETN
GP2
Input
Output
Output
Output
GP1
—
GP0
—
Supply voltages
46
3
—
DVSS
2
Digital Ground 2
DGND Plane
3V or 5V
—
DVDD1
Digital Power
0.1uF,1µF to DVSS1
4
DVSS
1
3
Digital Ground 1
DGND Plane
21
22
32
34
36
37
38
39
42
45
5V
—
AVDD
Analog Power (Main)
Analog Ground (Main)
Analog Ground for TX Output
Analog Power for TX Output
Analog Ground for TX Output
Analog Clock Ground
Analog Clock Ground
Analog Clock Power
XTAL Power
0.1uF,1µF to AVSS
AGND Plane
3
4
AVSS3
AVSS
AVDD
AVSS4
—
6
AGND Plane
5V
—
4
0.1uF,1µF to AVSS
AGND Plane
—
AVSS
5
2
AGND Plane
—
AVSS
AGND Plane
5V
5V
—
AVDD
2
1
0.1uF,1µF to AVSS
0.1uF,1µF to AVSS
AGND Plane
2
1
AVDD
AVSS
1
XTAL Ground
4
AFE1302
SBWS014
To insure that TX distortion and noise do not degrade the
RX downstream performance, external filtering and trans-
hybrid loss of greater than 30dB is required. Refer to
Figure 6 for an external circuit and contract TI for a detailed
reference design document.
THEORY OF OPERATION
The AFE1302 consists of a transmit (TX) channel, a receive
(RX) channel, and a digital interface to connect to an ADSL
DSP. In addition, VCXO circuitry and a VCXO control
DAC are included for precise clock generation.
The TX channel receives digital data at the nominal rate of
1.104MWords/s to 8.832MWords/s. These TX data words
are interpolated up to the AFE1302 clock rate of 35.328MHz.
The data is converted to analog form with a 16-bit delta-
sigma DAC and bandwidth limited with a fourth-order,
switched-capacitor low-pass filter. The filter output is buff-
ered and drives off-chip to an external Burr-Brown line-
driver circuit from Texas Instruments. This line driver is
configured as an LC passive filter to provide additional out-
of-band noise and distortion attenuation (see System sec-
tion). Transmit power can be reduced with a combination of
digital and analog attenuation to ensure compliance with the
G.992.2 “politeness” rule.
DIGITAL DATA TRANSMISSION
Data is transmitted to the AFE1302 from the DSP on the
TX[0:3] lines, as shown in Figure 1. The Data TX[0:3]
changes during the rising edge of CLKM within the DSP,
and the Data are valid on the falling edge of CLKM for the
AFE to read. The minimum setup and hold time are 5ns (see
Figure 2); the start of a new sample is indicated by CLWD
being HIGH.
AFE1302
ADSL DSP
4
4
TX[0:3]
RX[0:3]
In the RX channel, the analog receive signal is input to a PGA.
The output of the first-order, switched capacitor filter is digi-
tized with a 16-bit delta-sigma ADC. A decimation filter
ensures a compliant word rate (1.104MWords/s to
8.832MWords/s) to the ADSL digital chip.
CTRLIN
Control
Register
Precise phase alignment is required to ensure proper opera-
tion of the ADSL modem. The active circuitry required to
create a VCXO is included on the AFE1302. This includes
the gain element as well as a 10-bit, monotonic DAC. The
only external components required are a varactor, load
capacitor, and crystal.
CLWD
CLKNIB
CLKM
÷4N
÷N
NOTE: N = 1, 2, 4, 8 set by control register.
TX DISTORTION AND NOISE REQUIREMENTS
The TX output is a DMT signal generated by the AFE1302.
This output contains the desired DMT signal in the TX
frequency band as well as unwanted noise and distortion in
both the TX and RX frequency bands. The inband TX
distortion and noise is specified by the MultiTone Power
Ratio (MTPR) test. Since MTPR is better than 70 dB, full-
rate ADSL performance is guaranteed for TX upstream
signals.
FIGURE 1. AFE1302/DSP Interface.
Data is transmitted to the DSP from the AFE1302 on the
RX[0:3] lines, as shown in Figure 1. The Data RX[0:3]
changes during the rising edge of CLKM within the AFE,
and the Data are valid on the falling edge of CLKM for the
DSP to read. The minimum setup and hold time are 5ns (see
Figure 2); the start of a new sample is indicated by CLWD
being HIGH.
However, TX distortion and noise can also limit down-
stream RX performance. TX noise and distortion can de-
grade RX signal quality since the TX output is connected to
the RX input through filters, line driver, and hybrid. Three
tests show out-of-band TX performance as used in the
ADSL system. Total harmonic distortion (THD) shows the
overall linearity of the TX signals. The next test uses a
typical ADSL DMT TX signal and measures the largest
distortion tone in the RX band. The largest distortion tone in
the RX band is –98 dBVrms or –124 dBm/Hz as measured
in a 4.3125 kHz bandwidth. In the last test, TX noise is
measured by transmitting no signal. Noise as shaped by the
TX filter is lower than –116dBm/Hz in the RX band.
During normal operation, a 16-bit TX data word is generated
by the DSP. This TX data is sent from the DSP to the AFE
via four serial lines TX[0:3]. Each serial line is clocked by
CLKM at 35.328MHz or by CLKNIB at 35.328MHz di-
vided by N. CLKNIB and CLWD can be changed by
programming N via the control register.
The RX word output rate and TX word input rate can be
changed by programming N in the control register for values
of 1, 2, 4, or 8. For instance, setting N = 1 sets the TX and
RX data word rate to 8.832Mwords/s.
5
AFE1302
SBWS014
CLKM/CLKNIB
CLWD
tS
tH
RX[0:3]/TX[0:3]
N0
N1
N2
N3
NOTE: CLKM = 35.328; For N = 1, CLKNIB = 35.328MHz, CLWD = 8.832MHz; tS: Setup Time, min tS = 5ns; tH: Hold Time, min tH = 5ns.
FIGURE 2. AFE1302 Transmit/Receive Timing Diagram.
TRANSMIT DATA
RECEIVE DATA
Transmit data TX[0:3] passed to the AFE1302 will be
Binary Two’s Complement with one or two sign bits de-
pending on bit 9 in the AFE1302 control register at address
001 (see Table V). Bit 9 = 0 is two sign bits and bit 9 = 1
is one sign bit. Please refer to Tables I and II.
Data RX[0:3] received from the AFE1302 will be in the
format shown in Tables III and IV:
BIT MAP\NIBBLE
N0
N1
N2
N3
RX0
RX1
RX2
RX3
data bit 0 (LSB) data bit 4
data bit 8 data bit 12
data bit 9 data bit 13
data bit 1
data bit 2
data bit 3
data bit 5
BIT MAP\NIBBLE
N0
N1
N2
N3
data bit 6 data bit 10 data sign
data bit 7 data bit 11 data sign
TX0
TX1
TX2
TX3
data bit 0 (LSB) data bit 4
data bit 8 data bit 12
data bit 9 data bit 13
data bit 1
data bit 2
data bit 3
data bit 5
TABLE III. AFE1302 RX Data Format, Address 001,
Bit 9 = 0.
data bit 6 data bit 10 data sign
data bit 7 data bit 11 data sign
TABLE I. AFE1302 TX Data Format, Address 001, Bit 9 = 0.
This corresponds to the internal data structure as follows
(sign bit is repeated):
This corresponds to the internal data structure as follows
(sign bit is repeated):
INTERNAL DATA BIT Sign Sign 13 12 11 10 9 8 7
EXTERNAL DATA BIT 15 14 13 12 11 10 9 8 7
6
6
5 4 3 2 1 0
5 4 3 2 1 0
INTERNAL DATA BIT 15 14 13 12 11 10 9 8 7
EXTERNAL DATA BIT Sign Sign 13 12 11 10 9 8 7
6
6
5 4 3 2 1 0
5 4 3 2 1 0
BIT MAP\NIBBLE
N0
N1
N2
N3
RX0
RX1
RX2
RX3
data bit 0 (LSB) data bit 4
data bit 8 data bit 12
data bit 9 data bit 13
BIT MAP\NIBBLE
N0
N1
N2
N3
data bit 1
data bit 2
data bit 3
data bit 5
TX0
TX1
TX2
TX3
data bit 0 (LSB) data bit 4
data bit 8 data bit 12
data bit 9 data bit 13
data bit 6 data bit 10 data bit 14
data bit 7 data bit 11 data sign
data bit 1
data bit 2
data bit 3
data bit 5
data bit 6 data bit 10 data bit 14
data bit 7 data bit 11 data sign
TABLE IV. AFE1302 RX Data Format, Address 001, Bit 9 = 1.
This corresponds to the internal data structure as follows:
TABLE II. AFE1302 TX Data Format, Address 001, Bit 9 = 1.
This corresponds to the internal data structure as follows:
INTERNAL DATA BIT Sign 14 13 12 11 10 9
EXTERNAL DATA BIT 15 14 13 12 11 10 9
8
8
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
INTERNAL DATA BIT
15 14 13 12 11 10 9
8
8
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
EXTERNAL DATA BIT Sign 14 13 12 11 10 9
6
AFE1302
SBWS014
CLIP EVENT
PROGRAMMING THE AFE1302
Receive data (AFEG_RX) is generated in the AFE1302 with
additional headroom. For the one sign-bit case, if AFEG_RX
data is greater than 7FFF, it will be clipped to 7FFF.
If AFEG_RX data is less than 8000, it will be clipped to
8000. For the two sign-bit case, if AFEG_RX data is greater
than 3FFF, it will be clipped to 3FFF. If AFEG_RX data is
less than C000, it will be clipped to C000. During clip, pin
CLIP will be asserted HIGH for monitoring purposes. Pin
CLIP will remain HIGH until 0 is written to address = 010,
bit 3 in AFE1302 control register.
The internal AFE control register, as shown in Table V, is
used to set the programmable features of the AFE1302 and to
set the VCXO frequency. Serial data is sent from the DSP to
the AFE control register on the CTRLIN pin in 16-bit blocks.
This data is clocked into the AFE1302 on the falling edge of
CLWD. AFEREG data is valid when followed by at least 16
stop bits (HIGH). The timing is shown in Figure 3. During
programming, all AFE1302 functions are active. Data ID
code 0 through 5 must be configured for normal operation;
data ID code 6 and 7 are reserved for future use.
CLWD
CTRLIN
Start Bit
12 Data Bits
Data ID
3 Bit
≥ 16 HIGH Stop Bits
CLWD
tS
tH
CTRLIN
NOTE: CLWD = 8.832MHz/N; tS: Setup Time, min tS = 10ns; tH: Hold Time, min tH = 10ns.
FIGURE 3. AFE1302 Program Timing.
7
AFE1302
SBWS014
START
BIT
DATA ID
DATA BITS
M
S
B
L
S
B
REGISTER DESCRIPTIONS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RX REGISTER
0
0
0
0
0
0
0
0
X
External Gain Control GC1 (1 Bit)
External Gain Control GC0 (1 Bit)
AGC RX Gain Setting –6dB (6 Bits)
AGC RX Gain Setting –5dB (6 Bits)
AGC RX Gain Setting X dB (6 Bits)
AGC RX Gain Setting 40dB (6 Bits)
X = 1, Filter Setting 1.1MWords/s; X = 0, Filter Setting 8.8MWords/s
Reserved, Must Be Set As Shown
X
0
0
X
1
0
0
X
0
0
0
X
1
0
0
X
1
0
0
X
1
0
1
X
0
X
0
0
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TX REGISTER
0
0
0
0
0
0
0
0
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
1
X
1
Transmit Attenuator Setting = 0dB (5 Bits)
Transmit Attenuator Setting = –1dB (5 Bits)
Transmit Attenuator Setting = X dB (5 Bits)
Transmit Attenuator Setting = –31dB (5 Bits)
GP2 (General-Purpose Output 2)
X
X
GP1 (General-Purpose Output 1)
X
GP0 (General-Purpose Output 0)
X
X = 1, RX and TX Data Format Has 1 Sign Bit and 15 Data Bits
X = 0, RX and TX Data Format Has 2 Sign Bits and 14 Data Bits
Reserved, Must Be Set As Shown
0
0
0
1
0
0
1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
AFE REGISTER
0
X
0
1
0
Digital Loopback TX to RX Through Digital Section (1 Bit)
X = 1, Loopback Mode; X = 0, Normal Operation Mode
Analog Loopback TX to RX Through Analog Section (1 Bit)
X = 1, Loopback Mode; X = 0, Normal Operation Mode
X = 1, RX Enable Mode
0
X
0
1
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
0
0
1
1
X
0
1
0
1
Data Word Clock Divider (2 Bits)
Data Word Clock = 8.832MHz (2 Bits)
Data Word Clock = 4.416MHz (2 Bits)
Data Word Clock = 2.208MHz (2 Bits)
Data Word Clock = 1.104MHz (2 Bits)
X
Clear CLIP Signal: X = 1, RX is Clipping; X = 0, CLIP Cleared
Reserved, Must Be Set As Shown
0
0
1
0
0
1
15 14 13 12 11 10
9
X
0
8
X
0
7
X
0
6
X
0
5
X
0
4
3
2
0
0
0
0
1
1
1
1
1
0
1
1
1
1
VCXO DAC VALUE REGISTER
VCXO DAC Input Word (10 Bits)
0
0
0
0
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
VCXO DAC Input Word = 0 (10 Bits)
VCXO DAC Input Word = +FS (10 Bits)
Reserved, Must Be Set As Shown
1
1
1
1
1
0
0
15 14 13 12 11 10
9
X
8
X
7
X
6
5
4
3
2
1
1
1
0
0
0
0
0
INTERFACE REGISTER
Reserved
0
X
X
X
X
X
0
X
X = 0, TX[3:0] Should Be Latched On Falling CLKNIB
X = 1, TX[3:0] Should Be Latched On Rising CLKNIB
X = 0, RX[3:0] Should Be Latched On Falling CLKNIB
X = 1, RX[3:0] Should Be Latched On Rising CLKNIB
Digital Loopback RX Into TX:
0
0
0
X
1
1
1
0
0
0
0
0
0
X
X = 1 Loopback Mode; X = 0 Normal Mode
Reserved, Must Be Set As Shown
0
15 14 13 12 11 10
9
0
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
1
0
1
1
0
1
0
1
RESERVED
Reserved, Must Be Set As Shown
0
0
0
1
X
X
1
X
X
1
X
X
1
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved, Data ID 6
Reserved, Data ID 7
NOTE: All registers are initially set to zero.
TABLE V. AFE1302 Control Register.
8
AFE1302
SBWS014
LAYOUT
DIGITAL-TO-ANALOG CONVERTER
The analog front-end of an ADSL system has a number of
conflicting requirements. It must accept and deliver digital
outputs at fairly high rates of speed, and convert the line
input to a high precision (14-bit) digital output. Thus, there
are two sections of the AFE1302: the digital section, and the
analog section. The recommended VCXO circuit layout is
shown in Figure 4.
The Digital-to-Analog Converter (DAC) data for the TX
channel is deserialized and written in four 4-bit registers and
coded in two’s complement, as shown in Table VI.
DAC/ADC HEXDATA
ANALOG I/O
1 SIGN BIT
Positive Full-Scale
Mid-Scale
7FFF
0000
8000
Negative Full-Scale
DIGITAL LAYOUT
TABLE VI. One Sign Bit.
The power supply for the digital section of the AFE1302 can
range from 3.3V to 5V. This supply should be decoupled to
digital ground with a ceramic 0.1µF capacitor placed as
close as possible to digital ground (DVSS) and digital power
(DVDD). Ideally, both a digital power-supply plane and a
digital ground plane should run to and underneath the digital
pins of the AFE1302. However, DVDD may be supplied by
a wide printed circuit board trace. A digital ground plane
underneath all digital pins is strongly recommended.
ANALOG-TO-DIGITAL CONVERTER
The Analog-to-Digital Converter (ADC) data from the RX
channel is stored in four 4-bit registers and coded in two’s
complement, as shown in Table VII.
DAC/ADC HEXDATA
ANALOG I/O
2 SIGN BITS
Positive Full-Scale
Mid-Scale
3FFF
0000
C000
ANALOG LAYOUT
Negative Full-Scale
The remaining portion of the AFE1302 should be considered
analog. Note that AVDD must be in the 4.75V to 5.25V
range. All AVSS pins should be connected directly to a
common analog ground plane and all AVDD pins should be
connected to an analog 5V power plane. Both of these planes
should have a low impedance path to the power supply. The
analog power-supply pins should be decoupled to analog
ground with both a 10µF tantalum capacitor and a 0.1µF
ceramic capacitor. The ceramic capacitors should be placed
as close to the AFE1302 as possible. The placement of the
tantalum capacitor is not as critical, but should be close to
the pin. In each case, the capacitor should be connected
between AVDD and AVSS.
TABLE VII. Two Sign Bits.
SCALABLE TIMING
The AFE1302 scales operation with the clock frequency.
All internal filters change frequency with the clock speed so
that the unit can be used at different frequencies just by
changing the clock speed.
For the RX channel, the digital filtering of the delta-sigma
converter scales directly with the clock speed. For the TX
channel, the power spectral density scales directly with the
clock rate. The transformer and external filter need to be
changed for different frequency requirements.
No Ground/Power Planes
Or Other Traces In This Area
Sensitive Points
Ground
Plane
To AFE1302 Pin #41
FIGURE 4. VCXO Circuit Layout, Approximately Two Times Actual Size.
9
AFE1302
SBWS014
proper system operation. An on-chip fourth-order low-pass
transmit filter has been included on the AFE1302 to reduce
transmit noise in the receive bandwidth. However, external
filtering, as shown in the reference design in Figure 6, is
required on the transmitter output to optimize the receive
path noise mask. The reference design circuit not only
implements extra filtering for the transmit noise, but also
includes the drivers necessary to achieve the G.992.2
specified +13dBm output power on the line, thus achieving
a minimum component solution.
SYSTEM
This analog front-end will give the best performance only
when included in an optimized system. This section de-
scribes external components that will work best with the
AFE1302. See Figure 5 for the basic connection diagram.
TRANSMIT
The key noise specification for an ADSL analog front-end
is the noise that is added to the RX channel. It is essential
to reduce the transmit noise that reaches the receiver for
VREF1 VRNRX VRPRX VRNTX VRPTX
CMO
CMI
ADSL DSP
TX[0:3]
RX[0:3]
TXP
TXN
GP0
GP1
AFE
Telephone Line
CTRLIN
CLWD
AFE1302
External
Circuit
GC0
GC1
RXP
CLKNIB
CLKM
RXN
DVDD1
AVDD1, 2, 3, and 4
3.3V to 5V Digital
5V Analog
FIGURE 5. Basic Connection Diagram.
AFE1302
CPE
0.8:1
UTP Line
LC Passive
TX Filter/Line Driver
HP POTS
CO
TX
Hybrid
Filter
DSP
Computer
G
High-Pass/
AA Filter
Receive
Amp
RX
G
FIGURE 6. CPE Block Diagram (contact factory for detatiled reference design).
10
AFE1302
SBWS014
separate the transmit and receive signals. When the AFE1302
drives long twisted-pair loops, the transmit signal is much
larger than the receive signal. The hybrid will ideally eliminate
all of the transmit signal at the receive input. However, for
poorly matched lines, the actual reduction may be quite small.
Without external filtering between the transmit output and the
receive input, the transmit signal will clip the receive input
before the on-chip receive filter can reduce the transmit signal.
Therefore, external receive filters are required to eliminate
transmit noise. Refer to Figure 6 for an external circuit and
contact the factory for a detailed reference design document.
The specifications for the complete system solution are given
in Table VIII. The numbers include the effects of both the
AFE1302 and the surrounding external components, includ-
ing a Burr-Brown TX line driver from Texas Instruments.
RECEIVE
Receive channel external components include a hybrid, receive
amplifier, fifth-order high-pass passive filter, and first-order,
low-pass, anti-alias filter. The ADSL system is frequency
division multiplexed on a single twisted pair. Filters are used to
ADSL FRONT-END SYSTEM PERFORMANCE
PARAMETER
CONDITIONS
VALUE
UNITS
TX PATH
Peak Signal Amplitude to Telephone Line
12
100
13
Vp-p
Ω
Load Impedance
Output Power
To Line (100Ω Match)
dBm
kHz
Low-Pass Filter Corner Frequency
Passband Ripple
127
3
dB
Group Delay Variation
Output Noise, Out of Band
15
ms
See Note (2)
–142
dBm/Hz
RX PATH
RX Input
MTPR
12.5
70
Vp-p
dB
Noise Floor
PGA = 40dB
–142
157
1.1
3
dBm/Hz
kHz
External High-Pass Filter Corner Frequency
Anti-Alias Filter Corner Frequency
Passband Ripple
MHz
dB
NOTE: (1) dBm referenced from average tone power and spread over 4kHz receive tone bins. (2) Measured at 200kHz with typical ADSL multitone transmission signal.
TABLE VIII. ADSL Front-End System Performance when using the AFE1302 in a Texas Instruments Reference Design
Evaluation Board. Typical at 25°C, AVDD = +5V, DVDD = +3.3V, fCLK = 35.328MHz, TX output and RX input
measured at line side.
11
AFE1302
SBWS014
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
AFE1302Y/250
AFE1302Y/2K
ACTIVE
ACTIVE
TQFP
TQFP
PFB
PFB
48
48
250
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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