AFE7906IABJ [TI]
六通道、5MHz 至 12GHz、3GSPS、射频采样 ADC | ABJ | 400 | -40 to 85;
| 型号： | AFE7906IABJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 六通道、5MHz 至 12GHz、3GSPS、射频采样 ADC | ABJ | 400 | -40 to 85 射频 |
| 文件： | 总80页 (文件大小：6967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AFE7906
ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
AFE7906 具有3GSPS ADC 的6 通道、5MHz 至12GHz 射频采样接收器
1 特性
3 说明
• 申请完整数据表
• 六个射频采样14 位、3 GSPS ADC
• 最大射频信号带宽：
– 4 个ADC：每个ADC 为1200 MHz
– 6 个ADC：每个ADC 为600 MHz
• 射频频率范围：5 MHz 至12 GHz
• 数字步进衰减器(DSA)：25 dB 范围，0.5 dB 步进
• 单频带DDC（在6 个通道上）和双频带DDC（在
4 个通道上）
AFE7906 是一款高性能、高带宽、多通道接收器，集
成了六个射频采样 ADC。此器件具有高达 12GHz 的
工作频率，支持直接在 L、S、C 和 X 带频率范围内进
行射频采样，无需额外的频率转换级。密度和灵活性提
高后可支持高通道数、多任务系统。
每个接收器链均包含一个25dB 范围的数字步进衰减器
(DSA)，后跟一个 3GSPS 模数转换器 (ADC)。四个接
收器通道都有模拟峰值功耗检测器和各种数字功耗检测
器，可辅助进行外部或内部自主自动增益控制器，另外
还具有射频过载检测器，用于提供器件可靠性保护。灵
活的抽取选项提供高达 1200MHz（对于四个 RX）或
600MHz 的数据带宽优化。
• 每个DDC 通道16 个NCO
• 可选内部PLL/VCO，提供ADC 采样率下的ADC
时钟或外部时钟
• Sysref 对齐检测器
该器件包含一个 SYSREF 时序检测器，用于优化相对
于器件时钟的SYSREF 输入时序。
• 串行器/解串器数据接口：
– 可兼容JESD204B 和JESD204C
– 8 个高达29.5 Gbps 的串行器/解串器发送器
– 子类1 多器件同步
封装信息
封装(1)
封装尺寸(2)
器件型号
AFE7906
• 封装：17mm × 17mm FCBGA，间距0.8 mm
FC-BGA
17.00mm × 17.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。
• 雷达
• 导引头前端
• 国防无线电
• 无线通信测试
空白
DSA
FB
DDC
Buffer
SHA
ADC
1FB+/-
1RX+/-
DSA
DSA
Buffer
SHA
RX
DDC
ADC
ADC
RX
DDC
Buffer
SHA
1STX+/-
2RX+/-
2STX+/-
3STX+/-
4STX+/-
5STX+/-
6STX+/-
PLL
/2,3,4,6
CLKIN+/-
SYSREF+/-
7STX+/-
DSA
DSA
RX
DDC
Buffer
SHA
ADC
ADC
4RX+/-
3RX+/-
8STX+/-
Buffer
SHA
RX
DDC
DSA
Buffer
SHA
FB
DDC
ADC
2FB+/-
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASAF7
AFE7906
www.ti.com.cn
ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
Table of Contents
6.7 Digital Electrical Characteristics................................14
6.8 Power Supply Electrical Characteristics................... 15
6.9 Timing Requirements................................................17
6.10 Switching Characteristics........................................18
6.11 Typical Characteristics............................................ 19
7 Device and Documentation Support............................70
7.1 接收文档更新通知..................................................... 70
7.2 支持资源....................................................................70
7.3 Trademarks...............................................................70
7.4 静电放电警告............................................................ 70
7.5 术语表....................................................................... 70
8 Mechanical, Packaging, and Orderable Information..70
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 说明（续）.........................................................................3
5 Revision History.............................................................. 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 RF ADC Electrical Characteristics.............................. 6
6.6 PLL/VCO/Clock Electrical Characteristics................ 12
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English Data Sheet: SBASAF7
AFE7906
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
4 说明（续）
每个接收器链均包含一个25dB 范围的数字步进衰减器(DSA)，后跟一个3GSPS 模数转换器(ADC)。每个接收器
通道都有多个模拟峰值功耗检测器和各种数字功耗检测器，可辅助进行外部或内部自主自动增益控制器，另外还
具有一个射频过载检测器，用于提供器件可靠性保护。灵活的抽取选项可为数据带宽提供高达 1200MHz 的优化
（对于四条不带FB 路径的RX），或为带两条FB 路径（每条1200MHz 带宽）提供600MHz 的优化。
该器件包含一个SYSREF 时序检测器，用于优化相对于器件时钟的SYSREF 输入时序。
5 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from July 9, 2022 to May 30, 2023 (from Revision B (July 2022) to Revision C (May
2023))
Page
• 将“器件信息”更改为封装信息 表.................................................................................................................... 1
• Changed IIH and IIL units to µA......................................................................................................................... 14
Changes from March 11, 2022 to July 8, 2022 (from Revision A (March 2022) to Revision B
(July 2022))
Page
• Deleted ABJ from the Thermal Information table. The table applies to both ABJ and the ALK packages......... 4
• Changed 0RX - 3RX to 1RX - 4RX in several plots..........................................................................................42
• Changed 0RX - 3RX to 1RX - 4RX in several plots..........................................................................................47
Changes from Revision * (January 2022) to Revision A (March 2022)
Page
• 向“申请完整数据表”添加了特性 .................................................................................................................... 1
• Added the Specification tables to the data sheet................................................................................................4
•
Changed Power Mode 4 to fRX = 2.25 GHz.....................................................................................................15
• Added the Typical Characteristics section to the data sheet............................................................................ 19
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English Data Sheet: SBASAF7
AFE7906
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
DVDD0P9, VDDT0P9
1.2
V
–0.3
VDD1P2RX, VDD1P2TXCLK, VDD1P2TXENC, VDD1P2PLL,
VDD1P2PLLCLKREF, VDD1P2FB, VDD1P2FBCML,
1.4
2.1
V
V
–0.3
–0.5
Supply Voltage
VDD1P2RXCML
Range
VDD1P8RX, VDD1P8RXCLK, VDD1P8TX, VDD1P8TXDAC,
VDD1P8TXENC, VDD1P8PLL, VDD1P8PLLVCO, VDD1P8FB,
VDD1P8FBCLK, VDD1P8GPIO, VDDA1P8
{1/2/3/4}RXIN+/-
VDDRX1P8+0.3
V
V
V
V
–0.5
–0.5
–0.3
–0.3
1FBIN+/-, 2FB+/-
VDDFB1P8+0.3
REFCLK+/-, SYSREF+/-
1.4
1.4
{1:8}STX+/-
Pin Volatge
Range
GPIO{B/C/D/E}x, SPICLK, SPISDIO, SPISDO, SPISEN, RESETZ,
BISTB0, BISTB1
VDD1P8GPIO +
0.3
V
–0.5
VDDCLK1P8 +
0.3
IFORCE, VSENSE
SRDAMUX1, SRDAMUX2
any input
V
V
–0.3
–0.3
VDDA1P8+0.3
20
Peak Input
Current
mA
TJ
Junction temperature
Storage temperature
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard
ESD control process. Manufacturing with less than 250-V CDM is possible if necessary precautions are taken.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBASAF7
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
DVDD0P9, VDDT0P9
Supply voltage 0.9V
Supply voltage 1.2V
0.9
0.925
0.95
1.25
V
V
VDD1P2{RX/TXCLK/TXENC/FB/PLL/
PLLCLKREF/FBCML/RXCML}
1.15
1.2
1.8
VDD1P8{RX/RXCLK/TX/TXDAC/
TXENC/PLL/PLLVCO/FB/FBCLK/
GPIO}, VDDA1P8
Supply voltage 1.8V
1.75
1.85
V
TA
Ambient temperature
85
°C
°C
°C
–40
Operating Junction Temperature
Maximum Operating Junction Temperature
110(1)
TJ
125
(1) Prolonged use at or above this junction temperature can increase the device failure-in-time (FIT) rate. Refer to SBAA403 application
note for additional details
6.4 Thermal Information
AFE7906
THERMAL METRIC(1)
FC-BGA
400 PINS
16.2
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
0.42
4.85
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.12
4.6
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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English Data Sheet: SBASAF7
AFE7906
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.5 RF ADC Electrical Characteristics
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1500MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF
491.52MHz below 6GHz input frequency and External clock mode with fCLK = 2949.12MHz above 6GHz input frequency;
nominal power supplies; DSA Setting =3dB; SerDes rate =24.33Gbps; unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADCRES
FRFin
ADC resolution
14
bits
RF input frequency range
5
12000
MHz
fIN = 5 MHz, DSA=0dB, fADC
1500MSPS, fNCO = 17MHz, Decimate
by 48
=
-0.4
-2.2
-2.5
fIN = 30 MHz, DSA=0dB, fADC
=
1500MSPS, fNCO = 30MHz, Decimate
by 24
fIN = 410 MHz, DSA=0dB, fADC
3000MSPS, fNCO = 400MHz,
Decimate by 12
=
Min Full scale input power, at device
pins (1)
PFS_CW,min
dBm
fIN = 830 MHz, DSA=0dB
fIN = 1760 MHz, DSA=0dB
fIN = 2610 MHz, DSA=0dB
fIN = 3610 MHz, DSA=0dB
fIN = 4910 MHz, DSA=0dB
fIN = 8150 MHz, DSA=0dB
fIN = 9610 MHz, DSA=0dB
-2.9
-2.8
-1.8
-0.4
0.1
2.1
4.3
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
19.7
17.8
17.6
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24
fIN = 410 MHz, fADC = 3000MSPS,
fNCO = 400MHz, Decimate by 24
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
16.7
17.0
18
MAX Full scale input power - reliability
limited, at device pins
PFS_CW,MAX
dBm
18.5
19.3
21.3
23.5
100.0
25.0
0.5
RTERM
Input reference impedance
DSA Attenuation range
DSA Attenuation step
Ω
ATTrange
dB
dB
Delta=Gatt(X)-Gatt(X-1),
Fin=3610MHz, after calibration
DSA Attenuation step accuracy
0.1
0.9
1.8
ATTstep
DSA Gain Steps Phase accuracy
any 8dB range
Fin=3610MHz, after calibration
Fin=4910MHz, after calibration
deg
DSA Gain Steps Phase accuracy
any 8dB range
Measured Over 80MHz BW
Measured Over 200MHz BW
Measured Over 400MHz BW
0.2
0.5
1.1
Gflat
Gain flatness
dB
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBASAF7
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6.5 RF ADC Electrical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1500MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF
491.52MHz below 6GHz input frequency and External clock mode with fCLK = 2949.12MHz above 6GHz input frequency;
nominal power supplies; DSA Setting =3dB; SerDes rate =24.33Gbps; unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 5 MHz, DSA = 3dB, fADC
=
1500MSPS, fNCO = 17MHz, Decimate
by 48
-147.1
fIN = 30 MHz, DSA = 3dB, fADC
=
1500MSPS, fNCO = 30MHz, Decimate
by 24
-150.7
-155.4
fIN = 410 MHz, DSA = 3dB, fADC
3000MSPS, fNCO = 400MHz,
Decimate by 24
=
fIN = 830 MHz, DSA = 3dB(3)
fIN = 1760 MHz, DSA = 3dB(3)
fIN = 2610 MHz, DSA = 3dB(3)
fIN = 3610 MHz, DSA = 3dB(3)
fIN = 4910 MHz, DSA = 3dB(3)
fIN = 8110 MHz, DSA = 3dB(3)
fIN = 9610 MHz, DSA = 3dB(3)
-156.2
-156.0
-155.4
-155.1
-155.1
-152
-151
Noise Density
(small signal = -30dBFS)
NSD
dBFS/Hz
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48,
3<=Atten<=22
-147.8
-151.5
-156.6
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24,
3<=Atten<=22
fIN = 410 MHz, 3<=Atten<=22, fADC
3000MSPS, fNCO = 400MHz,
Decimate by 24
=
fIN = 830 MHz, 3<=Atten<=22
fIN = 1760 MHz, 3<=Atten<=25
fIN = 2610 MHz, 3<=Atten<=25
fIN = 3610 MHz, 3<=Atten<=25
fIN = 4910 MHz, 3<=Atten<=25
fIN = 8150 MHz, 3<=Atten<=25
fIN = 9610 MHz, 3<=Atten<=25
-156.0
-155.8
-155.7
-155.4
-155.8
-152.5
-152.5
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
29.4
24.5
19.3
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24
fIN = 410 MHz, fADC = 3000MSPS,
fNCO = 400MHz, Decimate by 24
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
19.1
19.0
20.9
22.8
22.4
27.3
30
Noise Figure min
DSA Atten=0 - 3dB
NFmin
dB
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English Data Sheet: SBASAF7
AFE7906
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.5 RF ADC Electrical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1500MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF
491.52MHz below 6GHz input frequency and External clock mode with fCLK = 2949.12MHz above 6GHz input frequency;
nominal power supplies; DSA Setting =3dB; SerDes rate =24.33Gbps; unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
30.6
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24
25.1
20.1
fIN = 410 MHz, fADC = 3000MSPS,
fNCO = 400MHz, Decimate by 24
Noise Figure(4)
DSA Atten=4dB
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
20.0
20.6
21.9
23.5
22.3
27.9
30.7
NF
dB
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
45.9
40.2
35.0
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24
fIN = 410 MHz, fADC = 3000MSPS,
fNCO = 400MHz, Decimate by 24
Noise Figure(4)
DSA Atten=20dB
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
34.7
35.2
36.0
37.3
37.6
42.8
45
NFmax
dB
fIN = 30±1 MHz, fADC = 1500MSPS,
fNCO = 30MHz, Decimate by 24
-82
-75
fIN = 400MHz and 405MHz, fADC
3000MSPS, fNCO = 400MHz,
Decimate by 24
=
fIN = 840 MHz, 3<=Atten<=12
fIN = 1770 MHz, 3<=Atten<=12
fIN = 2610 MHz, 3<=Atten<=12
fIN = 3610 MHz, 3<=Atten<=12
fIN = 4920 MHz, 3<=Atten<=12
-82
-84
-74
-77
-76
3rd order intermodulation 2 tones at at
fIN ± 10MHz
-7dBFS each tone
IMD3
dBc
fIN = 8150 MHz, 3<=Atten<=12,
25MHz tone spacing
-59
-60
fIN = 9610 MHz, 3<=Atten<=12,
25MHz tone spacing
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English Data Sheet: SBASAF7
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6.5 RF ADC Electrical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1500MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF
491.52MHz below 6GHz input frequency and External clock mode with fCLK = 2949.12MHz above 6GHz input frequency;
nominal power supplies; DSA Setting =3dB; SerDes rate =24.33Gbps; unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
78
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24
100
94
fIN = 410 MHz, fADC = 3000MSPS,
fNCO = 400MHz, Decimate by 24
Spurious Free Dynamic Range
within output bandwidth, AIN = -3
dBFS
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
88
81
88
84
79
78
71
SFDR
dBFS
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
-84
-91
-90
fIN = 30 MHz, fADC = 1500MSPS,
Bypass Mode (TI only test mode)
fIN = 410 MHz, fADC = 3000MSPS,
Bypass Mode (TI only test mode)
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
-86
-90
-88
-87
-84
-70
-70
2nd Harmonic Distortion
AIN = -3 dBFS(2)
HD2
dBFS
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
-78
-96
-94
fIN = 30 MHz, fADC = 1500MSPS,
Bypass Mode (TI only test mode)
fIN = 410 MHz, fADC = 3000MSPS,
Bypass Mode (TI only test mode)
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
-80
-85
-86
-78
-75
-70
-70
3rd Harmonic Distortion
AIN = -3 dBFS
HD3
dBFS
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.5 RF ADC Electrical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1500MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF
491.52MHz below 6GHz input frequency and External clock mode with fCLK = 2949.12MHz above 6GHz input frequency;
nominal power supplies; DSA Setting =3dB; SerDes rate =24.33Gbps; unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
-94
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24
-94
-94
fIN = 410 MHz, fADC = 3000MSPS,
fNCO = 400MHz, Decimate by 24
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
-88
-81
-88
-84
-82
-78
-71
SFDR excl. HD2 and HD3
AIN = -3 dBFS
HDn, n>3
SFDR
HD2
dBFS
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
101
105
95
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24
fIN = 410 MHz, fADC = 3000MSPS,
fNCO = 400MHz, Decimate by 24
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
89
89
95
87
90
83
80
Spurious Free Dynamic Range
AIN = -13 dBFS
dBFS
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
-104
-91
fIN = 30 MHz, fADC = 1500MSPS,
Bypass Mode (TI only test mode)
fIN = 410 MHz, fADC = 3000MSPS,
Bypass Mode (TI only test mode)
-104
2nd Harmonic Distortion(2)
AIN = -13 dBFS
fIN = 830 MHz, with board trim
fIN = 1760 MHz, with board trim
fIN = 2610 MHz, with board trim
fIN = 3610 MHz, with board trim
fIN = 4910 MHz, with board trim
fIN = 8150 MHz, with board trim
fIN = 9610 MHz, with board trim
-79
-102
-100
-101
-99
dBFS
-107
-107
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.5 RF ADC Electrical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1500MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with fREF
491.52MHz below 6GHz input frequency and External clock mode with fCLK = 2949.12MHz above 6GHz input frequency;
nominal power supplies; DSA Setting =3dB; SerDes rate =24.33Gbps; unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
-103
fIN = 30 MHz, fADC = 1500MSPS,
Bypass Mode (TI only test mode)
-84
-91
fIN = 381 MHz, fADC = 3000MSPS,
Bypass Mode (TI only test mode)
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
-95
-95
3rd Harmonic Distortion
AIN = -13 dBFS
HD3
dBFS
-98
-97
-94
-100
-102
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
-104
-105
-95
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24
fIN = 410 MHz, fADC = 3000MSPS,
fNCO = 400MHz, Decimate by 24
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
-89
-89
-95
-90
-90
-83
-80
SFDR excl. HD2 and HD3
AIN = -13 dBFS
HDn, n>3
dBFS
fIN = 5 MHz, fADC = 1500MSPS, fNCO
= 17MHz, Decimate by 48
-98
-98
fIN = 30 MHz, fADC = 1500MSPS, fNCO
= 30MHz, Decimate by 24
fIN = 400 MHz
fIN = 830 MHz
fIN = 1760 MHz
fIN = 2610 MHz
fIN = 3610 MHz
fIN = 4910 MHz
fIN = 8150 MHz
fIN = 9610 MHz
-88
-77
-71
-74
-77
-65
-68
-68
Near Channel:
1RXIN to 2RXIN
3RXIN to 4RXIN
1FBIN to 1RXIN
2FBIN to 3RXIN
RX-RX/FB
Isolation
dB
(1) The input fullscale at minimum attenuation can be reduce by adding a digital gain range to the DSA, extending the useful range of the
DSA. The noise figure remains constant over the digital gain range.
(2) After HD2 trim on specific printed circuit board.
(3) From DSA = 3dB down to 0dB, NSD increases 1dB per DSA dB
(4)
NF increase 1dB per DSA 1dB above DSA = 3dB
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.6 PLL/VCO/Clock Electrical Characteristics
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; Reference clock input frequency
491.52MHz (unless otherwise noted), phase noise normalized to fVCO
.
PARAMETER
VCO1 min frequency
VCO1 max frequency
VCO2 min frequency
VCO2 max frequency
VCO3 min frequency
VCO3 max frequency
VCO4 min frequency
VCO4 max frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GHz
GHz
GHz
GHz
GHz
GHz
GHz
GHz
7.2
fVCO1
fVCO2
fVCO3
fVCO4
7.68
8.848
9.8304
9.216
10.24
12.288
11.7965
1, 2, 3,
4, 6 or 8
DIVFBADC
DIVRXADC
ADC sample rate divider from VCO rate
ADC sample rate divider
1, 2, 3,
4, 6 or 8
600kHz
800kHz
1MHz
-113
-116
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz
-119
Closed Loop Phase Noise FPLL
11.79848 GHz FREF=491.52MHz
=
1.8MHz
5MHz
-125
-133
50MHz
600kHz
800kHz
1MHz
–141
-114
–118
–120
–127
–135
–142
–113
–116
–119
–125
–134
–140
–116
–119
–122
–127
–136
–143
-43.4
-47.6
-46.2
Closed Loop Phase Noise
FPLL=8.84736 GHz FREF=491.52MHz
1.8MHz
5MHz
50MHz
600kHz
800kHz
1MHz
PNVCO
Closed Loop Phase Noise FPLL= 9.8403
GHz FREF=491.52MHz
1.8MHz
5MHz
50MHz
600kHz
800kHz
1MHz
Closed Loop Phase Noise FPLL
=
7.86432GHz FREF=491.52MHz
1.8MHz
5MHz
50MHz
fPLL=11.79848 GHz, [1KHz, 100MHz]
fPLL=8.8536 GHz, [1KHz, 100MHz]
fPLL=9.8304 GHz, [1KHz, 100MHz]
Frms
Clock PLL integrated phase error(1)
fPFD
PFD frequency
100
0.1
500
12
PNpll_flat
FREF
Normalized PLL flat Noise
Input Clock frequency
fVCO = 11796.48MHz
dBc/Hz
GHz
–226.5
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.6 PLL/VCO/Clock Electrical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; Reference clock input frequency
491.52MHz (unless otherwise noted), phase noise normalized to fVCO
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSS
Input Clock level
0.6
1.8 Vppdiff
AC
Coupling
Only
Coupling
Parallel resistance
Parallel capacitance
100
0.5
Ω
REFCLK input impedance(2)
pF
(1) Single Sideband, not including the reference clock contribution
(2) Refer to S11 data available from TI for impedance vs frequency
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6.7 Digital Electrical Characteristics
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CML SerDes Outputs [8:1]STX+/-
Full rate mode
19
9.5
29.5
16.25
8.125
4.062
2.031
0.42
Half rate mode
FSerDes
SerDes Bit Rate
Quarter rate mode
1/8th rate mode
1/16th rate mode
4.75
Gbps
2.375
1.1875
TJ
Total Jitter Tolerance
UI
mVpp
V
VSTDIFF
VSTCOM
ZSTdiff
TRF
SerDes Transmitter Output Amplitude
SerDes Output Common Mode
SerDes Output Impedance
Output rise and fall time
Output total jitter
differential
20-80%
500
0.4
1000
0.55
0.45
100
Ω
ps
UI
8
TTJ
0.21
CMOS I/O: GPIO{B/C/D/E}x, SPICLK, SPISDIO, SPISDO, SPISEN, RESETZ, BISTB0, BISTB1
0.6×VDD1
P8GPIO
VIH
VIL
High-Level Input Voltage
Low-Level Input Voltage
V
V
0.4×VDD1
P8GPIO
IIH
IIL
High-Level Input Current
Low-Level Input Current
CMOS input capacitance
250
250
µA
µA
pF
–250
–250
CL
2
VDD1P8G
PIO–0.2
VOH
VOL
High-Level Output Voltage
Low-Level Output Voltage
V
V
0.2
Differential Inputs: SYSREF+/- Mode A
FSYSREFMAX
VSWINGSRMAX
VSWINGSRMIN
VSWINGSRMIN
SYSREF Input Frequency Maximum
40
1.8
0.3
0.6
MHz
SYSREF Input Swing Maximum
SYSREF Input Swing Minimum
SYSREF Input Swing Minimum
Vppdiff(2)
Vppdiff(2)
Vppdiff(2)
fREF < 500MHz
fREF > 500MHz
SYSREF Input Common Mode Voltage
Maximum
VCOMSRMAX
VCOMSRMIN
0.8
V
V
SYSREF Input Common Mode Voltage
Minimum
0.6
ZT
CL
Input termination
Input capacitance
differential
100 (1)
0.5
Ω
Each pin to GND
pF
LVDS Inputs: 0SYNCIN+/- and 1SYNCIN+/-
VICOM
VID
Input Common Voltage
Differential Input Voltage swing
Input termination
1.2
450
100
V
Vppdiff(2)
Ω
ZT
differential
LVDS Outputs: 0SYNCOUT+/- and 1SYNCOUT+/-
VOCOM
VOD
ZT
Output Common Voltage
Differential Output Voltage swing
Internal Termination
1.2
500
100
V
Vppdiff(2)
Ω
(1) SYSREF termination is programmable between 100Ω, 150Ωand 300Ω
(2) Vppdiff is the difference between the maximum differential voltage (positive value) and minimum differential voltage (negative value).
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.8 Power Supply Electrical Characteristics
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; fADC = 2949.12MSPS; nominal
power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Group 3A: VDD1P8FB + VDD1P8RX +
VDD1P8TX
673
mA
Group 3B: VDD1P8FBCLK +
VDD1P8RXCLK + VDD1P8TXDAC+
VDD1P8GPIO + VDDA1P8
IVDD1P8
376
mA
Group 3C: VDD1P8PLL +
VDD1P8PLLVCO
17.5
557
75
mA
mA
mA
Mode 1: 4R, fADC = 3 GSPS, DDCRX = 6x
Decimation, fRX = 1.85 GHz, 8b/10b
coding, 20 Gbps, RX: 4-8-4-1
Group 2A: VDD1P2FB + VDD1P2RX
Group 2B: VDD1P2TXCLK +
VDD1P2TXENC
IVDD1P2
Group 2C: VDD1P2FBCML +
VDD1P2RXCML + VDD1P2PLLCLKREF
68
mA
IVDD0P9
Pdiss
Group 1A: DVDD0P9 + VDDT0P9
Power Dissipation
1582
4208
mA
mW
Group 3A: VDD1P8FB + VDD1P8RX +
VDD1P8TX
1006
548
mA
mA
Group 3B: VDD1P8FBCLK +
VDD1P8RXCLK + VDD1P8TXDAC+
VDD1P8GPIO + VDDA1P8
IVDD1P8
Group 3C: VDD1P8PLL +
VDD1P8PLLVCO
17.5
839
92
mA
mA
mA
Mode 2: 4R2F, fADC = 3 GSPS, DDCFB
=
DDCRX = 6x Decimation, fRX = 1.85 GHz,
8b/10b coding, 20 Gbps, RX: 4-8-4-1, FB:
2-4-4-1
Group 2A: VDD1P2FB + VDD1P2RX
Group 2B: VDD1P2TXCLK +
VDD1P2TXENC
IVDD1P2
Group 2C: VDD1P2FBCML +
VDD1P2RXCML + VDD1P2PLLCLKREF
68
mA
IVDD0P9
Pdiss
Group 1A: DVDD0P9 + VDDT0P9
Power Dissipation
2174
5996
mA
mW
Group 3A: VDD1P8FB + VDD1P8RX +
VDD1P8TX
672
506
mA
mA
Group 3B: VDD1P8FBCLK +
VDD1P8RXCLK + VDD1P8TXDAC+
VDD1P8GPIO + VDDA1P8
IVDD1P8
Group 3C: VDD1P8PLL +
VDD1P8PLLVCO
17.5
552
76
mA
mA
mA
Mode 4: 4R, fADC = 3 GSPS, DDCRX = 2x
Decimation , fRX = 2.25 GHz, 64/66
coding, 24.75 Gbps, RX: 8-8-2-1
Group 2A: VDD1P2FB + VDD1P2RX
Group 2B: VDD1P2TXCLK +
VDD1P2TXENC
IVDD1P2
Group 2C: VDD1P2FBCML +
VDD1P2RXCML + VDD1P2PLLCLKREF
68
mA
IVDD0P9
Pdiss
Group 1A: DVDD0P9 + VDDT0P9
Power Dissipation
1613
4468
mA
mW
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.8 Power Supply Electrical Characteristics (continued)
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; fADC = 2949.12MSPS; nominal
power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Group 3A: VDD1P8FB + VDD1P8RX +
VDD1P8TX
1005
mA
Group 3B: VDD1P8FBCLK +
VDD1P8RXCLK + VDD1P8TXDAC+
VDD1P8GPIO + VDDA1P8
IVDD1P8
562
mA
Group 3C: VDD1P8PLL +
VDD1P8PLLVCO
Mode 5: 4R2F, fADC = 3 GSPS, DDCRX
12x Decimation Dual Channel, DDCFB
3x Decimation, fRX = 1.85 and 2.65 GHz,
8b/10b coding, 20 Gbps, RX: 4-16-8-1,
FB: 4-4-4-1
=
=
17.5
837
92
mA
mA
mA
Group 2A: VDD1P2FB + VDD1P2RX
Group 2B: VDD1P2TXCLK +
VDD1P2TXENC
IVDD1P2
Group 2C: VDD1P2FBCML +
VDD1P2RXCML + VDD1P2PLLCLKREF
68
mA
IVDD0P9
Pdiss
Group 1A: DVDD0P9 + VDDT0P9
Power Dissipation
2359
6195
mA
mW
Group 3A: VDD1P8FB + VDD1P8RX +
VDD1P8TX
671
374
mA
mA
Group 3B: VDD1P8FBCLK +
VDD1P8RXCLK + VDD1P8TXDAC+
VDD1P8GPIO + VDDA1P8
IVDD1P8
Group 3C: VDD1P8PLL +
VDD1P8PLLVCO
17.5
555
75
mA
mA
mA
Mode 6: 4R, fADC = 3 GSPS, DDCRX
=
12x Decimation Dual Channel, fRX = 1.85
and 2.65 GHz, 8b/10b coding, 20 Gbps,
RX: 4-16-8-1
Group 2A: VDD1P2FB + VDD1P2RX
Group 2B: VDD1P2TXCLK +
VDD1P2TXENC
IVDD1P2
Group 2C: VDD1P2FBCML +
VDD1P2RXCML + VDD1P2PLLCLKREF
67
mA
IVDD0P9
Pdiss
Group 1A: DVDD0P9 + VDDT0P9
Power Dissipation
1702
4305
mA
mW
Group 3A: VDD1P8FB + VDD1P8RX +
VDD1P8TX
16
mA
mA
Group 3B: VDD1P8FBCLK +
VDD1P8RXCLK + VDD1P8TXDAC+
VDD1P8GPIO + VDDA1P8
IVDD1P8
295
Group 3C: VDD1P8PLL +
VDD1P8PLLVCO
12
4
mA
mA
mA
Mode 7: same configuration as mode 2,
Sleep Mode. SLEEP pin is pull high.
Group 2A: VDD1P2FB + VDD1P2RX
Group 2B: VDD1P2TXCLK +
VDD1P2TXENC
24
IVDD1P2
Group 2C: VDD1P2FBCML +
VDD1P2RXCML + VDD1P2PLLCLKREF
45
mA
IVDD0P9
Pdiss
Group 1A: DVDD0P9 + VDDT0P9
Power Dissipation
156
818
mA
mW
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6.9 Timing Requirements
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; fADC = 2949.12MSPS; nominal
power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
MIN
NOM
MAX
UNIT
Timing: SYSREF+/-
ts(SYSREF)
Setup Time, SYSREF+/- Valid to Rising Edge of CLK+/-
50
50
ps
ps
th(SYSREF) Hold Time, SYSREF+/- Valid after Rising Edge of CLK+/-
Timing: Serial ports
ts(SENB)
th(SENB)
ts(SDIO)
Setup Time, SENB to Rising Edge of SCLK
Hold Time, SENB after last Rising Edge of SCLK (1)
Setup Time, SDIO valid to Rising Edge of SCLK
Hold Time, SDIO valid after Rising Edge of SCLK
Minimum SCLK period: registers write
15
ns
ns
ns
ns
ns
ns
ns
ns
ms
5 + tSCLK
15
5
th(SDIO)
t(SCLK)_W
t(SCLK)_R
25
50
0
Minimum SCLK period: registers read
Minimum Data Output delay after Falling Edge of SCLK
Maximum Data Output delay after Falling Edge of SCLK
Minimum RESETZ Pulse Width
td(data_out)
tRESET
15
1
(1) SDEN\\ need to be held one more extra clock cycle with the last SCLK edge
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6.10 Switching Characteristics
Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; fADC = 2949.12MSPS; nominal
power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RX Channel Latency
LMFS=2-16-16-1, 122.88 MSPS, 24x
Decimation, Serdes rate = 16.22Gbps
(JESD204C)
92
108
118
153
LMFS=4-16-8-1, 245.76 MSPS, 12x
Decimation, Serdes rate = 16.22Gbps
(JESD204C)
interface
clock
tJESDRX
RX input to JESD output Latency
cycles(1)
LMFS=2-8-8-1, 368.64 MSPS, 8x
Decimation, Serdes rate = 16.22Gbps
(JESD204C)
LMFS=4-8-4-1, 491.52 MSPS, 6x
Decimation, Serdes rate = 16.22Gbps
(JESD204C)
FB Channel Latency
SerDes Transmitter Analog Delay
3.6
ns
LMFS=1-2-8-1, 368.64 MSPS, 8x
Decimation
151
interface
clock
tJESDFB
FB input to JESD output Latency
cycles(1)
LMFS=2-4-4-1, 491.52 MSPS, 6x
Decimation
177
(1) Interface clock cycles is the period of the digital interface clock rate, e.g. 1GSPS = 1ns.
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
1
0.5
Temp = -40C
Temp = 25C
Temp = 110C
0.4
0.3
0.2
0.1
0
0.5
0
-0.5
-1
DSA = 0dB
DSA = 4dB
DSA = 8dB
DSA = 12dB
DSA = 16dB
DSA = 20dB
DSA = 24dB
-0.1
-0.2
-0.3
-0.4
-0.5
-1.5
-2
-2.5
-3
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Input Frequency (MHz)
0
4
8
12
16
20
24
DSA Setting (dB)
Normalized to 30 MHz
Differential Amplitude Error = PIN(DSA Setting –1) –
PIN(DSA Setting) + 1
图6-1. RX In-Band Gain Flatness, fIN = 30 MHz
图6-2. RX Uncalibrated Differential Amplitude Error vs DSA
Setting at 30 MHz
4
3.5
3
0.05
Temp = -40C
Temp = 25C
Temp = 110C
0.04
0.03
0.02
0.01
0
2.5
2
1.5
1
-0.01
-0.02
-0.03
-0.04
-0.05
0.5
0
Temp = -40C
Temp = 25C
Temp = 110C
-0.5
-1
0
4
8
12
16
20
24
0
4
8
12
16
20
24
DSA Setting (dB)
DSA Setting (dB)
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
Differential Amplitude Error = PIN(DSA Setting –1) –
Setting = 0) + (DSA Setting)
PIN(DSA Setting) + 1
图6-4. RX Uncalibrated Integrated Amplitude Error vs DSA
图6-3. RX Calibrated Differential Amplitude Error vs DSA
Setting at 30 MHz
Setting at 30 MHz
0.1
1
0.8
0.6
0.4
0.2
0
Temp = -40C
Temp = 25C
Temp = 110C
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
-0.2
-0.4
-0.6
Temp = -40C
Temp = 25C
Temp = 110C
-0.8
-1
0
4
8
12
16
20
24
0
4
8
12
16
20
24
DSA Setting (dB)
DSA Setting (dB)
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
Differential Phase Error = PhaseIN(DSA Setting –1) –
Setting = 0) + (DSA Setting)
PhaseIN(DSA Setting)
图6-5. RX Calibrated Integrated Amplitude Error vs DSA Setting 图6-6. RX Uncalibrated Differential Phase Error vs DSA Setting
at 30 MHz
at 30 MHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
1
0.8
0.6
0.4
0.2
0
1
0.5
0
Temp = -40C
Temp = 25C
Temp = 110C
-0.5
-1
-1.5
-2
-0.2
-0.4
-0.6
-0.8
-1
-2.5
-3
Temp = -40C
Temp = 25C
Temp = 110C
-3.5
-4
0
4
8
12
16
20
24
0
4
8
12
16
20
24
DSA Setting (dB)
DSA Setting (dB)
Differential Phase Error = PhaseIN(DSA Setting –1) –
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
PhaseIN(DSA Setting)
Setting = 0)
图6-7. RX Calibrated Differential Phase Error vs DSA Setting at 图6-8. RX Uncalibrated Integrated Phase Error vs DSA Setting
30 MHz
at 30 MHz
1
0.8
0.6
0.4
0.2
0
Temp = -40C
Temp = 25C
Temp = 110C
-0.2
-0.4
-0.6
-0.8
-1
0
4
8
12
16
20
24
DSA Setting (dB)
With 0.8 GHz matching
AIN = -3 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz,
Decimate by 24x
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
Setting = 0)
图6-10. RX Output FFT at 5 MHz
图6-9. RX Calibrated Integrated Phase Error vs DSA Setting at
30 MHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
AIN = -6 dBFS, fADC = 1500 MSPS, fNCO = 32. , Decimate by
24x
AIN = -12 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz,
Decimate by 24x
图6-11. RX Output FFT at 5 MHz
图6-12. RX Output FFT at 5 MHz
AIN = -30 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz,
Decimate by 24x
AIN = -60 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz,
Decimate by 24x
图6-13. RX Output FFT at 5 MHz
图6-14. RX Output FFT at 5 MHz
AIN = -3 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz,
Decimate by 24x
AIN = -6 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz,
Decimate by 24x
图6-15. RX Output FFT at 30 MHz
图6-16. RX Output FFT at 30 MHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
AIN = -12 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz,
Decimate by 24x
AIN = -30 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz,
Decimate by 24x
图6-17. RX Output FFT at 30 MHz
图6-18. RX Output FFT at 30 MHz
-142
Temp = -40C, DSA = 0dB
-143
-144
-145
-146
-147
-148
-149
-150
-151
-152
Temp = -40C, DSA = 3dB
Temp = 25C, DSA = 0dB
Temp = 25C, DSA = 3dB
Temp = 110C, DSA = 0dB
Temp = 110C, DSA = 3dB
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
AIN = -60 dBFS, fADC = 1500 MSPS, fNCO = 32.13 MHz,
Decimate by 24x
Input Amplitude (dBFS)
fADC = 1500MSPS, fNCO = 32.13MHz, Decimate by 24x
图6-19. RX Output FFT at 30 MHz
图6-20. NSD vs Input Amplitude at 30 MHz with DSA = 0 and
3dB
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
-147
-147.5
-148
-142
-144
-146
-148
-150
-152
Temp = -40C
Temp = 25C
Temp = 110C
AIN = -12dBFS, Temp = -40C
AIN = -12dBFS, Temp = 25C
AIN = -12dBFS, Temp = 110C
AIN = -3dBFS, Temp = -40C
AIN = -3dBFS, Temp = 25C
AIN = -3dBFS, Temp = 110C
-148.5
-149
-149.5
-150
-150.5
-151
-151.5
-152
-152.5
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
0
5
10
15
20
25
25
20
Input Amplitude (dBFS)
DSA Setting (dB)
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
图6-21. NSD vs Input Amplitude at 30 MHz with DSA = 12
图6-22. NSD vs DSA Attenuation at 30 MHz
-85
-60
DSA = 3dB, Temp = -40C
AIN = -13dBFS, Temp = -40C
AIN = -13dBFS, Temp = 25C
AIN = -13dBFS, Temp = 110C
AIN = -7dBFS, Temp = -40C
AIN = -7dBFS, Temp = 25C
AIN = -7dBFS, Temp = 110C
-90
-95
-65
DSA = 3dB, Temp = 25C
DSA = 3dB, Temp = 110C
DSA = 12dB, Temp = -40C
DSA = 12dB, Temp = 25C
DSA = 12dB, Temp = 110C
-70
-100
-105
-110
-115
-120
-125
-130
-135
-75
-80
-85
-90
-95
-100
-105
-110
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
0
5
10
15
20
Input Amplitude (dBFS, per tone)
DSA Setting (dB)
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
图6-23. IMD3 vs Input Amplitude at 30 MHz
图6-24. IMD3 vs DSA Setting at 30 MHz
-85
-60
DSA = 3dB, Temp = -40C
-12dBFS, -40C
-12dBFS, 25C
-12dBFS, 110C
-6dBFS, -40C
-6dBFS, 25C
-6dBFS, 110C
-3dBFS, -40C
-3dBFS, 25C
-3dBFS, 110C
-90
-95
DSA = 3dB, Temp = 25C
DSA = 3dB, Temp = 110C
DSA = 12dB, Temp = -40C
DSA = 12dB, Temp = 25C
DSA = 12dB, Temp = 110C
-70
-80
-100
-105
-110
-115
-120
-125
-130
-90
-100
-110
-120
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
0
2
4
6
8
10
12
14
16
18
Input Amplitude (dBFS)
DSA Setting (dB)
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
fADC = 1500 MSPS, fNCO = 32. , Decimate by 24x
图6-25. HD2 vs Input Amplitude at 30 MHz
图6-26. HD2 vs DSA Setting at 30 MHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
-70
-75
-50
-60
DSA = 3dB, Temp = -40C
DSA = 3dB, Temp = 25C
DSA = 3dB, Temp = 110C
DSA = 12dB, Temp = -40C
DSA = 12dB, Temp = 25C
DSA = 12dB, Temp = 110C
-12dBFS, -40C
-12dBFS, 25C
-12dBFS, 110C
-6dBFS, -40C
-6dBFS, 25C
-6dBFS, 110C
-3dBFS, -40C
-3dBFS, 25C
-3dBFS, 110C
-80
-85
-90
-70
-95
-100
-105
-110
-115
-120
-125
-130
-80
-90
-100
-110
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
0
2
4
6
8
10
12
14
16
18
20
Input Amplitude (dBFS)
DSA Setting (dB)
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
fADC = 1500 MSPS, fNCO = 32.13 MHz, Decimate by 24x
图6-27. HD3 vs Input Amplitude at 30 MHz
图6-28. HD3 vs DSA Setting at 30 MHz
Normalized to 4000 MHz
Differential Amplitude Error = PIN(DSA Setting –1) –
PIN(DSA Setting) + 1
图6-29. RX In-Band Gain Flatness, fIN = 400 MHz
图6-30. RX Uncalibrated Differential Amplitude Error vs DSA
Setting at 30 MHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
Differential Amplitude Error = PIN(DSA Setting –1) –
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
PIN(DSA Setting) + 1
Setting = 0) + (DSA Setting)
图6-31. RX Calibrated Differential Amplitude Error vs DSA
图6-32. RX Uncalibrated Integrated Amplitude Error vs DSA
Setting at 400 MHz
Setting at 400 MHz
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
Differential Phase Error = PhaseIN(DSA Setting –1) –
Setting = 0) + (DSA Setting)
PhaseIN(DSA Setting)
图6-33. RX Calibrated Integrated Amplitude Error vs DSA
图6-34. RX Uncalibrated Differential Phase Error vs DSA
Setting at 400 MHz
Setting at 400 MHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
Differential Phase Error = PhaseIN(DSA Setting –1) –
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
PhaseIN(DSA Setting)
Setting = 0)
图6-35. RX Calibrated Differential Phase Error vs DSA Setting 图6-36. RX Uncalibrated Integrated Phase Error vs DSA Setting
at 400 MHz
at 400 MHz
fNCO = 400MHz
图6-38. RX Output FFT at 405 MHz and -3dBFS
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
Setting = 0)
图6-37. RX Calibrated Integrated Phase Error vs DSA Setting at
400 MHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
fNCO = 400MHz
fNCO = 400MHz
图6-39. RX Output FFT at 405 MHz and -6dBFS
图6-40. RX Output FFT at 405 MHz and -12dBFS
fNCO = 400MHz
fNCO = 400MHz
图6-41. RX Output FFT at 405 MHz and -30dBFS
图6-42. RX Output FFT at 405 MHz and -60dBFS
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
fOFFSET = 50MHz
图6-44. NSD vs DSA Setting at 400MHz
fOFFSET = 50MHz
图6-43. NSD vs Input Amplitude at 400MHz
图6-46. IMD3 vs DSA Setting at 400MHz
图6-45. IMD3 vs Input Amplitude at 400MHz
图6-47. IMD3 vs Tone Spacing at 400MHz
图6-48. HD3 vs Input Amplitude at 400MHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.1 RX Typical Characteristics 30 MHz and 400 MHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 62.5
MSPS (decimate by 24x), PLL clock mode with fREF = 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB. Default conditions at
400 MHz: ADC Sampling Rate = 1500 MSPS, output sample rate = 125 MSPS (decimate by 12x), PLL clock mode with fREF
= 500 MHz, AIN = –3 dBFS, DSA setting = 3 dB.
图6-49. HD3 vs DSA Setting at 400MHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.2 RX Typical Characteristics at 800MHz
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.4
0.2
0
0.13
0.1
DSA=4dB
DSA=6dB
DSA=8dB
DSA=10dB
DSA=12dB
DSA=14dB
0.07
0.04
0.01
-0.02
-0.05
-0.08
-0.11
-0.14
-0.17
-0.2
-0.2
-0.4
-0.6
-0.8
-1
1RX
2RX
3RX
4RX
700
800
900
Output Frequency (MHz)
1000
1100
-40 -30 -20 -10
0
10 20 30 40 50 60 70
Temperature (èC)
With 0.8 GHz matching, normalized to 830 MHz
With 0.8 GHz matching, normalized to fullscale at 25°C for
each channel
图6-50. RX In-Band Gain Flatness for Channel 1RX, fIN = 830
MHz
图6-51. RX Input Fullscale vs Temperature and Channel at
800MHz
7
6
5
4
3
2
1
0
0.3
1RX
2RX
3RX
4RX
0.25
0.2
0.15
0.1
0.05
0
-1
1RX
-2
-3
-4
2RX
3RX
4RX
-0.05
-0.1
-40 -30 -20 -10
0
10 20 30 40 50 60 70
0
5
10
15
20
25
Temperature (èC)
DSA (dB)
With 0.8 GHz matching, normalized to phase at 25°C
With 0.8 GHz matching
Differential Amplitude Error = PIN(DSA Setting –1) –
图6-52. RX Input Phase vs Temperature and DSA at fOUT = 0.8
GHz
PIN(DSA Setting) + 1
图6-53. RX Uncalibrated Differential Amplitude Error vs DSA
Setting at 0.8 GHz
0.03
2.7
2.4
2.1
1.8
1.5
1.2
0.9
1RX
2RX
3RX
4RX
0.025
0.02
0.015
0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.025
1RX
2RX
3RX
4RX
0.6
0.3
0
0
5
10
15
20
25
0
5
10
15
20
25
DSA (dB)
DSA (dB)
With 0.8 GHz matching
With 0.8 GHz matching
Differential Amplitude Error = PIN(DSA Setting –1) –
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
PIN(DSA Setting) + 1
Setting = 0) + (DSA Setting)
图6-54. RX Calibrated Differential Amplitude Error vs DSA
图6-55. RX Uncalibrated Integrated Amplitude Error vs DSA
Setting at 0.8 GHz
Setting at 0.8 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.2 RX Typical Characteristics at 800MHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.16
0.14
0.12
0.1
0.6
0.4
0.2
0
1RX
2RX
3RX
4RX
1RX
2RX
3RX
4RX
0.08
0.06
0.04
0.02
0
-0.2
-0.4
-0.02
-0.04
0
5
10
15
20
25
0
5
10
15
20
25
DSA (dB)
DSA (dB)
With 0.8 GHz matching
With 0.8 GHz matching
Differential Phase Error = PhaseIN(DSA Setting –1) –
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
PhaseIN(DSA Setting)
Setting = 0) + (DSA Setting)
图6-57. RX Uncalibrated Differential Phase Error vs DSA
图6-56. RX Calibrated Integrated Amplitude Error vs DSA
Setting at 0.8 GHz
Setting at 2.6 GHz
0.5
1.2
0.9
0.6
0.3
0
1RX
2RX
3RX
4RX
0.4
0.3
0.2
0.1
0
-0.3
-0.6
-0.1
-0.2
-0.3
-0.4
-0.9
-1.2
1RX
2RX
3RX
4RX
0
5
10
15
20
25
0
5
10
15
20
25
DSA (dB)
DSA (dB)
With 0.8 GHz matching
With 0.8 GHz matching
Differential Phase Error = PhaseIN(DSA Setting –1) –
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
PhaseIN(DSA Setting)
Setting = 0)
图6-58. RX Calibrated Differential Phase Error vs DSA Setting 图6-59. RX Uncalibrated Integrated Phase Error vs DSA Setting
at 0.8 GHz
at 0.8 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.2 RX Typical Characteristics at 800MHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.6
0.4
0.2
0
0
-10
1RX
2RX
3RX
4RX
SNR = 63.2dBFS
-20
-30
-40
-50
-60
-70
-0.2
-0.4
-0.6
-80
-90
-100
-110
-120
0
5
10
15
20
25
-250 -200 -150 -100 -50
0
Output Frequency (MHz)
50 100 150 200 250
DSA (dB)
With 0.8 GHz matching
With 0.8 GHz matching, fIN = 840 MHz, AIN= –3 dBFS
图6-61. RX Output FFT at 0.8 GHz
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
Setting = 0)
图6-60. RX Calibrated Integrated Phase Error vs DSA Setting at
0.8 GHz
-153.8
DSA = 4dB
-154
-147
-40 èC, DSA = 4dB
DSA = 12dB
-40 èC, DSA = 12dB
-148
25 èC, DSA = 4dB
-154.2
-154.4
-154.6
-154.8
-155
-149
25 èC, DSA = 12dB
110 èC, DSA = 4dB
-150
110 èC, DSA = 12dB
-151
-152
-153
-154
-155
-156
-157
-155.2
-155.4
-155.6
-155.8
-156
-40 -25 -10
5
20
35
50
65
80
95 110
-30
-25
-20
Input Amplitude (dBFS)
-15
-10
-5
0
Temperature (èC)
With 0.8 GHz matching, 12.5-MHz offset from tone
With 0.8 GHz matching, DSA Setting = 12 dB, 12.5-MHz offset
from tone
图6-62. RX Noise Spectral Density vs Temperature at 0.8 GHz
图6-63. RX Noise Spectral Density vs Input Amplitude and
Temperature at 0.8 GHz
-147
-80
1RX, DSA = 4dB
1RX, DSA = 12dB
2RX, DSA = 4dB
2RX, DSA = 12dB
-40 èC
25 èC
-82
110èC
-84
-148
-149
3RX, DSA = 4dB
3RX, DSA = 12dB
-150
-151
-152
-153
-154
-155
-156
-157
-86
-88
-90
-92
-94
-96
-98
-30
-25
-20
Input Amplitude (dBFS)
-15
-10
-5
0
0
2
4
6
8
DSA (dB)
10
12
14
16
With 0.8 GHz matching, 12.5-MHz offset from tone
A.
With 0.8 GHz matching, each tone –7 dBFS, tone spacing =
20 MHz
图6-64. RX Noise Spectral Density vs Input Amplitude and
Channel at 0.8 GHz
图6-65. RX IMD3 vs DSA Setting and Temperature at 0.8 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.2 RX Typical Characteristics at 800MHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-90
-92
-86
-90
-40 èC
25 èC
110èC
-94
-94
-96
-98
-40 èC
25 èC
110èC
-98
-102
-106
-110
-114
-118
-122
-100
-102
-104
-106
-108
-110
0
2
4
6
8
DSA (dB)
10
12
14
16
-36 -33 -30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
With 0.8 GHz matching, tone spacing = 20 MHz, DSA = 4 dB
With 0.8 GHz matching, each tone –7 dBFS, tone spacing =
20 MHz
图6-67. RX IMD3 vs Input Level and Temperature at 0.8 GHz
图6-66. RX IMD5 vs DSA Setting and Temperature at 0.8 GHz
-85
-85
-40 èC
-40 èC
25 èC
25 èC
-90
-90
110èC
110èC
-95
-95
-100
-105
-110
-115
-120
-100
-105
-110
-115
-120
-30
-27
-24
-21
-18
-15
Input Amplitude (dBFS)
-12
-9
-6
-36 -33 -30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
With 0.8 GHz matching, tone spacing = 20 MHz, DSA = 12 dB
With 0.8 GHz matching, tone spacing = 20 MHz, DSA = 12 dB
图6-68. RX IMD3 vs Input Level and Temperature at 0.8 GHz
图6-69. RX IMD5 vs Input Level and Temperature at 0.8 GHz
-55
-60
1RX
2RX
3RX
4RX
-40èC
25èC
-63
110èC
-66
-60
-65
-70
-75
-80
-85
-90
-95
-69
-72
-75
-78
-81
-84
-87
3
6
9
12
15
18
3
6
9
12
15
18
DSA (dB)
DSA (dB)
With 0.8 GHz matching, measured after HD2 trim, DDC
bypass mode (TI only mode for characterization)
With 0.8 GHz matching, measured after HD2 trim, DDC
bypass mode (TI only mode for characterization)
图6-70. RX HD2 vs DSA Setting and Channel at 0.8 GHz
图6-71. RX HD2 vs DSA Setting and Temperature at 0.8 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.2 RX Typical Characteristics at 800MHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-61
-66
-71
-76
-81
-86
-91
-96
-69
-74
-79
-84
-89
-94
-40 èC, DSA=4dB
-40 èC, DSA=12dB
25 èC, DSA=4dB
25 èC, DSA=12dB
110 èC, DSA=4dB
110 èC, DSA=12dB
1RX
2RX
3RX
4RX
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3
0
3
5
7
9
11
DSA (dB)
13
15
17 18
With 0.8 GHz matching, measured after HD2 trim, DDC
bypass mode (TI only mode for characterization)
With 0.8 GHz matching, DDC bypass mode (TI only mode for
characterization)
图6-72. RX HD2 vs Input Level and Temperature at 0.8 GHz
图6-73. RX HD3 vs DSA Setting and Channel at 0.8 GHz
-70
-69
-40èC
25èC
1RX
2RX
3RX
4RX
-75
-80
110èC
-72
-85
-75
-78
-81
-84
-87
-90
-95
-100
-105
-110
-115
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3
0
3
6
9
12
15
18
DSA (dB)
With 0.8 GHz matching, DDC bypass mode (TI only mode for
characterization)
With 0.8 GHz matching, DDC bypass mode (TI only mode for
characterization)
图6-75. RX HD3 vs Input Level and Channel at 0.8 GHz
图6-74. RX HD3 vs DSA Setting and Temperature at 0.8 GHz
-65
-70
100
1RX
2RX
3RX
4RX
-75
-80
95
90
85
80
-85
-90
-95
-100
-105
-110
-40 èC, DSA=4dB
-40 èC, DSA=12dB
25 èC, DSA=4dB
25 èC, DSA=12dB
110 èC, DSA=4dB
110 èC, DSA=12dB
-115
-120
-125
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3
0
0
2
4
6
8
DSA (dB)
10
12
14
16
With 0.8 GHz matching, DDC bypass mode (TI only mode for
characterization)
With 0.8 GHz matching
图6-77. RX Non-HD2/3 vs DSA Setting at 0.8 GHz
图6-76. RX HD3 vs Input Level and Temperature at 0.8 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.2 RX Typical Characteristics at 800MHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-80
-82
-84
-86
-88
-90
-92
-94
-94
-96
1RX
2RX
3RX
4RX
1RX
2RX
3RX
4RX
-98
-100
-102
-104
-106
-108
-110
-112
MIN
TYP
Supply Voltage
MAX
MIN
TYP
Supply Voltages
MAX
With 0.8 GHz matching, –7 dBFS each tone, 20-MHz tone
spacing, all supplies at MIN, TYP, or MAX recommended
operating voltages
With 0.8 GHz matching, –7 dBFS each tone, 20-MHz tone
spacing, all supplies at MIN, TYP, or MAX recommended
operating voltages
图6-78. RX IMD3 vs Supply and Channel at 0.8 GHz
图6-79. RX IMD5 vs Supply and Channel at 0.8 GHz
-154
-154.2
-154.4
-154.6
-154.8
-155
-155.2
-155.4
-155.6
-155.8
1RX
2RX
3RX
4RX
-156
MIN
TYP
Supply Voltages
MAX
With 0.8 GHz matching, 12.5-MHz offset, all supplies at MIN, TYP, or MAX recommended operating voltages
图6-80. RX Noise Spectral Density vs Supply and Channel at 0.8 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.6
0.4
0.2
0
0.3
0.2
0.1
0
DSA=4dB
DSA=6dB
DSA=8dB
DSA=10dB
DSA=12dB
DSA=14dB
-0.1
-0.2
-0.3
-0.4
-0.5
-0.2
-0.4
-0.6
-0.8
1RX
2RX
3RX
4RX
1650
1750
1850
Output Frequency (MHz)
1950
2050
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (èC)
With 1.8 GHz matching, normalized to 1.75 GHz
With 1.8 GHz matching, normalized to fullscale at 25°C for
each channel
图6-81. RX In-Band Gain Flatness, fIN = 1750 MHz
图6-82. RX Input Fullscale vs Temperature and Channel at 1.75
GHz
25
20
15
10
5
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
-5
1RX
2RX
-10
3RX
4RX
-15
-20
1RX
2RX
3RX
4RX
-0.25
-0.3
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (èC)
0
5
10
15
20
25
DSA (dB)
With 2.6 GHz matching, normalized to phase at 25°C
With 1.8 GHz matching
Differential Amplitude Error = PIN(DSA Setting –1) –
图6-83. RX Input Phase vs Temperature and DSA at fIN = 1.75
GHz
PIN(DSA Setting) + 1
图6-84. RX Uncalibrated Differential Amplitude Error vs DSA
Setting at 1.75 GHz
0.03
0.1
-0.1
-0.3
-0.5
-0.7
1RX
2RX
3RX
4RX
0.025
0.02
0.015
0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.025
-0.9
1RX
2RX
-1.1
3RX
4RX
-1.3
0
5
10
15
20
25
0
5
10
15
20
25
DSA (dB)
DSA (dB)
With 1.8 GHz matching
With 1.8 GHz matching
Differential Amplitude Error = PIN(DSA Setting –1) –
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
PIN(DSA Setting) + 1
Setting = 0) + (DSA Setting)
图6-85. RX Calibrated Differential Amplitude Error vs DSA
图6-86. RX Uncalibrated Integrated Amplitude Error vs DSA
Setting at 1.75 GHz
Setting at 1.75 GHz
Copyright © 2023 Texas Instruments Incorporated
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.016
0.014
0.012
0.01
1
0.5
0
1RX
2RX
3RX
4RX
0.008
0.006
0.004
0.002
0
-0.5
-1
-0.002
-0.004
-0.006
-0.008
-1.5
-2
1RX
2RX
3RX
4RX
0
5
10
15
20
25
0
5
10
15
20
25
DSA (dB)
DSA (dB)
With 1.8 GHz matching
With 1.8 GHz matching
Differential Phase Error = PhaseIN(DSA Setting –1) –
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
PhaseIN(DSA Setting)
Setting = 0) + (DSA Setting)
图6-88. RX Uncalibrated Differential Phase Error vs DSA
图6-87. RX Calibrated Integrated Amplitude Error vs DSA
Setting at 1.75 GHz
Setting at 1.75 GHz
0.5
0.2
1
0
-1
-2
-3
-4
-5
-6
-7
-0.1
-0.4
-8
1RX
2RX
3RX
4RX
-1
1RX
-0.7
2RX
3RX
4RX
-9
-10
-11
0
5
10
15
20
25
0
5
10
15
20
25
DSA (dB)
DSA (dB)
With 1.8 GHz matching
With 1.8 GHz matching
Differential Phase Error = PhaseIN(DSA Setting –1) –
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
PhaseIN(DSA Setting)
Setting = 0)
图6-89. RX Calibrated Differential Phase Error vs DSA Setting 图6-90. RX Uncalibrated Integrated Phase Error vs DSA Setting
at 1.75 GHz
at 1.75 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
1
0.5
0
0
-10
SNR = 60.9dBFS
-20
-30
-40
-50
-60
-70
-0.5
-1
-80
-90
1RX
2RX
3RX
4RX
-100
-110
-120
-1.5
0
5
10
15
20
25
-250 -200 -150 -100 -50
0
Output Frequency (MHz)
50 100 150 200 250
DSA (dB)
With 1.8 GHz matching
With 1.8 GHz matching, fIN = 2610 MHz, AIN= –3 dBFS
图6-92. RX Output FFT at 1.75 GHz
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
Setting = 0)
图6-91. RX Calibrated Integrated Phase Error vs DSA Setting at
1.75 GHz
-154.6
-154.8
-155
-145
-40 èC, DSA = 4dB
-146
-40 èC, DSA = 12dB
25 èC, DSA = 4dB
-147
25 èC, DSA = 12dB
-148
110 èC, DSA = 4dB
-149
110 èC, DSA = 12dB
-150
-151
-152
-153
-154
-155
-156
-157
-155.2
-155.4
-155.6
-155.8
DSA = 4dB
DSA = 12dB
-156
-40 -25 -10
5
20
35
50
65
80 95 110
-30
-25
-20
-15
Input Amplitude (dBFS)
-10
-5
0
Temperature (èC)
With 1.8 GHz matching, 12.5-MHz offset from tone
With 1.8 GHz matching, DSA Setting = 12 dB, 12.5-MHz offset
from tone
图6-93. RX Noise Spectral Density vs Temperature at 1.75 GHz
图6-94. RX Noise Spectral Density vs Input Amplitude and
Temperature at 1.75 GHz
-145
-70
1RX, DSA = 4dB
1RX, DSA = 12dB
2RX, DSA = 4dB
-40 èC
-146
-72
25 èC
110èC
-74
-147
2RX, DSA = 12dB
3RX, DSA = 4dB
3RX, DSA = 12dB
4RX, DSA = 4dB
4RX, DSA = 12dB
-148
-149
-150
-151
-152
-153
-154
-155
-156
-157
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-30
-25
-20
Input Amplitude (dBFS)
-15
-10
-5
0
0
2
4
6
8
10
DSA (dB)
12
14
16
18
20
With 1.8 GHz matching, 12.5-MHz offset from tone
With 1.8 GHz matching, each tone –7 dBFS, tone spacing =
20 MHz
图6-95. RX Noise Spectral Density vs Input Amplitude and
Channel at 1.75 GHz
图6-96. RX IMD3 vs DSA Setting and Temperature at 1.75 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-88
-92
-80
-85
-40 èC
25 èC
110èC
-40 èC
25 èC
110èC
-96
-90
-100
-104
-108
-112
-116
-120
-124
-95
-100
-105
-110
-115
-120
-125
-36 -33 -30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-36 -33 -30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
With 1.8 GHz matching, tone spacing = 20 MHz, DSA = 4 dB
With 1.8 GHz matching, tone spacing = 20 MHz, DSA = 12 dB
图6-97. RX IMD3 vs Input Level and Temperature at 1.75 GHz
图6-98. RX IMD3 vs Input Level and Temperature at 1.75 GHz
-75
-72
1RX
2RX
3RX
4RX
-40èC
25èC
110èC
-80
-85
-77
-82
-90
-87
-95
-92
-100
-105
-97
-102
3
5
7
9
11
DSA (dB)
13
15
17
19
3
5
7
9
11
DSA (dB)
13
15
17
19
With 1.8 GHz matching, fin = 1900MHz, measured after HD2
trim, DDC bypass mode (TI only mode for characterization)
With 1.8 GHz matching, fin = 1900MHz, measured after HD2
trim, DDC bypass mode (TI only mode for characterization)
图6-99. RX HD2 vs DSA Setting and Channel at 1.9 GHz
图6-100. RX HD2 vs DSA Setting and Temperature at 1.9 GHz
-75
-74
1RX, DSA=4dB
1RX, DSA=12dB
2RX, DSA=4dB
2RX, DSA=12dB
3RX, DSA=4dB
3RX, DSA=12dB
4RX, DSA = 4dB
4RX, DSA = 12dB
-40 èC, DSA=4dB
-40 èC, DSA=12dB
25 èC, DSA=4dB
25 èC, DSA=12dB
110 èC, DSA=4dB
110 èC, DSA=12dB
-80
-85
-79
-84
-90
-89
-95
-100
-105
-110
-115
-120
-125
-94
-99
-104
-109
-114
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3
0
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3
0
With 1.8 GHz matching, fin = 1900MHz, measured after HD2
trim, DDC bypass mode (TI only mode for characterization)
With 1.8 GHz matching, fin = 1900MHz, measured after HD2
trim, DDC bypass mode (TI only mode for characterization)
图6-101. RX HD2 vs Input Amplitude and Channel at 1.9 GHz
图6-102. RX HD2 vs Input Amplitude and Temperature at 1.9
GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-65
-70
-65
-70
-75
-80
-85
-90
-95
1RX
2RX
3RX
4RX
-40èC
25èC
110èC
-75
-80
-85
-90
-95
-100
-105
3
5
7
9
11
DSA (dB)
13
15
17
19
3
5
7
9
11
DSA (dB)
13
15
17
19
With 1.8 GHz matching, fin = 1900MHz, DDC bypass mode (TI
only mode for characterization)
With 1.8 GHz matching, fin = 1900MHz, DDC bypass mode (TI
only mode for characterization)
图6-103. RX HD3 vs DSA Setting and Channel at 1.9 GHz
图6-104. RX HD3 vs DSA Setting and Temperature at 1.9 GHz
-50
-65
1RX, DSA=4dB
1RX, DSA=12dB
2RX, DSA=4dB
2RX, DSA=12dB
3RX, DSA=4dB
3RX, DSA=12dB
4RX, DSA = 4dB
4RX, DSA = 12dB
-40 èC, DSA=4dB
-40 èC, DSA=12dB
25 èC, DSA=4dB
25 èC, DSA=12dB
110 èC, DSA=4dB
110 èC, DSA=12dB
-70
-75
-60
-70
-80
-85
-80
-90
-90
-95
-100
-105
-110
-115
-100
-110
-120
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3
0
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3
0
With 1.8 GHz matching, fin = 1900MHz, DDC bypass mode (TI
only mode for characterization)
With 1.8 GHz matching, fin = 1900MHz, DDC bypass mode (TI
only mode for characterization)
图6-105. RX HD3 vs Input Level and Channel at 1.9 GHz
图6-106. RX HD3 vs Input Level and Temperature at 1.9 GHz
95
81
1RX
2RX
3RX
4RX
80.8
80.6
80.4
80.2
80
90
85
80
79.8
79.6
79.4
79.2
79
75
1RX,
2RX
3RX
4RX
70
65
-30
-25
-20
Input Amplitude (dBFS)
-15
-10
-5
0
0
2
4
6
8
DSA (dB)
10
12
14
16
With 1.8 GHz matching, decimated by 3
With 1.8 GHz matching
图6-107. RX In-Band SFDR (±400 MHz) vs Input Amplitude at
图6-108. RX Non-HD2/3 vs DSA Setting at 1.75 GHz
1.75 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-84
-86
-151
-151.5
-152
1RX
2RX
3RX
4RX
-88
-90
-152.5
-153
-92
-94
-153.5
-154
-96
-98
-154.5
-155
-100
-102
-104
1RX
2RX
3RX
4RX
-155.5
-156
MIN
TYP
Supply Voltage
MAX
MIN
TYP
Supply Voltages
MAX
With 1.8 GHz matching, 12.5-MHz offset, all supplies at MIN,
TYP, or MAX recommended operating voltages
With 1.8 GHz matching, –7 dBFS each tone, 20-MHz tone
spacing, all supplies at MIN, TYP, or MAX recommended
operating voltages
图6-110. RX Noise Spectral Density vs Supply and Channel at
1.75 GHz
图6-109. RX IMD3 vs Supply and Channel at 1.75 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.4 RX Typical Characteristics 2.6GHz
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
2
1.5
1
2
1.5
1
DSA=4dB
DSA=6dB
DSA=8dB
DSA=10dB
DSA=12dB
DSA=14dB
0.5
0
0.5
0
-0.5
-1
-0.5
-1
1RX
2RX
3RX
4RX
-1.5
-2
-1.5
-2
2350 2400 2450 2500 2550 2600 2650 2700 2750 2800
Input Frequency (MHz)
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
With matching, normalized to power at 2.6 GHz for each DSA
setting
With 2.6 GHz matching, normalized to fullscale at 25°C for
each channel
图6-111. RX Inband Gain Flatness, fIN = 2600 MHz
图6-112. RX Input Fullscale vs Temperature and Channel at 2.6
GHz
10
0
1RX
2RX
3RX
4RX
SNR=62.5dBFS
-10
-20
8
6
4
-30
-40
2
0
-50
-60
-70
-2
-80
-4
-90
-6
-100
-110
-120
-8
-10
0
2
4
6
8
10 12 14 16 18 20 22 24
DSA Setting (dB)
-250
250
Frequency (MHz)
With 2.6 GHz matching
With 2.6 GHz matching, fIN = 2610 MHz, AIN= –3 dBFS
图6-114. RX Output FFT at 2.6 GHz
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
Setting = 0)
图6-113. RX Calibrated Integrated Phase Error vs DSA Setting
at 2.6 GHz
-152
-150
-151
-152
-153
-154
DSA = 4
DSA = 12
-152.5
-153
-153.5
-154
-154.5
-155
-40èC
25èC
105èC
-155
-156
-155.5
-156
-40
-20
0
20
40
60
80
100
120
-30
-25
-20
Input Amplitude (dBFS)
-15
-10
-5
0
Temperature (èC)
With 2.6 GHz matching, 12.5-MHz offset from tone
With 2.6 GHz matching, DSA Setting = 12 dB, 12.5-MHz offset
from tone
图6-115. RX Noise Spectral Density vs Temperature at 2.6 GHz
图6-116. RX Noise Spectral Density vs Input Amplitude and
Temperature at 2.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.4 RX Typical Characteristics 2.6GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-146
-148
-150
-152
-154
-156
-146
-148
-150
-152
-154
-156
-158
-160
1RX, DSA=4
1RX, DSA=12
2RX, DSA=4
2RX, DSA=12
3RX, DSA=4
3RX, DSA=12
4RX, DSA=4
4RX, DSA=12
DSA=0dB, -40C
DSA=0dB, 25C
DSA=0dB, 110C
DSA=3dB, -40C
DSA=3dB, 25C
DSA=3dB, 110C
DSA=12dB, -40C
DSA=12dB, 25C
DSA=12dB, 110C
-30
-25
-20 -10
Input Amplitude (dBFS)
-15
-5
0
-100
-80
-60
-40
-20
0
Input Amplitude (dBFS)
With 2.6 GHz matching, 12.5-MHz offset from tone
50-MHz offset from tone, external clock mode
图6-117. RX Noise Spectral Density vs Input Amplitude and
图6-118. RX Noise Spectral Density vs Input Amplitude at 2.61
Channel at 2.6 GHz
GHz (Ext. Clock)
-60
-70
-75
Temp=-40èC
Temp=25èC
Temp=110èC
-65
-80
-85
-70
-75
-80
-85
-90
-90
-95
-100
-105
-110
Temp=-40èC
Temp=25èC
-115
Temp=110èC
-120
0
2
4
6
DSA Setting (dB)
8
10
12
14
16
-40
-35
-30
-25
Input Level (dBFS)
-20
-15
-10
-5
0
With 2.6 GHz matching, tone spacing = 20 MHz, DSA = 4 dB
With 2.6 GHz matching, each tone –7 dBFS, tone spacing =
20 MHz
图6-120. RX IMD3 vs Input Level and Temperature at 2.6 GHz
图6-119. RX IMD3 vs DSA Setting and Temperature at 2.6 GHz
-75
-80
-85
-90
-95
-100
-105
-110
-115
Temp=-40èC
Temp=25èC
-120
Temp=110èC
-125
-40
-35
-30
-25
-20
-15
Input Level (dBFS)
-10
-5
0
With 2.6 GHz matching, tone spacing = 20 MHz, DSA = 12 dB
Tone spacing = 50 MHz, External clock mode
图6-121. RX IMD3 vs Input Level and Temperature at 2.6 GHz
图6-122. RX IMD3 vs Input Level at 2.6 GHz (Ext. Clock)
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.4 RX Typical Characteristics 2.6GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-60
-65
-70
-75
-80
-85
-90
1RX
2RX
-95
3RX
4RX
-100
2
4
6
8
10 12
DSA Setting (dB)
14
16
18
20
With 2.6 GHz matching, DDC bypass mode (TI only mode for
characterization)
External clock mode
图6-123. RX IMD3 vs Tone Spacing at 2.6 GHz (Ext. Clock)
图6-124. RX HD2 vs DSA Setting and Channel at 2.6 GHz
-70
-80
Temp=-40èC
-40C
Temp=25èC
-75
-80
25C
-85
-90
Temp=110èC
110C
-85
-95
-90
-100
-105
-110
-115
-120
-95
-100
-105
-110
-30
-25
-20
-15
Input Level (dBFS)
-10
-5
0
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
Input Amplitude (dBFS)
0
With 2.6 GHz matching, DDC bypass mode (TI only mode for
characterization)
External clock mode
图6-126. RX HD2 vs Input Level and Temperature at 2.6 GHz
图6-125. RX HD2 vs Input Level and Temperature at 2.6 GHz
-60
-65
-70
-75
-80
-85
-60
-65
-70
-75
-80
-85
-90
-90
1RX
2RX
Temp=-40èC
-95
-95
3RX
4RX
Temp=-25èC
Temp=110èC
-100
-100
2
4
6
8
10 12
DSA Setting (dB)
14
16
18
20
2
4
6
8
DSA Setting (dBc)
10
12
14
16
18
With 2.6 GHz matching, DDC bypass mode (TI only mode for
characterization)
With 2.6 GHz matching, DDC bypass mode (TI only mode for
characterization)
图6-127. RX HD3 vs DSA Setting and Channel at 2.6 GHz
图6-128. RX HD3 vs DSA Setting and Temperature at 2.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.4 RX Typical Characteristics 2.6GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-60
-65
-60
-65
1RX
2RX
3RX
4RX
Temp=-40èC
Temp=25èC
Temp=110èC
-70
-70
-75
-75
-80
-80
-85
-85
-90
-90
-95
-95
-100
-105
-110
-100
-105
-110
-30
-25
-20
-15
-10
Input Amplitude (dBFS)
-5
0
-30
-25
-20
-15
Input Level (dBFS)
-10
-5
0
With 2.6 GHz matching, DDC bypass mode (TI only mode for
characterization)
With 2.6 GHz matching, DDC bypass mode (TI only mode for
characterization)
图6-129. RX HD3 vs Input Level and Channel at 2.6 GHz
图6-130. RX HD3 vs Input Level and Temperature at 2.6 GHz
100
-70
-40èC
25èC
105èC
-40C
-75
25C
95
110C
-80
-85
-90
90
85
80
75
70
-95
-100
-105
-110
-115
-120
-30
-25
-20
-15
-10
Input Amplitude (dBFS)
-5
0
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
Input Amplitude (dBFS)
0
With 2.6 GHz matching, decimate by 4
External clock mode
图6-132. RX In-Band SFDR (±300 MHz) vs Input Amplitude and
图6-131. RX HD3 vs Input Level and Temperature at 2.6 GHz
Temperature at 2.6 GHz
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
-100
0
2
4
6
8
10
DSA Setting (dB)
12
14
16
18
With 2.6 GHz matching
External clock mode, 50MHz tone spacing, excluding 3rd order
distortion
图6-133. RX Non-HD2/3 vs DSA Setting at 2.6 GHz
图6-134. RX 2-tone SFDR vs Input Amplitude at 2.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.4 RX Typical Characteristics 2.6GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-150
-150.5
-151
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
1RX
2RX
3RX
4RX
1RX
2RX
3RX
4RX
-151.5
-152
-152.5
-153
-153.5
-154
MIN
TYP
Supply Voltages
MAX
MIN
TYP
Supply Voltages
MAX
With 2.6 GHz matching, 12.5-MHz offset, all supplies at MIN,
TYP, or MAX recommended operating voltages
With 2.6 GHz matching, –7 dBFS each tone, 20-MHz tone
spacing, all supplies at MIN, TYP, or MAX recommended
operating voltages
图6-136. RX Noise Spectral Density vs Supply and Channel at
2.6 GHz
图6-135. RX IMD3 vs Supply and Channel at 2.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.5 RX Typical Characteristics 3.5GHz
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
2
1.5
1
70
60
DSA=4dB
DSA=6dB
DSA=8dB
DSA=10dB
DSA=12dB
DSA=14dB
50
40
30
20
0.5
0
10
0
-10
-20
-30
-40
-50
-60
-70
-0.5
-1
DSA=0dB
DSA=2dB
DSA=4dB
DSA=6dB
DSA=8dB
DSA=10dB
DSA=12dB
DSA=14dB
DSA=16dB
DSA=18dB
DSA=20dB
DSA=22dB
DSA=24dB
-1.5
-2
-30
-10
10
30
50
70
90
110120
3400 3450 3500 3550 3600 3650 3700 3750 3800
Input Frequency (MHz)
Temperature (èC)
With 3.6 GHz matching, normalized to phase at 25°C
With 3.6 GHz matching, normalized to 3.6 GHz
图6-138. RX Input Phase vs Temperature at 3.6 GHz
图6-137. RX In-Band Gain Flatness, fIN = 3600 MHz
0.5
0.1
-40èC
-40èC
0.4
0.08
25èC
25èC
105èC
105èC
0.3
0.06
0.2
0.1
0.04
0.02
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.02
-0.04
-0.06
-0.08
-0.1
0
5
10 15
DSA Setting (dB)
20
25
0
5
10 15
DSA Setting (dB)
20
25
With 3.6 GHz matching
With 3.6 GHz matching
Differential Amplitude Error = PIN(DSA Setting –1) –
Differential Amplitude Error = PIN(DSA Setting –1) –
PIN(DSA Setting) + 1
PIN(DSA Setting) + 1
图6-139. RX Uncalibrated Differential Amplitude Error vs DSA
图6-140. RX Calibrated Differential Amplitude Error vs DSA
Setting at 3.6 GHz
Setting at 3.6 GHz
4
3.5
3
1
-40èC
0.8
25èC
105èC
0.6
2.5
2
0.4
0.2
0
1.5
1
-0.2
-0.4
-0.6
-0.8
-1
0.5
0
-40èC
25èC
-0.5
105èC
-1
0
5
10 15
DSA Setting (dB)
20
25
0
5
10 15
DSA Setting (dB)
20
25
With 3.6 GHz matching
With 3.6 GHz matching
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
Setting = 0) + (DSA Setting)
Setting = 0) + (DSA Setting)
图6-141. RX Uncalibrated Integrated Amplitude Error vs DSA
图6-142. RX Calibrated Integrated Amplitude Error vs DSA
Setting at 3.6 GHz
Setting at 3.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.5 RX Typical Characteristics 3.5GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
2
1.5
1
2.5
2
-40èC
25èC
105èC
-40èC
25èC
105èC
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
-2.5
0
5
10 15
DSA Setting (dB)
20
25
0
5
10 15
DSA Setting (dB)
20
25
With 3.6 GHz matching
With 3.6 GHz matching
Differential Phase Error = PhaseIN(DSA Setting –1) –
Differential Phase Error = PhaseIN(DSA Setting –1) –
PhaseIN(DSA Setting)
PhaseIN(DSA Setting)
图6-143. RX Uncalibrated Phase Error vs DSA Setting at 3.6
图6-144. RX Calibrated Differential Phase Error vs DSA Setting
GHz
at 3.6 GHz
5
4
2.5
-40èC
2
25èC
105èC
3
1.5
2
1
0.5
0
1
0
-1
-2
-0.5
-1
-3
-1.5
-2
-40èC
25èC
-4
105èC
-5
-2.5
0
5
10 15
DSA Setting (dB)
20
25
0
5
10 15
DSA Setting (dB)
20
25
With 3.6 GHz matching
With 3.6 GHz matching
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
Setting = 0)
Setting = 0)
图6-145. RX Uncalibrated Integrated Phase Error vs DSA
图6-146. RX Calibrated Integrated Phase Error vs DSA Setting
Setting at 3.6 GHz
at 3.6 GHz
0
-60
Temp=-40èC
Temp=25èC
Temp=110èC
SNR=62.2dBFS
-10
-20
-65
-30
-40
-70
-75
-80
-85
-90
-50
-60
-70
-80
-90
-100
-110
-120
-250
250
0
2
4
6
8
10
DSA Setting (dB)
12
14
16
Frequency (MHz)
With 3.6 GHz matching , fIN = 3610 MHz, AIN = –3 dBFS
图6-147. RX Output FFT at 3.6 GHz
With 3.5 GHz matching, each tone at –7 dBFS, 20-MHz tone
spacing
图6-148. RX IMD3 vs DSA Setting and Temperature at 3.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.5 RX Typical Characteristics 3.5GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-80
-85
-90
-95
-100
-105
-110
Temp=-40èC
-115
Temp=25èC
Temp=110èC
-120
-40
-35
-30
-25
-20
-15
DSA Setting (dB)
-10
-5
0
With 3.5 GHz matching, 20-MHz tone spacing
External clock mode, 20-MHz tone spacing, 2x Decimation
图6-149. RX IMD3 vs Input Level and Temperature at 3.6 GHz
图6-150. RX IMD3 vs Input Level
-60
-65
-70
-75
-80
-85
-90
1RX
2RX
-95
3RX
4RX
-100
2
4
6
8
10 12
DSA Setting (dB)
14
16
18
20
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
External clock mode, 2x Decimation
图6-151. RX IMD3 vs Tone Spacing at 3.76GHz
图6-152. RX HD2 vs DSA Setting and Channel at 3.6 GHz
-70
-71
-40èC
1RX
25èC
2RX
3RX
4RX
-75
-80
-74
110èC
-77
-85
-80
-83
-86
-89
-92
-90
-95
-100
-105
-110
-30
-25
-20
-15
-10
Input Amplitude (dBFS)
-5
0
3
6
9
12
15
18
DSA (dB)
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
图6-154. RX HD2 vs Input Level and Channel at 3.6 GHz
图6-153. RX HD2 vs DSA Setting and Temperature at 3.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.5 RX Typical Characteristics 3.5GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-70
Temp=-40èC
Temp=25èC
Temp=110èC
-75
-80
-85
-90
-95
-100
-105
-110
-30
-25
-20
-15
Input Level (dBFS)
-10
-5
0
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
External clock mode, 2x Decimation
图6-156. RX HD2 vs Input Level at 3.76 GHz
图6-155. RX HD2 vs Input Level and Temperature at 3.6 GHz
-60
-65
-70
-75
-80
-85
-90
-90
3160MHz
3760MHz
4340MHz
-95
-100
-105
-110
-115
-120
1RX
2RX
3RX
4RX
-95
-100
2
4
6
8
10 12
DSA Setting (dB)
14
16
18
20
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
Input Amplitude (dBFS)
0
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
External clock mode, 25°C, 2x Decimation
图6-157. RX HD2 vs Input Level
图6-158. RX HD3 vs DSA Setting and Channel at 3.6 GHz
-60
-65
-70
-75
-80
-85
-90
-64
-40èC
25èC
110èC
-67
-70
-73
-76
-79
-95
1RX
-100
-105
-110
2RX
3RX
4RX
-30
-25
-20
-15
-10
Input Amplitude (dBFS)
-5
0
3
6
9
12
15
18
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
DSA (dB)
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
图6-160. RX HD3 vs Input Level and Channel at 3.6 GHz
图6-159. RX HD3 vs DSA Setting and Temperature at 3.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.5 RX Typical Characteristics 3.5GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-70
-75
-60
-70
Temp=-40èC
Temp=25èC
Temp=110èC
-40C
25C
110C
-80
-80
-85
-90
-90
-95
-100
-110
-120
-100
-105
-110
-30
-25
-20
-15
Input Level (dBFS)
-10
-5
0
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
Input Amplitude (dBFS)
0
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
External clock mode, 2x Decimation
图6-162. RX HD3 vs Input Level at 3.76GHz
图6-161. RX HD3 vs Input Level and Temperature at 3.6 GHz
-140
1RX, DSA=4dB
1RX, DSA=12dB
2RX, DSA=4dB
2RX, DSA=12dB
3RX, DSA=4dB
3RX, DSA=12dB
4RX, DSA=4dB
4RX, DSA=12dB
-142
-144
-146
-148
-150
-152
-154
-156
-158
-160
-30
-25
-20
-15
Input Level (dBFS)
-10
-5
0
With 3.5 GHz matching, 12.5-MHz offset from tone
External clock mode, 25°C, 2x Decimation
图6-164. RX Noise Spectral Density vs Input Level and DSA
图6-163. RX HD3 vs Input Level
Setting at 3.6 GHz
110
1RX
2RX
3RX
4RX
105
100
95
90
85
80
75
70
-30
-25
-20
-15
-10
Input Amplitude (dBFS)
-5
0
With 3.5 GHz matching
External clock mode, 25°C, 2x Decimation
图6-166. RX In-Band SFDR (±200 MHz) vs Input Level and
图6-165. RX Noise Spectral Density vs Input Level at 3.76GHz
Channel at 3.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.5 RX Typical Characteristics 3.5GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
90
85
80
75
70
65
60
-80
-85
DSA=0dB, -40C
DSA=0dB, 25C
DSA=0dB, 110C
DSA=3dB, -40C
DSA=3dB, 25C
DSA=3dB, 110C
-90
-95
-100
-105
-110
1RX
2RX
3RX
4RX
0
2
4
6
8
10
DSA Setting (dB)
12
14
16
18
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
Input Amplitude per Tone (dBFS)
0
With 3.5 GHz matching
External clock mode, 20MHz tone spacing, excluding 3rd order
distortion
图6-167. RX SFDR Excluding HD2/3 vs DSA Setting and
Channel at 3.6 GHz
图6-168. RX 2-tone SFDR vs Input Amplitude and DSA Setting
at 3.7 GHz
-70
1RX
2RX
-72
3RX
4RX
-74
-76
-78
-80
-82
-84
-86
-88
-90
External clock mode, 20MHz tone spacing, excluding 3rd order
distortion
MIN
TYP
MAX
Supply Voltages
With 3.6 GHz matching, –7 dBFS each tone, 20-MHz tone
spacing, all supplies at MIN, TYP, or MAX recommended
operating voltages
图6-169. RX 2-tone SFDR vs Input Amplitude and Frequency at
3.7 GHz
图6-170. RX IMD3 vs Supply Voltage and Channel at 3.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.5 RX Typical Characteristics 3.5GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-90
-92
-152
-152.5
-153
1RX
2RX
3RX
4RX
-94
-96
-153.5
-154
-98
-100
-102
-104
-106
-108
-110
-154.5
-155
1RX
2RX
3RX
4RX
-155.5
-156
MIN
TYP
MAX
MIN
TYP
MAX
Supply Voltages
Supply Voltages
With 3.6 GHz matching, tone at –20 dBFS, 12.5-MHz offset
frequency, all supplies at MIN, TYP, or MAX recommended
operating voltages
With 3.6 GHz matching, –7 dBFS each tone, 20-MHz tone
spacing, all supplies at MIN, TYP, or MAX recommended
operating voltages
图6-172. RX Noise Spectral Density vs Supply Voltage and
图6-171. RX IMD5 vs Supply Voltage and Channel at 3.6 GHz
Channel at 3.6 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.6 RX Typical Characteristics 4.9GHz
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.6
0.4
0.2
0
1
0.7
DSA=4dB
DSA=6dB
DSA=8dB
DSA=10dB
DSA=12dB
DSA=14dB
0.4
0.1
-0.2
-0.5
-0.8
-1.1
-1.4
-1.7
-2
-0.2
-0.4
-0.6
-0.8
1RX
2RX
3RX
4RX
-2.3
4700
4800
4900
Output Frequency (MHz)
5000
5100
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (èC)
With matching, normalized to power at 4.9GHz for each DSA
setting
With 4.9 GHz matching, normalized to fullscale at 25°C for
each channel
图6-173. RX Inband Gain Flatness, fIN = 4900 MHz
图6-174. RX Input Fullscale vs Temperature and Channel at 4.9
GHz
65
55
45
35
25
15
5
0.15
0.1
0.05
0
-0.05
-0.1
-5
-0.15
1RX
2RX
1RX
2RX
-15
3RX
4RX
-0.2
3RX
4RX
-25
-35
-0.25
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (èC)
0
5
10
15
20
25
DSA (dB)
With 4.9 GHz matching, normalized to phase at 25°C
With 4.9 GHz matching
Differential Amplitude Error = PIN(DSA Setting –1) –
图6-175. RX Input Phase vs Temperature and DSA at fOUT = 4.9
GHz
PIN(DSA Setting) + 1
图6-176. RX Uncalibrated Differential Amplitude Error vs DSA
Setting at 4.9 GHz
0.03
1.2
1RX
2RX
3RX
4RX
1RX
0.025
0.02
1
0.8
0.6
0.4
0.2
0
2RX
3RX
4RX
0.015
0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.025
-0.2
-0.4
-0.6
0
5
10
15
20
25
0
5
10
15
20
25
DSA (dB)
DSA (dB)
With 4.9 GHz matching
With 4.9 GHz matching
Differential Amplitude Error = PIN(DSA Setting –1) –
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
PIN(DSA Setting) + 1
Setting = 0) + (DSA Setting)
图6-177. RX Calibrated Differential Amplitude Error vs DSA
图6-178. RX Uncalibrated Integrated Amplitude Error vs DSA
Setting at 4.9 GHz
Setting at 4.9 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.6 RX Typical Characteristics 4.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.05
0.04
0.03
0.02
0.01
0
2
1.5
1
1RX
2RX
3RX
4RX
0.5
0
-0.5
-1
1RX
2RX
3RX
4RX
-1.5
-2
-0.01
-0.02
-2.5
0
5
10
15
20
25
0
5
10
15
20
25
DSA (dB)
DSA (dB)
With 4.9 GHz matching
With 4.9 GHz matching
Differential Phase Error = PhaseIN(DSA Setting –1) –
Integrated Amplitude Error = PIN(DSA Setting) –PIN(DSA
PhaseIN(DSA Setting)
Setting = 0) + (DSA Setting)
图6-180. RX Uncalibrated Differential Phase Error vs DSA
图6-179. RX Calibrated Integrated Amplitude Error vs DSA
Setting at 4.9 GHz
Setting at 4.9 GHz
1.5
1
3
2
0.5
0
1
0
-0.5
-1
-1
-2
-3
-1.5
1RX
-2
2RX
1RX
-4
2RX
3RX
4RX
3RX
4RX
-2.5
-3
-5
-6
0
5
10
15
20
25
0
5
10
15
20
25
DSA (dB)
DSA (dB)
With 4.9 GHz matching
With 4.9 GHz matching
Differential Phase Error = PhaseIN(DSA Setting –1) –
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
PhaseIN(DSA Setting)
Setting = 0)
图6-181. RX Calibrated Differential Phase Error vs DSA Setting
图6-182. RX Uncalibrated Integrated Phase Error vs DSA
at 4.9 GHz
Setting at 4.9 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.6 RX Typical Characteristics 4.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
1
0.5
0
0
-10
SNR = 60dBFS
-20
-30
-40
-0.5
-1
-50
-60
-70
-1.5
-2
-80
-90
1RX
2RX
3RX
4RX
-100
-110
-120
-2.5
-3
-250 -200 -150 -100 -50
0
Output Frequency (MHz)
50 100 150 200 250
0
5
10
15
20
25
DSA (dB)
With 4.9 GHz matching, fIN = 4910 MHz, AIN= –3 dBFS
图6-184. RX Output FFT at 4.9 GHz
With 4.9 GHz matching
Integrated Phase Error = Phase(DSA Setting) –Phase(DSA
Setting = 0)
图6-183. RX Calibrated Integrated Phase Error vs DSA Setting
at 4.9 GHz
-154.8
-145
DSA = 4dB
DSA = 12dB
-155
-40 èC, DSA = 4dB
-146
-40 èC, DSA = 12dB
25 èC, DSA = 4dB
-147
25 èC, DSA = 12dB
-148
110 èC, DSA = 4dB
-155.2
-155.4
-155.6
-155.8
-156
-149
110 èC, DSA = 12dB
-150
-151
-152
-153
-154
-155
-156
-157
-40 -25 -10
5
20
35
50
65
80
95 110
-30
-25
-20 -10
Input Amplitude (dBFS)
-15
-5
0
Temperature (èC)
With 4.9 GHz matching, 12.5-MHz offset from tone
With 4.9 GHz matching, DSA Setting = 12 dB, 12.5-MHz offset
from tone
图6-185. RX Noise Spectral Density vs Temperature at 4.9 GHz
图6-186. RX Noise Spectral Density vs Input Amplitude and
Temperature at 4.9 GHz
-145
-64
1RX, DSA = 4dB
1RX, DSA = 12dB
2RX, DSA = 4dB
-40 èC
25 èC
-146
110èC
-69
-147
2RX, DSA = 12dB
3RX, DSA = 4dB
3RX, DSA = 12dB
4RX, DSA = 4dB
4RX, DSA = 12dB
-148
-149
-150
-151
-152
-153
-154
-155
-156
-157
-74
-79
-84
-89
-94
-30
-25
-20
Input Amplitude (dBFS)
-15
-10
-5
0
0
2
4
6
8
10
DSA (dB)
12
14
16
18
20
With 4.9 GHz matching, 12.5-MHz offset from tone
With 4.9 GHz matching, each tone –7 dBFS, tone spacing =
20 MHz
图6-187. RX Noise Spectral Density vs Input Amplitude and
Channel at 4.9 GHz
图6-188. RX IMD3 vs DSA Setting and Temperature at 4.9 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.6 RX Typical Characteristics 4.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-80
-85
-75
-80
-40 èC
25 èC
110èC
-40 èC
25 èC
110èC
-90
-85
-95
-90
-100
-105
-110
-115
-120
-125
-130
-95
-100
-105
-110
-115
-120
-125
-36 -33 -30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-36 -33 -30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
With 4.9 GHz matching, tone spacing = 20 MHz, DSA = 4 dB
With 4.9 GHz matching, tone spacing = 20 MHz, DSA = 12 dB
图6-189. RX IMD3 vs Input Level and Temperature at 4.9 GHz
图6-190. RX IMD3 vs Input Level and Temperature at 4.9 GHz
-70
-70
1RX
2RX
3RX
4RX
-40èC
-72
25èC
-73
110èC
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-76
-79
-82
-85
-88
-91
-94
0
2
4
6
8
DSA (dB)
10
12
14
16
3
6
9
12
15
18
DSA (dB)
With 4.9 GHz matching, measured after HD2 trim, DDC
bypass mode (TI only mode for characterization)
With 4.9 GHz matching, measured after HD2 trim, DDC
bypass mode (TI only mode for characterization)
图6-191. RX HD2 vs DSA Setting and Channel at 4.9 GHz
图6-192. RX HD2 vs DSA and Temperature at 4.9 GHz
-72
-62
-40 èC
1RX
2RX
3RX
-75
25 èC
-78
-64
110èC
-81
-66
4RX
-68
-84
-87
-70
-72
-74
-76
-78
-80
-82
-90
-93
-96
-99
-102
-105
-108
-111
-114
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3 -1
3
5
7
9
11
DSA (dB)
13
15
17
19
With 4.9 GHz matching, measured after HD2 trim, DDC
bypass mode (TI only mode for characterization)
With 4.9 GHz matching, DDC bypass mode (TI only mode for
characterization)
图6-193. RX HD2 vs Input Level and Temperature at 4.9 GHz
图6-194. RX HD3 vs DSA Setting and Channel at 4.9 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.6 RX Typical Characteristics 4.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-62
-65
-68
-71
-74
-77
-80
-65
-70
-40èC
25èC
110èC
1RX
2RX
3RX
4RX
-75
-80
-85
-90
-95
-100
-105
-110
3
6
9
12
15
18
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3 -1
DSA (dB)
With 4.9 GHz matching, DDC bypass mode (TI only mode for
characterization)
With 4.9 GHz matching, DDC bypass mode (TI only mode for
characterization)
图6-195. RX HD3 vs DSA Setting and Temperature at 4.9 GHz
图6-196. RX HD3 vs Input Level and Channel at 4.9 GHz
-66
102
-40 èC
1RX
2RX
-69
99
25 èC
-72
110èC
-75
3RX
4RX
96
93
90
87
84
81
78
75
72
69
66
-78
-81
-84
-87
-90
-93
-96
-99
-102
-105
-108
-30 -27 -24 -21 -18 -15 -12
Input Amplitude (dBFS)
-9
-6
-3 -1
-30
-27
-24
-21
-18
-15
Input Amplitude (dBFS)
-12
-9
-6
With 4.9 GHz matching, DDC bypass mode (TI only mode for
characterization)
With 4.9 GHz matching, decimate by 3
图6-198. RX In-Band SFDR (±400 MHz) vs Input Amplitude and
Channel at 4.9 GHz
图6-197. RX HD3 vs Input Level and Temperature at 4.9 GHz
83
-70
1RX
2RX
3RX
4RX
1RX
2RX
3RX
4RX
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
82.5
82
81.5
81
80.5
80
79.5
79
0
2
4
6
8
DSA (dB)
10
12
14
16
MIN
TYP
Supply Voltage
MAX
With 4.9 GHz matching
With 4.9 GHz matching, –7 dBFS each tone, 20-MHz tone
spacing, all supplies at MIN, TYP, or MAX recommended
operating voltages
图6-199. RX Non-HD2/3 vs DSA Setting at 4.9 GHz
图6-200. RX IMD3 vs Supply and Channel at 4.9 GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.6 RX Typical Characteristics 4.9GHz (continued)
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-151
-151.5
-152
-152.5
-153
-153.5
-154
-154.5
-155
1RX
2RX
3RX
4RX
-155.5
-156
MIN
TYP
Supply Voltages
MAX
With 4.9 GHz matching, 12.5-MHz offset, all supplies at MIN, TYP, or MAX recommended operating voltages
图6-201. RX Noise Spectral Density vs Supply and Channel at 4.9 GHz
6.11.7 RX Typical Characteristics 6.8GHz
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 3000MSPS, output sample rate =
1500MSPS (decimate by 2x), External clock mode , AIN = –3 dBFS, DSA setting = 3 dB.
1
1
0.8
0.6
0.4
0.2
0
-40C
25C
110C
0
-1
-2
-3
-0.2
-0.4
-0.6
-0.8
-1
DSA = 0
DSA = 2
DSA = 4
DSA = 6
DSA = 8
DSA = 10
DSA = 12
DSA = 14
DSA = 16
DSA = 20
DSA = 24
-4
6000
6200
6400
6600
6800
7000
7200
0
2
4
6
8
10 12 14 16 18 20 22 24 26
DSA Setting (dB)
Input Frequency (MHz)
图6-203. RX Uncalibrated Differential Amplitude Error at
Normalized to 6.6GHz
6.851GHz
图6-202. RX In-Band Gain Flatness
0.1
0.08
0.06
0.04
0.02
0
-40C
25C
110C
-0.02
-0.04
-0.06
-0.08
-0.1
0
2
4
6
8
10 12 14 16 18 20 22 24 26
DSA Setting (dB)
图6-205. RX Uncalibrated Integrated Amplitude Error at
Calibrated at 25°C, held at -40 and 110°C
6.851GHz
图6-204. RX Calibrated Differential Amplitude Error at 6.851GHz
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ZHCSOT2C –JANUARY 2022 –REVISED MAY 2023
6.11.7 RX Typical Characteristics 6.8GHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 3000MSPS, output sample rate =
1500MSPS (decimate by 2x), External clock mode , AIN = –3 dBFS, DSA setting = 3 dB.
0.1
-40C
0.08
25C
110C
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
2
4
6
8
10 12 14 16 18 20 22 24 26
DSA Setting (dB)
图6-207. RX Uncalibrated Differential Phase Error at 6.851GHz
Calibrated at 25°C, held at -40 and 110°C
图6-206. RX Calibrated Integrated Amplitude Error at 6.851GHz
20
-40C
25C
110C
15
10
5
0
-5
-10
-15
-20
0
2
4
6
8
10 12 14 16 18 20 22 24 26
DSA Setting (dB)
图6-209. RX Uncalibrated Integrated Phase Error at 6.851GHz
Calibrated at 25°C, held at -40 and 110°C
图6-208. RX Calibrated Differential Phase Error at 6.851GHz
FNCO = 6.851GHz, FIN offset -130kHz
Calibrated at 25°C, held at -40 and 110°C
图6-211. RX Output FFT at 6.851GHz and -3dBFS
图6-210. RX Calibrated Integrated Phase Error at 6.851GHz
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6.11.7 RX Typical Characteristics 6.8GHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 3000MSPS, output sample rate =
1500MSPS (decimate by 2x), External clock mode , AIN = –3 dBFS, DSA setting = 3 dB.
0
-20
-40
-60
-80
-100
-120
-750
-500
-250
0
250
500
750
Frequency (MHz)
FNCO = 6.851GHz, FIN offset -130kHz
FNCO = 6.851GHz, FIN offset -130kHz
图6-212. RX Output FFT at 6.851GHz and -6dBFS
图6-213. RX Output FFT at 6.851GHz and -12dBFS
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
-750
-500
-250
0
250
500
750
-750
-500
-250
0
250
500
750
Frequency (MHz)
Frequency (MHz)
FNCO = 6.851GHz, FIN offset -130kHz
FNCO = 6.851GHz, FIN offset -130kHz
图6-214. RX Output FFT at 6.851GHz and -30dBFS
图6-215. RX Output FFT at 6.851GHz and -60dBFS
-140
-80
-40C, DSA=0
-40C, DSA=3
-40C, DSA=12
25C, DSA=0
25C, DSA=3
25C, DSA=12
110C, DSA=0
110C, DSA=3
110C, DSA=12
DSA=0, -40C
DSA=0, 25C
-142
-144
-146
-148
-150
-152
-154
-85
DSA=0, 110C
DSA=3, -40C
DSA=3, 25C
-90
DSA=3, 110C
DSA=6, -40C
DSA=6, 25C
-95
DSA=6, 110C
-100
-105
-110
-60
-50
-40
-30
-20
-10
0
-60
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
Input Amplitude per Tone (dBFS)
图6-216. RX NSD vs Input Amplitude at 6.851GHz
100MHz Tone Spacing
图6-217. RX IMD3 vs Input Amplitude at 6.851GHz
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6.11.7 RX Typical Characteristics 6.8GHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 3000MSPS, output sample rate =
1500MSPS (decimate by 2x), External clock mode , AIN = –3 dBFS, DSA setting = 3 dB.
-70
-60dBFS, -40C
-60dBFS, 25C
-60dBFS, 110C
-30dBFS, -40C
-30dBFS, 25C
-30dBFS, 110C
-13dBFS, -40C
-13dBFS, 25C
-13dBFS, 110C
-75
-80
-85
-90
-95
-100
-105
-110
0
50
100
150
200
250
300
350
400
Tone Spacing (MHz)
图6-219. RX IMD3 vs Tone Spacing at 6.851GHz
100MHz Tone Spacing
图6-218. RX IMD3 vs DSA Setting at 6.851GHz
图6-220. RX NSD vs DSA Setting at 6.851GHz
图6-221. RX HD2 vs Input Amplitude at 6.851GHz
-90
-40C
25C
110C
-95
-100
-105
-110
-115
-120
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
Input Amplitude (dBFS)
0
DSA = 0dB
DSA = 12dB
图6-222. RX HD2 vs Input Amplitude at 6.851GHz
图6-223. RX HD2 vs Input Amplitude at 6.851GHz
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6.11.7 RX Typical Characteristics 6.8GHz (continued)
Typical values at TA = +25°C. Default conditions at 30MHz: ADC Sampling Rate = 3000MSPS, output sample rate =
1500MSPS (decimate by 2x), External clock mode , AIN = –3 dBFS, DSA setting = 3 dB.
-80
-85
-80
-85
-40C
25C
110C
DSA=0, -40C
DSA=0, 25C
DSA=0, 110C
DSA=12, -40C
DSA=12, 25C
DSA=12, 110C
-90
-90
-95
-95
-100
-105
-110
-115
-120
-100
-105
-110
0
2
4
6
8
10
12
14
16
18
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
Input Amplitude (dBFS)
0
DSA Setting (dB)
图6-224. RX HD2 vs DSA Setting at 6.851GHz
图6-225. RX HD3 vs Input Amplitude at 6.851GHz
100MHz tone spacing, excluding 3rd order distortion
图6-226. RX HD3 vs DSA Setting at 6.851GHz
图6-227. RX 2-tone SFDR vs Input Amplitude at 6.85GHz
图6-228. RX Additive Phase Noise at 6.85GHz
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6.11.8 PLL and Clock Typical Characteristics
Typical values at TA = +25°C with nominal supplies. Unless otherwise noted, fREF = 491.52 MHz, Phase noise measured at
TX output
-90
data
linear fit
-95
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
103
104
105
106
Offset Frequency (Hz)
measured at TX output, normalized to 12GHz by
20*log10(12GHz/FOUT
图6-230. RX Addative Phase Noise at 9.61GHz
)
图6-229. Phase Noise vs Offset Frequency for PLL
and External Clock at 12GHz
-80
-80
fVCO=11796.48MHz
fVCO=8847.36MHz
fVCO=7864.32MHz
25èC
-40èC
110èC
-90
-100
-110
-120
-130
-140
-150
-160
-90
-100
-110
-120
-130
-140
-150
-160
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
PLL enabled, fREF = 491.52MSPS, measured at 2TXOUT
图6-231. Phase Noise vs Offset Frequency and
图6-232. Phase Noise for 12-GHz VCO vs Offset
fVCO at fOUT = 2610 MHz
Frequency and Temperature at fOUT = 1910 MHz
-80
-80
fOUT=2610MHz
fOUT=3510MHz
fOUT=4910MHz
fOUT=2610MHz
fOUT=3510MHz
fOUT=4910MHz
-90
-100
-110
-120
-130
-140
-150
-160
-100
-120
-140
-160
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
图6-233. Phase Noise for 12-GHz VCO vs Offset
图6-234. Phase Noise for 12-GHz VCO vs Offset
Frequency and fOUT at –40°C
Frequency and fOUT at 25°C
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-80
-90
-80
-90
fOUT=2610MHz
fOUT=3510MHz
fOUT=4910MHz
low CP setting
high CP setting
mid CP setting
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
1E+3
1E+4
1E+5 1E+6
freq_offset(KHz)
1E+7
1E+8
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
图6-236. Phase Noise for 12-GHz VCO vs Offset
图6-235. Phase Noise for 12-GHz VCO vs Offset
Frequency and CP Setting at fOUT = 2.6 GHz
Frequency and fOUT at 110°C
-40
-120
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 122.88MHz
fREF = 245.76MHz
-42
-121
fREF = 368.64MHz
fREF = 491.52MHz
fREF = 368.64MHz
fREF = 491.52MHz
-44
-46
-122
-123
-48
-50
-52
-54
-56
-58
-60
-124
-125
-126
-127
-128
-129
-130
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
PLL enabled, fVCO = 11796.48 MHz, 1-kHz to 100-MHz,
single-sided integration bandwidth, measured at 2TXOUT
PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT
图6-238. Phase Noise for 12-GHz VCO at 600kHz
图6-237. Integrated Phase Noise for 12-GHz VCO
Offset vs Temperature and fREF at fOUT = 2.6 GHz
vs Temperature and fREF at fOUT = 2.6 GHz
-125
-126
-127
-128
-129
-130
-131
-125
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 368.64MHz
fREF = 491.52MHz
-126
-127
-128
-129
-130
-131
-132
-133
-134
-135
-132
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 368.64MHz
fREF = 491.52MHz
-133
-134
-135
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
A.
PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT
PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT
图6-239. Phase Noise for 12-GHz VCO at 800-kHz
图6-240. Phase Noise for 12-GHz VCO at 1-MHz
Offset vs Temperature and fREF at fOUT = 2.6 GHz
Offset vs Temperature and fREF at fOUT = 2.6 GHz
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-130
-140
-141
-142
-143
-144
-145
-146
-147
-148
-149
-150
fREF = 122.88MHz
fREF = 122.88MHz
-131
-132
-133
-134
-135
-136
-137
-138
-139
-140
fREF = 245.76MHz
fREF = 368.64MHz
fREF = 491.52MHz
fREF = 245.76MHz
fREF = 368.64MHz
fREF = 491.52MHz
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT
PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT
图6-241. Phase Noise for 12-GHz VCO at 1.8-MHz
图6-242. Phase Noise for 12-GHz VCO at 5-MHz
Offset vs Temperature and fREF at fOUT = 2.6 GHz
Offset vs Temperature and fREF at fOUT = 2.6 GHz
-150
-151
-152
-153
-154
-155
-156
-80
25èC
-40èC
110èC
-90
-100
-110
-120
-130
-140
-150
-160
-157
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 368.64MHz
fREF = 491.52MHz
-158
-159
-160
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
-40
-20
0
20
40
60
80
100
Temperature (èC)
PLL enabled, fVCO = 9830.4 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT
图6-243. Phase Noise for 12-GHz VCO at 50-MHz
图6-244. Phase Noise for 10-GHz VCO vs Offset
Offset vs Temperature and fREF at fOUT = 2.6 GHz
Frequency and Temperature at fOUT = 1910 MHz
-80
-80
fOUT=2610MHz
fOUT=3510MHz
fOUT=4910MHz
fOUT=2610MHz
fOUT=3510MHz
fOUT=4910MHz
-90
-100
-110
-120
-130
-140
-150
-160
-90
-100
-110
-120
-130
-140
-150
-160
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
PLL enabled, fVCO = 9830.4 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
PLL enabled, fVCO = 9830.4 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
图6-245. Phase Noise for 10-GHz VCO vs Offset
图6-246. Phase Noise for 10-GHz VCO vs Offset
Frequency and fOUT at –40°C
Frequency and fOUT at 25°C
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-80
-90
-40
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
fOUT=2610MHz
fOUT=3510MHz
fOUT=4910MHz
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 491.52MHz
-100
-110
-120
-130
-140
-150
-160
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
-40
-20
0
20
40
60
80
100
Temperature (èC)
PLL enabled, fVCO = 9830.4 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
PLL enabled, fVCO = 9830.4 MHz, 1-kHz to 100-MHz, single-
sided integration bandwidth, measured at 2TXOUT
图6-247. Phase Noise for 10-GHz VCO vs Offset
图6-248. Integrated Phase Noise for 10-GHz VCO
Frequency and fOUT at 110°C
vs Temperature and fREF at fOUT = 2.6 GHz
-120
-125
-126
-127
-128
-129
-130
-131
-132
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 368.64MHz
-121
-122
-123
-124
-125
-126
-127
-128
-129
-130
-133
fREF = 122.88MHz
fREF = 245.76MHz
-134
fREF = 491.52MHz
60 80 100
-135
-40
-40
-20
0
20
40
60
80
100
-20
0
20
40
Temperature (èC)
Temperature (èC)
PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT
PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT
图6-249. Phase Noise for 10-GHz VCO at 600 kHz 图6-250. Phase Noise for 10-GHz VCO at 800 kHz
vs Temperature and fREF at fOUT = 2.6 GHz
vs Temperature and fREF at fOUT = 2.6 GHz
-125
-130
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 491.52MHz
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 491.52MHz
-126
-131
-127
-132
-128
-129
-130
-131
-132
-133
-134
-135
-133
-134
-135
-136
-137
-138
-139
-140
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT
PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT
图6-251. Phase Noise for 10-GHz VCO at 1 MHz vs 图6-252. Phase Noise for 10-GHz VCO at 1.8 MHz
Temperature and fREF at fOUT = 2.6 GHz
vs Temperature and fREF at fOUT = 2.6 GHz
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-140
-150
-151
-152
-153
-154
-155
-156
-157
-158
-159
-160
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 491.52MHz
-141
-142
-143
-144
-145
-146
-147
-148
-149
-150
fREF = 122.88MHz
fREF = 245.76MHz
fREF = 491.52MHz
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT
PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT
图6-253. Phase Noise for 10-GHz VCO at 5 MHz vs 图6-254. Phase Noise for 10-GHz VCO at 50 MHz
Temperature and fREF at fOUT = 2.6 GHz
vs Temperature and fREF at fOUT = 2.6 GHz
-80
-80
25èC
-40èC
110èC
fOUT=2610MHz
fOUT=3510MHz
fOUT=4910MHz
-90
-100
-110
-120
-130
-140
-150
-160
-90
-100
-110
-120
-130
-140
-150
-160
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
图6-255. Phase Noise for 9-GHz VCO vs Offset
图6-256. Phase Noise for 9-GHz VCO vs Offset
Frequency and Temperature at fOUT = 1910 MHz
Frequency and fOUT at 25°C
-80
-80
fOUT=2610MHz
fOUT=3510MHz
fOUT=4910MHz
fOUT=2610MHz
fOUT=3510MHz
fOUT=4910MHz
-90
-100
-110
-120
-130
-140
-150
-160
-90
-100
-110
-120
-130
-140
-150
-160
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
图6-257. Phase Noise for 9-GHz VCO vs Offset
Frequency and fOUT at –40°C
图6-258. Phase Noise for 9-GHz VCO vs Offset
Frequency and fOUT at 110°C
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-60
-70
-80
-90
1kHz
10kHz
100kHz
1MHz
10MHz
100MHz
25èC
-40èC
110èC
-80
-100
-110
-120
-130
-140
-150
-160
-90
-100
-110
-120
-130
-140
-150
-160
1E+3
1E+4
1E+5 1E+6
Offset Frequency (Hz)
1E+7
1E+8
-40
-20
0
20
40
60
Phase Noise (dBc)
80
100
120
D303
PLL enabled, fVCO = 7864.32 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS,
minimum LPF BW, measured at 2TXOUT
图6-260. Phase Noise for 8-GHz VCO vs Offset
Frequency and Temperature at fOUT = 1910 MHz
图6-259. Phase Noise for 9-GHz VCO vs
Temperature Over Offset Frequency at fOUT = 2.6
GHz
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7 Device and Documentation Support
7.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
7.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
7.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
7.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
7.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBASAF7
70
Submit Document Feedback
Product Folder Links: AFE7906
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AFE7906IABJ
AFE7906IALK
ACTIVE
ACTIVE
FCBGA
FCBGA
ABJ
ALK
400
400
90
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-220C-168 HR
-40 to 85
-40 to 85
AFE7906I
Samples
Samples
Non-RoHS
& Green
Call TI
AFE7906
SNPB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
AFE7906IABJ
AFE7906IALK
ABJ
ALK
FCBGA
FCBGA
400
400
90
90
6 x 16
6 x 16
150
150
315 135.9 7620 19.5
315 135.9 7620 19.5
21
21
19.2
19.2
Pack Materials-Page 1
PACKAGE OUTLINE
ABJ0400A
FCBGA - 2.65 mm max height
SCALE 0.750
BALL GRID ARRAY
17.2
16.8
A
BALL A1 CORNER
17.2
16.8
(
16)
B
2.65
2.29
(1.4)
0.2 C
C
SEATING PLANE
NOTE 4
0.76
0.56
BALL TYP
0.12 C
0.5
0.3
TYP
15.2 TYP
SYMM
(0.9) TYP
0.8 TYP
Y
V
T
W
U
R
N
L
P
M
K
H
F
15.2
TYP
SYMM
J
G
E
C
A
0.55
0.45
400X
D
B
0.15
0.08
C A B
C
NOTE 3
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18 20
0.8 TYP
2
4
6
8
4221311/C 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
www.ti.com
EXAMPLE BOARD LAYOUT
ABJ0400A
FCBGA - 2.65 mm max height
BALL GRID ARRAY
(0.8) TYP
4
5
2 3
6
7
8
10
16
18
19 20
17
1
9
11 12 13 14 15
A
B
C
D
E
F
(0.8) TYP
G
H
J
400X ( 0.4)
SYMM
K
L
M
N
P
R
T
U
V
W
Y
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
(
0.4)
0.025 MAX
0.025 MIN
METAL
UNDER
MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221311/C 03/2022
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ABJ0400A
FCBGA - 2.65 mm max height
BALL GRID ARRAY
(0.8) TYP
(
0.4) TYP
10
4
5
2 3
6
7
8
16
18
19 20
17
1
9
11 12 13 14 15
A
B
(0.8)
TYP
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
Y
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:6X
4221311/C 03/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
ALK0400A
FCBGA - 2.65 mm max height
SCALE 0.750
BALL GRID ARRAY
17.2
16.8
A
BALL A1 CORNER
17.2
16.8
(
16)
B
2.65
2.29
(1.4)
0.2 C
C
SEATING PLANE
NOTE 4
0.76
0.56
BALL TYP
0.12 C
0.5
0.3
TYP
15.2 TYP
SYMM
(0.9) TYP
0.8 TYP
Y
V
T
W
U
R
N
L
P
M
K
H
F
15.2
TYP
SYMM
J
G
E
C
A
0.55
0.45
400X
D
B
0.15
0.08
C A B
C
NOTE 3
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18 20
0.8 TYP
2
4
6
8
4225930/B 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
5. Pb-Free die bump and SnPb solder ball.
www.ti.com
EXAMPLE BOARD LAYOUT
ALK0400A
FCBGA - 2.65 mm max height
BALL GRID ARRAY
(0.8) TYP
4
5
2 3
6
7
8
10
16
18
19 20
17
1
9
11 12 13 14 15
A
B
C
D
E
F
(0.8) TYP
G
H
J
400X ( 0.4)
SYMM
K
L
M
N
P
R
T
U
V
W
Y
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
(
0.4)
0.025 MAX
0.025 MIN
METAL
UNDER
MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225930/B 03/2022
NOTES: (continued)
6. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ALK0400A
FCBGA - 2.65 mm max height
BALL GRID ARRAY
(0.8) TYP
(
0.4) TYP
10
4
5
2 3
6
7
8
16
18
19 20
17
1
9
11 12 13 14 15
A
B
(0.8)
TYP
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
Y
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:6X
4225930/B 03/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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