AMC1333M10 [TI]
具有 10MHz 内部时钟和 CMOS 接口的 ±1V 输入电压、增强型隔离调制器;型号: | AMC1333M10 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 10MHz 内部时钟和 CMOS 接口的 ±1V 输入电压、增强型隔离调制器 时钟 |
文件: | 总36页 (文件大小:2064K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AMC1333M10
ZHCSQM2 – MAY 2022
AMC1333M10 具有 10MHz 内部时钟的
±1V 输入、增强型隔离式 Δ-Σ 精密调制器
1 特性
3 说明
•
•
•
线性输入电压范围:±1V
AMC1333M10 是一款精密 Δ-Σ 调制器,此调制器的输
出与输入电路由抗电磁干扰性能极强的隔离层隔开。该
隔离栅经认证可提供高达 8000VPEAK 的增强型隔离,
符 合 DIN EN IEC 60747-17 (VDE 0884-17) 和
UL1577 标准,并且可支持高达 1.5kVRMS 的工作电
压。该隔离层可将系统中以不同共模电压电平运行的各
器件隔开,防止高电压冲击导致低压侧器件电气损坏或
对操作员造成伤害。
高输入阻抗:2.4GΩ(典型值)
低直流误差:
– 失调电压误差:±0.5 mV(最大值)
– 温漂±4µV/°C(最大值)
– 增益误差:±0.2%(最大值)
– 增益漂移:±40ppm/°C(最大值)
高 CMTI:100kV/µs(最小值)
内部 10MHz 时钟发生器
高侧电源缺失检测
低 EMI:符合 CISPR-11 和 CISPR-25 标准
安全相关认证:
•
•
•
•
•
AMC1333M10 具有 ±1V 双极宽输入电压范围和高输
入电阻,因此可直接连接高电压应用中的电阻分压器。
AMC1333M10 的输出位流与内部生成的时钟同步。通
过使用集成式数字滤波器(如 TMS320F2807x 或
TMS320F2837x 微控制器系列中的数字滤波器)来抽
取位流,该器件可在 39kSPS 数据速率下实现 16 位分
辨率和 87dB 的动态范围。
– 符合 DIN EN IEC 60747-17 (VDE 0884-17) 标
准的 8000VPEAK 增强型隔离
– 符合 UL1577 标准且长达 1 分钟的 5700VRMS
隔离
AMC1333M10 采用 8 引脚宽体 SOIC 封装,额定的工
业级工作温度范围为 –40°C 至 +125°C。
•
额定的工业级工作温度范围:–40°C 至 +125°C
2 应用
器件信息(1)
•
•
•
•
电机驱动器
器件型号
封装
封装尺寸(标称值)
变频器
AMC1333M10
SOIC (8)
5.85mm × 7.50mm
保护继电器
电源
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
High-side supply
(3.3 V or 5 V)
Low-side supply
(3.3 V or 5 V)
VAC
AMC1333M10
AVDD
INP
DVDD
CLKOUT
DOUT
+1 V
–1 V
0 V
ISO
-ADC
MCU
INN
AGND
DGND
典型应用
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBASA71
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Power Ratings.............................................................6
6.6 Insulation Specifications............................................. 7
6.7 Safety-Related Certifications...................................... 8
6.8 Safety Limiting Values.................................................8
6.9 Electrical Characteristics.............................................9
6.10 Switching Characteristics........................................11
6.11 Timing Diagrams..................................................... 11
6.12 Insulation Characteristics Curves........................... 12
6.13 Typical Characteristics............................................13
7 Detailed Description......................................................17
7.1 Overview...................................................................17
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
8.3 What to Do and What Not to Do............................... 26
9 Power Supply Recommendations................................27
10 Layout...........................................................................28
10.1 Layout Guidelines................................................... 28
10.2 Layout Example...................................................... 28
11 Device and Documentation Support..........................29
11.1 Documentation Support.......................................... 29
11.2 接收文档更新通知................................................... 29
11.3 支持资源..................................................................29
11.4 Trademarks............................................................. 29
11.5 Electrostatic Discharge Caution..............................29
11.6 术语表..................................................................... 29
12 Mechanical, Packaging, and Orderable
Information.................................................................... 29
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
May 2022
*
Initial release.
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
5 Pin Configuration and Functions
AVDD
INP
1
2
3
4
8
7
6
5
DVDD
CLKOUT
DOUT
INN
AGND
DGND
Not to scale
图 5-1. DWV Package, 8-Pin SOIC (Top View)
表 5-1. Pin Functions
PIN
NAME
TYPE
NO.
1
DESCRIPTION
AVDD
INP
High-side power
Analog input
Analog (high-side) power supply(1)
Noninverting analog input
Inverting analog input
2
3
INN
Analog input
4
AGND
DGND
DOUT
CLKOUT
DVDD
High-side ground
Low-side ground
Digital output
Analog (high-side) ground reference
Digital (low-side) ground reference
Modulator data output
5
6
7
Digital output
Modulator clock output
8
Low-side power
Digital (low-side) power supply(1)
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
see(1)
MIN
–0.3
MAX
UNIT
AVDD to AGND
Power-supply voltage
6.5
6.5
V
DVDD to DGND
–0.3
Analog input voltage
Digital input voltage
Digital output voltage
Input current
On the INP and INN pins
AGND – 5
DGND – 0.5
DGND – 0.5
–10
AVDD + 0.5
DVDD + 0.5
DVDD + 0.5
10
V
V
On the CLKIN pin
On the DOUT pin
V
Continuous, any pin except power-supply pins
Junction, TJ
mA
150
Temperature
°C
Storage, Tstg
–65
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions . If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per per ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVDD
DVDD
High-side supply voltage
Low-side supply voltage
AVDD to AGND
DVDD to DGND
3.0
2.7
5.0
3.3
5.5
5.5
V
V
ANALOG INPUT
VClipping Differential input voltage before clipping output
VIN = VINP – VINN
±1.25
V
V
V
VFSR
Specified linear differential full-scale voltage
Absolute common-mode input voltage(1)
VIN = VAINP – VAINN
(VINP + VINN) / 2 to AGND
–1
–2
1
AVDD
(VINP + VINN) / 2 to AGND,
3.0 V ≤ AVDD < 4.5 V,
|VINP – VINN| ≤ 1.25 V
–0.8
–0.8
AVDD – 2.4
2.1
VCM
Operating common-mode input voltage(2)
V
(VINP + VINN) / 2 to AGND,
4.5 V ≤ AVDD ≤ 5.5 V,
|VINP – VINN| ≤ 1.25 V
TEMPERATURE RANGE
TA Specified ambient temperature
–40
25
125
°C
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
(2) See the Analog Input section for more details.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: AMC1333M10
AMC1333M10
www.ti.com.cn
UNIT
ZHCSQM2 – MAY 2022
6.4 Thermal Information
DWV (SOIC)
8 PINS
94
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
36
RθJB
ΨJT
ΨJB
Junction-to-board thermal resistance
46.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
11.5
44.4
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
AVDD = DVDD = 5.5 V
VALUE
78
UNIT
PD
Maximum power dissipation (both sides)
mW
27
AVDD = 3.6 V
AVDD = 5.5 V
DVDD = 3.6 V
DVDD = 5.5 V
PD1
Maximum power dissipation (high-side supply)
Maximum power dissipation (low-side supply)
mW
mW
46
18
32
PD2
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance(1)
External creepage(1)
Shortest pin-to-pin distance through air
≥ 8.5
≥ 8.5
mm
mm
CPG
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance) of the double
insulation
DTI
CTI
Distance through insulation
≥ 0.021
mm
V
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
≥ 600
I
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
Overvoltage category
per IEC 60664-1
DIN EN IEC 60747-17 (VDE 0884-17)(2)
Maximum repetitive peak
VIORM
At AC voltage
2120
VPK
isolation voltage
At AC voltage (sine wave)
1500
2120
8000
9600
9800
VRMS
VDC
Maximum-rated isolation
VIOWM
working voltage
At DC voltage
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
Tested in air, 1.2/50-µs waveform per IEC 62368-1
Maximum transient
VIOTM
VPK
isolation voltage
VIMP
Maximum impulse voltage(3)
VPK
VPK
Maximum surge
Tested in oil (qualification test),
1.2/50-µs waveform per IEC 62368-1
VIOSM
12800
≤ 5
isolation voltage(4)
Method a, after input/output safety test subgroups 2 and 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤ 5
qpd
Apparent charge(5)
pC
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875
× VIORM, tm = 1 s
≤ 5
Barrier capacitance,
input to output(6)
CIO
RIO
VIO = 0.5 VPP at 1 MHz
~1.5
pF
Ω
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(6)
VIO = 500 V at 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
2
55/125/21
UL1577
VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production test)
VISO
Withstand isolation voltage
5700
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.7 Safety-Related Certifications
VDE
UL
DIN EN IEC 60747-17 (VDE 0884-17),
EN IEC 60747-17,
DIN EN IEC 62368-1 (VDE 0868-1),
EN IEC 62368-1,
Recognized under 1577 component recognition program
IEC 62368-1 Clause : 5.4.3 ; 5.4.4.4 ; 5.4.9
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 94°C/W, TJ = 150°C, TA = 25°C,
AVDD = DVDD = 5.5 V
242
Safety input, output,
or supply current
IS
mA
RθJA = 94°C/W, TJ = 150°C, TA = 25°C,
AVDD = DVDD = 3.6 V
369
Safety input, output,
or total power(1)
PS
TS
RθJA = 94°C/W, TJ = 150°C, TA = 25°C
1330
150
mW
°C
Maximum safety temperature
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × AVDDmax + IS × DVDDmax, where AVDDmax is the maximum high-side voltage and DVDDmax is the maximum controller-side
supply voltage.
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, INP
= –1 V to +1 V, and INN = AGND = 0 V; typical specifications are at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
RIN
Single-ended input resistance
Differential input resistance
INN = AGND
0.1
0.1
2.4
3
GΩ
GΩ
RIND
INP = INN = AGND,
IIB = (IINP + IINN) / 2
IIB
Input bias current
–10
±3
10
5
nA
TCIIB
IIO
Input bias current temperature drift
Input offset current
–7
±1
2
pA/°C
nA
IIO = IINP – IINN
INN = AGND
–5
CIN
Single-ended input capacitance
Differential input capacitance
Common-mode transient immunity
pF
CIND
CMTI
2
pF
|AGND – DGND| = 1 kV
100
150
kV/µs
INP = INN, fIN = 0 Hz,
VCM min ≤ VCM ≤ VCM max
–104
CMRR
PSRR
Common-mode rejection ratio
Power-supply rejection ratio
dB
dB
INP = INN, fIN = 10 kHz,
–0.5 V ≤ VIN ≤ 0.5 V
–89
–86
–86
PSRR vs AVDD, at DC
PSRR vs AVDD, 100-mV and
10-kHz ripple
DC ACCURACY
EO
Offset error(1) (2)
INP = INN = AGND, TA = 25°C
TA = 25°C
–0.5
–4
±0.04
±0.6
0.5
4
mV
TCEO
EG
Offset error temperature drift(4)
Gain error(2)
µV/°C
–0.2%
–40
±0.03%
±20
0.2%
TCEG
DNL
INL
Gain error temperature drift(5)
Differential nonlinearity
Integral nonlinearity(3)
40 ppm/°C
Resolution: 16 bits
Resolution: 16 bits
–0.99
–5
0.99
LSB
LSB
±1.6
–91
15
5
AC ACCURACY
VIN = 2 VPP, fIN = 1 kHz,
single-ended input (AINN = AGND)
THD
Total harmonic distortion(6)
–82
dB
DIGITAL OUTPUT (CMOS)
CLOAD
Output load capacitance
pF
V
DVDD –
0.1
IOH = –20 µA
IOH = –4 m
VOH
High-level output voltage
Low-level output voltage
DVDD –
0.4
IOL = 20 µA
IOL = 4 m
0.1
0.4
VOL
V
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, INP
= –1 V to +1 V, and INN = AGND = 0 V; typical specifications are at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD rising
2.1
1.95
2.2
2.65
2.5
AVDD undervoltage detection
threshold
AVDDUV
DVDDUV
IAVDD
V
AVDD falling
DVDD rising
2.45
2.65
2.2
V
V
DVDD undervoltage detection
threshold
DVDD falling
1.8
3 V ≤ AVDD ≤ 3.6 V
4.5 V ≤ AVDD ≤ 5.5 V
5.8
6.4
7.6
High-side supply current
mA
8.4
2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
4
5.1
5.8
IDVDD
Low-side supply current
mA
4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
4.4
(1) This parameter is input referred.
(2) The typical value includes one sigma statistical variation.
(3) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCEO = (EO,MAX – EO,MIN) / TempRange where EO,MAX and EO,MIN refer to the maximum and minimum EO values measured within the
temperature range (–40 to 125℃).
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %)
measured within the temperature range (–40 to 125℃).
(6) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
9.5
TYP
10
MAX
10.5
55%
UNIT
fCLK
Internal clock frequency
Internal clock duty cycle
MHz
45%
50%
DOUT hold time after rising edge of
CLKOUT
tH
tD
CLOAD = 15 pF
3.5
ns
ns
DOUT hold time after rising edge of
CLKOUT
CLOAD = 15 pF
15
6
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
2.5
3.2
2.2
2.9
tr
DOUT and CLKOUT rise time
ns
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
6
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
6
tf
DOUT and CLKOUT fall time
Device start-up time
ns
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
6
AVDD step from 0 to 3.0 V with
DVDD ≥ 2.7 V to bitstream valid,
0.1% settling
tASTART
0.25
ms
6.11 Timing Diagrams
tCLKIN
tHIGH
CLKOUT
50%
tLOW
tH
tD
tr / tf
90%
10%
DOUT
图 6-1. Digital Interface Timing
DVDD
AVDD
CLKOUT
DOUT
tSTART
Bitstream not valid (analog settling)
Valid bitstream
图 6-2. Device Start-Up Timing
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.12 Insulation Characteristics Curves
1400
1200
1000
800
600
400
200
0
0
50
100
150
TA (°C)
D070
图 6-4. Thermal Derating Curve for Safety-Limiting Power per
图 6-3. Thermal Derating Curve for Safety-Limiting Current per
VDE
VDE
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 VRMS, operating lifetime = 135 years
图 6-5. Reinforced Isolation Capacitor Lifetime Projection
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.13 Typical Characteristics
at AVDD = 5 V, DVDD = 3.3 V, INP = –1 V to 1 V, INN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
0.2
0.15
0.1
10
TA = -40 C
TA = 25 C
TA = 85 C
0.05
0
1
-0.05
-0.1
-0.15
-0.2
Device 1
Device 2
Device 3
0.1
-1.5
-1
-0.5
0
0.5
1
1.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
(VINP - VINN) (V)
D074
Temperature (°C)
D073
Total uncalibrated output error (in %) is defined as:
(Output Code / 216) – (VIN + 1.25 V) / 2.5 V) × 100,
where VIN = (VINP – VINN
)
图 6-7. Single-Ended Input Resistance vs Temperature
图 6-6. Total Uncalibrated Output Error vs Input Voltage
10
8
6
4
2
0
-2
-4
-6
-8
-10
-1.4
-1
-0.6
-0.2
0.2
0.6
1
1.4
VCM (V)
D003
图 6-8. Differential Input Resistance vs Temperature
图 6-9. Input Bias Current vs Common-Mode Input Voltage
10
8
10
8
6
6
4
4
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
3
3.5
4
4.5
AVDD (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D004
D005
图 6-10. Input Bias Current vs High-Side Supply Voltage
图 6-11. Input Bias Current vs Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.13 Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, INP = –1 V to 1 V, INN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
0
-20
0
-20
OSR = 8
OSR = 256
OSR = 8
OSR = 256
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
fIN (kHz)
fRipple (kHz)
D038
D041
图 6-12. Common-Mode Rejection Ratio vs Ripple Frequency
图 6-13. Power-Supply Rejection Ratio vs Ripple Frequency
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.1
-0.2
-0.3
-0.3
Device 1
Device 1
Device 2
Device 3
Device 2
Device 3
-0.4
-0.5
-0.4
-0.5
3
3.5
4
4.5
AVDD (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D027
D026
图 6-14. Offset Error vs High-Side Supply Voltage
0.4
图 6-15. Offset Error vs Temperature
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
3
3.5
4
4.5
AVDD (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D020
D021
图 6-16. Gain Error vs High-Side Supply Voltage
图 6-17. Gain Error vs Temperature
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.13 Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, INP = –1 V to 1 V, INN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
5
4
6
5
4
3
2
1
0
Device 1
Device 2
Device 3
3
2
1
0
-1
-2
-3
-4
-5
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
-40 -25 -10
5
20 35 50 65 80 95 110 125
VIN (V)
Temperature (°C)
D028
D030
图 6-18. Integral Nonlinearity vs Input Voltage
图 6-19. Integral Nonlinearity vs Temperature
-70
-70
Device 1
Device 1
Device 2
Device 3
Device 2
Device 3
-75
-80
-75
-80
-85
-85
-90
-90
-95
-95
-100
-105
-110
-100
-105
-110
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
VDD (V)
Temperature (°C)
D056
D059
图 6-20. Total Harmonic Distortion vs High-Side Supply Voltage
图 6-21. Total Harmonic Distortion vs Temperature
-70
-75
-80
-85
-90
-95
-70
Device 1
Device 2
Device 3
-75
-80
-85
-90
-95
-100
-100
-105
-110
Device 1
Device 2
Device 3
-105
-110
0.01
0.1
1
10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
fIN (kHz)
VIN (VPP)
D052
D049
图 6-22. Total Harmonic Distortion vs Input Signal Frequency
图 6-23. Total Harmonic Distortion vs Input Signal Amplitude
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
6.13 Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, INP = –1 V to 1 V, INN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted)
108
107
106
105
104
103
102
0.1
1
10
100
1000
Frequency (kHz)
D017
sinc3, OSR = 1, frequency bin width = 1 Hz
sinc3, OSR = 256, VIN = 2 VPP
图 6-24. Noise Density With Both Inputs Shorted to HGND
图 6-25. Frequency Spectrum With 1-kHz Input Signal
0
-20
8.5
IAVDD vs AVDD
IDVDD vs DVDD
7.5
-40
6.5
5.5
4.5
3.5
2.5
-60
-80
-100
-120
-140
-160
0.1
1
10
20
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Frequency (kHz)
D015
xVDD (V)
D043
sinc3, OSR = 256, VIN = 2 VPP
图 6-26. Frequency Spectrum With 10-kHz Input Signal
图 6-27. Supply Current vs Supply Voltage
8.5
IAVDD
IDVDD
7.5
6.5
5.5
4.5
3.5
2.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D044
图 6-28. Supply Current vs Temperature
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
7 Detailed Description
7.1 Overview
The input stage of the AMC1333M10 consists of a fully differential amplifier that feeds the switched-capacitor
input of a second-order, delta-sigma (ΔΣ) modulator. The modulator converts the analog input signal into a digital
bitstream that is transferred across the isolation barrier that separates the high-side from the low-side. The
isolated data output DOUT of the converter provides a stream of digital ones and zeros that is synchronous to
the internally generated clock source at the CLKOUT pin. The time average of this serial bitstream output is
proportional to the analog input voltage.
The silicon-dioxide (SiO2) based capacitive isolation barrier supports a high level of magnetic field immunity, as
described in the ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used
in the AMC1333M10 to transmit data across the isolation barrier, and the isolation barrier characteristics itself,
result in high reliability and common-mode transient immunity.
7.2 Functional Block Diagram
AVDD
DVDD
AMC1333M10
INP
CLKOUT
DOUT
Digital
Interface
Modulator
INN
AGND
DGND
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
7.3 Feature Description
7.3.1 Analog Input
The high-impedance input stage of the AMC1333M10 feeds a second-order, switched-capacitor, feed-forward
ΔΣ modulator. The modulator converts the analog signal into a bitstream that is transferred over the isolation
barrier, as described in the Isolation Channel Signal Transmission section. The high-impedance and low bias-
current input makes the AMC1333M10 suitable for isolated, high-voltage-sensing applications that typically
employ high-impedance resistor dividers.
For reduced offset and offset drift, the input buffer is chopper-stabilized with the chopping frequency set at fCLK
/
32. 图 7-1 shows the spur at 312.5 kHz that is generated by the chopping frequency for a modulator clock of 10
MHz.
0
-20
-40
-60
-80
-100
-120
-140
-160
0.1
1
10
100
1000
Frequency (kHz)
D016
sinc3 filter, OSR = 1, fIN = 1 kHz
图 7-1. Quantization Noise Shaping
There are two restrictions on the analog input signals (INP and INN). First, if the input voltage exceeds the input
range specified in the Absolute Maximum Ratings table, the input current must be limited to 10 mA because the
device input electrostatic discharge (ESD) diodes turn on. Second, the linearity and noise performance of the
device are ensured only when the differential analog input voltage remains within the specified linear full-scale
range VFSR and within the specified input common-mode voltage range VCM, as shown in 图 7-2 and as specified
in the Recommended Operating Conditions table.
图 7-2. Common-Mode Input Voltage Range With a Differential Input Signal of ±1.25 V
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
7.3.2 Modulator
图 7-3 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the
AMC1333M10. The output V5 of the 1-bit, digital-to-analog converter (DAC) is subtracted from the input voltage
VIN = (VINN – VINP), providing an analog voltage V1 at the input of the first integrator stage. The output of the first
integrator feeds the input of the second integrator stage, resulting in an output voltage V3 that is summed with
the input signal VIN and the output of the first integrator V2. Depending on the polarity of the resulting voltage
V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by
changing the associated analog output voltage V5, causing the integrators to progress in the opposite direction
and forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1
V2
V3
V4
VIN
Integrator 1
DAC
Integrator 2
+
–
Σ
Σ
DOUT
0 V
–
V5
图 7-3. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies, as depicted in 图 7-1. Therefore, use a low-pass
digital filter at the output of the device to increase the overall performance. This filter is also used to convert the
1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's C2000™
and Sitara™ microcontroller families offer a suitable programmable, hardwired filter structure, termed a sigma-
delta filter module (SDFM), optimized for usage with the AMC1333M10. Alternatively, a field-programmable gate
array (FPGA) or complex programmable logic device (CPLD) can be used to implement the filter.
7.3.3 Isolation Channel Signal Transmission
The AMC1333M10 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-4, to transmit the
modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) illustrated in the
Functional Block Diagram transmits an internally generated, high-frequency carrier across the isolation barrier
to represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the
carrier used inside the AMC1333M10 is 480 MHz.
图 7-4 shows the concept of the on-off keying scheme.
Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
图 7-4. OOK-Based Modulation Scheme
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
7.3.4 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time.
A differential input of 1 V produces a stream of ones and zeros that are high 90% of the time. With 16 bits of
resolution, that percentage ideally corresponds to code 58982. A differential input of –1 V produces a stream
of ones and zeros that are high 10% of the time and ideally results in code 6553 with 16-bit resolution. These
input voltages are also the specified linear range of the AMC1333M10. If the input voltage value exceeds this
range, the output of the modulator shows nonlinear behavior as the quantization noise increases. The output of
the modulator clips with a constant stream of zeros with an input less than or equal to –1.25 V, or with a constant
stream of ones with an input greater than or equal to 1.25 V. In this case, however, the AMC1333M10 generates
a single 1 (if the input is at negative full-scale) or 0 (if the input is at positive full-scale) every 128 clock cycles to
indicate proper device function (see the Output Behavior in Case of a Full-Scale Input section for more details).
图 7-5 shows the input voltage versus the output modulator signal.
+ FS (Analog Input)
Modulator Output
– FS (Analog Input)
Analog Input
图 7-5. Modulator Output vs Analog Input
The density of ones in the output bitstream can be calculated using 方程式 1 for any input voltage (VIN = VINP
– VINN) value with the exception of a full-scale input signal, as described in Output Behavior in Case of a
Full-Scale Input:
V
+ V
IN
Clipping
Clipping
ρ =
(1)
2 × V
7.3.4.1 Output Behavior in Case of a Full-Scale Input
If a full-scale input signal is applied to the AMC1333M10 (that is, |VIN| ≥ |VClipping|), the device generates a single
one or zero every 128 bits at DOUT, as shown in 图 7-6, depending on the actual polarity of the signal being
sensed. In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the
system level.
CLKOUT
DOUT
DOUT
VIN –1.25 V
VIN ≥ 1.25 V
127 CLKIN cycles
127 CLKIN cycles
图 7-6. Full-Scale Output of the AMC1333M10
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
7.3.4.2 Output Behavior in Case of a Missing High-Side Supply
If the high-side supply is missing, the device provides a constant bitstream of logic 0's at the output, as shown in
图 7-7; that is, DOUT is permanently low. A one is not generated every 128 clock pulses, which differentiates this
condition from a valid negative full-scale input. This feature is useful to identify high-side power-supply problems
on the board.
CLKIN
DOUT
AVDD
Data valid
valid
0
Data valid
valid
missing
图 7-7. Output of the AMC1333M10 in Case of a Missing High-Side Supply
7.4 Device Functional Modes
The AMC1333M10 is operational when the power supplies AVDD and DVDD are applied as specified in the
Recommended Operating Conditions table.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The high input impedance, low input bias current, bipolar input voltage range, excellent accuracy, and low
temperature drift make the AMC1333M10 a high-performance solution for industrial applications where isolated
AC or DC voltage sensing is required.
8.2 Typical Application
Isolated modulators are widely used for voltage measurements in high-voltage applications that must be isolated
from a low-voltage domain. Typical applications are AC line voltage measurements, either line-to-neutral or
line-to-line in grid-connected equipment.
图 8-1 illustrates a simplified schematic of an AC motor drive application that uses three AMC1333M10 devices
to measure the AC line voltage on each phase of a three-phase system. The AC line voltage is divided down
to an approximate ±1-V level across the bottom resistor (RSNS) of a high-impedance resistive divider that is
sensed by the AMC1333M10. The digital output of the AMC1333M10 is galvanically isolated from the input
and processed by a digital sigma-delta filter module (SDFM) inside the TMS320F28x7x microcontroller on the
low-voltage side of the system. A common high-side power supply (AVDD) for all three AMC1333M10 devices
is generated from the low-side supply (DVDD) of the system by an isolated DC/DC converter circuit. A low-cost
solution is based on the push-pull driver SN6501 and a transformer that supports the desired isolation voltage
ratings.
The high-impedance input, high input voltage range, and the high common-mode transient immunity (CMTI) of
the AMC1333M10 ensure reliable and accurate operation even in high-noise environments.
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
DC-Link
EMI
Filter
L1
L2
L3
M
3~
R1
R2
Number of unit resistors
depends on
design requirements.
RSNS
N
N
Low-side supply
(3.3 V or 5 V)
100 nF 1 uF
100 nF 1 uF
100 nF 1 uF
AMC1333M10
TMS320F28x7x
AVDD
DVDD
INP
CLKOUT
DOUT
SDx-C1
SDx-D1
INN
AGND
DGND
1 μF 100 nF 100 pF
1 μF 100 nF 100 pF
1 μF 100 nF 100 pF
AMC1333M10
AVDD
DVDD
CLKOUT
DOUT
INP
SDx-C2
SDx-D2
INN
AGND
DGND
AMC1333M10
AVDD
DVDD
CLKOUT
DOUT
INP
SDx-C3
SDx-D3
INN
AGND
DGND
TPS76350
SN6501
NC
EN
GND
IN
D1
GND
VCC
D2
VOUT = 5 V
OUT
GND
10 μF 100 nF
10 μF
100 nF 4.7 μF
图 8-1. Using the AMC1333M10 for AC Line-Voltage Sensing in an AC Motor Drive Application
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
8.2.1 Design Requirements
表 8-1 lists the parameters for this typical application.
表 8-1. Design Requirements
PARAMETER
120-VRMS LINE VOLTAGE
120 V ±10%, 60 Hz
3.3 V or 5 V
230-VRMS LINE VOLTAGE
System input voltage
230 V ±10%, 50 Hz
3.3 V or 5 V
3.3 V or 5 V
75 V
High-side supply voltage
Low-side supply voltage
3.3 V or 5 V
Maximum resistor operating voltage
75 V
Voltage drop across the sense resistor (RSNS) for a linear response
Current through the resistive divider, ICROSS
±1 V (maximum)
100 μA
±1 V (maximum)
100 μA
8.2.2 Detailed Design Procedure
This discussion covers the 230-VRMS example. The procedure for calculating the resistive divider for the 120-
VRMS use case is identical.
The 100-μA, cross-current requirement at peak input voltage (360 V) determines that the total impedance of
the resistive divider is 3.6 MΩ. The impedance of the resistive divider is dominated by the top resistors (shown
exemplary as R1 and R2 in 图 8-1) and the voltage drop across RSNS can be neglected for a short time. The
maximum allowed voltage drop per unit resistor is specified as 75 V; therefore, the total minimum number of unit
resistors in the top portion of the resistive divider is 360 V / 75 V = 5. The calculated unit value is 3.6 MΩ / 5 =
720 kΩ, and the next closest value from the E96 series is 715 kΩ.
The sense resistor value RSNS is sized such that the voltage drop across the impedance at maximum input
voltage (360 V) equals the linear full-scale input voltage (VFSR) of the AMC1333M10 (that is, +1 V). RSNS is
calculated as RSNS = VFSR / (VPeak – VFSR) × RTOP, where RTOP is the total value of the top resistor string (5 ×
715 kΩ = 3575 kΩ). The resulting value for RSNS is 10.04 kΩ, and the next closest value from the E96 series is
10.0 kΩ.
表 8-2 summarizes the design of the resistive divider.
表 8-2. Resistor Value Examples
PARAMETER
120-VRMS LINE VOLTAGE
230-VRMS LINE VOLTAGE
Peak voltage
190 V
634 kΩ
3
360 V
715 kΩ
5
Unit resistor value, RTOP
Number of unit resistors in RTOP
Sense resistor value, RSNS
10.2kΩ
1912.2 kΩ
99.4 μA
1.013 V
6.3 mW
18.9 mW
10.0 kΩ
3885.0 kΩ
100.4 μA
1.004 V
7.2 mW
36.2 mW
Total resistance value (RTOP + RSNS)
Resulting current through resistive divider, ICROSS
Resulting full-scale voltage drop across sense resistor RSNS
Peak power dissipated in RTOP unit resistor
Total peak power dissipated in resistive divider
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
8.2.2.1 Input Filter Design
Placing an RC filter in front of the isolated modulator improves signal-to-noise performance of the signal path.
In practice, however, the impedance of the resistor divider is high and only a small value filter capacitor can be
used not to limit the signal bandwidth to an unacceptable low value. Design the input filter such that the cutoff
frequency of the filter is at least one order of magnitude lower than the sampling frequency (10 MHz) of the
internal ΔΣ modulator.
Most voltage-sensing applications use high-impedance resistor dividers in front of the isolated amplifier to scale
down the input voltage. In this case, an additional resistor is not required and a single capacitor (as shown in 图
8-2) is sufficient to filter the input signal.
AMC1333M10
AVDD
DVDD
CLKOUT
DOUT
100 pF
INP
INN
AGND
DGND
图 8-2. Input Filter
8.2.2.2 Bitstream Filtering
The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). 方程式 2 shows a sinc3-type filter, which is
a very simple filter that is built with minimal effort and hardware.
3
-OSR
≈
’
1- z
H z =
( )
∆
∆
÷
÷
1- z-1
«
◊
(2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-
order modulator. All characterization in this document is also done with a sinc3 filter with an oversampling ratio
(OSR) of 256 and an output word width of 16 bits.
An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining the ADS1202 with
an FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for
download at www.ti.com.
For modulator output bitstream filtering, a device from TI's C2000 or Sitara microcontroller families is
recommended. These families support multichannel dedicated hardwired filter structures that significantly
simplify system level design by offering two filtering paths per channel: one path provides high-accuracy results
for the control loop and the other provides a fast-response path for overcurrent detection.
A delta sigma modulator filter calculator is available for download at www.ti.com that aids in the filter design and
selecting the right OSR and filter order to achieve the desired output resolution and filter response time.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
8.2.3 Application Curve
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators. 图
8-3 shows the ENOB of the AMC1333M10 with different oversampling ratios.
16
sinc3
sinc2
14
sinc1
12
10
8
6
4
2
0
1
10
100
1000
OSR
D013
图 8-3. Measured Effective Number of Bits vs Oversampling Ratio
8.3 What to Do and What Not to Do
Do not leave the inputs of the AMC1333M10 unconnected (floating) when the device is powered up. If either
modulator input is left floating, the input bias current can drive this input beyond the specified common-mode
input voltage range. If both inputs are beyond that range, the gain of the front-end diminishes and the output
bitstream is not valid.
Connect the high-side ground (AGND) to INN, either by a hard short or through a resistive path. A DC current
path between INN and AGND is required to define the input common-mode voltage. Take care not to exceed the
input common-mode range, as specified in the Recommended Operating Conditions table. For best accuracy,
route the ground connection as a separate trace that connects directly to the sense resistor rather than shorting
AGND to INN directly at the input to the device. See the Layout section for more details.
Do not connect protection diodes to the inputs (INP or INN) of the AMC1333M10. Diode leakage current can
introduce significant measurement error especially at high temperatures. The input pin is protected against high
voltages by its ESD protection circuit and the high impedance of the external restive divider.
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
9 Power Supply Recommendations
In a typical application, the high-side power supply (AVDD) for the AMC1333M10 is generated from the low-side
supply (DVDD) by an isolated DC/DC converter. A low-cost solution is based on the push-pull driver SN6501 and
a transformer that supports the desired isolation voltage ratings.
The AMC1333M10 does not require any specific power-up sequencing. The high-side power supply (AVDD)
is decoupled with a low-ESR, 100-nF capacitor (C1) parallel to a low-ESR, 1-μF capacitor (C2). The low-side
power supply (DVDD) is equally decoupled with a low-ESR, 100-nF capacitor (C3) parallel to a low-ESR, 1-μF
capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible. 图 9-1 shows a
decoupling diagram for the AMC1333M10.
VAC
R1
DVDD
C2 1 µF
C4 1 µF
AMC1333M10
R2
C1 100 nF
C3 100 nF
AVDD
DVDD
CLKOUT
DOUT
INP
to MCU
to MCU
C5
100 pF
RSNS
INN
AGND
DGND
图 9-1. Decoupling of the AMC1333M10
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
图 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1333M10 supply pins) and placement of the other components required by the device. For
best performance, place the sense resistor close to the device input pins (INN and INP).
10.2 Layout Example
Clearance area, to be
kept free of any
conductive materials.
C2
C1
C4
C3
to MCU
to MCU
INP
INN
CLKOUT
DOUT
AMC1333M10
DGND
Top Metal
Inner or Bottom Layer Metal
Via
图 10-1. Recommended Layout of the AMC1333M10
Copyright © 2022 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: AMC1333M10
AMC1333M10
ZHCSQM2 – MAY 2022
www.ti.com.cn
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
•
•
Texas Instruments, Isolation Glossary application report
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
Texas Instruments, TMS320F28004x Piccolo™ Microcontrollers data sheet
Texas Instruments, TMS320F2807x Piccolo™ Microcontrollers data sheet
Texas Instruments, TMS320F2837xD Dual-Core Delfino™ Microcontrollers data sheet
Texas Instruments, TPS763 Low-Power, 150-mA, Low-Dropout Linear Regulator data sheet
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity
Texas Instruments, Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor
Control Applications application report
•
•
Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
Texas Instruments, Delta Sigma Modulator Filter Calculator design tool
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅 TI
的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: AMC1333M10
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1333M10DWVR
ACTIVE
SOIC
DWV
8
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
1333M10
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC1333M10DWVR
SOIC
DWV
8
1000
330.0
16.4
12.05 6.15
3.3
16.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DWV
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
AMC1333M10DWVR
8
1000
Pack Materials-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022,德州仪器 (TI) 公司
相关型号:
©2020 ICPDF网 联系我们和版权申明