BQ24080DRCT [TI]
SINGLE-CHIP, LI-ION AND LI-POL CHARGER IC; 单芯片，锂离子和锂聚合物充电器IC
| 型号： | BQ24080DRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE-CHIP, LI-ION AND LI-POL CHARGER IC |
| 文件： | 总16页 (文件大小：912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq24080
www.ti.com
SLUS698B–MARCH 2006–REVISED MAY 2006
SINGLE-CHIP, LI-ION AND LI-POL CHARGER IC
FEATURES
DESCRIPTION
•
Small 3 mm × 3 mm MLP Package
The bq24080 is a highly integrated and flexible Li-Ion
linear charge device targeted at space-limited
charger applications. It offers an integrated power
FET and current sensor, high-accuracy current and
voltage regulation, charge status, and charge
termination, in a single monolithic device. An external
resistor sets the magnitude of the charge current.
•
Integrated Power FET and Current Sensor for
Up to 1-A Charge Applications From AC
Adapter
•
•
Precharge Conditioning With Safety Timer
Charge and Power Good (AC Adapter Present
With Fixed Safety) Status Output
The bq24080 charges the battery in three phases:
conditioning, constant current, and constant voltage.
Charge is terminated based on minimum current. An
internal charge timer provides a backup safety for
charge termination. The bq24080 automatically
restarts the charge if the battery voltage falls below
an internal threshold. The bq24080 automatically
enters sleep mode when the input supply is
removed.
•
Automatic Sleep Mode for Low-Power
Consumption
•
•
Fixed 7-Hour Fast Charge Safety Timer
Ideal for Low-Dropout Charger Designs for
Single-Cell Li-Ion or Li-Pol Packs in
Space-Limited Portable Applications
APPLICATIONS
•
•
•
•
PDAs, MP3 Players
Digital Cameras
Internet Appliances
Smartphones
VDC
PACK+
BATTERY PACK
bq24080
AC
ADAPTER
GND
+
1
IN
OUT 10
SYSTEM
PACK-
SYSTEM
2
3
4
5
GND
9
8
7
6
CE
INTERFACE
STAT1
STAT2
VSS
PG
GND
R
SET
ISET
UDG-02184
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
bq24080
www.ti.com
SLUS698B–MARCH 2006–REVISED MAY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
CHARGE
REGULATION
VOLTAGE (V)
FAST-CHARGE TIMER
(HOURS)
PART
NUMBER(1)(2)
TJ
FUNCTIONS
MARKINGS
bq24080DRCR
bq24080DRCT
-40°C to 125°C
4.2
CE and PG
7
BRO
(1) The DRC package is available taped and reeled only in quantities of 3,000 devices per reel.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
DISSIPATION RATINGS
TA < 40°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
PACKAGE
θJA
θJC
DRC(1)
46.87 °C/W
4.95 °C/W
1.5 W
0.021 W/°C
(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2 x 3 via matrix.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
bq24080
-0.3 to 7
15
UNIT
V
VI
Input voltage(2)
IN, CE, ISET, OUT, PG, STAT1, STAT2
Output sink/source current
Output current
STAT1, STAT2, PG
OUT
mA
A
1.5
TA
Operating free-air temperature range
Junction temperature range
°C
-40 to 125
TJ
°C
Tstg
Storage temperature
–65 to 150
300
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to VSS
.
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
0
MAX
6.5
UNIT
V
VCC
TJ
Supply voltage
Operating junction temperature range
125
°C
2
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bq24080
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SLUS698B–MARCH 2006–REVISED MAY 2006
ELECTRICAL CHARACTERISTICS
over 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
INPUT CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC(VCC)
VCC current
VCC > VCC(min)
1.2
2
2
5
mA
Sum of currents into OUT pin,
VCC < V(SLP)
ICC(SLP)
Sleep current
ICC(STBY)
IIB(OUT)
IIB(CE)
Standby current
CE = High, 0°C ≤ TJ ≤ 85°C
Charge DONE, VCC > VCC(MIN)
CE = High
150
5
µA
Input current on OUT pin
Input current on CE pin
1
1
VOLTAGE REGULATION VO(REG) + V(DO–MAX) ≤ VCC , I(TERM) < IO(OUT) ≤ 1 A
VO(REG)
Output voltage
4.2
V
TA = 25°C
–0.35%
–1%
0.35%
1%
Voltage regulation accuracy
VO(OUT) = VO(REG), IO(OUT) = 1 A
VO(REG) + V(DO)) ≤ VCC
V(DO)
Dropout voltage (V(IN)–V(OUT)
)
350
500
mV
CURRENT REGULATION
IO(OUT)
Output current range(1)
VI(OUT) > V(LOWV)
VI(IN) – VI(OUT) > V(DO)
CC ≥ 4.5 V
,
,
50
1000
mA
V
V
Voltage on ISET pin, VCC ≥ 4.5 V,
VI ≥ 4.5 V, VI(OUT) > V(LOWV)
VI – VI(OUT) > V(DO)
V(SET)
Output current set voltage
Output current set factor
,
2.463
2.5
2.538
50 mA ≤ IO(OUT) ≤ 1 A
10 mA ≤ IO(OUT) < 50 mA
1 mA ≤ IO(OUT) < 10 mA
307
296
246
322
320
320
337
346
416
K(SET)
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION
Precharge to fast-charge transition
threshold
V(LOWV)
Voltage on OUT pin
2.8
3
3.2
V
V
CC(MIN) ≥ 4.5 V, tFALL = 100 ns,
Deglitch time for fast-charge to
precharge transition
10-mV overdrive,
VI(OUT) decreasing below threshold
250
5
375
500
100
270
ms
mA
mV
IO(PRECHG) Precharge range(2)
V(PRECHG) Precharge set voltage
TERMINATION DETECTION
0 V < VI(OUT) < V(LOWV), t < t(PRECHG)
Voltage on ISET pin,
VO(REG) = 4.2 V,
0 V < VI(OUT) > V(LOWV), t < t(PRECHG)
240
255
Charge termination detection
I(TERM)
VI(OUT) > V(RCH), t < t(TRMDET)
5
100
265
mA
mV
range(3)
Voltage on ISET pin,
VO(REG) = 4.2 V,
VI(OUT) > V(RCH), t < t(TRMDET)
Charge termination detection set
V(TERM)
voltage
235
250
375
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns
Deglitch time for termination
detection
tTRMDET
charging current decreasing below
10-mV overdrive
250
500
ms
(1) See Equation 2 in the Function Description section.
(2) See Equation 1 in the Function Description section.
(3) See Equation 3 in the Function Description section.
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bq24080
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SLUS698B–MARCH 2006–REVISED MAY 2006
ELECTRICAL CHARACTERISTICS (continued)
over 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY RECHARGE THRESHOLD
VO(REG)
–
VO(REG)
–
VO(REG)–
V(RCH)
Recharge threshold
V
0.115
0.10
0.085
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns
t(DEGL)
Deglitch time for recharge detect
decreasing below or increasing
above threshold, 10-mV overdrive
250
375
500
ms
STAT1, STAT2, and PG OUTPUTS
VOL
Low-level output saturation voltage
IO = 5 mA
0.25
0.4
V
CHARGE ENABLE (CE), INPUTS
VIL
Low-level input voltage
High-level input voltage
CE, low-level input current
CE, high-level input current
IIL = 10 µA
IIL = 20 µA
0
1.4
-1
V
VIH
IIL
µA
IIH
1
TIMERS
t(PRECHG)
t(CHG)
I(FAULT)
Precharge time
1,620
1,800
25,200
200
1,930
s
s
Charge time
22,680
27,720
Timer fault recovery current
µA
SLEEP COMPARATOR
V
CC ≤ VI(OUT)
V(SLP)
Sleep-mode entry threshold voltage
+ 80 mV
2.3 V ≤ VI(OUT) ≤ VO(REG)
V
V
+ 190
CC ≥ VI(OUT)
V(SLPEXIT) Sleep-mode exit threshold voltage
Sleep-mode deglitch time
V(IN) decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
250
375
500
2.6
ms
THERMAL SHUTDOWN ENTRY THRESHOLDS
T(SHTDWN) Thermal trip threshold
Thermal hysteresis
165
15
TJ increasing
°C
UNDERVOLTAGE LOCKOUT
V(UVLO)
Undervoltage lockout
Hysteresis
Decreasing VCC
2.4
2.5
27
V
mV
4
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bq24080
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SLUS698B–MARCH 2006–REVISED MAY 2006
PIN ASSIGNMENT
DRC PACKAGE
(TOP VIEW)
VSS STAT2 STAT1 GND
IN
5
4
3
bq24080
8
2
1
6
7
9
10
GND
ISET
OUT
CE
PG
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1
IN
I
I
Adapter dc voltage
CE
9
Charge enable input (active low voltage, min 0.1 µF input capacitor)
Ground
GND
ISET
OUT
PG
2, 7
6
-
I
Charge current. Precharge and termination set point.
Charge current output (minimum 0.1 µF capacitor to ground)
Power-good status output (open-drain)
Charge status output 1 (open-drain)
Charge status output 2 (open-drain)
Ground
10
8
O
O
O
O
-
STAT1
STAT2
VSS
3
4
5
There is an internal electrical connection between the exposed thermal pad and VSS pin of the device. The
exposed thermal pad must be connected to the same potential as the VSS pin on the printed-circuit board. Do
not use the thermal pad as the primary ground input for the device. VSS pin must be connected to
ground at all times.
Thermal
Pad
-
-
5
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bq24080
www.ti.com
SLUS698B–MARCH 2006–REVISED MAY 2006
FUNCTIONAL BLOCK DIAGRAM
V
I(IN)
IN
OUT
V
I(OUT)
ISET
V
I(SET)
GND
sensefet
REF
BIAS
AND
UVLO
V
O(REG)
UVLO
CHG ENABLE
CE
V
V
BAT
I(OUT)
SLEEP
ISET
*
V
I(IN)
PRECHARGE
(C/10)
CHARGE
CONTROL,
TIMER,
V
O(REG)
AND
GND
DISPLAY
LOGIC
V
RECHARGE
I(OUT)
*
PG
V
I(OUT)
PRECHARGE
*
V
I(SET)
STAT1
V
I(SET)
TERM
*
STAT2
VSS
SIGNAL DEGLITCHED
*
UDG-02185
6
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bq24080
www.ti.com
SLUS698B–MARCH 2006–REVISED MAY 2006
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
450
I
= 1000 mA
O(OUT)
400
350
I
= 750 mA
= 500 mA
= 250 mA
O(OUT)
300
250
I
O(OUT)
200
150
I
O(OUT)
100
50
0
0
50
100
150
o
T
J
- Junction Temperature - C
Figure 1.
The bq24080 supports a precision Li-Ion, Li-Pol charging system suitable for single cells. Figure 2 shows a
typical charge profile, and Figure 3 shows an operational flow chart.
PreœConditioning
Phase
Current Regulation Phase
Voltage Regulation and Charge Termination Phase
Regulation
Voltage
Regulation
Current
Charge
Voltage
Minimum
Charge
Voltage
Charge
Complete
Charge
Pre-
Conditioning
and Term
Current
Detect
UDG-04087
Figure 2. Typical Charging Profile
7
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bq24080
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SLUS698B–MARCH 2006–REVISED MAY 2006
FUNCTIONAL DESCRIPTION
POR
SLEEP MODE
V
> V
I(OUT)
CC
No
Indicate SLEEP
MODE
checked at
all times
Yes
Regulate
I
O(PRECHG)
Reset and Start
timer
(PRECHG)
V
I(OUT)
<V
(LOWV)
Yes
t
Indicate Charge-
In-Progress
No
Reset all timers,
Start t timer
(CHG)
Regulate Current
or Voltage
Indicate Charge-
In-Progress
No
V
<V
I(OUT) (LOWV)
Yes
Yes
t
(PRECHG)
No
Expired?
Expired?
t
(CHG)
Yes
No
Yes
Fault Condition
V
<V
I(OUT) (LOWV)
Yes
Indicate Fault
No
V
>V
(RCH)
?
I(OUT)
I
(TAPER)
No
detection?
No
Enable I
(FAULT)
current
Yes
No
Turn off charge
V
>V
?
(RCH)
I(OUT)
Yes
Indicate DONE
Yes
Yes
No
Disable I
(FAULT)
current
V
<V ?
(RCH)
I(OUT)
Figure 3. Operational Flow Chart
8
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bq24080
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SLUS698B–MARCH 2006–REVISED MAY 2006
FUNCTIONAL DESCRIPTION (continued)
Battery Preconditioning
During a charge cycle if the battery voltage is below the V(LOWV) threshold, the bq24080 applies a precharge
current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor connected between
the ISET and VSS, RSET determines the precharge rate. The V(PRECHG) and K(SET) parameters are specified in the
specifications table.
K
x V
(SET)
(PRECHG)
I
=
O(PRECHG)
R
SET
(1)
The bq24080 activates a safety timer, t(PRECHG), during the conditioning phase. If the V(LOWV) threshold is not
reached within the timer period, the bq24080 turns off the charger and enunciates FAULT on the STATx pins.
See the Timer Fault Recovery section for additional details.
Battery Fast Charge Constant Current
The bq24080 offers on-chip current regulation with programmable set point. The resistor connected between the
ISET and VSS, RSET determines the charge rate. The V(SET) and K(SET) parameters are specified in the
specifications table.
K
x V
(SET)
(SET)
I
=
O(OUT)
R
SET
(2)
Battery Fast Charge Voltage Regulation
The voltage regulation feedback is through the OUT pin. This input is tied directly to the positive side of the
battery pack. The bq24080 monitors the battery-pack voltage between the OUT and VSS pins. When the battery
voltage rises to VO(REG) threshold, the voltage regulation phase begins and the charging current begins to taper
down.
As a safety backup, the bq24080 also monitors the charge time in the charge mode. If charge is not terminated
within this time period, t(CHG), the charger is turned off and FAULT is set on the STATx pins. See the Timer Fault
Recovery section for additional details.
Charge Termination Detection and Rescue
The bq24080 monitors the charging current during the voltage regulation phase. Once the termination threshold,
I(TERM), is detected, charge is terminated. The V(TERM) and K(SET) parameters are specified in the specifications
table.
K
x V
(SET)
(TERM)
I
=
O(TERM)
R
SET
(3)
After charge termination, the bq24080 restarts the charge once the voltage on the OUT pin falls below the V(RCH)
threshold. This feature keeps the battery at full capacity at all times.
The bq24080 monitors the charging current during the voltage regulation phase. Once the termination threshold,
I(TERM), is detected, the charge is terminated immediately.
The resistor connected between the ISET and VSS, RSET determines the current level at the termination
threshold.
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bq24080
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SLUS698B–MARCH 2006–REVISED MAY 2006
FUNCTIONAL DESCRIPTION (continued)
Sleep Mode
The bq24080 enters the low-power sleep mode if the input power (IN) is removed from the circuit. This feature
prevents draining the battery during the absence of input supply.
Change Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the following table.
These status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the
open-drain transistor is turned off.
Table 1. Status Pin Summary
CHANGE STATE
Precharge in progress
Fast charge in progress
Charge done
STAT1
ON
STAT2
ON
ON
OFF
ON
OFF
Charge suspend (temperature)
Timer fault
OFF
OFF
Sleep mode
PG Output
The open-drain PG (Power Good) output pulls low when a valid input voltage is present. This output is turned
off, (high impedance) sleep mode. The PG pin can be used to drive an LED or communicate to the host
processor.
CE Input (Charge Enabled)
The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the
charge and a high-level signal disables the charge and places the device in a low-power mode. A high-to-low
transition on this pin also resets all timers and timer fault conditions.
10
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bq24080
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SLUS698B–MARCH 2006–REVISED MAY 2006
Timer Fault Recovery
As shown in Figure 3, bq24080 provides a recovery method to deal with timer fault conditions. The following
summarizes this method:
Condition Number 1
OUT pin voltage is above the recharge threshold (V(RCH)), and a timeout fault occurs.
Recovery method: bq24080 waits for the OUT pin voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge, or battery removal. Once the OUT pin voltage falls
below the recharge threshold, the bq24080 clears the fault and starts a new charge cycle. A POR or CE toggle
also clears the fault.
Condition number 2
OUT pin voltage is below the recharge threshold (V(RCH)), and a timeout fault occurs
Recovery method: Under this scenario, the bq24080 applies the I(FAULT) current. This small current is used to
detect a battery removal condition and remains on as long as the battery voltage stays below the recharge
threshold. If the OUT pin voltage goes above the recharge threshold, then the bq24080 disables the I(FAULT)
current and executes the recovery method described for condition number 1. Once the OUT pin voltage falls
below the recharge threshold, the bq24080 clears the fault and starts a new charge cycle. A POR or CE toggle
also clears the fault.
Selecting Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on the input power pin. A 0.1-µF
ceramic capacitor, placed in close proximity to the IN pin and GND pad works well. In some applications, it may
be necessary to protect against a hot plug input voltage overshoot. This is done in three ways:
1. The best way is to add an input zener, 6.2 V, between the IN pin and VSS.
2. A low power zener is adequate for the single event transient. Increasing the input capacitance lowers the
characteristic impedance which makes the input resistance move effective at damping the overshoot, but
risks damaging the input contacts by the high inrush current.
3. Placing a resistor in series with the input dampens the overshoot, but causes excess power dissipation.
The bq24080 only requires a small capacitor for loop stability. A 0.1-µF ceramic capacitor placed between the
OUT and GND pad is typically sufficient.
1.5 kW
100 kW
AC
bq24080
ADAPTER
PACK+
VDC
1
IN
OUT 10
+
0.1 mF
1.5 kW
PACK-
0.1 mF
GND
2
GND
9
CE
1.5 kW
3
4
5
STAT1
STAT2
VSS
8
7
6
PG
GND
Charge Current
Translator Output
ISET
1.13 kW
R
SET
Figure 4. Typical Application Circuit
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SLUS698B–MARCH 2006–REVISED MAY 2006
APPLICATION INFORMATION
Thermal Considerations
The bq24080 is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled, QFN/SON PCB Attachment (TI
Literature Number SLUA271).
The most common measure of package thermal performance is thermal impedance (θJA) measured (or
modeled) from the device junction to the air surrounding the package surface (ambient). The mathematical
expression for θJA is:
T - T
J
A
q
=
JA
P
(4)
Where:
•
•
•
TJ = device junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
•
•
•
•
•
•
•
Orientation of the device (horizontal or vertical)
Volume of the ambient air surrounding the device under test and airflow
Whether other surfaces are in close proximity to the device being tested
Use multiple 10 - 13 mil vias in the PowerPAD™ to copper ground plane.
Avoid cutting the ground plane with a signal trace near the power IC.
The PCB must be sized to have adequate surface area for heat dissipation.
FR4 (figerglass) thickness should be minimized.
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal Power
FET. It can be calculated from the following equation:
P = (V - V
(IN)
) x I
(OUT)
O(OUT)
(5)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 2.
PCB Layout Considerations
It is important to pay special attention to the PCB layout. The following provides some guidelines:
•
To obtain optimal performance, the decoupling capacitor from VCC to V(IN) and the output filter capacitors
from OUT to VSS should be placed as close as possible to the bq24080, with short trace runs to both signal
and VSS pins. The VSS pin should have short trace runs to the GND pin.
•
All low-current VSS connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small-signal ground path and
the power ground path.
•
•
The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces.
The bq24080 is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB
design guidelines for this package are provided in the application note entitled, QFN/SON PCB Attachment
(TI Literature Number SLUA271).
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