BQ24735_17 [TI]
1- to 4-Cell Li Battery SMBus Charge Controller for Supporting Turbo Boost Mode With N-Channel Power MOSFET Selector;
| 型号： | BQ24735_17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1- to 4-Cell Li Battery SMBus Charge Controller for Supporting Turbo Boost Mode With N-Channel Power MOSFET Selector 电池 |
| 文件： | 总42页 (文件大小：1517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq24735
www.ti.com
SLUSAK9 –SEPTEMBER 2011
1-4 Cell Li+ Battery SMBus Charge Controller for Supporting Turbo Boost Mode with
N-Channel Power MOSFET Selector
Check for Samples: bq24735
1
FEATURES
DESCRIPTION
The bq24735 is
a high-efficiency, synchronous
2
•
Adapter and Battery Provides Power to
System Together to Support Intel® CPU Turbo
Boost Mode
battery charger, offering low component count for
space-constraint, multi-chemistry battery charging
applications.
•
SMBus Host-Controlled NMOS-NMOS
Synchronous Buck Converter with
Programmable 615kHz, 750kHz, and 885kHz
Switching Frequencies
The bq24735 supports Turbo Boost by allowing
battery discharge energy to system when system
power demand is temporarily higher than adapter
maximum power level so that adapter will not crash.
•
•
•
Automatic N-channel MOSFET Selection of
System Power Source from Adapter or Battery
Driven by Internal Charge Pumps
The bq24735 utilizes two charge pumps to separately
drive n-channel MOSFETs (ACFET, RBFET and
BATFET) for automatic system power source
selection.
Enhanced Safety Features for Over Voltage
Protection, Over Current Protection, Battery,
Inductor and MOSFET Short Circuit Protection
SMBus controlled input current, charge current, and
charge voltage DACs allow for very high regulation
accuracies that can be easily programmed by the
system power management micro-controller.
Programmable Input Current, Charge Voltage,
Charge Current Limits
–
–
–
–
±0.5% Charge Voltage Accuracy up to 19.2V
±3% Charge Current Accuracy up to 8.128A
±3% Input Current Accuracy up to 8.064A
The bq24735 uses internal input current register or
external ILIM pin to throttle down PWM modulation to
reduce the charge current.
±2% 20x Adapter Current or Charge Current
Amplifier Output Accuracy
The bq24735 charges one, two, three or four series
Li+ cells, and is available in a 20-pin, 3.5x3.5 mm2
QFN package.
•
•
Programmable Battery Depletion Threshold,
and Battery LEARN Function
PIN CONFIGURATION
Programmable Adapter Detection and
Indicator
•
•
•
Integrated Soft Start
20
19
18
17
16
Integrated Loop Compensation
1
2
3
4
5
15 LODRV
14 GND
ACN
ACP
Real Time System Control on ILIM pin to Limit
Charge Current
•
•
•
AC Adapter Operating Range 4.5V-24V
CMSRC
ACDRV
ACOK
13 SRP
bq24735
5µA Off-State Battery Discharge Current
12 SRN
0.65mA (0.8mA max) Adapter Standby
Quiescent Current
20-pin 3.5 x 3.5 mm2 QFN Package
11 BATDRV
6
7
8
9
10
•
APPLICATIONS
•
Portable Notebook Computers, UMPC,
Ultra-Thin Notebook, and Netbook
•
•
Handheld Terminal
Industrial and Medical Equipment
Portable Equipment
•
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Intel is a registered trademark of Intel.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
bq24735
SLUSAK9 –SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Q6
BSS138W
Reverse
Input
Protection
U2
IMD2A
R12
1M
EN
R13
3.01M
D2
BAT54C
Q1 (ACFET)
FDS6680A
Q2 (RBFET)
FDS6680A
RAC 10m?
SYSTEM
Adapter +
Adapter -
C17
2200pF
C16
0.1µF
Ri
2?
*
Total
Csys
R9
10 Ω
*
C1
0.1µF
C3
0.1µF
Ci
2.2µF
220µF
*
C5
1µF
ACN
VCC
C2
0.1µF
R6
4.02 kW
R10
4.02 kW
R11
4.02 kW
BATDRV
Q5 (BATFET)
FDS6680A
ACP
C15
0.01µF
C6
1µF
CMSRC
ACDRV
REGN
BTST
D1
BAT54
R1
430 kW
C9
10uF
C8
10uF
ACDET
ILIM
R2
66.5 kW
Q3
Sis412DN
HIDRV
PHASE
R8
100 kW
RSR
10m?
C7
0.047µF
U1
bq24735
R7
316 kW
Pack +
L1
4.7µH
Q4
Sis412DN
C10
10µF
C11
10µF
+3.3V
R3
10 kW
R4
10 kW
R5
10 kW
LODRV
GND
Pack -
SDA
HOST
SMBus
SCL
SRP
SRN
Dig I/O
ADC
R14
*
ACOK
IOUT
C13
0.1µF
10 Ω
PowerPad
C14
0.1µF
R15
*
C4
100 pF
7.5 W
Dig I/O
EN
Fs = 750kHz, IADPT = 4.096A, ICHRG = 2.944A, ILIM = 4A, VCHRG = 12.592V, 90W adapter and 3S2P battery pack
Use 0Ω for better current sensing accuracy, use 10Ω/7.5Ω resistor for reversed battery connection protection. See
application information about negative output voltage protection for hard shorts on battery to ground or battery
reversed connection.
The total Csys is the lump sum of system capacitance. It is not required by charger IC. Use Ri and Ci for adapter hot
plug-in voltage spike damping. See application information about input filter design.
Figure 1. Typical System Schematic with Two NMOS Selector
2
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SLUSAK9 –SEPTEMBER 2011
D3
PDS1040
Q1 (ACFET)
FDS6680A
RAC 10 mW
SYSTEM
Adapter +
Adapter -
C17
2200 pF
C16
0.1µF
Ri
2 ?
*
Total
Csys
R9
10 Ω
*
C1
0.1µF
C3
0.1µF
Ci
*
2.2µF
220µF
C5
1µF
ACN
VCC
C2
0.1µF
R6
4.02 kW
R10
4.02 kW
BATDRV
Q5 (BATFET)
FDS6680A
ACP
R11
4.02 kW
C15
0.01µF
C6
1µF
CMSRC
ACDRV
ACDET
REGN
BTST
D1
BAT54
R1
430 kW
C9
10uF
C8
10uF
R2
66.5 kW
Q3
Sis412DN
HIDRV
PHASE
R8
RSR
10m?
C7
0.047µF
100 kW
ILIM
U1
bq24735
R7
549 kW
Pack +
Pack -
L1
4.7µH
Q4
Sis412DN
C10
10µF
C11
10µF
+3.3V
R3
10 kW
R4
10 kW
R5
10 kW
LODRV
GND
SDA
HOST
SMBus
SCL
SRP
SRN
Dig I/O
ADC
R14
*
ACOK
IOUT
C13
0.1µF
10 Ω
PowerPad
C14
0.1µF
R15
*
C4
100 pF
7.5 Ω
Fs = 750kHz, IADPT = 2.816A, ICHRG = 1.984A, ILIM = 2.54A, VCHRG = 12.592V, 65W adapter and 3S2P battery pack
Use 0Ω for better current sensing accuracy, use 10Ω/7.5Ω resistor for reversed battery connection protection. See
application information about negative output voltage protection for hard shorts on battery to ground or battery
reversed connection.
The total Csys is the lump sum of system capacitance. It is not required by charger IC. Use Ri and Ci for adapter hot
plug-in voltage spike damping. See application information about input filter design.
Figure 2. Typical System Schematic with One NMOS Selector and Schottky Diode
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Q1 (ACFET)
FDS6680A
Q2 (RBFET)
FDS6680A
RAC 10 mW
Adapter +
SYSTEM
C17
2200pF
C16
0.047µF
Total
Csys
R9
4.7W
*
C1
0.1 µF
C3
0.1µF
µF
220
Adapter -
C5
1µF
Q5 (BATFET)
Si4435DDY
Din
BAT54A
*
ACN
VCC
R6
C2
0.1µF
4.02 kW
R10
4.02 kW
R11
4.02 kW
BATDRV
D2
SL42
ACP
R12
100 kW
C6
1µF
CMSRC
ACDRV
ACDET
REGN
BTST
D1
BAT54
R1
430 kW
C9
10uF
C8
10uF
R2
487 kW
Q3
Sis412DN
HIDRV
PHASE
R8
100 kW
RSR
10 mW
C7
0.047µF
ILIM
U1
bq24735
R7
549
kW
Pack +
L1
4.7µH
Q4
Sis412DN
+3.3V
C10 C11
µF 10µF
10
R3 R4
10 kW 10 kW
R5
10 kW
LODRV
GND
Pack -
SDA
HOST SMBus
SCL
SRP
SRN
Dig I/O
ADC
R14
*
ACOK
IOUT
C13
0.1µF
10 W
PowerPad
C14
0.1µF
R15
7.5 W
C4
100 pF
*
Fs = 750kHz, IADPT = 2.048A, ICHRG = 1.984A, ILIM = 2.54A, VCHRG = 4.200V, 12W adapter and 1S2P battery pack
Use 0Ω for better current sensing accuracy, use 10Ω/7.5Ω resistor for reversed battery connection protection. See
application information about negative output voltage protection for hard shorts on battery to ground or battery
reversed connection.
The total Csys is the total lump sum of system capacitance. It is not required by charger IC. Use Din for reverse input
voltage protection. See application information about reverse input voltage protection.
Figure 3. Typical System Schematic for 5V Input 1S Battery
ORDERING INFORMATION(1)
ORDERING NUMBER
PART NUMBER
bq24735
IC MARKING
PACKAGE
QUANTITY
(Tape and Reel)
bq24735RGRR
bq24735RGRT
3000
250
BQ735
20-PIN 3.5 x 3.5mm2 QFN
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document; or, see the TI
web site at www.ti.com.
4
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SLUSAK9 –SEPTEMBER 2011
THERMAL INFORMATION
bq24735
THERMAL METRIC(1)
UNITS
RGR (20 PIN)
(2)
θJA
Junction-to-ambient thermal resistance
46.8
56.9
46.6
0.6
θJCtop
θJB
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
°C/W
ψJT
Junction-to-top characterization parameter(5)
(6)
ψJB
Junction-to-board characterization parameter
15.3
4.4
θJCbot
Junction-to-case (bottom) thermal resistance(7)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a clod plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
(2)
VALUE
UNIT
MIN
–0.3
–2
MAX
30
SRN, SRP, ACN, ACP, CMSRC, VCC
PHASE
30
Voltage range
ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK
BTST, HIDRV, ACDRV, BATDRV
–0.3
–0.3
–0.5
7
V
36
Maximum difference SRP–SRN, ACP–ACN
0.5
voltage
Junction temperature range, TJ
Storage temperature range, Tstg
–40
–55
155
155
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM MAX UNIT
SRN, SRP, ACN, ACP, CMSRC, VCC
PHASE
24
-2
24
V
Voltage range
ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK
BTST, HIDRV, ACDRV, BATDRV
SRP–SRN, ACP–ACN
0
6.5
0
30
Maximum difference voltage
Junction temperature range, TJ
Storage temperature range, Tstg
–0.2
0
0.2
125
150
V
°C
°C
–55
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ELECTRICAL CHARACTERISTICS
4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
OPERATING CONDITIONS
VVCC_OP VCC Input voltage operating range
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG Battery voltage range
TEST CONDITIONS
MIN
TYP
MAX UNIT
4.5
24
V
1.024
16.716
-0.5%
19.2
V
V
16.8 16.884
0.5%
ChargeVoltage() = 0x41A0H
12.529 12.592 12.655
V
V
V
ChargeVoltage() = 0x3130H
ChargeVoltage() = 0x20D0H
ChargeVoltage() = 0x1060H
–0.5%
8.350
–0.6%
4.163
–0.7%
0.5%
8.45
VBAT_REG_ACC
Charge voltage regulation accuracy
8.4
0.6%
4.221
0.7%
4.192
CHARGE CURRENT REGULATION
Charge current regulation differential
VIREG_CHG_RNG
VIREG_CHG = VSRP - VSRN
0
81.28
mV
mA
voltage range
3973
–3%
1946
–5%
410
4096
2048
512
4219
3%
ChargeCurrent() = 0x1000H
2150
5%
mA
mA
mA
mA
ChargeCurrent() = 0x0800H
ChargeCurrent() = 0x0200H
ChargeCurrent() = 0x0100H
ChargeCurrent() = 0x0080H
614
20%
340
33%
192
50%
Charge current regulation accuracy 10mΩ
current sensing resistor
ICHRG_REG_ACC
–20%
172
256
–33%
64
128
–50%
INPUT CURRENT REGULATION
Input current regulation differential voltage
VIREG_DPM_RNG
VIREG_DPM = VACP – VACN
0
80.64
mV
mA
range
3973
–3%
1946
–5%
870
4096
2048
1024
512
4219
3%
InputCurrent() = 0x1000H
2150
5%
mA
mA
mA
InputCurrent() = 0x0800H
InputCurrent() = 0x0400H
InputCurrent() = 0x0200H
Input current regulation accuracy 10mΩ
current sensing resistor
IDPM_REG_ACC
1178
15%
640
–15%
384
–25%
25%
INPUT CURRENT OR CHARGE CURRENT SENSE AMPLIFIER
VACP/N_OP
VSRP/N_OP
VIOUT
Input common mode range
Output common mode range
IOUT output voltage range
IOUT output current
Voltage on ACP/ACN
Voltage on SRP/SRN
4.5
0
24
19.2
3.3
1
V
V
0
V
IIOUT
0
mA
V/V
AIOUT
Current sense amplifier gain
V(ICOUT)/V(SRP-SRN) or V(ACP-ACN)
V(SRP-SRN) or V(ACP-ACN) = 40.96mV
V(SRP-SRN) or V(ACP-ACN) = 20.48mV
V(SRP-SRN) or V(ACP-ACN) = 10.24mV
V(SRP-SRN) or V(ACP-ACN) = 5.12mV
V(SRP-SRN) or V(ACP-ACN) = 2.56mV
V(SRP-SRN) or V(ACP-ACN) = 1.28mV
For stability with 0 to 1mA load
20
–2%
–4%
2%
4%
–15%
–20%
–33%
–50%
15%
20%
33%
50%
100
VIOUT_ACC
Current sense output accuracy
CIOUT_MAX
Maximum output load capacitance
pF
6
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ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
REGN REGULATOR
VREGN_REG
REGN regulator voltage
V
VCC > 6.5V, VACDET > 0.6V (0-45mA load)
5.5
50
6
6.5
V
VREGN = 0V, VVCC > UVLO charge enabled and not in
TSHUT
75
mA
IREGN_LIM
REGN current limit
VREGN = 0V, VVCC > UVLO charge disabled or in
TSHUT
7
14
1
mA
REGN output capacitor required for
stability
ILOAD = 100µA to 50mA
CREGN
µF
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
Under voltage rising threshold
UVLO
VVCC rising
VVCC falling
3.5
3.75
340
4
V
Under voltage hysteresis, falling
mV
FAST DPM COMPARATOR (FAST_DPM)
Fast DPM comparator stop charging rising threshold with respect to input current limit, voltage
across input sense resistor rising edge
VFAST_DPM
103%
107%
111%
QUIESCENT CURRENT
Battery BATFET OFF STATE Current,
VVBAT = 16.8V, VCC disconnect from battery, BATFET
charge pump off, BATFET turns off, TJ = 0 to 85°C
BATFET off,
IBAT_BATFET_OFF
5
µA
µA
ISRP + ISRN + IPHASE + IACP + IACN
Battery BATFET ON STATE Current,
BATFET on,
ISRP + ISRN + IPHASE + IVCC + IACP + IACN
VVBAT = 16.8V, VCC connect from battery, BATFET
charge pump on, BATFET turns on, TJ = 0 to 85°C
IBAT_BATFET_ON
25
Standby quiescent current, IVCC + IACP
IACN
+
V
VCC > UVLO, VACDET > 0.6V, charge disabled,
ISTANDBY
IAC_NOSW
IAC_SW
0.65
1.5
10
0.8
3
mA
mA
mA
TJ = 0 to 85°C
Adapter bias current during charge,
IVCC + IACP + IACN
VVCC > UVLO, 2.4V < VACDET < 3.15V,
charge enabled, no switching, TJ = 0 to 85°C
Adapter bias current during charge,
IVCC + IACP + IACN
VVCC > UVLO, 2.4V < VACDET < 3.15V,
charge enabled, switching, MOSFET Sis412DN
ACOK COMPARATOR
VACOK_RISE
ACOK rising threshold
ACOK falling hysteresis
V
V
V
VCC > UVLO, VACDET rising
2.376
35
2.4
55
2.424
75
V
VACOK_FALL_HYS
VCC> UVLO, VACDET falling
mV
VCC> UVLO, VACDET rising above 2.4V,
100
0.9
150
1.3
200
ms
s
First time OR ChargeOption() bit [15] = 0
VACOK_RISE_DEG
ACOK rising deglitch (Specified by design)
VVCC> UVLO, VACDET rising above 2.4V,
(NOT First time) AND ChargeOption() bit [15] = 1
(Default)
1.7
0.8
VWAKEUP_RISE
VWAKEUP_FALL
WAKEUP detect rising threshold
WAKEUP detect falling threshold
V
VCC> UVLO, VACDET rising
VCC> UVLO, VACDET falling
0.57
0.51
V
V
V
0.3
VCC to SRN COMPARATOR (VCC_SRN)
VVCC-SRN_FALL
VVCC-SRN _RHYS
VCC-SRN falling threshold
VCC-SRN rising hysteresis
VVCC falling towards VSRN
VVCC rising above VSRN
70
125
150
200
200
mV
mV
100
ACN to SRN COMPARATOR (ACN_SRN)
VACN-SRN_FALL
VACN-SRN_RHYS
ACN to BAT falling threshold
ACN to BAT rising hysteresis
VACN falling towards VSRN
VACN rising above VSRN
120
40
200
80
280
120
mV
mV
HIGH SIDE IFAULT COMPARATOR (IFAULT_HI)(1)
VIFAULT_HI_RISE ACP to PHASE rising threshold
LOW SIDE IFAULT COMPARATOR (IFAULT_LOW)(1)
VIFAULT_LOW_RISE PHASE to GND rising threshold
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
ChargeOption() bit [8] = 1 (Default)
450
750
1200
mV
mV
ChargeOption() bit [8] = 0 Disable function
ChargeOption() bit [7] = 0 (Default)
ChargeOption() bit [7] = 1
70
135
230
220
340
140
VACOV
ACDET over voltage rising threshold
ACDET over voltage falling hysteresis
VACDET rising
VACDET falling
3.05
50
3.15
75
3.25
100
V
VACOV_HYS
mV
(1) User can adjust threshold via SMBus ChargeOption() REG0x12.
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ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT OVER-CURRENT COMPARATOR (ACOC)(2)
Adapter over current rising threshold with
ChargeOption() bit [1] = 1 (Default)
300%
333%
366%
VACOC
respect to input current limit, voltage
across input sense resistor rising edge
ChargeOption() bit [1] = 0 Disable function
ChargeOption() Bit [1] = 1 (333%),
InputCurrent () = 0x0400H (10.24mV)
VACOC_min
VACOC_max
tACOC_DEG
Min ACOC threshold clamp voltage
Max ACOC threshold clamp voltage
ACOC deglitch time (Specified by design)
40
135
2.3
45
150
4.2
50
165
6.6
mV
mV
ms
ChargeOption() Bit [1] = 1 (333%),
InputCurrent () = 0x1F80H (80.64mV)
Voltage across input sense resistor rising to disable
charge
BAT OVER-VOLTAGE COMPARATOR (BAT_OVP)
VOVP_RISE
Over voltage rising threshold as
percentage of VBAT_REG
VSRN rising
VSRN falling
103%
104%
102%
106%
VOVP_FALL
Over voltage falling threshold as
percentage of VBAT_REG
CHARGE OVER-CURRENT COMPARATOR (CHG_OCP)
ChargeCurrent()=0x0xxxH
54
80
60
90
66
100
130
mV
mV
mV
Charge over current rising threshold,
measure voltage drop across current
sensing resistor
VOCP_RISE
ChargeCurrent()=0x1000H – 0x17C0H
ChargeCurrent()=0x1800 H– 0x1FC0H
110
120
CHARGE UNDER-CURRENT COMPARATOR (CHG_UCP)
VUCP_FALL Charge under-current falling threshold
LIGHT LOAD COMPARATOR (LIGHT_LOAD)
VSRP falling towards VSRN
1
5
9
mV
VLL_FALL
Light load falling threshold
Light load rising hysteresis
1.25
1.25
mV
mV
Measure the voltage drop across current sensing
resistor
VLL_RISE_HYST
BATTERY DEPLETION COMPARATOR (BAT_DEPL) [1]
ChargeOption() bit [12:11] = 00
ChargeOption() bit [12:11] = 01
ChargeOption() bit [12:11] = 10
ChargeOption() bit [12:11] = 11 (Default)
ChargeOption() bit [12:11] = 00
ChargeOption() bit [12:11] = 01
ChargeOption() bit [12:11] = 10
ChargeOption() bit [12:11] = 11 (Default)
55.53% 59.19% 63.5%
58.68% 62.65% 67.5%
62.17% 66.55% 71.5%
Battery depletion falling threshold,
percentage of voltage regulation limit, VSRN
falling
VBATDEPL_FALL
66.06% 70.97%
77%
400
430
450
490
225
240
255
280
305
325
345
370
mV
mV
mV
mV
Battery depletion rising hysteresis, VSRN
rising
VBATDEPL_RHYST
Battery Depletion Rising Deglitch
(Specified by design)
Delay to turn off ACFET and turn on BATFET during
LEARN cycle
tBATDEPL_RDEG
600
ms
BATTERY LOWV COMPARATOR (BAT_LOWV)
VBATLV_FALL
VBATLV_RHYST
IBATLV
Battery LOWV falling threshold
Battery LOWV rising hysteresis
Battery LOWV charge current limit
VSRN falling
2.4
2.5
200
0.5
2.6
V
mV
A
VSRN rising
10 mΩ current sensing resistor
THERMAL SHUTDOWN COMPARATOR (TSHUT)
TSHUT
Thermal shutdown rising temperature
Thermal shutdown hysteresis, falling
Temperature rising
Temperature falling
155
20
°C
°C
TSHUT_HYS
ILIM COMPARATOR
VILIM_FALL
ILIM as CE falling threshold
ILIM as CE rising threshold
VILIM falling
VILIM rising
60
90
75
90
mV
mV
VILIM_RISE
105
120
LOGIC INPUT (SDA, SCL)
VIN_ LO Input low threshold
VIN_ HI
0.8
1
V
V
Input high threshold
Input bias current
2.1
IIN_ LEAK
V = 7 V
–1
μA
LOGIC OUTPUT OPEN DRAIN (ACOK, SDA)
VOUT_ LO
Output saturation voltage
Leakage current
5 mA drain current
V = 7 V
500
1
mV
IOUT_ LEAK
–1
μA
(2) User can adjust threshold via SMBus ChargeOption() REG0x12.
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ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUT (ACDET, ILIM)
IIN_ LEAK
Input bias current
V = 7 V
–1
1
μA
PWM OSCILLATOR
FSW
PWM switching frequency
PWM increase frequency
PWM decrease frequency
ChargeOption () bit [9] = 0 (Default)
ChargeOption() bit [10:9] = 11
ChargeOption() bit [10:9] = 01
600
665
465
750
885
615
900
1100
765
kHz
kHz
kHz
FSW+
FSW–
BATFET GATE DRIVER (BATDRV)
IBATFET
BATDRV charge pump current limit
40
60
µA
VBATFET
Gate drive voltage on BATFET
VBATDRV - VSRN when VSRN > UVLO
5.5
6.1
6.5
7.4
V
Minimum load resistance between
BATDRV and SRN
RBATDRV_LOAD
RBATDRV_OFF
500
5
kΩ
kΩ
BATDRV turn-off resistance
I = 30 µA
6.2
ACFET GATE DRIVER (ACDRV)
IACFET
ACDRV charge pump current limit
40
60
μA
VACFET
Gate drive voltage on ACFET
V
ACDRV–VCMSRC when VVCC> UVLO
5.5
6.1
6.5
7.4
V
Minimum load resistance between ACDRV
and CMSRC
RACDRV_LOAD
RACDRV_OFF
VACFET_LOW
500
5
kΩ
kΩ
V
ACDRV turn-off resistance
I = 30 µA
6.2
5.9
ACDRV Turn-Off when Vgs voltage is low
(Specified by design)
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON High side driver turn-on resistance
RDS_HI_OFF
V
V
V
BTST – VPH = 5.5 V, I = 10 mA
6
10
Ω
Ω
High side driver turn-off resistance
BTST – VPH = 5.5 V, I = 10 mA
0.65
1.3
Bootstrap refresh comparator threshold
voltage
BTST – VPH when low side refresh pulse is requested
VBTST_REFRESH
3.85
4.3
4.7
V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON Low side driver turn-on resistance
RDS_LO_OFF Low side driver turn-off resistance
PWM DRIVER TIMING
tLOW_HIGH Driver dead time from low side to high side
tHIGH_LOW Driver dead time from high side to low side
INTERNAL SOFT START
ISTEP Soft start current step
tSTEP Soft start current step time
SMBus TIMING CHARACTERISTICS
VREGN = 6 V, I = 10 mA
VREGN = 6 V, I = 10 mA
7.5
0.9
12
Ω
Ω
1.4
20
20
ns
ns
64
mA
In CCM mode 10mΩ current sensing resistor
240
μs
tR
SCLK/SDATA rise time
1
300
50
μs
ns
μs
μs
μs
μs
ns
ns
µs
μs
kHz
tF
SCLK/SDATA fall time
tW(H)
SCLK pulse width high
4
4.7
4.7
4
tW(L)
SCLK Pulse Width Low
Setup time for START condition
tSU(STA)
tH(STA)
tSU(DAT)
tH(DAT)
tSU(STOP)
t(BUF)
FS(CL)
START condition hold time after which first clock pulse is generated
Data setup time
250
300
4
Data hold time
Setup time for STOP condition
Bus free time between START and STOP condition
Clock Frequency
4.7
10
100
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ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
HOST COMMUNICATION FAILURE
ttimeout
tBOOT
SMBus bus release timeout(3)
25
10
35
ms
ms
s
Deglitch for watchdog reset signal
Watchdog timeout period, ChargeOption() bit [14:13] = 01(4)
Watchdog timeout period, ChargeOption() bit [14:13] = 10(4)
Watchdog timeout period, ChargeOption() bit [14:13] = 11(4) (Default)
35
44
88
53
105
210
tWDI
70
s
140
175
s
(3) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(4) User can adjust threshold via SMBus ChargeOption() REG0x12.
Figure 4. SMBus Communication Timing Waveforms
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
FIGURE NO.
Figure 5
VCC, ACDET, REGN and ACOK Power up
Charge Enable by ILIM
Figure 6
Current Soft-start
Figure 7
Charge Disable by ILIM
Figure 8
Continuous Conduction Mode Switching Waveforms
Cycle-by-Cycle Synchronous to Non-synchronous
100% Duty and Refresh Pulse
System Load Transient (Input DPM)
Battery Insertion
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Efficiency vs Output Current
Buck to Boost Mode
Boost to Buck Mode
SPACER
SPACER
CH1: ILIM, 1V/div, CH4: inductor current, 1A/div, 20ms/div
CH1: VCC, 10V/div, CH2: ACDET, 2V/div, CH3: ACOK, 5V/div,
CH4: REGN, 5V/div, 40ms/div
Figure 5. VCC, ACDET, REGN and ACOK Power Up
Figure 6. Charge Enable by ILIM
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CH1: ILIM, 1V/div, CH4: inductor current, 1A/div, 4us/div
CH1: Vin, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div,
CH4: inductor current, 2A/div, 2ms/div
Figure 7. Current Soft-Start
Figure 8. Charge Disable by ILIM
CH1: PHASE, 10V/div, CH2: LODRV, 5V/div, CH3: HIDRV, 10V/div,
CH4: inductor current, 2A/div, 400ns/div
CH1: PHASE, 10V/div, CH2: LODRV, 5V/div, CH3: HIDRV, 10V/div,
CH4: inductor current, 1A/div, 400ns/div
Figure 9. Continuous Conduction Mode Switching
Waveforms
Figure 10. Cycle-by-Cycle Synchronous to
Non-synchronous
CH1: PHASE, 10V/div, CH2: LODRV, 5V/div, CH4: inductor current, CH2: battery current, 2A/div, CH3: adapter current, 2A/div, CH4:
2A/div, 4us/div system load current, 2A/div, 100us/div
Figure 12. System Load Transient (Input DPM)
Figure 11. 100% Duty and Refresh Pulse
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98
97
96
95
94
93
92
91
90
89
88
3-cell 12.6 V
4-cell 16.8 V
2-cell 8.4 V
V
= 20 V,
IN
F = 750 kHz,
L = 4.7 mH
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Charge Current
CH1: PHASE, 20V/div, CH2: battery voltage, 5V/div, CH3: LODRV,
10V/div, CH4: inductor current, 2A/div, 400us/div
Figure 13. Battery Insertion
Figure 14. Efficiency vs Output Current
CH3: adapter current, 2A/div, CH4: battery current, 2A/div, 10ms/div CH3: adapter current, 2A/div, CH4: battery current, 2A/div, 10ms/div
Figure 15. Buck to Boost Mode Figure 16. Boost to Buck Mode
Pin Functions – 20-Pin QFN
PIN
DESCRIPTION
NO. NAME
1
2
3
4
ACN
Input current sense resistor negative input. Place an optional 0.1µF ceramic capacitor from ACN to GND for
common-mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.
ACP
Input current sense resistor positive input. Place a 0.1µF ceramic capacitor from ACP to GND for common-mode
filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.
CMSRC ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the common source of ACFET (Q1) and
RBFET (Q2) limits the in-rush current on CMSRC pin.
ACDRV Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel MOSFET
(RBFET). ACDRV voltage is 6V above CMSRC when voltage on ACDET pin is between 2.4V to 3.15V, voltage on VCC
pin is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin so that ACFET and RBFET can be
turned on to power the system by AC adapter. Place a 4kΩ resistor from ACDRV to the gate of ACFET and RBFET
limits the in-rush current on ACDRV pin.
5
ACOK
AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when
voltage on ACDET pin is between 2.4V and 3.15V, and voltage on VCC is above UVLO and voltage on VCC pin is
275mV above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above
conditions can not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to
the pull-up supply rail.
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Pin Functions – 20-Pin QFN (continued)
PIN
DESCRIPTION
NO. NAME
6
ACDET
Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to
ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK
comparator and IOUT are both active.
7
IOUT
Buffered adapter or charge current output, selectable with SMBus command ChargeOption(). IOUT voltage is 20 times
the differential voltage across sense resistor. Place a 100pF or less ceramic decoupling capacitor from IOUT pin to
GND.
8
9
SDA
SCL
ILIM
SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ
pull-up resistor according to SMBus specifications.
SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a 10kΩ
pull-up resistor according to SMBus specifications.
10
Charge current limit input. Program ILIM voltage by connecting a resistor divider from system reference 3.3V rail to ILIM
pin to GND pin. The lower of ILIM voltage or DAC limit voltage sets charge current regulation limit. To disable the
control on ILIM, set ILIM above 1.6V. Once voltage on ILIM pin falls below 75mV, charge (buck mode) or discharge
(boost mode) is disabled. Charge and discharge is enabled when ILIM pin rises above 105mV.
11
12
BATDRV Charge pump output to drive Battery to System n-channel MOSFET (BATFET). BATDRV voltage is 6V above SRN to
turn on BATFET to power the system from battery. BATDRV voltage is SRN voltage to turn off BATFET to power
system from AC adapter. Place a 4kΩ resistor from BATDRV to the gate of BATFET limits the in-rush current on
BATDRV pin.
SRN
Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin to a 7.5
Ω resistor first then from resistor another terminal connect a 0.1µF ceramic capacitor to GND for common-mode filtering
and connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide
differential mode filtering. See application information about negative output voltage protection for hard shorts on battery
to ground or battery reverse connection by adding small resistor.
13
14
SRP
GND
Charge current sense resistor positive input. Connect SRP pin to a 10 Ω resistor first then from resistor another terminal
connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide
differential mode filtering. See application information about negative output voltage protection for hard shorts on battery
to ground or battery reverse connection by adding small resistor.
IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the power
pad underneath IC.
15
16
LODRV
REGN
Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate.
Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when
voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from
REGN to GND.
17
BTST
High side power MOSFET driver power supply. Connect a 0.047µF capacitor from BTST to PHASE, and a bootstrap
Schottky diode from REGN to BTST.
18
19
20
HIDRV
PHASE
VCC
High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate.
High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET.
Input supply, diode OR from adapter or battery voltage. Use 10Ω resistor and 1µF capacitor to ground as low pass filter
to limit inrush current.
PowerPAD
Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPad plane. Always
solder PowerPad to the board, and have vias on the PowerPad plane connecting to analog ground and power ground
planes. It also serves as a thermal pad to dissipate the heat.
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FUNCTIONAL BLOCK DIAGRAM
135
1.07
Figure 17. Functional Block Diagram for bq24735
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DETAILED DESCRIPTION
SMBus Interface
The bq24735 operates as a slave, receiving control inputs from the embedded controller host through the SMBus
interface. The bq24735 uses a simplified subset of the commands documented in System Management Bus
Specification V1.1, which can be downloaded from www.smbus.org. The bq24735 uses the SMBus Read-Word
and Write-Word protocols (see Figure 18) to communicate with the smart battery. The bq24735 performs only as
a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In
addition, the bq24735 has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit
manufacturer ID register (0xFEH).
SMBus communication is enabled with the following conditions:
•
•
VVCC is above UVLO;
VACDET is above 0.6V;
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 19 and
Figure 20 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is
low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24735 because either the
master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24735
supports the charger commands as described in Table 2.
a) Write-Word Format
SLAVE
ADDRESS
COMMAND
BYTE
LOW DATA
BYTE
HIGH DATA
BYTE
S
W
ACK
ACK
ACK
ACK
P
7 BITS
1b
0
1b
0
8 BITS
1b
0
8 BITS
1b
0
8 BITS
1b
0
MSB LSB
MSB LSB
MSB LSB
MSB LSB
Preset to 0b0001001 ChargeCurrent() = 0x14H D7
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
D0
D15
D8
ChargeOption() = 0x12H
b) Read-Word Format
SLAVE
ADDRESS
COMMAND
BYTE
SLAVE
ADDRESS
LOW DATA
BYTE
HIGH DATA
BYTE
S
W
ACK
ACK
S
R
ACK
ACK
NACK
P
7 BITS
1b
0
1b
0
8 BITS
1b
0
7 BITS
1b
1
1b
0
8 BITS
1b
0
8 BITS
1b
1
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB
LSB
Preset to 0b0001001
DeviceID() = 0xFFH
Preset to
0b0001001
D7 D0
D15 D8
ManufactureID() = 0xFEH
ChargeCurrent() = 0x14H
ChargeVoltage() = 0x15H
InputCurrent() = 0x3FH
ChargeOption() = 0x12H
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 18. SMBus Write-Word and Read-Word Protocols
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Figure 19. SMBus Write Timing
A
B
C
D
E
F
G
H
I
J
K
tLOW tHIGH
SMBCLK
SMBDATA
A
= START CONDITION
E = SLAVE PULLS SMBDATA LINE LOW
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
K = NEW START CONDITION
Figure 20. SMBus Read Timing
Battery-Charger Commands
The bq24735 supports six battery-charger commands that use either Write-Word or Read-Word protocols, as
summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24735. The
ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x000BH.
Table 2. Battery Charger Command Summary
REGISTER ADDRESS
0x12H
REGISTER NAME
ChargeOption()
ChargeCurrent()
ChargeVoltage()
InputCurrent()
READ/WRITE
Read or Write
Read or Write
Read or Write
Read or Write
Read Only
DESCRIPTION
Charger Options Control
7-Bit Charge Current Setting
11-Bit Charge Voltage Setting
6-Bit Input Current Setting
Manufacturer ID
POR STATE
0xF902H
0x0000H
0x0000H
0x1000H
0x0040H
0x000BH
0x14H
0x15H
0x3FH
0XFEH
ManufacturerID()
DeviceID()
0xFFH
Read Only
Device ID
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Setting Charger Options
By writing ChargeOption() command (0x12H or 0b00010010), bq24735 allows users to change several charger
options after POR (Power On Reset) as shown in Table 3.
Table 3. Charge Options Register (0x12H)
BIT
BIT NAME
DESCRIPTION
[15]
ACOK Deglitch Time Adjust ACOK deglitch time.
Adjust
After POR, the first time the adapter plug in occurs, deglitch time is always 150ms no matter if this bit is
0 or 1. This bit only sets the next ACOK deglitch time after ACFET turns off at least one time. To change
this option, VCC pin voltage must be above UVLO and ACDET pin voltage must be above 0.6V to
enable IC SMBus communication.
0: ACOK rising edge deglitch time 150ms
1: ACOK rising edge deglitch time 1.3s <default at POR>
[14:13] WATCHDOG Timer
Adjust
Set maximum delay between consecutive SMBus Write charge voltage or charge current command. The
charge will be suspended if IC does not receive write charge voltage or write charge current command
within the watchdog time period and watchdog timer is enabled.
The charge will be resumed after receive write charge voltage or write charge current command when
watchdog timer expires and charge suspends. During boost function, the timer is fixed to 175s if it is
enabled.
00: Disable Watchdog Timer
01: Enabled, 44 sec
10: Enabled, 88 sec
11: Enable Watchdog Timer (175s) <default at POR>
[12:11] BAT Depletion
Comparator
This is used for LEARN function and boost mode function battery over discharge protection. During
LEARN cycle, when the IC detects battery voltage is below depletion voltage threshold, the IC turns off
BATFET and turned on ACFET to power the system from AC adapter instead of the battery. During
boost mode function, when the IC detects battery voltage is below depletion voltage threshold, IC stops
boost function. The rising edge hysteresis is 340mV. Set ChargeVoltage() register value to 0V will
disable this function.
Threshold Adjust
00: Falling Threshold = 59.19% of voltage regulation limit (~2.486V/cell)
01: Falling Threshold = 62.65% of voltage regulation limit (~2.631V/cell)
10: Falling Threshold = 66.55% of voltage regulation limit (~2.795V/cell)
11: Falling Threshold = 70.97% of voltage regulation limit (~2.981V/cell) < default at POR>
[10]
[9]
EMI Switching
Frequency Adjust
0: Reduce PWM switching frequency by 18% <default at POR>
1: Increase PWM switching frequency by 18%
EMI Switching
0: Disable adjust PWM switching frequency <default at POR>
Frequency Enable
1: Enable adjust PWM switching frequency
[8]
IFAULT_HI
Comparator
Threshold Adjust
Short circuit protection high side MOSFET voltage drop comparator threshold.
0: function is disabled
1: 750mV <default at POR>
[7]
[6]
IFAULT_LOW
Comparator
Threshold Adjust
Short circuit protection low side MOSFET voltage drop comparator threshold. This is also used for
cycle-by-cycle current limit protection threshold during boost function.
0: 135mV <default at POR>
1: 230mV
LEARN Enable
Set this bit 1 start battery learn cycle. IC turns off ACFET and turns on BATFET to discharge battery
capacity. When battery voltage reaches threshold defined in bit [12;11], the BATFET is turned off and
ACFET is turned on to finish battery learn cycle. After finished learn cycle, this bit is automatically reset
to 0. Set this bit 0 will stop battery learn cycle. IC turns off BATFET and turns on ACFET.
0: Disable LEARN Cycle <default at POR>
1: Enable LEARN Cycle
[5]
[4]
[3]
[2]
[1]
IOUT Selection
0: IOUT is the 20x adapter current amplifier output <default at POR>
1: IOUT is the 20x charge current amplifier output
AC Adapter Indication 0: AC adapter is not present (ACDET < 2.4V) <default at POR>
(Read Only)
1: AC adapter is present (ACDET > 2.4V)
BOOST Enable
0: Disable Turbo BOOST function <default at POR>
1: Enable Turbo BOOST function
Boost Mode Indication 0: Charger is not in boost mode <default at POR>
(Read Only)
1: Charger is in boost mode
ACOC Threshold
Adjust
0: function is disabled
1: 3.33x of input current regulation limit <default at POR>
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Table 3. Charge Options Register (0x12H) (continued)
BIT
BIT NAME
DESCRIPTION
[0]
Charge Inhibit
0: Enable Charge <default at POR>
1: Inhibit Charge
Setting the Charge Current
To set the charge current, write a 16bit ChargeCurrent() command (0x14H or 0b00010100) using the data format
listed in Table 4. With 10mΩ sense resistor, the bq24735 provides a charge current range of 128mA to 8.128A,
with 64mA step resolution. Sending ChargeCurrent() below 128mA or above 8.128A clears the register and
terminates charging. Upon POR, charge current is 0A. A 0.1µF capacitor between SRP and SRN for differential
mode filtering is recommended, 0.1µF capacitor between SRN and ground for common mode filtering, and an
optional 0.1µF capacitor between SRP and ground for common mode filtering. Meanwhile, the capacitance on
SRP should not be higher than 0.1µF in order to properly sense the voltage across SRP and SRN for
cycle-by-cycle under-current and over current detection.
The SRP and SRN pins are used to sense RSR with default value of 10mΩ. However, resistors of other values
can also be used. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy;
but, at the expense of higher conduction loss. If the current sensing resistor value is too high, it may trigger an
over current protection threshold because the current ripple voltage is too high. In such a case, either a higher
inductance value or a lower current sensing resistor value should be used to limit the current ripple voltage level.
A current sensing resistor value no more than 20mΩ is suggested.
To provide secondary protection, the bq24735 has an ILIM pin with which the user can program the maximum
allowed charge current. Internal charge current limit is the lower one between the voltage set by
ChargeCurrent(), and voltage on ILIM pin. To disable this function, the user can pull ILIM above 1.6V, which is
the maximum charge current regulation limit. Equation 1 shows the voltage set on ILIM pin with respect to the
preferred charge current limit:
V
= 20 × V
(
- VSRN = 20 ´ I
)
´ RSR
ILIM
SRP
CHG
(1)
Table 4. Charge Current Register (0x14H), Using 10mΩ Sense Resistor
BIT
0
BIT NAME
DESCRIPTION
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
–
1
–
2
–
3
–
4
–
5
–
6
Charge Current, DACICHG 0
0 = Adds 0mA of charger current.
1 = Adds 64mA of charger current.
7
8
Charge Current, DACICHG 1
Charge Current, DACICHG 2
Charge Current, DACICHG 3
Charge Current, DACICHG 4
Charge Current, DACICHG 5
Charge Current, DACICHG 6
0 = Adds 0mA of charger current.
1 = Adds 128mA of charger current.
0 = Adds 0mA of charger current.
1 = Adds 256mA of charger current.
9
0 = Adds 0mA of charger current.
1 = Adds 512mA of charger current.
10
11
12
0 = Adds 0mA of charger current.
1 = Adds 1024mA of charger current.
0 = Adds 0mA of charger current.
1 = Adds 2048mA of charger current.
0 = Adds 0mA of charger current.
1 = Adds 4096mA of charger current.
13
14
15
–
–
–
Not used.
Not used.
Not used.
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Setting the Charge Voltage
To set the output charge regulation voltage, write a 16bit ChargeVoltage() command (0x15H or 0b00010101)
using the data format listed in Table 5. The bq24735 provides charge voltage range from 1.024V to 19.200V,
with 16mV step resolution. Sending ChargeVoltage() below 1.024V or above 19.2V clears the register and
terminates charging. Upon POR, charge voltage limit is 0V.
The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible, and place a decoupling capacitor (0.1µF recommended) as close to the IC as possible to
decouple high frequency noise.
Table 5. Charge Voltage Register (0x15H)
BIT
0
BIT NAME
DESCRIPTION
Not used.
-
1
-
Not used.
2
-
Not used.
3
-
Not used.
4
Charge Voltage, DACV 0
0 = Adds 0mV of charger voltage.
1 = Adds 16mV of charger voltage.
5
6
Charge Voltage, DACV 1
Charge Voltage, DACV 2
Charge Voltage, DACV 3
Charge Voltage, DACV 4
Charge Voltage, DACV 5
Charge Voltage, DACV 6
Charge Voltage, DACV 7
Charge Voltage, DACV 8
Charge Voltage, DACV 9
Charge Voltage, DACV 10
-
0 = Adds 0mV of charger voltage.
1 = Adds 32mV of charger voltage.
0 = Adds 0mV of charger voltage.
1 = Adds 64mV of charger voltage.
7
0 = Adds 0mV of charger voltage.
1 = Adds 128mV of charger voltage.
8
0 = Adds 0mV of charger voltage.
1 = Adds 256mV of charger voltage.
9
0 = Adds 0mV of charger voltage.
1 = Adds 512mV of charger voltage.
10
11
12
13
14
15
0 = Adds 0mV of charger voltage.
1 = Adds 1024mV of charger voltage.
0 = Adds 0mV of charger voltage.
1 = Adds 2048mV of charger voltage.
0 = Adds 0mV of charger voltage.
1 = Adds 4096mV of charger voltage.
0 = Adds 0mV of charger voltage.
1 = Adds 8192mV of charger voltage.
0 = Adds 0mV of charger voltage.
1 = Adds 16384mV of charger voltage.
Not used.
Setting Input Current
System current normally fluctuates as portions of the system are powered up or put to sleep. With the input
current limit, the output current requirement of the AC wall adapter can be lowered, reducing system cost.
The total input current, from a wall cube or other DC source, is the sum of the system supply current and the
current required by the charger. When the input current exceeds the set input current limit, the bq24735
decreases the charge current to provide priority to system load current. As the system current rises, the available
charge current drops linearly to zero. Thereafter, all input current goes to system load and input current
increases.
During DPM regulation, the total input current is the sum of the device supply current IBIAS, the charger input
current, and the system load current ILOAD, and can be estimated as follows:
é
ê
ë
ù
ú
û
IBATTERY ´ VBATTERY
I
= ILOAD
+
+ IBIAS
INPUT
V
´ η
IN
(2)
where η is the efficiency of the charger buck converter (typically 85% to 95%).
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To set the input current limit, write a 16-bit InputCurrent() command (0x3FH or 0b00111111) using the data
format listed in Table 6. When using a 10mΩ sense resistor, the bq24735 provides an input-current limit range of
128mA to 8.064A, with 128mA resolution. The suggested input current limit is set to no less than 512mA.
Sending InputCurrent() below 128mA or above 8.064A clears the register and terminates charging. Upon POR,
the default input current limit is 4096mA.
The ACP and ACN pins are used to sense RAC with default value of 10mΩ. However, resistors of other values
can also be used. For a larger sense resistor, larger sense voltage is given, and a higher regulation accuracy;
but, at the expense of higher conduction loss.
If input current rises above FAST_DPM threshold, the charger will reduce charging current to allow the input
current drop. After a typical 260-µs delay time, if input current is still above FAST_DPM threshold, the charger
will shut down. The charger will soft restart to charge the battery if the adapter still has power to charge the
battery. This prevents a crash if the adapter is overloaded when the system has a high and fast loading transient.
The waiting time between shut down and restart charging is a natural response time of the input current limit
loop.
Table 6. Input Current Register (0x3FH), Using 10mΩ Sense Resistor
BIT
0
BIT NAME
DESCRIPTION
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
–
1
–
2
–
3
–
4
–
5
–
6
–
7
Input Current, DACIIN 0
0 = Adds 0mA of input current.
1 = Adds 128mA of input current.
8
Input Current, DACIIN 1
Input Current, DACIIN 2
Input Current, DACIIN 3
Input Current, DACIIN 4
Input Current, DACIIN 5
0 = Adds 0mA of input current.
1 = Adds 256mA of input current.
9
0 = Adds 0mA of input current.
1 = Adds 512mA of input current.
10
11
12
0 = Adds 0mA of input current.
1 = Adds 1024mA of input current.
0 = Adds 0mA of input current.
1 = Adds 2048mA of input current.
0 = Adds 0mA of input current.
1 = Adds 4096mA of input current.
13
14
15
–
–
–
Not used.
Not used.
Not used.
Support Turbo Boost Function
The bq24735 supports Turbo Boost function by allowing battery discharge energy to system when system power
demand is temporarily higher than adapter maximum power level so that adapter will not crash. After POR, the
ChargeOption() bit[3] is 0 which disable Turbo Boost function. To enable it, the ChargeOption() bit [3] must be
written to 1 by host.
When input current is higher than the FAST_DPM comparator threshold, if Turbo Boost function is enabled,
charger IC will allow battery discharge and charger converter will change from buck converter to boost converter.
During Turbo Boost mode the adapter current is regulated at input current limit level so that adapter will not
crash. The battery discharge current depends on system current requirement and adapter current limit. The
SMBus timer can be enabled to prevent converter running at Turbo Boost mode for too long.
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Adapter Detect and ACOK Output
The bq24735 uses an ACOK comparator to determine the source of power on VCC pin, either from the battery or
adapter. An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The
adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage,
but lower than the maximum allowed adapter voltage.
The open drain ACOK output requires external pull up resistor to system digital rail for a high level. It can be
pulled to external rail under the following conditions:
•
•
•
V
VCC > UVLO;
2.4V < VACDET < 3.15V (not in ACOVP condition, nor in low input voltage condition);
VCC–VSRN > 275mV (not in sleep mode);
V
The first time after IC POR always gives 150ms ACOK rising edge delay no matter what the ChargeOption
register value is. Only after the ACDET pin voltage is pulled below 2.4V (but not below 0.6V, which resets the IC
and forces the next ACOK rising edge deglitch time to be 1.3s) and the ACFET has been turned off at least one
time, the 1.3s (or 150ms) delay time is effective for the next time the ACDET pin voltage goes above 2.4V. To
change this option, the VCC pin voltage must above UVLO, and the ACDET pin voltage must be above 0.6V
which enables the IC SMBus communication and sets ChargeOption() bit[15] to 0 which sets the next ACOK
rising deglitch time to be 150ms. The purpose of the default 1.3s rising edge deglitch time is to turn off the
ACFET long enough when the ACDET pin is pulled below 2.4V by excessive system current, such as over
current or short circuit.
Adapter Over Voltage (ACOVP)
When the ACDET pin voltage is higher than 3.15V, it is considered as adapter over voltage. ACOK will be pulled
low, and charge will be disabled. ACFET will be turned off to disconnect the high voltage adapter to system
during ACOVP. BATFET will be turned on if turns on conditions are valid. See the System Power Selection
section for details.
When ACDET pin voltage falls below 3.15V and above 2.4V, it is considered as adapter voltage returns back to
normal voltage. ACOK will be pulled high by external pull up resistor. BATFET will be turned off and ACFET and
RBFET will be turned on to power the system from adapter. The charge can be resumed if enable charge
conditions are valid. See the Enable and Disable Charging section for details.
System Power Selection
The bq24735 automatically switches adapter or battery power to system. The battery is connected to system at
POR if battery exists. The battery is disconnected from system and the adapter is connected to system after
default 150ms delay (first time, the next time default is 1.3s and can be changed to 150ms) if ACOK goes HIGH.
An automatic break-before-make logic prevents shoot-through currents when the selectors switch.
The ACDRV drives a pair of common-source (CMSRC) n-channel power MOSFETs (ACFET and RBFET)
between adapter and ACP (see Figure 1 for details). The ACFET separates adapter from battery or system, and
provides a limited di/dt when plugging in adapter by controlling the ACFET turn-on time. Meanwhile it protects
adapter when system or battery is shorted. The RBFET provides negative input voltage protection and battery
discharge protection when adapter is shorted to ground, and minimizes system power dissipation with its low
RDS(on) compared to a Schottky diode.
When the adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off, disconnecting
adapter from system. BATDRV stays at VSRN + 6V to connect battery to system if all the following conditions are
valid:
•
•
•
V
V
V
VCC > UVLO;
SRN > UVLO;
ACN < 200mV above VSRN (ACN_SRN comparator);
Approximately 150ms (first time; the next time default is 1.3s and can be changed to 150ms) after the adapter is
detected (ACDET pin voltage between 2.4V and 3.15V), the system power source begins to switch from battery
to adapter if all the following conditions are valid:
•
•
Not in LEARN mode or in LEARN mode and VSRN is lower than battery depletion threshold;
ACOK high
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The gate drive voltage on ACFET and RBFET is VCMSRC + 6V. If the ACFET/RBFET have been turned on for
20ms, and the voltage across gate and source is still less than 5.9V, ACFET and RBFET will be turned off. After
1.3s delay, it resumes turning on ACFET and RBFET. If such a failure is detected seven times within 90
seconds, ACFET/RBFET will be latched off and an adapter removal and system shut down is required to force
ACDET < 0.6V to reset the IC. After IC reset from latch off, ACFET/RBFET can be turned on again. After 90
seconds, the failure counter will be reset to zero to prevent latch off. With ACFET/RBFET off, charge is disabled.
To turn off ACFET/RBFET, one of the following conditions must be valid:
•
•
In LEARN mode and VSRN is above battery depletion threshold;
ACOK low
To limit the in-rush current on ACDRV pin, CMSRC pin and BATDRV pin, a 4kΩ resistor is recommended on
each of the three pins.
To limit the adapter inrush current when ACFET is turned on to power system from adapter, the Cgs and Cgd
external capacitor of ACFET must be carefully selected. The larger the Cgs and Cgd capacitance, the slower turn
on of ACFET will be and less inrush current of adapter. However, if Cgs or Cgd is too large, the ACDRV-CMSRC
voltage may still go low after the 20ms turn on time window is expired. To make sure ACFET will not be turned
on when adapter is hot plugged in, the Cgs value should be 20 times or higher than Cgd. The most cost effective
way to reduce adapter in-rush current is to minimize system total capacitance.
Battery LEARN Cycle
A battery LEARN cycle can be activated via SMBus command (ChargeOption() bit[6]=1 enable LEARN cycle,
bit[6]=0 disable LEARN cycle). When LEARN is enabled with ACFET/RBFET connected, the system power
selector logic is over-driven to switch to battery by turning off ACFET/RBFET and turning on BATFET. LEARN
function allows the battery to discharge in order to calibrate the battery gas gauge over a complete
discharge/charge cycle. The controller automatically exits LEARN cycle when the battery voltage is below battery
depletion threshold, and the system switches back to adapter input by turning off BATFET and turning on
ACFET/RBFET. After LEARN cycle, the LEARN bit is automatically reset to 0. The battery depletion threshold
can be set to 59.19%, 62.65%, 66.55%, and 70.97% of voltage regulation level via SMBus command
(ChargeOption() bit[12:11]).
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Enable and Disable Charging
In Charge mode, the following conditions have to be valid to start charge:
•
•
•
•
•
Charge is enabled via SMBus (ChargeOption() bit [0]=0, default is 0, charge enabled);
ILIM pin voltage higher than 105mV;
All three regulation limit DACs have valid value programmed;
ACOK is valid (See the Adapter Detect and ACOK Output section for details);
ACFET and RBFET turns on and gate voltage is high enough (See the System Power Selection section for
details);
•
•
•
VSRN does not exceed BATOVP threshold;
IC Temperature does not exceed TSHUT threshold;
Not in ACOC condition (See the Input Over Current Protection (ACOC) section for details);
One of the following conditions will stop on-going charging:
•
•
•
•
•
•
•
•
•
•
Charge is inhibited via SMBus (ChargeOption() bit[0]=1);
ILIM pin voltage lower than 75mV;
One of three regulation limit DACs is set to 0 or out of range;
ACOK is pulled low (See the Adapter Detect and ACOK Output section for details);
ACFET turns off;
VSRN exceeds BATOVP threshold;
TSHUT IC temperature threshold is reached;
ACOC is detected (See the Input Over Current Protection (ACOC) section for details);
Short circuit is detected (See the Inductor Short, MOSFET Short Protection section for details);
Watchdog timer expires if watchdog timer is enabled (See the Charger Timeout section for details);
Automatic Internal Soft-Start Charger Current
Every time the charge is enabled, the charger automatically applies soft-start on charge current to avoid any
overshoot or stress on the output capacitors or the power converter. The charge current starts at 128mA, and the
step size is 64mA in CCM mode for a 10mΩ current sensing resistor. Each step lasts around 240µs in CCM
mode, till it reaches the programmed charge current limit. No external components are needed for this function.
During DCM mode, the soft start up current step size is larger and each step lasts for longer time period due to
the intrinsic slow response of DCM mode.
High Accuracy Current Sense Amplifier
As an industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current or the
charge current, selectable via SMBUS (ChargeOption() bit[5]=0 select the input current, bit[5]=1 select the
charge current) by host. The CSA senses voltage across the sense resistor by a factor of 20 through the IOUT
pin. Once VCC is above UVLO and ACDET is above 0.6V, CSA turns on and IOUT output becomes valid. To
lower the voltage on current monitoring, a resistor divider from IOUT to GND can be used and accuracy over
temperature can still be achieved.
A 100pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay.
Charge Timeout
The bq24735 includes a watchdog timer to terminate charging if the charger does not receive a write
ChargeVoltage() or write ChargeCurrent() command within 175s (adjustable via ChargeOption() command). If a
watchdog timeout occurs all register values keep unchanged but charge is suspended. Write ChargeVoltage() or
write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. The watchdog
timer can be disabled, or set to 44s, 88s or 175s via SMBus command (ChargeOption() bit[14:13]). After
watchdog timeout write ChargeOption() bit[14:13] to disable watchdog timer also resume charging.
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Converter Operation
The synchronous buck PWM converter uses a fixed frequency voltage mode control scheme and internal type III
compensation network. The LC output filter gives a characteristic resonant frequency
1
¦
=
o
2p LoCo
(3)
The resonant frequency fo is used to determine the compensation to ensure there is sufficient phase margin and
gain margin for the target bandwidth. The LC output filter should be selected to give a resonant frequency of
10–20 kHz nominal for the best performance. Suggest component value as charge current of 750kHz default
switching frequency is shown in Table 7.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Table 7. Suggest Component Value as Charge Current of Default 750kHz
Switching Frequency
Charge Current
Output Inductor Lo (µH)
Output Capacitor Co (µF)
Sense Resistor (mΩ)
2A
6.8 or 8.2
20
3A
5.6 or 6.8
20
4A
3.3 or 4.7
20
6A
3.3
30
8A
2.2
40
10
10
10
10
10
The bq24735 has three loops of regulation: input current, charge current and charge voltage. The three loops are
brought together internally at the error amplifier. The maximum voltage of the three loops appears at the output
of the error amplifier EAO. An internal saw-tooth ramp is compared to the internal error control signal EAO (see
Figure 17) to vary the duty-cycle of the converter. The ramp has offset of 200mV in order to allow 0% duty-cycle.
When the battery charge voltage approaches the input voltage, EAO signal is allowed to exceed the saw-tooth
ramp peak in order to get a 100% duty-cycle. If voltage across BTST and PHASE pins falls below 4.3V, a refresh
cycle starts and low-side n-channel power MOSFET is turned on to recharge the BTST capacitor. It can achieve
duty cycle of up to 99.5%.
Continuous Conduction Mode (CCM)
With sufficient charge current the bq24735’s inductor current never crosses zero, which is defined as continuous
conduction mode. The controller starts a new cycle with ramp coming up from 200mV. As long as EAO voltage is
above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO
voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and
LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent
cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the
low-side power MOSFET conducts the inductor current.
During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the
LSFET turn-on keeps the power dissipation low, and allows safely charging at high currents.
Discontinuous Conduction Mode (DCM)
During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to zero, the
converter enters Discontinuous Conduction Mode. Every cycle, when the voltage across SRP and SRN falls
below 5mV (0.5A on 10mΩ), the under current-protection comparator (UCP) turns off LSFET to avoid negative
inductor current, which may boost the system via the body diode of HSFET.
During the DCM mode the loop response automatically changes. It changes to a single pole system and the pole
is proportional to the load current.
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Both CCM and DCM are synchronous operation with LSFET turn-on every clock cycle. If the average charge
current goes below 125mA on 10mΩ current sensing resistor or the battery voltage falls below 2.5V, the LSFET
keeps turn-off. The battery charger operates in non-synchronous mode and the current flows through the LSFET
body diode. During non-synchronous operation, the LSFET turns on only for a refreshing pulse to charge the
BTST capacitor. If the average charge current goes above 250mA on 10mΩ current sensing resistor, the LSFET
exits non-synchronous mode and enters synchronous mode to reduce LSFET power loss.
Input Over Current Protection (ACOC)
The bq24735 cannot maintain the input current level if the charge current has been already reduced to zero.
After the system current continues increasing to the 3.33X of input current DAC set point (with 4.2ms blank out
time), ACFET/RBFET is latches off and an adapter removal and system shutdown is required to force ACDET <
0.6V to reset IC. After IC reset from latch off, ACFET/RBFET can be turned on again.
The ACOC function threshold can be set to 3.33x of input DPM current or disable this function via SMBus
command (ChargeOption() bit [1]).
Charge Over Current Protection (CHGOCP)
The bq24735 has a cycle-by-cycle peak over current protection. It monitors the voltage across SRP and SRN,
and prevents the current from exceeding of the threshold based on the DAC charge current set point. The
high-side gate drive turns off for the rest of the cycle when the over current is detected, and resumes when the
next cycle starts.
The charge OCP threshold is automatically set to 6A, 9A, and 12A on a 10mΩ current sensing resistor based on
charge current register value. This prevents the threshold to be too high which is not safe or too low which can
be triggered in normal operation. Proper inductance should be selected to prevent OCP triggered in normal
operation due to high inductor current ripple.
Battery Over Voltage Protection (BATOVP)
The bq24735 will not allow the high-side and low-side MOSFET to turn-on when the battery voltage at SRN
exceeds 104% of the regulation voltage set-point. If BATOVP last over 30ms, charger is completely disabled.
This allows quick response to an over-voltage condition – such as occurs when the load is removed or the
battery is disconnected. A 4mA current sink from SRP to GND is on only during BATOVP and allows discharging
the stored output inductor energy that is transferred to the output capacitors. Set ChargeVoltage() register value
to 0V will not trigger BATOVP function.
Battery Shorted to Ground (BATLOWV)
The bq24735 will limit inductor current if the battery voltage on SRN falls below 2.5V. After 1ms charge is reset.
After 4-5 ms the charge is resumed with soft-start if all the enable conditions in the “Enable and Disable
Charging” sections are satisfied. This prevents any overshoot current in inductor which can saturate inductor and
may damage the MOSFET. The charge current is limited to 0.5A on 10mΩ current sensing resistor when
BATLOWV condition persists and LSFET keeps off. The LSFET turns on only for a refreshing pulse to charge
BTST capacitor.
Thermal Shutdown Protection (TSHUT)
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off for
self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction
temperature falls below 135°C. During thermal shut down, the REGN LDO current limit is reduced to 16mA.
Once the temperature falls below 135°C, charge can be resumed with soft start.
EMI Switching Frequency Adjust
The charger switching frequency can be adjusted ±18% to solve EMI issue via SMBus command.
ChargeOption() bit [9]=0 disable the frequency adjust function. To enable frequency adjust function, set
ChargeOption() bit[9]=1. Set ChargeOption() bit [10]=0 to reduce switching frequency, set bit[10]=1 to increase
switching frequency.
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If frequency is reduced, for a fixed inductor the current ripple is increased. Inductor value must be carefully
selected so that it will not trig cycle-by-cycle peak over current protection even for the worst condition such as
higher input voltage, 50% duty cycle, lower inductance and lower switching frequency.
Inductor Short, MOSFET Short Protection
The bq24735 has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is
achieved through monitoring the voltage drop across RDS(on) of the MOSFETs after a certain amount of blanking
time. In case of MOSFET short or inductor short circuit, the over current condition is sensed by two comparators
and two counters will be triggered. After seven times of short circuit events, the charger will be latched off and
ACFET and RBFET are turned off to disconnect adapter from system. BATFET is turned on to connect battery
pack to system. To reset the charger from latch-off status, the IC VCC pin must be pulled below UVLO or the
ACDET pin must be pulled below 0.6V. This can be achieved by removing the adapter and shut down the
operation system. The low side MOSFET short circuit voltage drop threshold can be adjusted via SMBus
command. ChargeOption() bit[7] =0, 1 set the low side threshold 135mV and 230mV respectively. The high side
MOSFET short circuit voltage drop threshold can be adjusted via SMBus command. ChargeOption() bit[8] = 0, 1
disable the function and set the threshold 750mV respectively. During boost function, the low side MOSFET short
circuit protection threshold is used for cycle-by-cycle current limiting, charger will not latch up.
Due to the certain amount of blanking time to prevent noise when MOSFET just turn on, the cycle-by-cycle
charge over-current protection may detect high current and turn off MOSFET first before the short circuit
protection circuit can detect short condition because the blanking time has not finished. In such a case the
charger may not be able to detect short circuit and counter may not be able to count to seven then latch off.
Instead the charger may continuously keep switching with very narrow duty cycle to limit the cycle-by-cycle
current peak value. However, the charger should still be safe and will not cause failure because the duty cycle is
limited to a very short of time and MOSFET should be still inside the safety operation area. During a soft start
period, it may takes long time instead of just seven switching cycles to detect short circuit based on the same
blanking time reason.
Table 8. Component List for Typical System Circuit of Figure 1
PART DESIGNATOR
QTY
6
DESCRIPTION
C1, C2, C3, C13, C14, C16
Capacitor, Ceramic, 0.1µF, 25V, 10%, X7R, 0603
Capacitor, Ceramic, 100pF, 25V, 10%, X7R, 0603
Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 0603
Capacitor, Ceramic, 0.047µF, 25V, 10%, X7R, 0603
Capacitor, Ceramic, 10µF, 25V, 10%, X7R, 1206
Capacitor, Ceramic, 0.01µF, 25V, 10%, X7R, 0603
Capacitor, Ceramic, 2200pF, 25V, 10%, X7R, 0603
Capacitor, Ceramic, 2.2µF, 25V, 10%, X7R, 1210
Capacitor, Electrolytic, 220µF, 25V
C4
1
C5, C6
2
C7
1
C8, C9, C10, C11
4
C15
1
C17
1
Ci
1
Csys
1
D1
1
Diode, Schottky, 30V, 200mA, SOT-23, Fairchild, BAT54
Diode, Dual Schottky, 30V, 200mA, SOT-23, Fairchild, BAT54C
N-channel MOSFET, 30V, 12.5A, SO-8, Fairchild, FDS6680A
N-channel MOSFET, 30V, 12A, PowerPAK 1212-8, Vishay Siliconix, SiS412DN
N-channel MOSFET, 50V, 0.2A, SOT-323, Diodes, BSS138W
Inductor, SMT, 4.7µH, 5.5A, Vishay Dale, IHLP2525CZER4R7M01
Resistor, Chip, 430kΩ, 1/10W, 1%, 0603
D2
1
Q1, Q2, Q5
3
Q3, Q4
2
Q6
1
L1
1
R1
1
R2
1
Resistor, Chip, 66.5kΩ, 1/10W, 1%, 0603
R3, R4, R5
3
Resistor, Chip, 10kΩ, 1/10W, 1%, 0603
R6, R10, R11
3
Resistor, Chip, 4.02kΩ, 1/10W, 1%, 0603
R7
1
Resistor, Chip, 316kΩ, 1/10W, 1%, 0603
R8
1
Resistor, Chip, 100kΩ, 1/10W, 1%, 0603
R9
1
Resistor, Chip, 10Ω, 1/4W, 1%, 1206
R12
R13
1
Resistor, Chip, 1.00MΩ, 1/10W, 1%, 0603
1
Resistor, Chip, 3.01MΩ, 1/10W, 1%, 0603
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Table 8. Component List for Typical System Circuit of Figure 1 (continued)
PART DESIGNATOR
QTY
DESCRIPTION
R14
R15
RAC, RSR
Ri
1
1
2
1
1
1
Resistor, Chip, 10Ω, 1/10W, 5%, 0603
Resistor, Chip, 7.5Ω, 1/10W, 5%, 0603
Resistor, Chip, 0.01Ω, 1/2W, 1%, 1206
Resistor, Chip, 2Ω, 1/2W, 1%, 1210
Charger controller, 20 pin VQFN, TI, bq24735RGR
Dual digital transistor, 40V, 30mA, SC-74, Rohm, IMD2A
U1
U2
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APPLICATION INFORMATION
Negative Output Voltage Protection
Reversely insert the battery pack into the charger output during production or hard shorts on battery to ground
will generate negative output voltage on SRP and SRN pin. IC internal electrostatic-discharge (ESD) diodes from
GND pin to SRP or SRN pins and two anti-parallel (AP) diodes between SRP and SRN pins can be forward
biased and negative current can pass through the ESD diodes and AP diodes when output has negative voltage.
Insert two small resistors for SRP and SRN pins to limit the negative current level when output has negative
voltage. Suggest resistor value is 10 ohm for SRP pin and 7-8 Ω for SRN pin. After adding small resistors, the
suggested pre-charge current is at least 192mA for a 10m ohm current sensing resistor. Another method is using
a small diode parallel with output capacitor, when battery connection is reversed the diode turns on and limits the
negative voltage level. Using diode protection method without insertion of small resistors into SRP and SRN pin
can get the best charging current accuracy.
Reverse Input Voltage Protection
Q6, R12 and R13 in Figure 1 gives system and IC protection from reversed adapter voltage. In normal operation,
Q6 is turned off by negative Vgs. When adapter voltage is reversed, Q6 Vgs is positive. As a result, Q6 turns on
to short gate and source of Q2 so that Q2 is off. Q2 body diode blocks negative voltage to system. However,
CMSRC and ACDRV pins need R10 and R11 to limit the current due to the ESD diode of these pins when turned
on. Q6 must has low Vgs threshold voltage and low Qgs gate charge so it turns on before Q2 turns on. R10 and
R11 must have enough power rating for the power dissipation when the ESD diode is on. In Figure 2, the
Schottky diode D3 gives the reverse adapter voltage protection, no extra small MOSFET and resistors are
needed.
In Figure 3, the Schottky diode Din is used for the reverse adapter voltage protection.
Reduce Battery Quiescent Current
When the adapter is not present, if VCC is powered with voltage higher than UVLO directly or indirectly (such as
through a LDO or switching converter) from battery, the internal BATFET charge pump gives the BATFET pin 6V
higher voltage than the SRN pin to drive the n-channel BATFET. As a result, the battery has higher quiescent
current. This is only necessary when the battery powers the system due to a high system current that goes
through the MOSFET channel instead of the body diode to reduce conduction loss and extend the battery
working life. When the system is totally shutdown, it is not necessary to let the internal BATFET charge pump
work. The host controller can use a digital signal EN to disconnect the battery power path to the VCC pin by U2
in Figure 1. As a result, battery quiescent current can be minimized. The host controller still can get power from
BATFET body diode because the total system current is the lowest when the system is shutdown, so there is no
high conduction loss of the body diode.
Inductor Selection
The bq24735 has three selectable fixed switching frequency. Higher switching frequency allows the use of
smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current
(ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE
(4)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fS) and
inductance (L):
V
´ D ´ (1 - D)
IN
IRIPPLE
=
fS ´ L
(5)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9V to 12.6V for 3-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the
maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12V to
16.8V, and 12V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20-40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
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The bq24735 has charge under current protection (UCP) by monitoring charging current sensing resistor
cycle-by-cycle. The typical cycle-by-cycle UCP threshold is 5mV falling edge corresponding to 0.5A falling edge
for a 10mΩ charging current sensing resistor. When the average charging current is less than 125mA for a 10mΩ
charging current sensing resistor, the low side MOSFET is off until BTST capacitor voltage needs to refresh the
charge. As a result, the converter relies on low side MOSFET body diode for the inductor freewheeling current.
Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at
50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and
can be estimated by Equation 6:
ICIN = ICHG
´
D × (1 - D)
(6)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred
for 19-20V input voltage. 10-20μF capacitance is suggested for typical of 3-4A charging current.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current is given:
IRIPPLE
ICOUT
=
» 0.29 ´ IRIPPLE
2 ´
3
(7)
The bq24735 has internal loop compensator. To get good loop stability, the resonant frequency of the output
inductor and output capacitor should be designed between 10 kHz and 20 kHz. The preferred ceramic capacitor
is 25V X7R or X5R for output capacitor. 10-20μF capacitance is suggested for a typical of 3-4A charging current.
Place the capacitors after charging current sensing resistor to get the best charge current regulation accuracy.
Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Power MOSFETs Selection
Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are
preferred for 19-20V input voltage.
Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction
loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,
RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.
FOMtop = RDS(on) x QGD; FOMbottom = RDS(on) x QG
(8)
The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle
(D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance (RDS(ON)), input voltage (VIN), switching frequency
(fS), turn on time (ton) and turn off time (toff):
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1
2
2
= D ´ ICHG ´ RDS(on)
P
+
´ V ´ ICHG ´ (ton + toff ) ´ fs
IN
top
(9)
The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100°C junction
temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are
given by:
QSW
QSW
ton
=
, toff =
Ion
Ioff
(10)
where Qsw is the switching charge, Ion is the turn-on gate driving current and Ioff is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(QGD) and gate-to-source charge (QGS):
1
QSW = QGD
+
´ QGS
2
(11)
Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on
gate resistance (Ron) and turn-off gate resistance (Roff) of the gate driver:
VREGN - Vplt
Vplt
Ion
=
, Ioff =
Ron
Roff
(12)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
Pbottom = (1 - D) x ICHG 2 x RDS(on)
(13)
When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the
freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss
depends on its forward voltage drop (VF), non-synchronous mode charging current (INONSYNC), and duty cycle (D).
PD = VF x INONSYNC x (1 - D)
(14)
The maximum charging current in non-synchronous mode can be up to 0.25A for a 10mΩ charging current
sensing resistor or 0.5A if battery voltage is below 2.5V. The minimum duty cycle happens at lowest battery
voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the
maximum non-synchronous mode charging current.
Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second
order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The
input filter must be carefully designed and tested to prevent over voltage event on VCC pin.
There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin
voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.
However these two solutions may not have low cost or small size.
A cost effective and small size solution is shown in Figure 21. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used
for reverse voltage protection for VCC pin. C2 is VCC pin decoupling capacitor and it should be place to VCC pin
as close as possible. C2 value should be less than C1 value so R1 can dominant the equivalent ESR value to
get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage when adapter
hot plug-in. R2 and C2 should have 10us time constant to limit the dv/dt on VCC pin to reduce inrush current
when adapter hot plug in. R1 has high inrush current. R1 package must be sized enough to handle inrush current
power loss according to resistor manufacturer’s datasheet. The filter components value always need to be
verified with real application and minor adjustments may need to fit in the real application circuit.
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D1
R2(1206)
10-20 Ω
R1(2010)
2Ω
Adapter
connector
VCC pin
C1
2.2μF
C2
0.47-1μF
Figure 21. Input Filter
bq24735 Design Guideline
The bq24735 has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is
achieved through monitoring the voltage drop across RDS(on) of the MOSFETs after a certain amount of blanking
time. For a MOSFET short or inductor short circuit, the over current condition is sensed by two comparators, and
two counters are triggered. After seven occurrences of a short circuit event, the charger will be latched off. To
reset the charger from latch-off status, reconnect the adapter. Figure 22 shows the bq24735 short circuit
protection block diagram.
Adapter
ACN
BTST
ACP
SCP1
RAC
High-Side
MOSFET
RPCB
PHASE
L
REGN
RDC
Battery
Low-Side
MOSFET
COMP1
SCP2
COMP2
C
Count to 7
CLR
Latch off
Charger
Adapter
Plug in
Figure 22. Block Diagram of bq24735 Short Circuit Protection
In normal operation, the low side MOSFET current is from source to drain which generates a negative voltage
drop when it turns on, as a result the over current comparator can not be triggered. When the high side switch
short circuit or inductor short circuit happens, the large current of low side MOSFET is from drain to source and
can trig low side switch over current comparator. bq24735 senses the low side switch voltage drop through the
PHASE pin and GND pin.
The high-side FET short is detected by monitoring the voltage drop between ACP and PHASE. As a result, it not
only monitors the high side switch voltage drop, but also the adapter sensing resistor voltage drop and PCB trace
voltage drop from ACN terminal of RAC to charger high side switch drain. Usually, there is a long trance between
input sensing resistor and charger converting input, a careful layout will minimize the trace effect.
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To prevent unintentional charger shut down in normal operation, MOSFET RDS(on) selection and PCB layout is
very important. Figure 23 shows a improvement PCB layout example and its equivalent circuit. In this layout, the
system current path and charger input current path is not separated, as a result, the system current causes
voltage drop in the PCB copper and is sensed by the IC. The worst layout is when a system current pull point is
after charger input; as a result all system current voltage drops are counted into over current protection
comparator. The worst case for IC is when the total system current and charger input current sum equals the
DPM current. When the system pulls more current, the charger IC tries to regulate the RAC current as a constant
current by reducing the charging current.
I
DPM
R AC
System Path PCB Trace
I
System current
SYS
R
R
AC
PCB
I
CHRGIN
Charger input current
ACP
ACN
Charger
I
Charger Input PCB Trace
BAT
To ACP
To ACN
(a) PCB Layout
(b) Equivalent Circuit
Figure 23. Need improve PCB layout example.
Figure 24 shows the optimized PCB layout example. The system current path and charge input current path is
separated, as a result the IC only senses charger input current caused PCB voltage drop and minimized the
possibility of unintentional charger shut down in normal operation. This also makes PCB layout easier for high
system current application.
R AC
System Path PCB Trace
I
DPM
I
System current
SYS
Single point connection at RAC
Charger input current
R
R
PCB
AC
I
CHRGIN
ACP
ACN
I
Charger
(b) Equivalent Circuit
BAT
To ACP
To ACN
Charger Input PCB Trace
(a) PCB Layout
Figure 24. Optimized PCB layout example.
The total voltage drop sensed by IC can be express as the following equation.
Vtop = RAC x IDPM + RPCB x (ICHRGIN + (IDPM - ICHRGIN) x k) + RDS(on) x IPEAK
(15)
where the RAC is the AC adapter current sensing resistance, IDPM is the DPM current set point, RPCB is the PCB
trace equivalent resistance, ICHRGIN is the charger input current, k is the PCB factor, RDS(on) is the high side
MOSFET turn on resistance and IPEAK is the peak current of inductor. Here the PCB factor k equals 0 means the
best layout shown in Figure 24 where the PCB trace only goes through charger input current while k equals 1
means the worst layout shown in Figure 23 where the PCB trace goes through all the DPM current. The total
voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut
down in normal operation.
The low side MOSFET short circuit voltage drop threshold can be adjusted via SMBus command.
ChargeOption() bit[7] =0, 1 set the low side threshold 135mV and 230mV respectively. The high side MOSFET
short circuit voltage drop threshold can be adjusted via SMBus command. ChargeOption() bit[8] = 0, 1 disable
the function and set the threshold 750mV respectively. For a fixed PCB layout, host should set proper short
circuit protection threshold level to prevent unintentional charger shut down in normal operation.
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PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 25) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use
shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on
different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal
traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching
MOSFETs.
3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 26 for Kelvin connection for
best current accuracy). Place decoupling capacitor on these traces next to the IC
5. Place output capacitor next to the sensing resistor output and ground
6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC
use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling
8. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using power pad as the single ground
connection point. Or using a 0Ω resistor to tie analog ground to power ground (power pad should tie to
analog ground in this case if possible).
9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible
10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
11. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the QFN
information, See SCBA017 and SLUA271.
R1
L1
VBAT
PHASE
High
Frequency
Current
Path
VIN
BAT
GND
C2
C1
Figure 25. High Frequency Current Path
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Charge Current Direction
RSNS
To Inductor
To Capacitor and battery
Current Sensing Direction
To SRP and SRN pin
Figure 26. Sensing resistor PCB layout.
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Product Folder Link(s) :bq24735
PACKAGE OPTION ADDENDUM
www.ti.com
21-Sep-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
BQ24735RGRR
BQ24735RGRT
ACTIVE
ACTIVE
VQFN
VQFN
RGR
RGR
20
20
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24735RGRR
BQ24735RGRT
VQFN
VQFN
RGR
RGR
20
20
3000
250
330.0
180.0
12.4
12.4
3.75
3.75
3.75
3.75
1.15
1.15
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24735RGRR
BQ24735RGRT
VQFN
VQFN
RGR
RGR
20
20
3000
250
552.0
552.0
367.0
185.0
36.0
36.0
Pack Materials-Page 2
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