BQ25173DSGR [TI]
适用于 1 至 4 节超级电容器电池的 800mA 线性充电器 | DSG | 8 | -40 to 125;
| 型号： | BQ25173DSGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 1 至 4 节超级电容器电池的 800mA 线性充电器 | DSG | 8 | -40 to 125 电池 电容器 |
| 文件： | 总29页 (文件大小：2624K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ25173
ZHCSNR9 –NOVEMBER 2021
BQ25173：适用于1-4 芯超级电容器的800mA 线性电池充电器
1 特性
3 说明
• 可承受高达40V 的输入电压
• 自动睡眠模式，可降低功耗
BQ25173 是一款集成式 800mA 线性充电器，适用于
面向空间受限型应用的1-4 芯超级电容器。该器件具有
为超级电容器充电的单电源输出。可以将系统负载与超
级电容器并联；充电电流由系统和超级电容器共享。
– 350nA 泄漏电流
– 禁用充电时，输入泄漏电流为2µA
• 支持1-4 芯超级电容器
• 支持从0V 为超级电容器充电
• 操作可使用外部电阻器进行编程
– FB 引脚用于调节超级电容器稳压电压
– ISET 用于设置10mA 至800mA 的充电电流
• 高精度
在充电期间，内部控制环路会监视 IC 结温并在超过内
部温度阈值 TREG 时减小充电电流。此功能可为完全放
电的超级电容器提供快速充电。
充电器功率级和充电电流感测功能均完全集成。该充电
器具有高精度电流和电压调节环路功能、充电状态显示
和充电功能控制。充电电压和快速充电电流可通过外部
电阻编程设定。
– 充电电压精度为±1%
– 充电电流精度为±10%
• 充电特性
器件信息
封装(1)
封装尺寸（标称值）
器件型号
BQ25173
– CE 引脚用于充电功能控制
– 用于状态和故障指示的开漏输出
– 用于电源正常指示的开漏输出
• 集成故障保护
WSON (8)
2.0mm x 2.0mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 18V 输入过压保护
– 1000mA 过流保护
– 125°C 热调节；150°C 热关断保护
– OUT 短路保护
– ISET 引脚短路/开路保护
1s-4s supercapacitor
IN
OUT
VIN: 3.0V – 18V
VREF
VOUT: 0V – 10.5V
STAT
ISET
GND
FB
/CE
/PG
VREF
HOST
2 应用
BQ25173
• 智能仪表
• 条形码扫描仪
• 便携式医疗设备
• 仪表板摄像头
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDY6
BQ25173
ZHCSNR9 –NOVEMBER 2021
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Table of Contents
8 Application and Implementation..................................16
8.1 Application Information............................................. 16
8.2 Typical Applications.................................................. 16
9 Power Supply Recommendations................................20
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 20
10.3 Thermal Package....................................................20
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 接收文档更新通知................................................... 22
11.3 支持资源..................................................................22
11.4 Trademarks............................................................. 22
11.5 Electrostatic Discharge Caution..............................22
11.6 术语表..................................................................... 22
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Timing Requirements .................................................7
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................14
Information.................................................................... 23
4 Revision History
DATE
REVISION
NOTES
November 2021
*
Initial Release
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5 Pin Configuration and Functions
IN
ISET
/CE
1
2
3
4
8
7
6
5
OUT
FB
BQ25173
/PG
Thermal Pad
GND
STAT
图5-1. DSG (WSON) Package 8-Pin Top View
表5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
Input power. Connect to external DC supply. Bypass IN with at least 1-μF capacitor to GND,
placed close to the IC.
IN
1
P
I
Programs the device fast-charge current, ICHG. External resistor from ISET to GND defines fast-
charge current value. Expected range is 30 kΩ (10 mA) to 375 Ω (800 mA). ICHG = KISET / RISET
ISET
2
.
Active low charge enable pin. Charging is enabled when the CE pin is LOW. IC remains in
Shutdown mode and charging is disabled when the CE pin is HIGH. An internal pulldown
resistor (RPD_CE) enables the IC by default if this pin is floating.
CE
3
4
5
I
GND
STAT
Ground pin.
–
Open-drain charger status indication output. Connect to pullup rail with a 10-kΩresistor. LOW
indicates VOUT has reached 98% of the programmable regulation voltage, VREG. HIGH indicates
charge in progress.
O
Open-drain charger power-good output. Connect to pullup rail with a 10-kΩresistor. PG goes
PG
FB
6
7
O
I
LOW when VIN > VIN_LOWV and VOUT + VSLEEPZ < VIN < VIN_OV
.
Programs the supercapacitor regulation voltage, VREG. Use a feedback divider not exceeding 1
MΩfrom VOUT to GND to set the regulation voltage. The bottom of the resistor divider network
can be connected to PG for reduced power consumption when the input is removed (for VREG
≤5 V).
Supercapacitor connection. System load may be connected in parallel with supercapacitor.
Bypass OUT with at least 1-μF capacitor to GND, placed close to the IC.
OUT
8
P
P
Exposed pad beneath the IC for heat dissipation. Solder thermal pad to the board with vias
connecting to solid GND plane.
Thermal Pad
—
(1) I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
40
UNIT
V
Voltage
IN
Voltage
OUT
13
V
Voltage
CE, FB, ISET, STAT, PG
PG, STAT
5.5
5
V
Output Sink Current
Junction temperature, TJ
Storage temperature, Tstg
mA
°C
°C
150
150
–40
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the d ality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.0
0
NOM
MAX
18
UNIT
V
VIN
Input voltage
VOUT
Output voltage
10.5
V
IOUT
TJ
Output current
Junction temperature
IN capacitor
0.8
A
125
°C
µF
µF
kΩ
–40
1
CIN
COUT
RISET
OUT capacitor
ISET resistor
1
0.375
30
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6.4 Thermal Information
BQ25173
DSG (WSON)
8 PINS
75.2
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance (JEDEC(1)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
93.4
41.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.8
ΨJT
41.7
ΨJB
RθJC(bot)
17.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
3.0V < VIN < 18V and VIN > VOUT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
QUIESCENT CURRENTS
OUT= 4.2V, IN floating or IN = 0V - 5V,
Charge Disabled (CE high), TJ = 25 °C
0.350
0.350
0.8
0.6 µA
0.8 µA
1.2 µA
1.5 µA
IQ_OUT
IQ_OUT
ISD_IN
Quiescent output current (OUT)
Quiescent output current (OUT)
OUT= 4.2V, IN floating or IN = 0V - 5V,
Charge Disabled (CE high), TJ < 105 °C
OUT = 8.4V, IN floating or IN = 0V - 14V,
Charge Disabled (CE high), TJ = 25 °C
OUT = 8.4V, IN floating or IN = 0V - 14V,
Charge Disabled (CE high), TJ < 105 °C
0.8
IN = 5V, Charge Disabled (CE high), no
capacitor
2
4
6
µA
µA
Shutdown input current (IN) with
charge disabled
IN = 14V, Charge Disabled (CE high), no
capacitor
3.5
IN = 5V, OUT = 3.8V, Charge Enabled (CE
low), ICHG = 0A
IQ_IN
IQ_IN
Quiescent input current (IN)
Quiescent input current (IN)
0.45
0.45
0.6 mA
0.6 mA
IN = 14V, OUT = 7.6V, Charge Enabled (CE
low), ICHG = 0A
INPUT
VIN_OP
IN operating range
3.0
18
V
V
VIN_LOWV
VIN_LOWV
IN voltage to start charging
IN rising
IN falling
3.05
3.09
2.95
3.15
IN voltage to stop charging
2.80
95
3.10
V
VSLEEPZ
VSLEEP
VIN_OV
Exit sleep mode threshold
IN rising, VIN - VOUT, OUT = 4V
IN falling, VIN - VOUT, OUT = 4V
IN rising
135
80
175 mV
mV
Sleep mode threshold hysteresis
VIN overvoltage rising threshold
VIN overvoltage falling threshold
18.1
18.4
18.2
18.7
350
1
V
V
VIN_OVZ
IN falling
CONFIGURATION PINS SHORT/OPEN PROTECTION
RISET below this at startup, charger does not
initiate charge, power cycle or CE toggle to
reset
Highest resistor value considered
short
RISET_SHORT
Ω
CHARGER
VFB_REF
Feedback reference voltage
0.8
V
VFB_REF_ACC
Feedback reference voltage accuracy
-1
%
Tj = -40℃to 125℃
Typical charge current regulation
range
ICHG_RANGE
KISET
VOUT > VBAT_LOWV
10
800 mA
330
Charge current setting factor, ICHG
KISET / RISET
=
10mA < ICHG < 800mA
270
300
AΩ
720
450
90
800
500
100
10
880 mA
550 mA
110 mA
11 mA
RISET = 375Ω, OUT = 3.8V or 7.6V
RISET = 600Ω, OUT = 3.8V or 7.6V
RISET = 3.0kΩ, OUT = 3.8V or 7.6V
RISET = 30kΩ, OUT = 3.8V or 7.6V
ICHG_ACC
Charge current accuracy
9
OUT rising, as percentage of FB regulation
target
VCHG
Supercapacitor charged threshold
Charging path FET on-resistance
98
%
IOUT = 400mA, TJ = 25°C
845
845
1000
1450
mΩ
mΩ
RON
IOUT = 400mA, TJ = -40 - 125°C
CHARGER PROTECTION
IOUT_OCP Output current limit threshold
IOUT rising
0.9
1
1.1
A
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6.5 Electrical Characteristics (continued)
3.0V < VIN < 18V and VIN > VOUT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TEMPERATURE REGULATION AND TEMPERATURE SHUTDOWN
Typical junction temperature
regulation
TREG
125
°C
Thermal shutdown rising threshold
Thermal shutdown falling threshold
Temperature increasing
Temperature decreasing
150
135
°C
°C
TSHUT
LOGIC INPUT PIN (/CE)
VIH
Input high threshold level
1.3
3.3
V
VIL
Input low threshold level
0.4
V
RPD_CE
CE pin internal pulldown resistor
MΩ
LOGIC OUTPUT PIN (STAT, PG)
VOL
Output low threshold level
High-level leakage current
Sink current = 5mA
Pull up rail 3.3V
0.4
1
V
IOUT_BIAS
µA
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
CHARGER
tOUT_OCP_DGL
Deglitch time for IOUT_OCP, IOUT rising
100
µs
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6.7 Typical Characteristics
CIN = 1 µF, COUT = 1 µF
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-40èC
0èC
25èC
85èC
105èC
-40èC
0èC
25èC
85èC
105èC
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
4
6
8
10
VIN (V)
12
14
16
18
8
9
10
11
12
13
VIN (V)
14
15
16
17
18
IOUT = 10 mA
图6-1. Line Regulation
VOUT = 4.2 V
IOUT = 10 mA
VOUT = 8.4 V
图6-2. Line Regulation
10
8
10mA
50mA
100mA
200mA
400mA
600mA
800mA
6
4
2
0
-2
-4
-6
-8
-10
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
VOUT (V)
4
4.1
VIN = 5 V
Temp. = 25ºC
VIN = 5 V
VOUT = 4.2 V
图6-3. Load Regulation
图6-4. ICHG Accuracy vs. VOUT
图6-6. Dropout Voltage vs. Output Current
VIN = 5 V and 12 V
VOUT = 3.8 V and 7.6 V
图6-5. ICHG Accuracy vs. Temperature
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6.7 Typical Characteristics (continued)
CIN = 1 µF, COUT = 1 µF
5.5
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
-40èC
-40èC
0èC
25èC
85èC
105èC
5
0èC
25èC
4.5
105èC
125èC
4
3.5
3
2.5
2
1.5
1
0.5
2
4
6
8
10
VIN (V)
12
14
16
18
3
5
7
9
11
VIN (V)
13
15
17 18
CE Pin = HIGH
VOUT = 0 V
CE Pin = LOW
ICHG = 0 A
图6-7. Input Shutdown Current vs. Input Voltage
图6-8. Input Quiescent Current vs. Input Voltage
2
-40èC
1.8
0èC
25èC
1.6
105èC
125èC
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1
2
3
4
5 6
VOUT (V)
7
8
9
10
VIN = 0 V
图6-9. Output Quiescent Current vs. Output Voltage
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7 Detailed Description
7.1 Overview
The device has a single power output that charges the supercapacitor. The system load can be placed in parallel
with the supercapacitor; the charge current is shared between the system and supercapacitor.
The charger is designed for a single path from the input to the output to charge the supercapacitor. Upon
application of a valid input power source, the ISET pin is checked for short/open circuit.
The device attempts to charge the supercapacitor at the fast-charge current setting from fully discharged (0 V)
up to the programmable regulation voltage, VREG. Power dissipation in the IC is greatest in fast charge with a
lower supercapacitor voltage. If the IC temperature reaches TREG, the IC enters thermal regulation and reduces
the charge current as needed to keep the temperature from rising any further. The fast-charge current is
programmed using the ISET pin. 图7-1 shows the typical supercapacitor charging profile with thermal regulation.
At lower fast-charge settings, the junction temperature of the IC is less than TREG and thermal regulation is not
entered.
Once the supercapacitor has charged to the regulation voltage, the voltage loop takes control and holds the
voltage at the regulation voltage as the current tapers down to zero. There is no current termination threshold as
seen in Li-ion chargers.
Further details are described in 节7.3.
Regulation Voltage
VREG
OUT Voltage
Charge Current
ICHG
OUT Current
TJ Regulation
TREG
Fast-Charge
CC
Taper-Charge
CV
图7-1. Supercapacitor Charging Profile with Thermal Regulation
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7.2 Functional Block Diagram
OUT
IN
VFB
ICHG
VIN
+
+
VIN_OV
VSLEEPZ
VIN_LOWV
ICHG_REF
VFB_REF
INPUT
MONITOR
+
QBLK
CNTRL
FB
TREG
TJ
/PG
/CE
CEN
FAULT
ISET
ICHG_REF
VFB_REF
TREG
VREF
PIN DETECT
&
REF DAC
TJ
TJSHUT
+
STAT
/PG
TSHUT
STAT
/PG
CHARGE
CONTROL
GND
VFB
ICHG
STAT
OUT OCP
STAT
+
+
IOUT_OCP
V
FB_REF x 98%
STATE
MONITOR
BQ25173
FAULT
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7.3 Feature Description
7.3.1 Device Power Up from Input Source
When an input source is plugged in and charge is enabled, the device checks the input source voltage to turn on
all of the bias circuits. The device detects and sets the charge current limits before the linear regulator is started.
The power-up sequence from the input source is listed below:
1. ISET pin detection
2. Charger power up
7.3.1.1 ISET Pin Detection
After a valid VIN is plugged in and the CE pin is pulled LOW, the device checks the resistor on the ISET pin for a
short circuit (RISET < RISET_SHORT). If a short condition is detected, the charger remains in the FAULT state until
the input or CE pin is toggled. If the ISET pin is open circuit, the charger proceeds through pin detection and
starts the charger with no charge current. This pin is monitored during charging and changes in RISET while the
charger is operating immediately translates to changes in charge current.
An external pulldown resistor (±1% or better recommended to minimize charge current error) from the ISET pin
to GND sets the charge current as:
KISET
ICHG
=
RISET
(1)
where:
• ICHG is the desired fast-charge current
• KISET is the gain factor found in the electrical specifications
• RISET is the pulldown resistor from the ISET pin to GND
For charge currents below 50 mA, an extra RC circuit is recommended on the ISET pin to achieve a more stable
current signal. For greater accuracy at lower currents, part of the current-sensing FET is disabled to give better
resolution.
7.3.2 Supercapacitor Regulation Voltage
The device allows for the supercapacitor regulation voltage, VREG, to be programmed with a resistor divider
between the OUT and FB pins:
R
+ R
FBT
R
FBB
V
= V
×
FB_REF
(2)
REG
FBB
Where VFB_REF is listed in the electrical characteristcs table. The resistors can be seen in 图 7-2. The total
resistance (RFBT + RFBB) should not exceed 1 MΩ.
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RFBT
RFBB
FB
/CE
/PG
VREF
HOST
图7-2. BQ25173 Feedback Divider
7.3.3 Supercapacitor Charging Profile
The device charges a supercapacitor in two phases: constant current and constant voltage. Power dissipation in
the IC is greatest in fast charge with a lower supercapacitor voltage. If the IC temperature reaches TREG, the IC
enters thermal regulation and reduces the charge current as needed to keep the temperature from rising any
further. As the supercapacitor approaches the regulation voltage, the current tapers down to 0 mA. There is no
current termination threshold as seen in Li-Ion chargers.
7.3.4 Status Outputs (PG, STAT)
7.3.4.1 Power Good Indicator (PG Pin)
This open-drain pin pulls LOW to indicate a good input source when:
1. VIN above VIN_LOWV
2. VIN above VOUT + VSLEEPZ (not in SLEEP)
3. VIN below VIN_OV
The PG pin can be used as the GND connection for the bottom resistor in the feedback divider to prevent divider
leakage current from the supercapacitor when the charger is disabled. This is only recommended when VREG
≤
5 V (1-2s supercapacitors) as the absolute maximum rating on PG is 5.5 V. An example circuit can be seen in 图
8-1.
7.3.4.2 Charging Status Indicator (STAT)
The device indicates the charging state on the open-drain STAT pin. This pin can drive an LED.
表7-1. STAT Pin State
CHARGING STATE
STAT PIN STATE
High
VFB < 98% of VFB_REF
VFB > 98% of VFB_REF
Low
Fault (VIN OVP, OUT OCP, or ISET pin short)
Blink at 1 Hz
7.3.5 Protection Features
The device closely monitors input and output voltage, as well as internal FET current and temperature for safe
linear regulator operation.
7.3.5.1 Input Overvoltage Protection (VIN OVP)
If the voltage at the IN pin exceeds VIN_OV, the device enters STANDBY mode. Once the IN voltage recovers to
normal level, charging resumes.
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7.3.5.2 Output Overcurrent Protection (OUT OCP)
During normal operation, the OUT current should be regulated to the ISET programmed value. However, if a
short circuit occurs on the ISET pin, the OUT current may rise to an unintended level. If current at the OUT pin
exceeds IOUT_OCP, the device turns off after a deglitch, tOUT_OCP_DGL, and the device remains latched off. An
input supply or CE pin toggle is required to restart operation.
IOUT_OCP
ICHG
tOUT_OCP_DGL
RISET
Short Circuit
event on ISET
Charger
latched off
图7-3. Overcurrent Protection
7.3.5.3 Thermal Regulation and Thermal Shutdown (TREG and TSHUT
)
The device monitors its internal junction temperature (TJ) to avoid overheating and to limit the IC surface
temperature. When the internal junction temperature exceeds the thermal regulation limit, the device
automatically reduces the charge current to maintain the junction temperature at the thermal regulation limit
(TREG). During thermal regulation, the actual charging current is usually below the programmed value on the
ISET pin.
Additionally, device thermal shutdown turns off the linear regulator when the IC junction temperature exceeds the
TSHUT threshold. The charger resumes operation when the IC die temperature decreases below the TSHUT falling
threshold.
7.4 Device Functional Modes
7.4.1 Shutdown or Undervoltage Lockout (UVLO)
The device is in the shutdown state if the IN pin voltage is less than VIN_LOWV. The internal circuitry is powered
down, all the pins are high impedance, and the device draws from the input supply. Once the IN voltage rises
above the VIN_LOW threshold, the IC will enter Sleep Mode or Active Mode depending on the OUT pin voltage.
7.4.2 Sleep Mode
The device is in Sleep Mode when VIN_LOWV < VIN < VOUT + VSLEEPZ. The device waits for the input voltage to
rise above VOUT + VSLEEPZ to start operation.
7.4.3 Active Mode
The device is powered up and charges the supercapacitor when the CE pin is LOW and the IN voltage ramps
above both VIN_LOWV, and VOUT + VSLEEPZ. The device draws IQ_IN from the supply to bias the internal circuitry.
For details on the device power-up sequence, refer to 节7.3.1.
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7.4.3.1 Standby Mode
The device is in Standby Mode if a valid input supply is present and a recoverable fault is detected. The internal
circuitry is partially biased, and the device continues to monitor for the recoverable fault to be removed.
7.4.4 Fault Mode
The fault conditions are categorized into recoverable and nonrecoverable as follows:
• Recoverable, from which the device should automatically recover once the fault condition is removed:
– VIN OVP
• Nonrecoverable, requiring pin or input supply toggle to resume operation:
– OUT OCP
– ISET pin short detected
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
A typical application consists of the device configured as a standalone charger for a 1- to 4-cell supercapacitor.
The regulation voltage, VREG, is configured using a resistor divider between the OUT and FB pins. The charge
current is configured using a pulldown resistor on the ISET pin. Pulling the CE pin above VIH disables the
charging function. Charger and input supply status are reported with the STAT and PG pins.
8.2 Typical Applications
8.2.1 1s Supercapacitor Charger Design Example
1s supercapacitor
2.4V
VIN
IN
OUT
FB
604kΩ
301kΩ
VREF
10kΩ
VREF
1µF
STAT
ISET
GND
10kΩ
1µF
375Ω
/PG
/CE
HOST
BQ25173
图8-1. BQ25173 1s Supercapacitor Application Diagram
8.2.1.1 Design Requirements
• Supply voltage is 5 V to 18 V
• Fast charge current: ICHG = 800 mA
• Regulation voltage: VREG = 2.4 V
• CE is an open-drain control pin
• PG pin is used as the GND connection in the feedback divider to minimize supercapacitor current leakage
8.2.1.2 Detailed Design Procedure
• With RFBT = 604 kΩ, calculate RFBB so VREG = 2.4 V using 方程式2
• RISET = [KISET / ICHG] from electrical characteristics table.
– KISET = 300 AΩ
– RISET = [300 AΩ/0.8 A] = 375 Ω
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8.2.1.3 Application Curves
CIN = 1 µF, COUT = 1 µF, CSC = 25 F, VIN = 5 V (unless otherwise specified)
ICHG = 400 mA
ICHG = 400 mA
图8-2. Power Up with Supercapacitor
图8-3. Power Down with Supercapacitor
/CE pulled high
ICHG = 250 mA
/CE pulled low
ICHG = 400 mA
图8-4. Charge Disable
图8-5. Charge Enable
VOUT = 3.5 V
ICHG = 250 mA
VIN = 4 V →6 V
ICHG = 400 mA
VIN = 5 V →20 V
图8-7. IN Transient Response
图8-6. IN OVP Response
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VOUT = 4.2 V
ICHG = 250 mA
ICHG = 250 mA
ISYS = 0 mA →500
mA →0 mA
VOUT = 4.0 V →0 V
图8-9. OUT Short-Circuit Response
图8-8. OUT Transient Response
ISET = 1.2 kΩ→0 Ω
ISET = 50 mA →500 mA
图8-10. ISET Short-Circuit Response
图8-11. ISET Change Response
VREG = 2.5 V
ICHG = 400 mA
图8-12. Charge Complete
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8.2.2 4s Supercapacitor Charger Design Example
4s supercapacitor
2.2V / cap
VIN
IN
OUT
VREF
10kΩ
806kΩ
1µF
80.6kΩ
VREF
STAT
ISET
GND
FB
/CE
/PG
1µF
600Ω
HOST
10kΩ
BQ25173
图8-13. BQ25173 4s Supercapacitor Application Diagram
8.2.2.1 Design Requirements
The design requirements include the following:
• Supply voltage is 9 V to 18 V
• Fast charge current: ICHG = 500 mA
• Regulation voltage: VREG = 8.8 V
• CE is a control pin, pull high to disable the charger
8.2.2.2 Application Curves
For application curves, refer to 节8.2.1.3.
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 3.0 V and 18 V (up to 40 V
tolerant) and current capability of at least the maximum designed charge current. If located more than a few
inches from the IN and GND pins, a larger capacitor is recommended.
10 Layout
10.1 Layout Guidelines
To obtain optimal performance, the decoupling capacitor from IN to GND and the output filter capacitor from OUT
to GND should be placed as close as possible to the device, with short trace runs to both IN, OUT, and GND.
• All low-current GND connections should be kept separate from the high-current charge or discharge paths
from the supercapacitor. Use a single-point ground technique incorporating both the small signal ground path
and the power ground path.
• The high-current charge paths into the IN pin and from the OUT pin must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces.
10.2 Layout Example
IN
GND
OUT
FB
IN
OUT
FB
ISET
/CE
0402
0402
/PG
0402
STAT
GND
图10-1. BQ25173 Board Layout Example
10.3 Thermal Package
The most common measure of package thermal performance is thermal impedance (θJA) measured (or
modeled) from the chip junction to the air surrounding the package surface (ambient). The mathematical
expression for θJA is:
θJA = (TJ –T) / P
(3)
Where:
TJ = chip junction temperature
T = ambient temperature
P = device power dissipation
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Factors that can influence the measurement and calculation of θJA include:
• Whether or not the device is board mounted
• Trace size, composition, thickness, and geometry
• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested
Due to the charge profile of supercapacitors, maximum power dissipation is typically seen at the beginning of the
charge cycle when the voltage is at its lowest.
Device power dissipation, P, is a function of the charge rate and the voltage drop across the internal PowerFET.
P can be calculated from the following equation during charging:
P = [V(IN) –V(OUT)] × I(OUT)
(4)
The thermal loop feature reduces the charge current to limit excessive IC junction temperature. It is
recommended that the design not run in thermal regulation for typical operating conditions (nominal input voltage
and nominal ambient temperatures) and use the feature for nontypical situations such as hot environments or
higher than normal input source voltage. With that said, the IC will still perform as described, if the thermal loop
is always active.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25173DSGR
ACTIVE
WSON
DSG
8
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
B173
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
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PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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