BQ25570_14_技术文档

bq25570

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SLUSBH2C –MARCH 2013–REVISED JANUARY 2014

Ultra Low Power Harvester Power Management IC with Boost Charger, and Nano-Powered

Buck Converter

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1

FEATURES

•

Ultra Low Power DC/DC Boost Charger

•

Programmable Step Down Regulated Output

(Buck)

–

Cold-start Voltage: VIN ≥ 330 mV

–

High Efficiency up to 93%

Continuous Energy Harvesting From VIN as

low as 100 mV

Supports Peak Output Current up to 110

mA (typical)

–

Input Voltage Regulation Prevents

Collapsing High Impedance Input Sources

Programmable Maximum Power Point Tracking

(MPPT)

Full Operating Quiescent Current of 488 nA

(typical)

–

Provides Optimal Energy Extraction From a

Variety of Energy Harvesters including

Solar Panels, Thermal and Piezo Electric

Generators

Ship Mode with < 5 nA From Battery

•

Energy Storage

–

Energy can be Stored to Re-chargeable Li-

ion Batteries, Thin-film Batteries, Super-

capacitors, or Conventional Capacitors

APPLICATIONS

•

Energy Harvesting

•

Battery Charging and Protection

Solar Charger

–

Internally Set Undervoltage Level

Thermal Electric Generator (TEG) Harvesting

Wireless Sensor Networks (WSN)

Low Power Wireless Monitoring

Environmental Monitoring

User Programmable Overvoltage Levels

Battery Good Output Flag

–

Programmable Threshold and Hysteresis

Warn Attached Microcontrollers of Pending

Loss of Power

Bridge and Structural Health Monitoring (SHM)

Smart Building Controls

–

Can be Used to Enable or Disable System

Loads

Portable and Wearable Health Devices

Entertainment System Remote Controls

DESCRIPTION

The bq25570 is a highly integrated energy harvesting Nano-Power management solution that is well suited for

meeting the special needs of ultra low power applications. The product is specifically designed to efficiently

acquire and manage the microwatts (µW) to milliwatts (mW) of power generated from a variety of DC sources

like photovoltaic (solar) or thermal electric generators. The bq25570 is the first device of its kind to implement a

highly efficient boost charger with a nano-powered buck converter targeted toward products and systems, such

as wireless sensor networks (WSN) which have stringent power and operational demands. The design of the

bq25570 starts with a dc/dc boost converter/charger that requires only microwatts of power to begin operating.

Once started, the boost charger can effectively extract power from low voltage output harvesters such as

thermoelectric generators (TEGs) or single or dual cell solar panels. The boost charger can be started with VIN

as low as 330 mV, and once started, can continue to harvest energy down to VIN = 100 mV.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq25570

SLUSBH2C –MARCH 2013–REVISED JANUARY 2014

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION CONTINUED

The bq25570 also implements a programmable maximum power point tracking sampling network to optimize the

transfer of power into the device. The fraction of open circuit voltage that is sampled and held can be controlled

by pulling VOC_SAMP high or low (80% or 50% respectively) or by using external resistors. This sampled

voltage is maintained via internal sampling circuitry and held with an external capacitor (CREF) on the

VREF_SAMP pin. For example, solar cells typically operate with a maximum power point (MPP) of 80% of their

open circuit voltage. Connecting VOC_SAMP to VSTOR sets the MPPT threshold to 80% and results in the IC

regulating the voltage on the solar cell to ensure that the VIN_DC voltage does not fail below the voltage on

CREF which equals 80% of the solar panel's open circuit voltage. Alternatively, an external reference voltage can

be provided by a MCU to produce a more complex MPPT algorithm. In addition to the boost charging front end,

the bq25570 provides the system with an externally programmable regulated supply via the buck converter. The

regulated output has been optimized to provide high efficiency across low output currents (< 10 µA) to high

currents (~110 mA).

The bq25570 is designed with the flexibility to support a variety of energy storage elements. The availability of

the sources from which harvesters extract their energy can often be sporadic or time-varying. Systems will

typically need some type of energy storage element, such as a re-chargeable battery, super capacitor, or

conventional capacitor. The storage element will make certain constant power is available when needed for the

systems. The storage element also allows the system to handle any peak currents that can not directly come

from the input source.

To prevent damage to a customer’s storage element, both maximum and minimum voltages are monitored

against the internally set under-voltage (UV) and user programmable over-voltage (OV) levels.

To further assist users in the strict management of their energy budgets, the bq25570 toggles the battery good

(VBAT_OK) flag to signal an attached microprocessor when the voltage on an energy storage battery or

capacitor has dropped below a pre-set critical level. This should trigger the reduction of load currents to prevent

the system from entering an under voltage condition. There is also independent enable signals to allow the

system to control when to run the regulated output or even put the whole IC into an ultra-low quiescent current

sleep state.

All the capabilities of bq25570 are packed into a small foot-print 20-lead 3.5mm x 3.5 mm QFN package (RGR).

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SLUSBH2C –MARCH 2013–REVISED JANUARY 2014

TYPICAL APPLICATION SCHEMATIC

CSTOR

CBYP

+

BAT

VSTOR

VBAT

VOC_SAMP

L1

LBOOST

CIN

VREF_SAMP

L2

LBUCK

Boost

+

Solar

Controller

VOUT

System

Load

Cell

CREF

VBAT

COUT

-

VSS

Buck

Controller

MPPT

VIN_DC

VSS

Cold Start

VSTOR

Nano-Power

Management

Host

GPIO1

EN

GPIO2

GPIO3

VOUT_EN

VBAT_OK

bq25570

R_OUT2

R_OV2

R_OK3

R_OK2

R_OV1

R_OUT1

R_OK1

ORDERING INFORMATION

ORDERING NUMBER

(TAPE AND REEL)⁽¹⁾

PACKAGE

MARKING

PART NO.

PACKAGE

QUANTITY

bq25570RGRR

bq25570RGRT

B5570

3000

250

bq25570

QFN RGR

(1) The RGR package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel, T suffix for 250 parts per reel.

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

MIN

UNIT

MAX

VIN_DC, VOC_SAMP, VREF_SAMP, VBAT_OV, VRDIV, OK_HYST,

Input voltage

OK_PROG, VBAT_OK, VBAT, VSTOR, LBOOST, EN, VOUT_EN,

–0.3

5.5

V

VOUT_SET, LBUCK, VOUT⁽²⁾

Peak Input Power, PIN_PK

510

125

150

mW

°C

Operating junction temperature range, T_J

Storage temperature range, T_STG

–40

–65

°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS/ground terminal.

THERMAL INFORMATION

bq25570

THERMAL METRIC⁽¹⁾⁽²⁾

UNITS

RGR (20 PINS)

θ_JA

Junction-to-ambient thermal resistance

34.6

49.0

12.5

0.5

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

12.6

1.0

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

spacing

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX

5.1

UNIT

V

VIN(DC)

VBAT, VOUT

CIN

DC input voltage into VIN_DC⁽¹⁾

Voltage range⁽²⁾

0.1

2

5.5

V

Capacitance on VIN_DC pin

Capacitance on VSTOR pin

Capacitance on VOUT pin

4.7

µF

CSTOR

COUT

10

22

Capacitance or battery with at least the same equivalent capacitance on

VBAT pin

CBAT

100

µF

CREF

Capacitance on VREF_SAMP that stores the samped VIN reference

Total resistance for setting for MPPT reference if needed

Total resistance for setting VBAT_OK threshold voltage.

Total resistance for setting VOUT threshold voltage.

Total resistance for setting VBAT_OV voltage.

Inductance on LBOOST pin

9

18

10

20

13

11

22

15

nF

MΩ

µH

°C

R_OC1+ R_OC2

R_{OK 1}+ R_{OK 2}+ R_OK3

11

R_OUT1+ R_OUT2

11

R_OV1+ R_OV2

11

L1

L2

T_A

T_J

22

Inductance on LBUCK pin

4.7

–40

10

Operating free air ambient temperature

85

Operating junction temperature

105

°C

(1) Maximum input power ≤ 400 mW. Cold start has been completed

(2) VBAT_OV setting must be higher than VIN_DC

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ELECTRICAL CHARACTERISTICS

Over recommended temperature range, typical values are at T_A= 25°C. Unless otherwise noted, specifications apply for

conditions of VSTOR = 4.2 V, VOUT = 1.8 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR = 4.7 µF, L2 = 10 µH,

COUT = 22 µF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BOOST CHARGER

VIN(DC)

DC input voltage into VIN_DC

Cold-start completed

100

5100

285

mV

mA

0.5V < V_IN< 4.0 V; VSTOR

= 4.2 V

I-CHG(CBC_LIM)

Cycle-by-cycle current limit of charger

230

VBAT_OV > VSTOR >

VSTOR_CHGEN

Input power range for normal charging

0.005

1.6

510 mW

Minimum input voltage for cold start

circuit to start charging VSTOR

VBAT < VBAT_UV; VSTOR

= 0 V; 0°C < T_A< 85°C

VIN(CS)

330

400

1.9

mV

V

Voltage on VSTOR when cold start

operation ends and normal charger

operation commences

VSTOR_CHGEN

PIN(CS)

1.73

Minimum cold-start input power for

VSTOR to reach VSTOR_(CHGEN)and

allow normal charging to commence

VSTOR < VSTOR_(CHGEN)

5

µW

ms

Time for which switch between VSTOR

and VBAT closes when battery is hot

plugged into VBAT

Battery resistance = 300

Ω, Battery voltage = 3.3V

t_{BAT_HOT_PLUG}

50

QUIESCENT CURRENTS

VIN_DC = 0V; VSTOR =

2.1V; T_J= 25°C

488

445

1

700

900

615

815

5

EN = 0, VOUT_EN = 1 - Full operating

mode

VIN_DC = 0V; VSTOR =

2.1V; –40°C < T_J< 85°C

VIN_DC = 0V; VSTOR =

2.1V; T_J= 25°C

EN = 0, VOUT_EN = 0 - Partial standby

mode

I_Q

nA

VIN_DC = 0V; VSTOR =

2.1V; –40°C < T_J< 85°C

VBAT = 2.1 V; T_J= 25°C;

VSTOR = VIN_DC = 0 V

EN = 1, VOUT_EN = x - Ship mode

VBAT = 2.1 V; –40°C < T_J

< 85°C; VSTOR = VIN_DC

= 0 V

30

MOSFET RESISTANCES

ON resistance of switch between VBAT

R_DS(ON)-BAT

VBAT = 4.2 V

0.95

1.50

Ω

and VSTOR

Charger low side switch ON resistance

Charger high side switch ON resistance

Charger low side switch ON resistance

Charger high side switch ON resistance

Buck low side switch ON resistance

Buck high side switch ON resistance

Buck low side switch ON resistance

Buck high side switch ON resistance

Maximum charger switching frequency

Maximum buck switching frequency

0.70

2.30

0.80

3.70

0.80

1.60

1.00

2.40

1

0.90

3.00

1.00

4.80

1.00

2.00

1.20

2.90

R_{DS(ON)_CHG}

VBAT = 2.1 V

VBAT = 4.2 V

VBAT = 2.1 V

R_{DS(ON)_BUCK}

Ω

f_{SW_CHG}

MHz

kHz

f_{SW_BUCK}

500

Junction temperature when charging is

discontinued

VBAT_OV > VSTOR >

1.8V

T_{TEMP_SD}

125

C

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ELECTRICAL CHARACTERISTICS (continued)

Over recommended temperature range, typical values are at T_A= 25°C. Unless otherwise noted, specifications apply for

conditions of VSTOR = 4.2 V, VOUT = 1.8 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR = 4.7 µF, L2 = 10 µH,

COUT = 22 µF

PARAMETER

BATTERY MANAGEMENT

TEST CONDITIONS

MIN

TYP

MAX UNIT

Programmable voltage range for

overvoltage threshold

VBAT_OV

VBAT increasing

2.2

5.5

55

V

Battery over-voltage hysteresis (internal)

VBAT decreasing;

VBAT_OV = 5.25V

VBAT_OV_HYST

VDELTA

24

mV

VBAT_OV - VIN(DC)

Main boost charger on;

MPPT not sampling VOC

400

VBAT_UV

Under-voltage threshold

VBAT decreasing

1.91

1.95

15

2.0

32

V

VBAT_UV_HYST

VBAT_OK_HYST

Battery under-voltage hysteresis (internal) VBAT increasing

mV

Programmable voltage range of digital

signal indicating VSTOR (=VBAT) is OK

VBAT increasing

VBAT_UV

-2

VBAT_OV

V

mV

%

Programmable voltage range of digital

signal indicating VSTOR (=VBAT) is OK

VBAT_OK

_HYST –

50

VBAT_OK_PROG

VBAT_ACCURACY

VBAT decreasing

Overall Accuracy for threshold values

VBAT_OV, VBAT_OK

Selected resistors are 0.1%

tolerance

2

VBAT_OK (High) threshold voltage

VSTOR –

200

VBAT_OK(H)

VBAT_OK(L)

Load = 10 µA

mV

VBAT_OK (Low) threshold voltage

100

ENABLE THRESHOLDS

Voltage for EN high setting. Relative to

VBAT.

VBAT –

0.2

EN(H)

VBAT = 4.2V

VSTOR = 4.2V

V

EN(L)

Voltage for EN low setting

Voltage for VOUT_EN High setting.

0.3

VSTOR –

0.4

VOUT_EN(H)

VOUT_EN(L)

Voltage for VOUT_EN Low setting.

BIAS and MPPT CONTROL STAGE

VOC_SAMPLE

Time period between two MPPT samples

16

s

Settling time for MPPT sample

measurement of VIN_DC open circuit

voltage

VOC_STLG

Device not switching

256

ms

0.5 V < VIN < 4 V; IIN(DC)

= 10 mA

VIN_REG

MPPT_80

Regulation of VIN_DC during charging

10%

Voltage on VOC_SAMP to set MPPT

threshold to 0.80 of open circuit voltage of

VIN_DC

VSTOR –

0.015

V

Voltage on VOC_SAMP to set MPPT

threshold to 0.50 of open circuit voltage of

VIN_DC

MPPT_50

VBIAS

15

mV

V

Internal reference for the programmable

voltage thresholds

VSTOR ≥ VSTOR_CHGEN

1.205

1.21

1.217

6

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ELECTRICAL CHARACTERISTICS

Over recommended ambient temperature range, typical values are at T_A= 25°C. Unless otherwise noted, specifications apply

for conditions of VSTOR = 4.2 V, V_OUT= 1.8 V. External components, C_IN= 4.7 µF, L1 = 22 µH, CSTOR = 4.7 µF, L2 = 10

µH, C_OUT= 22 µF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BUCK CONVERTER

I_OUT= 10 mA;

1.3 V < V_OUT< 3.3 V

Output regulation (excluding resistor tolerance

error)

–2

2

%

I_OUT= 10 mA;

Output line regulation

0.09

%/V

VSTOR = 2.1 V to 5.5 V,

C_OUT= 22 µF

I_OUT= 100 µA to 95 mA,

VSTOR = 3.6 V, C_OUT= 22

µF

VOUT

Output load regulation

Output ripple

-0.01

30

%/mA

mVpp

VSTOR = 4.2V, I_OUT= 1 mA,

C_OUT= 22 μF

VSTOR –

Programmable voltage range for output voltage

threshold

1.3

93

V

(1)

0.2

IOUT

Output Current

VSTOR = 3.3V; V_OUT= 1.8 V

C_OUT= 22 µF

110

250

mA

μs

Startup time with EN low and VOUT_EN transition

to high (Standby Mode)

t_START-STBY

Startup time with VOUT_EN high and EN

transition from high to low (Ship Mode)

t_START-SHIP

C_OUT= 22 µF

100

185

ms

2.4 V < VSTOR < 5.5 V;

1.3 V < V_OUT< 3.3 V

I-BUCK(CBC-LIM)

Cycle-by-cycle current limit of buck converter

160

205

mA

(1) The dropout voltage can be computed as the maximum output current times the buck high side resistance.

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DEVICE INFORMATION

RGT PACKAGE

(TOP VIEW)

20

19

18

17

16

1

2

3

4

5

15

14

13

12

11

VSS

VIN_DC

VOC_SAMP

VREF_SAMP

EN

VOUT

bq25570

RGR

3.5x3.5mm

VBAT_OK

VOUT_SET

OK_PROG

6

7

8

9

10

Figure 1. bq25570 3.5mm x 3.5mm QFN-20 Package

PIN FUNCTIONS

NAME

I/O TYPE

DESCRIPTION

NO.

1

VSS

Input

Power ground for the boost charger.

2

VIN_DC

DC voltage input from energy harvesting source. Connect at least a 4.7 µF capacitor as

close as possible between this pin and pin 1.

3

VOC_SAMP

Input

Sampling pin for MPPT network. Connect to VSTOR to sample at 80% of input source

open circuit voltage. Connect to GND for 50% or connect to the mid-point of external

resistor divider between VIN_DC and GND.

Sample and hold circuit output for the reference set by the MPPT per VOC_SAMP.

Connect a 0.01 µF capacitor from this pin to GND.

4

5

VREF_SAMP

EN

Input

Iinput

Active low digital programming input for enabling/disabling the IC. Connect to GND to

enable the IC.

6

7

VOUT_EN

VBAT_OV

Input

Active high digital programming input for enabling/disabling the buck converter. Connect to

VSTOR to enable the buck converter.

Connect to the mid-point of external resistor divider between VRDIV and GND for setting

the VBAT overvoltage threshold.

8

9

VRDIV

NC

Output

Input

Connect high side of resistor divider networks to this biasing voltage.

Connect to ground using the IC's PowerPad.

10

OK_HYST

Input

Connect to the mid-point of external resistor divider between VRDIV and GND for setting

the VBAT_OK hystersis threshold.

11

12

OK_PROG

VOUT_SET

Input

Connect to the mid-point of external resistor divider between VRDIV and GND for setting

the VBAT_OK threshold.

Connect to the mid-point of external resistor divider between VRDIV and GND for setting

the VOUT regulation set point.

13

14

VBAT_OK

VOUT

Output

Digital output for battery good indicator. Internally referenced to the VSTOR voltage.

Buck converter output. Connect at least 22 µF output capacitor between this pin and pin 15

(VSS).

15

16

VSS

Supply

I/O

Power ground for the buck converter and analog/signal ground for the resistor dividers and

VREF_SAMP capacitor.

LBUCK

Inductor connection for the buck converter switching node. Connect at least a 4.7 µH

inductor between this pin and pin 14 (VOUT).

8

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PIN FUNCTIONS (continued)

NAME

I/O TYPE

DESCRIPTION

NO.

17

NC

Input

I/O

Connect to ground using the IC's PowerPad.

18

VBAT

Connect a rechargeable storage element with at least 100uF of equivalent capacitance

between this pin and either VSS pin.

19

20

VSTOR

Output

I/O

Connection for the output of the boost charger. Connect at least a 4.7 µF capacitor in

parallel with a 0.1 µF capacitor as close as possible to between this pin and pin 1 (VSS).

LBOOST

Inductor connection for the boost charger switching node. Connect a 22 µH inductor

between this pin and pin 2 (VIN_DC).

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TYPICAL APPLICATION CIRCUITS

VBAT_OV = 3.11 V, VBAT_OK = 2.39 V, VBAT_OK_HYST = 2.80 V, VOUT=1.80V, MPPT (V_OC) = 80%

L1 = 22 µH, L2 = 10 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF, COUT = 22 µF

R_OK1= 5.62 MΩ, R_OK2= 5.49 MΩ, R_OK3= 1.87 MΩ, R_OV1= 7.5 MΩ, R_OV2= 5.36 MΩ,

R_OUT1= 8.66 MΩ, R_OUT2= 4.22 MΩ

CSTOR

CBYP

+

BAT

VSTOR

VBAT

VOC_SAMP

LBOOST

L1

CIN

VREF_SAMP

L2

LBUCK

Boost

+

-

Solar

Cell

Controller

VOUT

System

Load

CREF

VBAT

COUT

VSS

Buck

Controller

MPPT

VIN_DC

VSS

Cold Start

VSTOR

Nano-Power

Management

Host

GPIO1

EN

GPIO2

GPIO3

VOUT_EN

VBAT_OK

bq25570

R_OUT2

R_OV2

R_OK3

R_OK2

R_OV1

R_OUT1

R_OK1

Figure 2. Typical Solar Application Circuit

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VBAT_OV = 4.18V, VBAT_OK = 3.5 V, VBAT_OK_HYST = 3.7 V, VOUT=2.5V, MPPT (V_OC) = 50%

L1 = 22 µH, L2 = 10 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF, COUT = 22 µF

R_OK1= 4.22 MΩ, R_OK2= 8.06 MΩ, R_OK3= 0.698 MΩ, R_OV1= 6.04 MΩ, R_OV2= 7.87 MΩ,

R_OUT1= 6.19 MΩ, R_OUT2= 6.65 MΩ

CBYP

CSTOR

+

BAT

VSTOR

VBAT

VOC_SAMP

LBOOST

L1

CIN

VREF_SAMP

L2

LBUCK

VOUT

Boost

Controller

System

Load

TEG

CREF

VSS

Buck

Controller

COUT

MPPT

VIN_DC

VSS

Cold Start

VSTOR

VBAT

Nano-Power

Management

Host

GPIO1

EN

GPIO2

GPIO3

VOUT_EN

VBAT_OK

bq25570

R_OV2

R_OK3

R_OUT2

R_OK2

R_OUT1

R_OV1

R_OK1

(1) See the Capacitor Selection section for guidance on sizing C_STOR

Figure 3. Typical TEG Application Circuit

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VBAT_OV = 3.31 V, VBAT_OK = 2.82 V, VBAT_OK_HYST = 3.12 V, VOUT = 1.30V, MPPT (V_OC) = 40%

L1 = 22 µH, L2 = 10 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF, COUT = 22 µF

R_OK1= 4.99 MΩ, R_OK2= 6.65 MΩ, R_OK3= 1.24 MΩ, R_OV1= 6.98 MΩ, R_OV2= 5.76 MΩ

R_OUT1= 12.1 MΩ, R_OUT2= 0.909 MΩ, R_OC1= 8.06 MΩ, R_OC2= 12 MΩ

CSTOR

CBYP

+

BAT

R_OC2

R_OC1

VSTOR

VBAT

VOC_SAMP

L1

MA4X79600LCT-ND

LBOOST

CIN

VREF_SAMP

L2

Vibration

Element

LBUCK

Boost

Controller

VOUT

System

Load

CREF

VSS

Buck

Controller

COUT

MA4X79600LCT-ND

MPPT

VIN_DC

VSS

Cold Start

VSTOR

VBAT

Nano-Power

Management

GPIO1

GPIO2

GPIO3

EN

Host

VOUT_EN

VBAT_OK

bq25570

R_OV2

R_OK3

R_OUT2

R_OK2

R_OUT1

R_OV1

R_OK1

(1) See the Capacitor Selection section for guidance on sizing C_STOR

Figure 4. Typical Externally Set MPPT Application Circuit

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VBAT_OV = 3.11 V, VBAT_OK = 2.39 V, VBAT_OK_HYST = 2.80 V, VOUT=1.80V, MPPT (V_OC) = 80%

L1 = 22 µH, L2 = 10 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF, COUT = 22 µF

R_OV1= 7.5 MΩ, R_OV2= 5.36 MΩ

R_OUT1= 8.66 MΩ, R_OUT2= 4.22 MΩ,

CSTOR

CBYP

+

BAT

VSTOR

VBAT

VOC_SAMP

LBOOST

L1

CIN

VREF_SAMP

L2

LBUCK

Boost

+

-

Solar

Cell

Controller

VOUT

System

Load

CREF

VBAT

COUT

VSS

Buck

Controller

MPPT

VIN_DC

VSS

Cold Start

VSTOR

Nano-Power

Management

Host

GPIO1

EN

GPIO2

GPIO3

VOUT_EN

VBAT_OK

bq25570

R_OUT2

R_OV2

VSTOR

R_OV1

R_OUT1

Figure 5. Typical VBAT_OK Disabled Application Circuit

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HIGH-LEVEL FUNCTIONAL BLOCK DIAGRAM

VSTOR

LBST

VBAT

LBUCK

VOUT

PFM Buck

Controller

VOUT_SET

PFM Boost Charger

Controller

VOUT_EN

VSS

Cold-start

Unit

Enable

VIN_DC

Interrupt

VBAT_OK

OK_PROG

VOC_SAMP

VREF_SAMP

BAT_SAVE

+

MPPT

Controller

+

Battery Threshold

Control

OT

VREF

OK

OK_HYST

Temp

Sensing

Element

Vref

Bias Reference &

Oscillator

VREF

VBAT_UV

VBAT_OV

VRDIV

EN

Figure 6. High-Level Functional Diagram

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TYPICAL CHARACTERISTICS

Table of Graphs

Unless otherwise noted, graphs were taken using Figure 2 with CIN = 4.7µF, L1 = Coilcraft 22µH LPS4018,

CSTOR = 4.7µF, L2 = Toko 10 µH DFE252012C, COUT = 22µF, VBAT_OV=4.2V, VOUT=1.8V

FIGURE

IN= 10 µA

Figure 7

Figure 8

vs. Input Voltage

vs. Input Current

IN= 100 µA

IIN = 10 mA

Figure 9

Charger Efficiency (η)⁽¹⁾

VIN = 2.0 V

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

VIN = 1.0 V

VIN = 0.5 V

VIN = 0.2 V

EN = 1, VOUT_EN = X (Ship Mode)

EN = 0, VOUT_EN = 0 (Standby Mode)

EN = 0, VOUT_EN = 1 (Active Mode)

vs. Output Current

vs. Input Voltage

VSTOR Quiescent Current

VBAT Quiescent Current

Buck Efficiency (η)

vs. VSTOR Voltage

vs. VBAT Voltage

vs. Output Current

vs. Input Voltage

Normalized Buck Output Voltage

vs. Temperature

Buck Maximum Output Current

vs. Input Voltage

VOUT = 1.8V - 100mV

Figure 22

vs. Output Current

vs. Input Voltage

vs.Output Current

vs. Input Voltage

Figure 23

Figure 24

Figure 25

Figure 26

Buck Major Switching Frequency

Buck Output Ripple

VBAT = 3.4-V charged Li coin cell; VIN_DC

= 1.0 V power supply; MPPT=50%; ZIN =

100Ω

Startup by taking EN low (from

ship mode)

ROUT = open

ROUT = 90 Ω

Figure 27

Figure 28

VBAT = 3.4-V charged Li coin cell; VIN_DC

= 1.0 V power supply; MPPT=50%; ZIN =

100Ω

Startup by taking EN low (from

ship mode), including VOUT

VBAT = 3.2-V charged Li coin cell; VIN_DC

= 2.0 V power supply; MPPT=50%; ZIN =

100Ω

Startup by taking VOUT_EN high

(from Standby mode)

Figure 29

Figure 30

Figure 31

VBAT = 3.2-V charged Li coin cell; VIN_DC VOC_SAMP = VSTOR to GND to

= 2.0 V power supply; ZIN = 100Ω

MPPT Operation

VSTOR

VBAT = 3.9-V charged 0.5F super cap;

100mA Load Transient on VOUT VIN_DC = 2.0 V power supply;

ROUT = open to 18 Ω to open

ROUT = open to 36 Ω to open

MPPT=50%; ZIN=100Ω

50mA Load Transient on VOUT

Figure 32

Figure 33

Charger Operational Waveform

during 50mA Load Transient

VBAT = 3.2-V charged Li coin cell; VIN_DC

= 2.0 V power supply; MPPT=50%; ZIN =

100Ω

ROUT = 36 Ω

Buck Operational Waveform

during 50mA Load Transient

Figure 34

VRDIV Waveform

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

VSTOR = 4.2V; VOUT = 1.8V

VRDIV Waveform - Zoom

VBAT_OK Operation

VSTOR ramped from 0 V to 4.2 V to 0 V

Charging a Super Cap on VBAT

Charging a Super Cap on VOUT

VBAT = 120 mF super capacitor

VOUT = 120 mF super capacitor

VIN_DC = sourcemeter with compliance =

1.2 V and ISC = 1.0 mA

(1) See SLUA691 for an explanation on how to take these measurements. Because the MPPT feature cannot be disabled on the bq25570,

these measurements need to be taken in the middle of the 16 s sampling period.

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100

90

100

90

80

70

60

50

40

30

20

10

0

I

= 10PA

IN

80

70

60

50

40

30

20

10

0

I

= 100 PA

IN

VSTOR = 2.0 V

VSTOR = 3.0 V

VSTOR = 5.5 V

VSTOR = 2.0 V

VSTOR = 3.0 V

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

3

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3

Input Voltage (V)

Figure 7. Charger Efficiency vs Input Voltage

Figure 8. Charger Efficiency vs Input Voltage

100

90

80

70

60

50

40

30

20

100.00

90.00

80.00

70.00

60.00

50.00

40.00

I

= 10 mA

V

= 2 V

IN

VSTOR = 2.0 V

VSTOR = 3.0 V

VSTOR = 5.5 V

VSTOR = 2.2 V

VSTOR = 3.0 V

VSTOR = 5.5 V

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

3

0.01

0.1

1

10

100

Input Voltage (V)

Input Current (mA)

Figure 9. Charger Efficiency vs Input Voltage

Figure 10. Charger Efficiency vs Input Current

100.00

90.00

80.00

70.00

60.00

50.00

40.00

30.00

20.00

100

90

80

70

60

50

40

30

20

V

= 0.5 V

IN

V

= 1 V

IN

VSTOR = 2.0 V

VSTOR = 3.0 V

VSTOR = 5.5 V

VSTOR = 1.8 V

VSTOR = 3.0 V

VSTOR = 5.5 V

0.01

0.1

1

Input Current (mA)

10

100

0.01

0.1

1

10

100

Input Current (mA)

Figure 11. Charger Efficiency vs Input Current

Figure 12. Charger Efficiency vs Input Current

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100

90

80

70

60

50

40

30

20

1600

1400

1200

1000

800

600

400

200

0

o

TA = 85C

T

= 85 C

A

o

V

= 0.2 V

TA = 25C

T

= 25 C

IN

A

o

A

C

= -40 C

A

VSTOR = 3.0 V

VSTOR = 2.0 V

VSTOR = 5.5 V

0.0

0.1

1.0

10.0

100.0

2

3

4

5

Input Current (mA)

Input Voltage (V)

Figure 13. Charger Efficiency vs Input Current

Figure 14. VSTOR Quiescent Current vs VSTOR Voltage:

Standby Mode

700

2000

1500

1000

500

0

o

TA = 85C

TA = 25^oC

T

= 85 C

T

= 25 C

A

600

500

400

300

200

100

0

= 25^oC

o

T

A

C

TA = 85C

T

= 85 C

A

= -40^oC

TA = -40^oCC

A

TA = -40C

A

T

2

3

4

5

2

3

4

5

Input Voltage (V)

Figure 15. VSTOR Quiescent Current vs VSTOR Voltage:

Active Mode

Figure 16. VBAT Quiescent Current vs VBAT Voltage: Ship

Mode

100

90

100

VOUT = 1.8V

95

80

90

85

VOUT = 1.8V, T = 25^oC

70

60

50

40

A

80

IOUT = 0.01mA

IOUT = 0.1mA

IOUT = 1mA

IOUT = 10mA

IOUT = 100mA

VSTOR = 2.1V

75

70

VSTOR = 3.6V

VSTOR = 5.5V

0.001

0.01

0.1

1

10

100

2.0

3.0

4.0

Input Voltage (V)

5.0

Output Current (mA)

Figure 17. Buck Efficiency vs Output Current

Figure 18. Buck Efficiency vs Input Voltage

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1.004

1.02

1.01

1

VOUT = 1.8V

1.002

VOUT = 1.8V

1

IOUT = 0.001mA

IOUT = 0.1mA

IOUT = 10mA

IOUT = 0.01mA

IOUT = 1mA

IOUT = 90mA

0.998

0.996

0.994

0.992

0.99

VSTOR = 5.5V

VSTOR = 3.6V

VSTOR = 2.1V

0.98

2.0

3.0

4.0

VSTOR Voltage (V)

5.0

0.001

0.01

0.1

1

10

100

Output Current (mA)

Figure 19. Normalized Buck Output Voltage vs Input Voltage

Figure 20. Normalized Buck Output Voltage vs Output

Current

1.02

170

IOUT = 0.01mA

o

TA = 85C

T

= 85 C

A

VOUT = 1.8V - 100 mV

160

150

140

130

120

110

100

90

VOUT = 1.8V

IOUT = 1mA

IOUT = 70mA

o

A

C

= 25 C

A

= 0^oC

1.01

1

A

C

o

T

= -40 C

TA = -40C

A

0.99

0.98

80

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80

Temperature (^oC)

2

3

4

5

VSTOR Voltage (V)

Figure 21. Normalized Buck Output Voltage vs Temperature

Figure 22. Buck Maximum Output Current vs Input Voltage

120

VOUT = 1.8V

100

80

100

80

IOUT = 0.5mA

IOUT = 5mA

IOUT = 100mA

IOUT = 50mA

60

40

20

0

40

VSTOR= 2.1V

VSTOR = 3V

VSTOR = 4.2V

VSTOR = 5.5V

20

0

10

20

30

40

50

60

70

80

90 100

2.1

2.6

3.1

3.6

4.1

4.6

5.1

Output Current (mA)

VSTOR Voltage (V)

Figure 23. Buck Major Switching Frequency vs Output

Current

Figure 24. Buck Major Switching Frequency vs Input

Voltage

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45

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

VOUT = 1.8V

VSTOR = 2.1V

VSTOR = 3V

VSTOR = 4.2V

VSTOR = 5.5V

IOUT = 0.5mA

IOUT = 5mA

IOUT = 50mA

IOUT = 100mA

0

10

20

30

40

50

60

70

80

90 100

2.1

2.6

3.1

3.6

4.1

4.6

5.1

Output Current (mA)

VSTOR Voltage (V)

Figure 25. Buck Output Voltage Ripple vs Output Current

Figure 26. Buck Output Voltage Ripple vs Input Voltage

Figure 27. Startup by taking EN low (from Ship mode)

Figure 28. Startup by taking EN low (from Ship mode),

including VOUT

Figure 29. Startup by taking VOUT_EN high (from Standby

mode)

Figure 30. MPPT Operation

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Figure 31. 100mA Load Transient on VOUT

Figure 32. 50 mA Load Transient on VOUT

Figure 33. Charger Operational Waveforms during 50mA

Load Transient

Figure 34. Buck Operational Waveforms during 50mA Load

Transient

Figure 35. VRDIV Waveform

Figure 36. VRDIV Waveform - Zoom

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Figure 37. VBAT_OK Operation

Figure 38. Charging a Super Cap on VBAT

Figure 39. Charging a Super Cap on VOUT

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DETAILED DESCRIPTION

Boost Charger Overview

The bq25570 includes both an ultra low quiescent current, efficient synchronous boost charger and buck

converter. The boost charger is intended to be powered from a high impedance DC source, such as a solar

panel, TEG or piezoelectric module; therefore, it regulates its input voltage (VIN_DC) in order to prevent the input

source from collapsing. The boost charger monitors its output voltage (VSTOR) and stops switching when

VSTOR reaches a resistor programmable threshold level. The buck converter is powered from VSTOR. Both

converters are based on a switching regulator architecture which maximizes efficiency while minimizing start-up

and operation power. Both use pulse frequency modulation (PFM) to maintain efficiency, even under light load

conditions. In addition, the boost charger implements battery protection features so that either rechargeable

batteries or capacitors can be used as energy storage elements at the storage element output (VBAT). Figure 6

is a high-level functional block diagram which highlights most of the major functional blocks inside the bq25570.

Enable Controls

There are two enable pins for the bq25570 in order to maximize the flexibility of control for the system. EN high

voltage is relative to VBAT. VOUT_EN high voltage is relative to VSTOR. When taken high (relative to VBAT),

the EN pin shuts down the IC completely including the boost charger, battery management circuitry and buck

converter. It also turns off the PFET that connects VBAT to VSTOR. This mode can be described as ship mode,

because it will put the IC in the lowest leakage state and provide a long storage period without discharging the

battery attached to VBAT. If it is not desired to control EN, it is recommended that this pin be tied to VSS, or

system ground. When EN is low, VOUT_EN is used to enable and disable the buck converter. The table below

summarizes the functionailty.

Table 1. Enable Functionality Table

EN PIN

LOGIC

LEVEL

VOUT_EN

PIN LOGIC

LEVEL

FUNCITONAL MODE

0

1

0

1

x

Buck standby mode. Boost charger and VBAT_OK are enabled. Buck converter is disabled.

Boost charger, buck converter and VBAT_OK enabled.

Ship mode. Boost charger, buck converter and VBAT_OK indication are disabled. (ship mode)

Startup Operation

The bq25570 has two circuits for boosting the input voltage, a low-power cold-start circuit, drawing power

excluxively from VIN_DC when ≥ VIN(CS), and the high efficiency main boost charger, with the bias rails drawing

power from VSTOR when ≥ VSTOR_CHGEN and the power stage drawing power from VIN_DC when ≥ VIN(DC)

minimum. When EN = 0 and VSTOR ≤ VSTOR_CHGEN, there are two options for charging the VSTOR

capacitor capacitor, CSTOR, to VSTOR_CHGEN for the main boost charger to turn on. The first option is to

allow the cold start circuit to charge VSTOR to VSTOR_CHGEN. Due to the body diode of the PFET connecting

VSTOR and VBAT, the cold start circuit must charge both the capacitor on CSTOR and the storage element

connected to VBAT up to VSTOR_CHGEN. When a rechargeable battery with an open protector is attached, the

charge time is typically short due to the minimum charge needed to close the FET. When large, discharged

super capacitors are attached, the charge time can be signficant. The second option is to connect a storage

element, charged above VSTOR_CHGEN, to VBAT. Assuming the voltages on VSTOR and VBAT are both

below 100mV, when a charged storage element is attached (i.e. hot-plugged) to VBAT, the IC turns on the

internal PFET between the VSTOR and VBAT pins for t_{BAT_HOT_PLUG}in order to charge CSTOR to

VSTOR_CHGEN. If a system load tied to VSTOR prevents the storage element from charging VSTOR within

t_{BAT_HOT_PLUG}, it is recommended to add an external PFET between the system load and VSTOR. An inverted

VBAT_OK signal can be used to drive the gate of this system-isolating PFET. Once the VSTOR pin voltage

reaches the internal under voltage threshold (VBAT_UV), the internal PFET stays on and the main boost charger

begins to charge the storage element if there is sufficient power available at the VIN_DC pin, as explained below.

If VSTOR does not reach VBAT_UV within 50ms, then the PFET turns off and the cold-start circuit turns on, also

as explained below.

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Boost Charger Cold-Start Operation (VSTOR < VSTOR_CHGEN and VIN_DC > VIN(CS) )

If the attached storage element does not charge CSTOR above VSTOR_CHGEN, VIN_DC ≥ VIN(CS) and EN =

0, the cold-start circuit turns on. The cold-start circuit is essentially an unregulated boost converter with lower

efficiency compared to the main boost charger. The energy harvester must supply sufficient power for the IC to

exit cold start. See the Energy Harvester Selection applications section for guidance.

When the CSTOR voltage reaches VSTOR_CHGEN, the main boost charger starts up. The VSTOR voltage from

the main boost charger is compared against the battery undervoltage threshold (VBAT_UV). When the VBAT_UV

threshold is reached, the PMOS switch between VSTOR and VBAT turns on, which allows the energy storage

element attached to VBAT to charge up. Cold start is not as efficient as the main boost charger. If there is not

sufficient input power available, the cold start circuit may run continuously and the VSTOR output may never

increase above VSTOR_CHGEN for the main boost charger to start up. The battery management thresholds are

explained later is this section. See the Energy Harvester Selection applications section for guidance on minimum

input power requirements.

Main Boost Charger Operation (VSTOR > VSTOR_CHGEN and VIN_DC > VIN(DC) )

The main boost charger charges the storage element attached at VBAT with the energy available from the high

impedance input source. For the first 32 ms (typical) after the boost charger is turned ON (assuming EN is low),

the charger is disabled to let the input rise to its open-circuit voltage. This is needed to obtain the reference

voltage which will be used for the remainder of the charger operation until the next MPPT sampling. The boost

charger employs pulse frequency modulation (PFM) mode of control to regulate the voltage at VIN_DC close to

the desired reference voltage. The reference voltage is set by the MPPT control scheme as described in the next

section. Input voltage regulation is obtained by transferring charge from the input to VSTOR only when the input

voltage is higher than the voltage on pin VREF_SAMP. The current through the inductor is controlled through

internal current sense circuitry. The peak current in the inductor is dithered internally to pre-determined levels in

order to maintain high efficiency of the charger across a wide input current range. The charger transfers up to a

maximum of 100 mA average input current (230mA typical peak inductor current). The boost charger is disabled

when the voltage on VSTOR reaches the OV condition to protect the battery connected at VBAT from

overcharging. In order for the battery to charge to VBAT_OV, the input power must exceed the power needed for

the load on VSTOR. See the Energy Harvester Selection applications section for guidance on minimum input

power requirements.

Maximum Power Point Tracking

Maximum power point tracking (MPPT) is implemented in order to maximize the power extracted from an energy

harvester source. The boost charger indirectly modulates the input impedance of the main boost charger by

regulating the charger's input voltage, as sensed by the VIN_DC pin, to the sampled reference voltage, as stored

on the VREF_SAMP pin. The MPPT circuit obtains a new reference voltage every 16 s (typical) by periodically

disabling the charger for 256 ms (typical) and sampling a fraction of the open-circuit voltage (VOC). For solar

harvesters, the maximum power point is typically 70%-80% and for thermoelectric harvesters, the MPPT is

typically 50%. Tying VOC_SAMP to VSTOR internally sets the MPPT regulation point to 80% of VOC. Tying

VOC_SAMP to GND internally sets the MPPT regulation point to 50% of VOC. If input source does not have

either 80% or 50% of VOC as its MPP point,, the exact ratio for MPPT can be optimized to meet the needs of the

input source being used by connecting external resistors R_OC1and R_OC2between VRDIV and GND with mid-

point at VOC_SAMP.

The reference voltage is set by the following expression:

æ

ç

è

ö

÷

ø

R_OC1

VREF_SAMP = VIN_DC(OpenCircuit)

R_OC1+ R_OC2

(1)

Storage Element / Battery Management

In this section the battery management functionality of the bq25570 integrated circuit (IC) is presented. The IC

has internal circuitry to manage the voltage across the storage element and to optimize the charging of the

storage element. For successfully extracting energy from the source, two different threshold voltages must be

programmed using external resistors, namely battery good threshold (VBAT_OK) and over voltage (OV)

threshold. The two user programmable threshold voltages and the internally set undervoltage threshold

determine the IC's region of operation. Figure 40 show plots of the voltage at the VSTOR pin and the various

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threshold voltages for two use cases 1) when a depleted battery is attached and the charger enters cold start

and 2) when a batttery charged above VBAT_UV is attached. For the best operation of the system, the

VBAT_OK should be used to determine when a load can be applied or removed. A detailed description of the

three voltage thresholds and the procedure for designing the external resistors for setting the three voltage

thresholds are described next.

5.5V

BOOST CONVERTER OFF

VBAT_OV

VSTOR=VBAT

MAIN BOOST

CONVERTER

ON

VBAT_OK_HYS

VBAT_OK

VBAT_UV

VBAT_OK

(VSTOR rising)

VSTOR

VSTOR_CHGEN

0V

V_DIODE

VBAT

COLD START ON

VIN_DC > 330mV

time

Figure 40. Charger Operation after a Depleted Storage Element is Attached

5.5V

BOOST CONVERTER OFF

VBAT_OV

VSTOR=VBAT

VBAT_OK_HYS

MAIN BOOST

CONVERTER

VBAT_OK

ON

VBAT_OK

VBAT_UV

(VSTOR rising)

0V

time

Attach Storage Element

Figure 41. Charger Operation after a Partially Charged Storage Element is Attached

When no input source is attached, the VSTOR node should be discharged to ground before attaching a storage

element. Hot-plugging a storage element that is charged (e.g., the battery protector is closed) and with the

VSTOR node above ground results in the PFET between VSTOR and VBAT remaining off until an input source

is attached. In addition, if a system load attached to VSTOR has fast transients that could pull VSTOR below

VBAT_UV, the internal PFET switch will turn off in order to recharge the CSTOR capacitor to VSTOR_CHGEN.

See the application section for guidance on sizing the VSTOR and/or VBAT capacitance to account for

transients. If the voltage applied at VIN_DC is greater than VSTOR or VBAT then current may flow until the

voltage at the input is reduced or the voltage at VSTOR and VBAT rise. This is considered an abnormal condition

and the boost charger does not operate.

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Battery Undervoltage Protection

To prevent rechargeable batteries from being deeply discharged and damaged, and to prevent completely

depleting charge from a capacitive storage element, the boost charger has an internally set undervoltage

(VBAT_UV) threshold plus an internal hysteresis voltage (VBAT_UV_HYST). The VBAT_UV threshold voltage

when the battery voltage is decreasing is internally set to 1.95V (typical). The undervoltage threshold when

battery voltage is increasing is given by VBAT_UV plus VBAT_UV_HYST. For most applications, the system load

should be connected to the VSTOR pin while the storage element should be connected to the VBAT pin. Once

the VSTOR pin voltage goes above the VBAT_UV_HYST threshold, the VSTOR pin and the VBAT pins are

shorted. The switch remains closed until the VSTOR pin voltage falls below VBAT_UV. The VBAT_UV threshold

should be considered a fail safe to the system and the system load should be removed or reduced based on the

VBAT_OK signal.

Battery Overvoltage Protection

To prevent rechargeable batteries from being exposed to excessive charging voltages and to prevent over

charging a capacitive storage element, the over-voltage (VBAT_OV) threshold level must be set using external

resistors. This is also the voltage value to which the charger will regulate the VSTOR/VBAT pin when the input

has sufficient power. The VBAT_OV threshold when the battery voltage is rising is given by Equation 2:

æ

ö

÷

ø

R_OV2

R_OV1

3

VBAT_OV = VBIAS 1 +

ç

2

è

(2)

The sum of the resistors is recommended to be no higher than 13 MΩ that is, R_OV1+ R_OV2= 13 MΩ. The

overvoltage threshold when battery voltage is decreasing is given by VBAT_OV_HYST. It is internally set to the

over voltage threshold minus an internal hysteresis voltage denoted by VBAT_OV_HYST. Once the voltage at

the battery exceeds VBAT_OV threshold, the boost charger is disabled. The charger will start again once the

battery voltage falls below the VBAT_OV_HYST level. When there is excessive input energy, the VBAT pin

voltage will ripple between the VBAT_OV and the VBAT_OV_HYST levels. SLUC484 provides help on sizing

and selecting the resistors.

CAUTION

If VIN_DC is higher than VSTOR and VSTOR is equal to VBAT_OV, the input VIN_DC

is pulled to ground through a small resistance to stop further charging of the attached

battery or capacitor. It is critical that if this case is expected, the impedance of the

source attached to VIN_DC be higher than 20 Ω and not a low impedance source.

Battery Voltage within Operating Range (VBAT_OK Output)

The charger allows the user to set a programmable voltage independent of the overvoltage and undervoltage

settings to indicate whether the VSTOR voltage (and therefore the VBAT voltage when the PFET between the

two pins is turned on) is at an acceptable level. When the battery voltage is decreasing the threshold is set by

Equation 3:

æ

ö

÷

ø

R_OK2

R_OK1

VBAT_OK_PROG = VBIAS 1 +

ç

è

(3)

When the battery voltage is increasing, the threshold is set by Equation 4:

æ

ö

÷

ø

R_OK2+ R_OK3

VBAT_OK_HYST = VBIAS 1 +

ç

R_OK1

è

(4)

The sum of the resistors is recommend to be no higher than approximately i.e., R_OK1+ R_OK2+ R_OK3= 13 MΩ. The

logic high level of this signal is equal to the VSTOR voltage and the logic low level is ground. The logic high level

has ~20 KΩ internally in series to limit the available current to prevent MCU damage until it is fully powered. The

VBAT_OK_PROG threshold must be greater than or equal to the UV threshold. For the best operation of the

system, the VBAT_OK should be setup to drive an external PFET between VSTOR and the system load in order

to determine when the load can be applied or removed to optimize the storage element capacity. SLUC484

provides help on sizing and selecting the resistors.

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Step Down (Buck) Converter Operation

The buck regulator takes input power from VSTOR, steps it down and provides a regulated voltage at the OUT

pin. It employs pulse frequency modulation (PFM) control to regulate the voltage close to the desired reference

voltage. The reference voltage is set by the user programmed resistor divider. The current through the inductor is

controlled through internal current sense circuitry. The peak current in the inductor is controlled to maintain high

efficiency of the converter across a wide input current range. The converter delivers an output current up to

110mA typical with a peak inductor current of 200 mA. The buck regulator is disabled when the voltage on

VSTOR drops below the VBAT_UV condition. The buck regulator continues to operate in pass (100% duty cycle)

mode, passing the input voltage to the output, as long as VSTOR is greater than VBAT_UV and less than VOUT.

Programming OUT Regulation Voltage

To set the proper output regulation voltage and input voltage power good comparator, the external resistors must

be carefully selected.

The OUT regulation voltage is then given by Equation 5:

æ

ç

è

ö

÷

ø

R_OUT2+ R_OUT1

VOUT = VBIAS

R_OUT1

(5)

Note that VBIAS is nominally 1.21V per the electrical specification table. The sum of the resistors is

recommended to be no greater than 13 MΩ , that is, R_OUT1+ R_OUT2= 13 MΩ. Higher resistors may result in poor

output voltage regulation and/or input voltage power good threshold accuracies due to noise pickup via the high

impedance pins or reduction of effective resistance due to parasitic resistances created from board assembly

residue. See Layout Considerations section for more details. SLUC484 provides help on sizing and selecting the

resistors.

Buck Converter Startup Behavior

The bq25570 buck converter has two startup responses: 1) from the ship-mode state (EN transitions from high to

low), and 2) from the standby state (VOUT_EN transitions from low to high). The first startup response out of the

ship-mode state has the longest time duration due to the internal circuitry being disabled. This response is shown

in Figure 28. The startup time takes approximately 100ms due to the internal Nano-Power management circuitry

needing to first, complete the 64 ms sample and hold cycle.

Startup from the standby state is shown in Figure 29. This response is much faster due to the internal circuitry

being pre-enabled. The startup time from this state is entirely dependent on the size of the output capacitor. The

larger the capacitor, the longer it will take to charge during startup. With COUT = 22 µF, the startup time is

approximately 400 µs. The buck converter can startup into a pre-biased output voltage.

Steady State Operation and Cycle by Cycle Behavior

Steady state operation for the boost charger is shown in Figure 33 and for the buck converter in

Figure 34. These plots highlight the inductor current waveform, the VSTOR and VOUT voltage ripple, and the

LBOOST and LBUCK switching nodes, respectively. Both use hysteretic control and pulse frequency modulation

(PFM) switching in order to maintain high efficiency at light load. As long as the VIN_DC voltage is above the

MPPT regulation set point (i.e. voltage at VREF_SAMP), the boost charger's low-side power FET turns on and

draws current until it reaches its respective peak current limit. These switching bursts continue until VSTOR

reaches the VBAT_OV threshold. The buck converter high-side power FET also turns on and draws current until

it reaches its respective peak current limit, with its switching bursts continuing until VOUT reaches the

VOUT_SET point. This cycle-by-cycle minor switching frequency is a function of each converter's inductor value,

peak current limit and voltage levels on each side of each inductor.

Once each respective capacitor, CSTOR for the boost and COUT for the buck, droops below a minimum value,

the hysteretic switching repeats. The DC voltages on CSTOR and COUT have a ripple voltage riding on top,

caused by each capacitor charging due to the switching bursts and then discharging to a minimum value. The

major frequency and duty cycle of CSTOR's ripple are a function of the VIN_DC regulation, VSTOR system load

and/or VBAT charging current, L1 inductance value and CSTOR capacitance value. The major frequency and

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duty cycle of COUT's ripple are a function of the VSTOR voltage, VOUT system load, L2 inductance value and

COUT capacitance value. At heavier output loads (larger output current), the time the converter is off is smaller

when compared to light load conditions. Figure 23 and Figure 24 show the major switching frequency versus load

current and VSTOR voltage, respectively, for the buck converter. Figure 25 and Figure 26 show the output

voltage ripple with COUT = 22 µF versus load current and VSTOR voltage, respectively, for the buck converter.

Nano-Power Management and Efficiency

The high efficiency of the bq25570 boost charger and buck converter is achieved via the proprietary Nano-Power

management circuitry and algorithm. This feature essentially samples and holds all references in order to reduce

the average quiescent current. That is, the internal circuitry is only active for a short period of time and then off

for the remaining period of time at the lowest feasible duty cycle. A portion of this feature can be observed in

Figure 35 where the VRDIV node is monitored. Here the VRDIV node provides a connection to the VSTOR

voltage (first pulse) and then generates the reference levels for the VBAT_OV, VBAT_OK and VOUT_SET

resistor dividers for a short period of time. The divided down values at each pin are sampled and held for

comparison against VBIAS as part of the hysteretic control. Since this biases a resistor string, the current

through these resistors is only active when the Nano-Power management circuitry makes the connection—hence

reducing the overall quiescent current due to the resistors. This process repeats every 64 ms.

The bq25570's boost charger efficiency is shown for various input power levels in Figure 7 through Figure 13.

The bq25570's buck converter efficiency versus output current is plotted in Figure 17 and versus input voltage in

Figure 18. All data points were captured by averaging the overall input current. This must be done due to the

periodic biasing scheme implemented via the Nano-Power management circuitry. In order to properly measure

the resulting input current when calculating the output to input efficiency, the input current efficiency data was

gathered using a source meter set to average over at least 50 samples.

Thermal Shutdown

Rechargeable Li-ion batteries need protection from damage due to operation at elevated temperatures. The

application should provide this battery protection and ensure that the ambient temperature is never elevated

greater than the expected operational range of 85°C.

The bq25570 uses an integrated temperature sensor to monitor the junction temperature of the device. Once the

temperature threshold is exceeded, the boost charger and buck converter are disabled. Once the temperature of

the device drops below this threshold, the boost charger and buck converter resume operation. To avoid

unstable operation near the overtemp threshold, a built-in hysteresis of approximately 5°C has been

implemented. Care should be taken to not over discharge the battery in this condition since the boost charger is

disabled. However, if the supply voltage drops to the VBAT_UV setting, the switch between VBAT and VSTOR

will open and protect the battery even if the device is in thermal shutdown.

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APPLICATION INFORMATION

Energy Harvester Selection

The energy harvesting source (e.g., solar panel, TEG, vibration element) must provide a minimum level of power

for the IC to operate as designed. The IC's minimum input power required to exit cold start can be estimated as

PIN > [(I-STR_ELM_LEAK_@1.8VX 1.8V) + (1.8V²/ RSTOR(CS))] / 0.05

where I-STR_ELM_LEAK_@1.8Vis the storage element leakage current at 1.8V and

RSTOR(CS) is the equivalent resitive load on VSTOR during cold start and 0.05 is an estimate of the worst case

efficiency of the cold start circuit.

Once the IC is out of cold start and the system load has been activated (e.g., using the VBAT_OK signal), the

energy harvesting element must provide the main boost charger with at least enough power to meet the average

system load. Assuming RSTOR(AVG) represents the average resistive load on VSTOR, the simplified equation

below gives an estimate of the IC's minimum input power needed during system operation:

PIN X η_EST> PLOAD = (VBAT_OV²/ RSTOR(AVG) + VBAT_OV * I-STR_ELM_LEAK_{@VBAT_OV}

)

where η_ESTcan be derived from the datasheet efficiency curves for the given input voltage and current and

VBAT_OV. The simplified equation above assumes that, while the harvester is still providing power, the system

goes into low power or sleep mode long enough to charge the storage element so that it can power the system

when the harvester eventually is down. Refer to SLUC461 for a design example that sizes the energy harvester.

Storage Element Selection

In order for the charge management circuitry to protect the storage element from over-charging or discharging,

the storage element must be connected to VBAT pin and the system load tied to the VSTOR pin. Many types of

elements can be used, such as capacitors, super capacitors or various battery chemistries. A storage element

with 100uF equivalent capacitance is required to filter the pulse currents of the PFM switching charger. The

equivalent capacitance of a battery can be computed as computed as

C_EQ= 2 x mAHr_BAT(CHRGD)x 3600 s/Hr / V_BAT(CHRGD)

In order for the storage element to be able to charge VSTOR capacitor (CSTOR) within the t_{VB_HOT_PLUG}(50 ms

typical) window at hot-plug; therefore preventing the IC from entering cold start, the time constant created by the

storage element's series resistance (plus the resistance of the internal PFET switch) and equivalent capacitance

must be less than t_{VB_HOT_PLUG}. For example, a battery's resistance can be computed as

R_BAT= V_BAT/ I_{BAT(CONTINUOUS)}from the battery specifications.

The storage element must be sized large enough to provide all of the system load during periods when the

harvester is no longer providing power. The harvester is expected to provide at least enough power to fully

charge the storage element while the system is in low power or sleep mode. Assuming no load on VSTOR (i.e.,

the system is in low power or sleep mode), the following equation estimates charge time from voltage VBAT1 to

VBAT2 for given input power is

PIN x η_ESTX t_CHRG= 1/2 X CEQ X (VBAT2²- VBAT1²)

Refer to SLUC461 for a design example that sizes the storage element.

Note that if there are large load transients or the storage element has significant impedance then it may be

necessary to increase the CSTOR capacitor from the 4.7uF minimum or add additional capacitance to VBAT in

order to prevent a droop in the VSTOR voltage. See below for guidance on sizing capacitors.

Inductor Selection

The boost charger and the buck converter each need an appropriately sized inductor for proper operation. The

inductor's saturation current should be at least 25% higher than the expected peak inductor currents

recommended below if system load transients on VSTOR and/or VOUT are expected. Since this device uses

hysteretic control for both the boost charger and buck converter, both are considered naturally stable systems

(single order transfer function).

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Boost Charger Inductor Selection

For the boost charger to operate properly, an inductor of appropriate value must be connected between

LBOOST, pin 20, and VIN_DC, pin 2. The boost charger internal control circuitry is designed to control the

switching behavior with a nominal inductance of 22 µH ± 20%. The inductor must have a peak current capability

of > 300 mA with a low series resistance (DCR) to maintain high efficiency.

A list of inductors recommended for this device is shown in Table 2.

Table 2.

INDUCTANCE (µH)

DIMENSIONS (mm)

4.0x4.0x1.7

PART NUMBER

LPS4018-223M

744031220

MANUFACTURER

Coilcraft

22

3.8x3.8x1.65

Wuerth

Buck Converter Inductor Selection

For buck converter to operate properly, an inductor of appropriate value must be connected between LBUCK, pin

16, and VOUT, pin 14. The buck converter internal control circuitry is designed to control the switching behavior

with a nominal inductance of 10 µH ± 20%. The inductor must have a peak current capability of > 200 mA with a

low series resistance (DCR) to maintain high efficiency. The speed of the peak current detect circuit sets the

inductor's lower bound to 4.7 µH. When using a 4.7 uH, the peak inductor current will increase when compared

to that of a 10 µH inductor, resulting in slightly higher major frequency.

A list of inductors recommended for this device is shown in Table 3.

Table 3.

INDUCTANCE (µH)

DIMENSIONS (mm)

2.0 x 2.5 x 1.2

4.0x4.0x1.7

PART NUMBER

DFE252012C-H-100M

LPS4018-103M

744029100

MANUFACTURER

Toko

10

4.7

Coilcraft

Wuerth

2.8x2.8x1.35

3.0x3.0x1.5

74438335100

Wuerth

2.5x2.0x1.2

74479889310

Wuerth

2.0 x 2.5 x 1.2

DFE252012R-H-4R7M

Toko

Capacitor Selection

In general, all the capacitors need to be low leakage. Any leakage the capacitors have will reduce efficiency,

increase the quiescent current and diminish the effectiveness of the IC for energy harvesting.

VREF_SAMP Capacitance

The MPPT operation depends on the sampled value of the open circuit voltage and the input regulation follows

the voltage stored on the CREF capacitor. This capacitor is sensitive to leakage since the holding period is

around 16 seconds. As the capacitor voltage drops due to any leakage, the input regulation voltage also drops

preventing proper operation from extraction the maximum power from the input source. Therefore, it is

recommended that the capacitor be an X7R or COG low leakage capacitor.

VIN_DC Capacitance

Energy from the energy harvester input source is initially stored on a capacitor, CIN, connected to VIN_DC, pin

2, and VSS, pin 1. For energy harvesters which have a source impedance which is dominated by a capacitive

behavior, the value of the harvester capacitor should scaled according to the value of the output capacitance of

the energy source, but a minimum value of 4.7 µF is recommended.

VSTOR Capacitance

Operation of the bq25570 requires two capacitors to be connected between VSTOR, pin 19, and VSS, pin 1. A

high frequency bypass capacitor of at 0.01 µF should be placed as close as possible between VSTOR and VSS.

In addition, a low ESR capacitor of at least 4.7 µF should be connected in parallel.

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VOUT Capacitance

The output capacitor is chosen based on transient response behavior and ripple magnitude. The lower the

capacitor value, the larger the ripple will become and the larger the droop will be in the case of a transient

response. It is recommended to use at least a 22 µF output capacitor between VOUT, pin 14 and VSS, pin 15,

for most applications.

Additional Capacitance on VSTOR or VBAT

If there are large, fast system load transients and/or the storage element has high resistance, then the CSTOR

capacitors may momentarily discharge below the VBAT_UV threshold in response to the transient. This causes

the bq25570 to turn off the PFET switch between VSTOR and VBAT and turn on the boost charger. The CSTOR

capacitors may further discharge below the VSTOR_CHGEN threshold and cause the bq25570 to enter Cold

Start. For instance, some Li-ion batteries or thin-film batteries may not have the current capacity to meet the

surge current requirements of an attached low power radio. To prevent VSTOR from drooping, either increasing

the CSTOR capacitance or adding additional capacitance in parallel with the storage element is recommended.

For example, if boost charger is configured to charge the storage element to 4.2 V and a 500 mA load transient

of 50 µs duration infrequently occurs, then, solving I = C x dv/dt for CSTOR gives :

CSTOR ≥ 500 mA x 50 µs/(4.2 V – 1.8 V) = 10.5 µF

(6)

Note that increasing CSTOR is the recommended solution but will cause the boost charger to operate in the less

efficient cold start mode for a longer period at startup compared to using CSTOR = 4.7 µF. If longer cold start run

times are not acceptable, then place the additional capacitance in parallel with the storage element.

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LAYOUT CONSIDERATIONS

As for all switching power supplies, the PCB layout is an important step in the design, especially at high peak

currents and high switching frequencies. If the layout is not carefully done, the boost charger and buck converter

could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current

path and for the power ground paths. The input and output capacitors as well as the inductors should be placed

as close as possible to the IC. For the boost charger, first priority are the output capacitors, including the 0.1uF

bypass capacitor (CBYP), followed by CSTOR, which should be placed as close as possible between VSTOR,

pin 19, and VSS, pin 1. Next, the input capacitor, CIN, should be placed as close as possible between VIN_DC,

pin 2, and VSS, pin 1. Last in priority is the boost charger's inductor, L1, which should be placed close to

LBOOST, pin 20, and VIN_DC, pin 2. For the buck converter, the output capacitor COUT should be placed as

close as possible between VOUT, pin 14, and VSS, pin 15. The buck converter inductor (L2) should be placed as

close as possible beween the switching node LBUCK, pin 16, and VOUT, pin 14. It is best to use vias and

bottom traces for connecting the inductors to their respective pins instead of the capacitors.

To minimize noise pickup by the high impedance voltage setting nodes (VBAT_OV, OK_PROG, OK_HYST,

VOUT_SET), the external resistors should be placed so that the traces connecting the midpoints of each divider

to their respective pins are as short as possible. When laying out the non-power ground return paths (e.g. from

resistors and CREF), it is recommended to use short traces as well, separated from the power ground traces and

connected to VSS pin 15. This avoids ground shift problems, which can occur due to superimposition of power

ground current and control ground current. The PowerPad should not be used as a power ground return path.

The remaining pins are either NC pins, that should be connected to the PowerPad as shown below, or digital

signals with minimal layout restrictions. See the EVM user's guide for an example layout (SLUUAA7).

In order to maximize efficiency at light load, the use of voltage level setting resistors > 1MΩ is recommended. In

addition, the sample and hold circuit output capacitor on VREF_SAMP must hold the voltage for 16s. During

board assembly, contaminants such as solder flux and even some board cleaning agents can leave residue that

may form parasitic resistors across the physical resistors/capacitors and/or from one end of a resistor/capacitor

to ground, especially in humid, fast airflow environments. This can result in the voltage regulation and threshold

levels changing significantly from those expected per the installed components. Therefore, it is highly

recommended that no ground planes be poured near the voltage setting resistors or the sample and hold

capacitor. In addition, the boards must be carefully cleaned, possibly rotated at least once during cleaning, and

then rinsed with de-ionized water until the ionic contamination of that water is well above 50 MOhm. If this is not

feasible, then it is recommended that the sum of the voltage setting resistors be reduced to at least 5X below the

measured ionic contamination.

THERMAL CONSIDERATIONS

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-

dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below.

•

Improving the power-dissipation capability of the PCB design

Improving the thermal coupling of the component to the PCB

Introducing airflow in the system

For more details on how to use the thermal parameters in the Thermal Table, check the Thermal Characteristics

Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).

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REVISION HISTORY

Changes from Original (March 2013) to Revision A

Page

•

Changed the data sheet from a Product Brief to Production data ........................................................................................ 3

Changes from Revision A (September 2013) to Revision B

Page

•

Changed values in the THERMAL INFORMATION table ..................................................................................................... 4

Changes from Revision B (September 2013) to Revision C

Page

•

Changed Feature: Continuous Energy Harvesting From Input Sources as low as 120 mV To: Continuous Energy

Harvesting From Input Sources as low as 100 mV .............................................................................................................. 1

•

Changed Feature From: High Efficiency up to 98% To: High Efficiency up to 93% ............................................................ 1

Changed text in the Description From: can continue to harvest energy down to V_IN= 120 mV. To: can continue to

harvest energy down to V_IN= 100 mV. ................................................................................................................................. 1

•

Changed Peak Input Power n the Absolute Maximum Ratings table From: MAX = 400 mW To: MAX = 510 mW ............. 4

Changed VIN(DC) in the Recommended Operating Conditions table From: MIN = 0.12 V MAX = 4 V To: MIN = 0.1

V MAX = 5.1 V ...................................................................................................................................................................... 4

•

Changed VIN(DC) in the Electrical Characteristics table From: MIN = 120 mV MAX = 4000 mV To: MIN = 100 mV

MAX = 5100 mV ................................................................................................................................................................... 5

•

Changed PIN in the Electrical Characteristics table From: MAX = 400 mW To: MAX = 510 mW ....................................... 5

Added VDELTA, VBAT_OV - VIN(DC to the ELECTRICAL CHARACTERISTICS table ..................................................... 6

Changed VOUT_EN(H) From: VSTOR - 0.2 To: VSTOR - 0.4 in the ELECTRICAL CHARACTERISTICS table ............... 6

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PACKAGE MATERIALS INFORMATION

www.ti.com

10-Dec-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ25570RGRR

BQ25570RGRT

VQFN

RGR

20

3000

250

330.0

180.0

12.4

3.75

1.15

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Dec-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ25570RGRR

BQ25570RGRT

VQFN

RGR

20

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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型号：	BQ25570_14
厂家：	TEXAS INSTRUMENTS
描述：	Ultra Low Power Harvester Power Management IC with Boost Charger, and Nano-Powered Buck Converter
文件：	总40页 (文件大小：1541K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ25570_14 [TI]

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