BQ25611DRTWT_技术文档

BQ25611D

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具有 USB 检测和 1.2A 升压运行的 BQ25611D I²C 控制型 3.0A 单节降压电池充电

器

1 特性

2 应用

•

高效 1.5MHz 同步开关模式降压充电器

•

手机、平板电脑

工业、医疗、便携式电子产品

– 在 2A 电流（5V 输入）下具有 92% 的充电效率

– ±0.4% 充电电压调节，阶跃为 10mV

– 可编程 JEITA 阈值

3 说明

BQ25611D 是适用于单节锂离子电池和锂聚合物电

池、高度集成的 3A 开关模式电池充电管理和系统电源

路径管理器件。该解决方案在系统和电池之间高度集成

输入反向阻断 FET（RBFET，Q1）、高侧开关 FET

（HSFET，Q2）、低侧开关 FET（LSFET，Q3）以

及电池 FET（BATFET，Q4）。其低阻抗电源路径对

开关模式运行效率进行了优化，缩短了电池充电时间并

延长了放电阶段的电池运行时间。

– 远程电池检测，可更快地进行充电

支持 USB On-The-Go (OTG)，可调输出电压范围

为 4.6V 至 5.15V

•

– 具有高达 1.2A 输出的升压转换器

– 在 1A 输出下具有 92% 的升压效率

– 精确的恒定电流 (CC) 限制

– 高达 500µF 容性负载的软启动

单个输入，支持 USB 输入以及高电压适配器或无线

电源

•

BQ25611D 是适用于锂离子电池和锂聚合物电池、高

度集成的 3A 开关模式电池充电管理和系统电源路径管

理器件。它可为智能手机和平板电脑等各种应用提供快

速充电功能和高输入电压。其低阻抗电源路径对开关模

式运行效率进行了优化，缩短了电池充电时间并延长了

放电阶段的电池运行时间。其输入电压和电流调节和电

池远程检测可以为电池提供最大的充电功率。

– 支持 4V 至 13.5V 输入电压范围，绝对最大输入

额定值为 22V

– 130ns 快速关断输入过压保护

– 通过 I²C（100mA 至 3.2A，100mA/阶跃）实现

可编程输入电流限制 (IINDPM)

器件信息 ⁽¹⁾

– 通过高达 5.4V 的 VINDPM 阈值自动跟踪电池电

压，从而实现最大功率

– 自动检测 USB SDP、CDP、DCP 以及非标准适

配器

封装尺寸（标称值）

器件型号

BQ25611D

封装

WQFN (24)

4.00mm x 4.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

•

窄 VDC (NVDC) 电源路径管理

– 无需电池或使用深度放电的电池即可使系统瞬时

启动

低 RDSON 19.5mΩ BATFET，可更大程度地降低

充电损耗和延长电池运行时间

– 用于运输模式的 BATFET 控制、使用和不使用

适配器的完全系统复位功能

•

运输模式下的 7µA 低电池泄漏电流

在系统待机时具有 9.5µA 的低电池泄漏电流

高精度电池充电曲线

– ±6% 充电电流调节

– ±7.5% 输入电流调节

简化版应用

– ±3% VINDPM 电压调节

– 用于电池完全充电的可编程充电完成计时器

高集成度包括所有 MOSFET、电流感应和环路补偿

安全相关认证：

•

– 经 IEC 62368-1 CB 认证

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

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www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

Product Folder Links: BQ25611D

1

English Data Sheet: SLUSDF6

BQ25611D

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ZHCSKO3B – JANUARY 2020 – REVISED SEPTEMBER 2020

Table of Contents

9.5 Register Maps...........................................................32

10 Application and Implementation................................46

10.1 Application Information........................................... 46

10.2 Typical Application.................................................. 46

10.3 Application Curves..................................................49

11 Power Supply Recommendations..............................51

12 Layout...........................................................................51

12.1 Layout Guidelines................................................... 51

12.2 Layout Example...................................................... 51

13 Device and Documentation Support..........................53

13.1 Device Support....................................................... 53

13.2 Documentation Support.......................................... 53

13.3 Receiving Notification of Documentation Updates..53

13.4 Support Resources................................................. 53

13.5 Trademarks.............................................................53

13.6 Electrostatic Discharge Caution..............................53

13.7 Glossary..................................................................53

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................3

6 Device Comparison Table...............................................4

7 Pin Configuration and Functions...................................4

8 Specifications.................................................................. 6

8.1 Absolute Maximum Ratings........................................ 6

8.2 ESD Ratings............................................................... 6

8.3 Recommended Operating Conditions.........................6

8.4 Thermal Information....................................................6

8.5 Electrical Characteristics.............................................7

8.6 Timing Requirements................................................12

8.7 Typical Characteristics..............................................14

9 Detailed Description......................................................16

9.1 Overview...................................................................16

9.2 Functional Block Diagram.........................................16

9.3 Feature Description...................................................17

9.4 Device Functional Modes..........................................30

Information.................................................................... 54

4 Revision History

Changes from Revision A (June 2020) to Revision B (September 2020)

Page

向特性列表添加了“安全相关认证”项目符号...................................................................................................1

更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1

•

• Added description about VQON to QON pin description....................................................................................4

• Changed max of BAT, SYS from 17 V to 7 V......................................................................................................6

• Changed max of V_{BAT_DPL}from 2.62 V to 2.55 V............................................................................................... 7

• Changed typ of V_{BAT_DPL}to 2.40 V.....................................................................................................................7

• Added additional 25°C spec for V_{BAT_DPL}..........................................................................................................7

• Added I_{HSFET_OCP}row........................................................................................................................................ 7

• Updated 表 9-2 ................................................................................................................................................ 18

• Updated BATFET Full System Reset section................................................................................................... 25

• Changed Bits 3-6 description from "Reserved" to "BQ25611D: 1010" in 表 9-19 ............................................32

Changes from Revision * (January 2020) to Revision A (June 2020)

Page

• Changed max of V_{REG_ACC}at 4.19 V from 4.206 V to 4.200 V...........................................................................7

2

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5 说明（续）

该解决方案在系统和电池之间高度集成输入反向阻断 FET（RBFET，Q1）、高侧开关 FET（HSFET，Q2）、低

侧开关 FET（LSFET，Q3）以及电池 FET（BATFET、Q4）。它还集成了自举二极管以进行高侧栅极驱动，从

而简化系统设计。I²C 串行接口和充电和系统设置使该器件成为一款真正灵活的解决方案。

该器件支持多种输入源，包括标准 USB 主机端口、USB 充电端口、兼容 USB 的高电压适配器和无线电源。该器

件符合 USB 2.0 和 USB 3.0 电源规格，具有输入电流和电压调节功能。该器件从系统检测电路（如 USB PHY 器

件）获取结果。

该器件通过单个电感器将降压充电器和升压稳压器集成在一个解决方案中。通过提供 5V 电压（可调 4.6V/

4.75V/5V/5.15V），恒定电流限值高达 1.2A，该器件可符合 USB On-the-Go (OTG) 运行功率额定值规格。

在应用适配器时，电源路径管理将系统电压调节至稍高于电池电压的水平，但不会降至 3.5V 最小系统电压（可编

程）以下。借助于这个特性，即使在电池电量完全耗尽或者电池被拆除时，系统也能保持运行。当达到输入电流

限值或电压限值时，电源路径管理会自动减小充电电流。随着系统负载持续增加，电池开始放电，直到满足系统

电源需求。该补充模式可防止输入源过载。

此器件在无需软件控制情况下启动并完成一个充电周期。它感应电池电压并通过三个阶段为电池充电：预充电、

恒定电流和恒定电压。在充电周期的末尾，当充电电流低于预设限值并且电池电压高于再充电阈值时，充电器自

动终止。如果已完全充电的电池降至再充电阈值以下，则充电器自动启动另一个充电周期。

此充电器提供针对电池充电和系统运行的多种安全特性，其中包括电池负温度系数热敏电阻监视、充电安全性计

时器和过压/过流保护。当结温超过 110°C 时，热调节会减小充电电流。状态寄存器报告充电状态和任何故障状

况。借助 I²C，VBUS_GD 位指示电源是否正常，当故障发生时， INT 输出会立即通知主机。

该器件还提供用于 BATFET 使能和复位控制的 QON 引脚，以退出低功耗出厂模式或完全系统复位功能。

BQ25611D 器件采用 24 引脚 4mm × 4mm x 0.75mm 薄型 WQFN 封装。

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6 Device Comparison Table

BQ25601

BQ25601D

BQ25611D

3.5 - 4.3 V (100 mV per step); 4.3

- 4.52 V (10 mV per step)

Programmable Charge Voltage

3.856 - 4.624 V, 32 mV per step 3.856 - 4.624 V, 32 mV per step

D+/D- USB Detection

Default I_CHG

No

Yes

1 A

2.04 A

6.4 V

2.04 A

6.4 V

Default V_ACOV

14.2 V

130 ns

VBUS OVP reaction-time

200 ns

Battery remote sensing with open/

short detection

No

Yes

JEITA, with fixed temperature

thresholds

JEITA, with fixed temperature

thresholds

JEITA, with adjustable

temperature thresholds

TS profile

TS ignore bit

No

Yes

Charge safety timer

5hr, 10 hr (default)

5 hr, 10 hr (default)

20 hr, 10 hr (default)

Allow QON fire when adapter is

present

No

Yes

Deglitch time for chagre termination

250 ms

50 ms

7 Pin Configuration and Functions

VAC

D+

1

2

3

4

5

6

18

17

16

15

14

13

GND

SYS

BAT

D-

Thermal

Pad

STAT

SCL

SDA

Not to scale

图 7-1. RTW Package 24-Pin WQFN Top View

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

13

Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor

is connected between SYS and BAT. Connect a 10 µF⁽²⁾closely to the BAT pin.

BAT

P

14

Battery voltage sensing pin for charge voltage regulation. In order to minimize the parasitic trace

resistance during charging, BATSNS pin is connected to the positive terminal of battery pack as close as

possible. If BATSNS pin is open or short to ground, BATSNS_STAT bit is set to 1 and charger regulates

the battery voltage through BAT pin.

BATSNS

BTST

10

21

AI

P

PWM high side driver positive supply. Internally, the BTST is connected to the cathode of the boot-strap

diode. Connect the 0.047-μF bootstrap capacitor⁽²⁾from SW to BTST.

4

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TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

CE

9

DI

Charge enable pin. When this pin is driven LOW, battery charging is enabled.

Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection

includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard

adaptors.

D+

2

3

AIO

Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection

includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard

adaptors.

D-

17

18

GND

Ground.

—

Open-drain interrupt output. Connect the INT to a logic rail through a 10-kΩ resistor. The INT pin sends

an active low, 256-µs pulse to the host to report charger device status and fault.

INT

7

8

DO

NC

Not connected.

—

Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Place a 10-µF

capacitor⁽²⁾on PMID to GND.

PMID

23

P

BATFET enable/reset control input. When the BATFET is in ship mode, a logic LOW of t_SHIPMODEduration

turns on BATFET to exit ship mode. When the BATFET is not in ship mode, a logic LOW of t_{QON_RST}

(minimum 8 s) duration resets SYS (system power) by turning BATFET off for t_{BATFET_RST}(minimum 250

ms) and then re-enables BATFET to provide full system power reset. The host chooses the BATFET reset

function with VBUS unplugged or not through I²C bit BATFET_RST_WVBUS. The pin is pulled up to V_QON

through 200 kΩ to maintain default HIGH logic during ship mode. It has an internal clamp to 6.5 V. QON

pin is pulled through 200-kΩ resistor to V_QON. V_QONis supplied from VBUS minus 2 diode voltage drop or

from VBAT minus 1 diode voltage drop. It has an internal voltage clamp to 6.5 V.

QON

12

DI

PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boot-strap

diode. Connect a 4.7-μF (10-V rating) ceramic capacitor⁽²⁾from REGN to analog GND. The capacitor

should be placed close to the IC.

REGN

22

P

I²C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.

I²C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.

SCL

SDA

5

6

DI

DIO

Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin

indicates charger status.

STAT

4

DO

Charge in progress: LOW.

Charge complete or charger in SLEEP mode: HIGH.

Charge suspend (fault response): blink at 1 Hz.

19

20

Switching node connecting to output inductor. Internally, SW is connected to the source of the n-channel

HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor⁽²⁾from SW to

BTST.

SW

P

15

16

System output connection point. The internal current sensing resistor is connected between SYS and BAT.

Connect a 10 µF (min)⁽²⁾closely to the SYS pin.

SYS

Battery temperature qualification voltage input. Connect a negative temperature coefficient thermistor

(NTC). Program temperature window with a resistor divider from REGN to TS to GND. Charge and boost

mode suspended when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor

from REGN to TS and a 10-kΩ resistor from TS to GND or set TS_IGNORE to HIGH to ignore TS pin. It

is recommended to use a 103AT-2 thermistor.

TS

11

AI

VAC

1

P

Input voltage sensing. This pin must be tied to VBUS.

Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between

VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor⁽²⁾from VBUS to GND and place it

as close as possible to the device.

VBUS

24

Ground reference for the device that is also the thermal pad used to conduct heat from the device. This

connection serves two purposes. The first purpose is to provide an electrical ground connection for the

device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB.

This pad should be tied externally to a ground plane.

Thermal Pad

P

—

(1) AI = Analog Input, AO = Analog Output, AIO = Analog Input Output, DI = Digital input, DO = Digital Output, DIO = Digital Input Output,

P = Power

(2) All capacitors are ceramic unless otherwise specified

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–2

MAX

22

16

7

UNIT

V

Voltage

VAC (converter not switching)

VBUS (converter not switching)

PMID (converter not switching)

SW

-2

V

–0.3

V

BAT, SYS (converter not switching)

BTST

V

22

7

V

BATSNS (converter not switching)

D+. D-, STAT, SCL, SDA, INT, CE, TS, QON, REGN

V

7

V

Output Sink

Current

STAT, INT

6

mA

T_J

Junction temperature

Storage temperature

150

°C

–40

–55

T_stg

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

13.5

4.52

3.2

3

UNIT

V

V_VBUS

V_BAT

I_VBUS

I_SW

Input voltage

4

Battery voltage

V

Input current

A

Output current (SW)

Fast charging current

RMS discharge current

Ambient temperature

A

I_BAT

T_A

6

A

85

°C

–40

8.4 Thermal Information

BQ25611D

THERMAL METRIC⁽¹⁾

RTW (WQFN)

24 Pins

35.6

UNIT

R_θJA

Junction-to-ambient thermal resistance (JEDEC⁽¹⁾

Junction-to-case (top) thermal resistance

)

°C/W

R_θJC(top)

22.7

6

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8.4 Thermal Information (continued)

BQ25611D

THERMAL METRIC⁽¹⁾

RTW (WQFN)

UNIT

24 Pins

11.9

0.2

R_θJB

Ψ_JT

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.2

Ψ_JB

R_θJC(bot)

2.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

QUIESCENT CURRENTS

VBAT = 4.5 V, VBUS floating or VBUS = 0V - 5 V,

SCL, SDA = 0 V or 1.8 V, T_J< 85 °C, BATFET

enabled

Quiescent battery current

(BATSNS, BAT, SYS, SW)

I_{Q_BAT}

9.5

15

µA

VBAT = 4.5 V, VBUS floating or VBUS = 0V - 5 V,

SCL, SDA = 0 V or 1.8 V, T_J< 85 °C, BATFET

disabled

Shipmode battery current

(BATSNS, BAT, SYS, SW)

I_{SHIP_BAT}

7

9.5

µA

Input current (VBUS) in buck

mode when converter is switching ISYS = 0 A

VBUS=5 V, charge disabled, converter switching,

I_VBUS

2.3

mA

VAC/VBUS = 5 V, HIZ mode, no battery

37

68

50

90

µA

I_{HIZ_VBUS}

Quiescent input current in HIZ

VAC/VBUS = 12 V, HIZ mode, no battery

Quiescent battery current

(BATSNS, BAT, SYS, SW) in

boost mode when converter is

switching

VBAT = 4.5 V, VBUS = 5 V, boost mode enabled,

converter switching, I_PMID= 0A

I_BST

2.4

mA

VBUS / VBAT SUPPLY

V_{VBUS_OP}

VBUS operating range

4

13.5

3.7

V

VBUS rising for active I2C, no

battery

V_{VBUS_UVLOZ}

VBUS rising

VBUS falling

3.3

3

VBUS falling to turnoff I2C, no

battery

V_{VBUS_UVLO}

3.3

V

V_{VBUS_PRESENT}VBUS to enable REGN

V_{VBUS_PRESENTZ}VBUS to disable REGN

VBUS rising

3.65

3.15

60

3.9

3.4

V

VBUS falling

V_SLEEP

Enter Sleep mode threshold

Exit Sleep mode threshold

VBUS falling, VBUS - VBAT, VBAT = 4V

VBUS rising, VBUS - VBAT, VBAT = 4V

VAC rising, OVP[1:0]=00

VAC rising, OVP[1:0]=01

VAC rising, OVP[1:0]=10

VAC rising, OVP[1:0]=11 (default)

VAC falling, OVP[1:0]=00

VAC falling, OVP[1:0]=01

VAC falling, OVP[1:0]=10

VAC falling, OVP[1:0]=11 (default)

15

115

5.45

6.1

110 mV

340 mV

V_SLEEPZ

220

5.85

6.4

6.07

6.75

V

VAC overvoltage rising threshold

to turn of switching

10.45

13.5

5.2

11 11.55

14.2 14.85

V_ACOV

5.6

6.2

5.8

6.45

11.1

14.5

5.8

VAC overvoltage falling threshold

to resume switching

10

10.7

13.9

13

BAT voltage for active I2C, no

VBUS

V_{BAT_UVLOZ}

VBAT rising

2.5

V

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BAT depletion rising threshold to

turn on BATFET

V_{BAT_DPLZ}

V_{BAT_DPL}

VBAT rising

VBAT falling

2.35

2.8

V

BAT depletion falling threshold to

turn off BATFET

2.18

2.40

2.55

BAT depletion falling threshold to

turn off BATFET

V_{BAT_DPL}

T_J= 25°C

2.40

3.9

2.50

4.0

V

V_POORSRC

Bad adapter detection threshold VBUS falling

3.75

3.5

POWER-PATH MANAGEMENT

Typical minimum system

regulation voltage

V_{SYS_MIN}

VBAT=3.2 V < SYS_MIN = 3.5 V, ISYS = 0 A

VREG = 4.35 V, Charge disabled, ISYS = 0 A

3.65

V

V_{SYS_OVP}

System overvoltage threshold

Blocking FET on-resistance

4.7

45

V

R_{ON_RBFET}

mΩ

High-side switching FET on-

resistance

R_{ON_HSFET}

R_{ON_LSFET}

V_BATFET

62

71

30

mΩ

mV

Low-side switching FET on-

resistance

BATFET forward voltage in

supplement mode

_

BAT discharge current 10 mA, converter running

FWD

BATTERY CHARGER

Typical charge voltage regulation

range

V_{REG_RANGE}

3.49

4.51

V

V_{REG_STEP}

V_{REG_ACC}

Typical charge voltage step

Charge voltage accuracy

4.29 V < VREG < 4.51 V

10

mV

V

4.073

4.173

4.332

4.432

4.09 4.106

4.19 4.200

4.35 4.367

4.45 4.468

VREG = 4.09 V, T_J= –40°C - 85°C

VREG = 4.19 V, T_J= –40°C - 85°C

VREG = 4.35 V, T_J= –40°C - 85°C

VREG = 4.45 V, T_J= –40°C - 85°C

V

Typical charge current regulation

range

I_{CHG_RANGE}

I_{CHG_STEP}

0

3

A

mA

A

Typical charge current regulation

step

60

ICHG = 0.24 A, VBAT = 3.1 V or 3.8 V, T_J= –40°C

- 85°C

0.2112

0.6768

0.24 0.2688

0.72 0.7632

1.38 1.4628

Fast charge current regulation

accuracy

ICHG = 0.72 A, VBAT = 3.1 V or 3.8 V, T_J= –40°C

- 85°C

I_{CHG_ACC}

A

ICHG = 1.38 A, VBAT = 3.1 V or 3.8 V, T_J= –40°C

- 85°C

1.2972

60

A

I_{PRECHG_RANGE}Typical pre-charge current range

780 mA

mA

I_{PRECHG_STEP}

Typical pre-charge current step

60

120

240

VBAT = 2.6 V, IPRECHG = 120 mA

VBAT = 2.6 V, IPRECHG = 240 mA

102

204

60

138 mA

276 mA

780 mA

mA

I_{PRECHG_ACC}

Precharge current accuracy

I_{TERM_RANGE}

I_{TERM_STEP}

Typical termination current range

Typical termination current step

60

ITERM = 180 mA, ICHG > 780 mA, VREG = 4.35

V, T_J= –40°C - 85°C

162

42

180

192 mA

78 mA

I_{TERM_ACC}

Termination current accuracy

ITERM = 60mA, ICHG = < 780 mA, VREG = 4.35

V, T_J= –40°C - 85°C

60

Battery short voltage rising

threshold to start pre-charge

V_{BAT_SHORTZ}

VBAT rising

2.13

2.25

2.35

V

8

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

2.15

110 mA

Battery short voltage falling

threshold to stop pre-charge

V_{BAT_SHORT}

I_{BAT_SHORT}

VBAT falling

1.85

2

V

Battery short trickle charging

current

VBAT < V_{BAT_SHORTZ}

VBAT rising

70

3

90

3.12

2.8

Battery LOWV rising threshold to

start fast-charge

3.24

2.9

V

V_BATLOWV

Battery LOWV falling threshold to

stop fast-charge

VBAT falling

2.7

VRECHG=0, VBAT falling (default)

VRECHG=1, VBAT falling

90

120

210

150 mV

245 mV

V_RECHG

Battery recharge threshold

185

System discharge load current

during SYSOVP

I_{SYS_LOAD}

30

mA

19.5

26

30

T_J= –40°C - 85°C

T_J= –40°C - 125°C

mΩ

R_{ON_BATFET}

Battery FET on-resistance

BATTERY OVER-VOLTAGE PROTECTION

Battery overvoltage rising

threshold

VBAT rising, as percentage of VREG

VBAT falling, as percentage of VREG

103

101

104

102

105

103

%

V_{BAT_OVP}

Battery overvoltage falling

threshold

INPUT VOLTAGE / CURRENT REGULATION

Typical input voltage regulation

V_{INDPM_RANGE}

range

3.9

5.4

V

mV

V

Typical input voltage regulation

step

V_{INDPM_STEP}

100

Typical input voltage regulation

V_{INDPM_ACC}

accuracy

4.365

4.45

0.1

4.5 4.635

VINDPM threshold to track

V_{INDPM_TRACK}

VBAT = 4.35 V, VINDPM_BAT_TRACK = VBAT +

200 mV

4.55

4.74

3.2

V

battery voltage

Typical input current regulation

range

I_{INDPM_RANGE}

I_{INDPM_STEP}

A

Typical input current regulation

100

mA

step

Input current regulation accuracy IINDPM = 500 mA (T_J=-40°C - 85°C)

Input current regulation accuracy IINDPM = 900 mA (T_J=-40°C-85°C)

I_{INDPM_ACC}

450

750

465

835

500 mA

900 mA

1500 mA

I_{INDPM_ACC}

Input current regulation accuracy IINDPM = 1500 mA (T_J=-40°C-85°C)

1300

1390

D+ / D- Detection

V_{DP_SRC}

D+ line source voltage

500

7

600

10

700 mV

D+ line data contact detect

VD + = 200 mV,

I_{DP_SRC}

14

µA

current source

I_{DP_SINK}

D+ line sink current

VD + = 500 mV,

D+ pin Rising,

VD+ = 500 mV

Pull up to 1.8 V

50

100

150

V_{DP_DAT_REF}

V_{DP_LGC_LOW}

R_{DP_DWN}

I_{D+_LKG}

D+ line data detect voltage

D+ line logic low.

250

400 mV

800 mV

D+ line pull-down resistance

Leakage current into D+ line

D- line source voltage

D- line sink current

14.25

24.8

1

kΩ

µA

–1

500

V_{DM_SRC}

600

100

700 mV

150 µA

400 mV

24.8

I_{DM_SINK}

VD- = 500 mV,

D- pin Rising,

VD- = 500 mV

50

V_{DM_DAT_REF}

R_{DM_DWN}

D- line data detect voltage

D- line pull-down resistance

250

14.25

kΩ

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_{D-_LKG}

Leakage current into D- line

Pull up to 1.8 V

1

µA

V

–1

D+/D- comparator threshold for

non-standard adapter

V_{D+/D- _2p8}

2.55

1.85

1.05

2.85

D+/D- comparator threshold for

non-standard adapter

V_{D+/D- _2p0}

V_{D+/D- _1p2}

2.15

1.35

V

D+/D- comparator threshold for

non-standard adapter

THERMAL REGULATION AND THERMAL SHUTDOWN

TREG = 90°C

TREG = 110°C

90

°C

Junction temperature regulation

accuracy

T_REG

110

Thermal Shutdown Rising

threshold

T_SHUT

Temperature Increasing

Temperature Decreasing

150

130

°C

Thermal Shutdown Falling

threshold

CHARGE MODE THERMISTOR COMPARATOR (JEITA 616J or HOT/COLD 616)

TS pin voltage rising threshold,

V_{T1_RISE%}

Charge suspended above this

voltage.

As Percentage to REGN (0°C w/ 103AT)

As Percentage to REGN

72.4

71.5

73.3

72

74.2

72.5

%

TS pin voltage falling threshold.

Charge re-enabled to 20% of

ICHG and VREG below this

voltage.

V_{T1_FALL%}

As Percentage to REGN, JEITA_T2 = 5°C w/

103AT

70.25 70.75 71.25

67.75 68.25 68.75

64.75 65.25 65.75

61.75 62.25 62.75

%

As Percentage to REGN, JEITA_T2 = 10°C w/

103AT

TS pin voltage rising threshold,

Charge back to 20% of ICHG and

VREG above this voltage.

V_{T2_RISE%}

V_{T2_FALL%}

V_{T3_FALL%}

As Percentage to REGN, JEITA_T2 = 15°C w/

103AT

As Percentage to REGN, JEITA_T2 = 20°C w/

103AT

%

As Percentage to REGN, JEITA_T2=5°C w/ 103AT

68.7

69.2

69.7

As Percentage to REGN, JEITA_T2=10°C w/

103AT

66.45 66.95 67.45

TS pin voltage falling threshold.

Charge back to ICHG and VREG

below this voltage.

As Percentage to REGN, JEITA_T2=15°C w/

103AT

63.7

60.7

64.2

61.2

64.7

61.7

%

As Percentage to REGN, JEITA_T2=20°C w/

103AT

As Percentage to REGN, JEITA_T3=40°C w/

103AT

47.75 48.25 48.75

44.25 44.75 45.25

As Percentage to REGN, JEITA_T3=45°C w/

103AT

TS pin voltage falling threshold.

Charge to ICHG and 4.1V below

this voltage.

As Percentage to REGN, JEITA_T3=50°C w/

103AT

40.2

37.2

40.7

37.7

41.2

38.2

As Percentage to REGN, JEITA_T3=55°C w/

103AT

10

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

As Percentage to REGN, JEITA_T3 = 40°C w/

103AT

48.8

49.3

49.8

46.3

42.3

39.5

%

As Percentage to REGN, JEITA_T3 = 45°C w/

103AT

45.3

41.3

38.5

45.8

41.8

39

TS pin voltage rising threshold.

Charge back to ICHG and VREG

above this voltage.

V_{T3_RISE%}

As Percentage to REGN, JEITA_T3 = 50°C w/

103AT

As Percentage to REGN, JEITA_T3 = 55°C w/

103AT

TS pin voltage falling threshold,

charge suspended below this

voltage.

V_{T5_FALL%}

As Percentage to REGN (60°C w/ 103AT)

As Percentage to REGN

33.7

35

34.2

35.5

35.1

36

%

TS pin voltage rising threshold.

Charge back to ICHG and 4.1V

above this voltage.

V_{T5_RISE%}

BOOST MODE THERMISTOR COMPARATOR (HOT/COLD)

TS pin voltage rising threshold,

V_{BCOLD_RISE%}

V_{BCOLD_FALL%}

V_{BHOT_FALL%}

boost mode is suspended above

this voltage.

79.5

30.2

80

72

80.5

32.2

%

As Percentage to REGN (–19.5°C w/ 103AT)

As Percentage to REGN (0°C w/ 103AT)

As Percentage to REGN, (64°C w/ 103AT)

TS pin voltage falling threshold

TS pin voltage threshold. boost

mode is suspended below this

voltage.

31.2

As Percentage to REGN, (55°C w/ 103AT),

REG0C[1:0] = 11

V_{BHOT_RISE%}

TS pin voltage rising threshold

39

%

SWITCHING CONVERTER

F_SW

PWM switching frequency

Maximum PWM Duty Cycle

Oscillator frequency

BAT falling

1.32

1.5

97

1.68 MHz

%

D_MAX

BOOST MODE CONVERTER

Battery voltage exiting boost

mode

V_{BST_BAT}

2.4

4.6

4.85

0.5

1.2

0.5

9

2.5

5

2.6

5.15

1.2

V

A

Typical boost mode voltage

regulation range

V_{BST_RANGE}

V_{BST_ACC}

I_{BST_RANGE}

I_{BST_ACC}

Boost mode voltage regulation

accuracy

IVBUS = 0 A, BOOST_V = 5 V

Typical boost mode current

regulation

Boost mode maximum output

current limit

1.4

10

1.6

Boost mode battery discharge

current clamp on RBFET Q1

I_{BST_OCP_Q1}

BOOST_LIM = 0.5 A

0.72

Boost mode battery discharge

current clamp on BATFET Q4

I_{SYS_OCP_Q4}

REGN LDO

V_VBUS= 5 V, I_REGN= 20 mA

V_VBUS= 9 V, I_REGN= 20 mA

V_VBUS= 5 V, V_REGN= 3.8 V

4.58

5.6

50

4.7

6

4.8

6.5

V

V_REGN

REGN LDO output voltage

REGN LDO current limit

I_REGN

mA

I2C INTERFACE (SCL, SDA)

Input high threshold level, SDA

and SCL

V_IH

V_IL

Pull up rail 1.8 V

1.3

V

Input low threshold level

0.4

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OL

Output low threshold level

High-level leakage current

Input high threshold level, SDA

Input low threshold level

Output low threshold level

High-level leakage current

Input high threshold level, SDA

Input low threshold level

Output low threshold level

High-level leakage current

Sink current = 5 mA

0.4

1

V

µA

V

I_BIAS

Pull up rail 1.8 V

Sink current = 5 mA

Pull up rail 1.8 V

Sink current = 5 mA

Pull up rail 1.8 V

V_{IH_SDA}

V_{IL_SDA}

V_{OL_SDA}

I_{BIAS_SDA}

V_{IH_SCL}

V_{IL_SCL}

V_{OL_SCL}

I_{BIAS_SCL}

1.3

0.4

1

V

µA

V

1.3

0.4

1

V

µA

LOGIC INPUT PIN

V_IH

Input high threshold level (/CE)

Input low threshold level (/CE)

High-level leakage current (/CE) Pull up rail 1.8 V

V

V_IL

0.4

1

I_{IN_BIAS}

µA

LOGIC OUTPUT PIN

Output low threshold level (/INT,

STAT, /PG)

V_OL

Sink current = 5 mA

Pull up rail 1.8 V

0.4

1

V

High-level leakage current (/INT,

STAT, /PG)

I_{OUT_BIAS}

µA

CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)

HSFET cycle-by-cycle over-

I_{HSFET_OCP}

5.2

8.0

A

current threshold

8.6 Timing Requirements

MIN

NOM

MAX

UNIT

VBUS / VBAT POWER UP

t_{VBUS_OV}

VBUS OVP Reaction-time

130

30

2

ns

ms

s

t_POORSRC

Bad adapter detection duration

Bad adapter detection retry wait time

t_{POORSRC_RETRY}

BATTERY CHARGER

t_{TERM_DGL}

Deglitch time for charge termination

30

20

10

ms

min

hr

t_{RECHG_DGL}

t_{TOP_OFF}

Deglitch time for recharge threshold

Typical top-off timer accuracy TOP_OFF_TIMER[1:0]=10

Charge safety timer accuracy, CHG_TIMER = 20hr

Charge safety timer accuracy, CHG_TIMER = 10hr

24

17

8

36

24

12

t_SAFETY

hr

QON Timing

QON low time to turn on BATFET and exit shipmode (–10℃ ≤ TJ

≤ 60℃)

t_SHIPMODE

0.9

1.3

s

QON low time before BATFET full system reset (–10℃ ≤ TJ ≤

60℃)

t_{QON_RST}

8

250

10

12

400

15

s

ms

s

t_{BATFET_RST}

t_{BATFET_DLY}

BATFET off time during full system reset (–10℃ ≤ TJ ≤ 60℃)

Delay time before BATFET turn off in ship mode (–10℃ ≤ TJ ≤

60℃)

DIGITAL CLOCK AND WATCHDOG

f_LPDIGDigital low-power clock (REGN LDO is disabled)

30

kHz

12

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MIN

NOM

500

160

MAX

UNIT

kHz

s

f_DIG

Digital power clock

t_{LP_WDT}

t_WDT

Watchdog Reset time

Watchdog Reset time (WATCHDOG REG05[5:4] = 160s)

s

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8.7 Typical Characteristics

95

90

85

80

75

70

96

94

92

90

88

86

84

82

VBAT=4.2V

VBAT=3.8V

VBAT=3.2V

VBUS = 5 V

VBUS = 9 V

VBUS = 12 V

65

60

0

0.5

1 1.5

Charge Current (A)

2

2.5

3

0

0.2

0.4

0.6

Boost Current (A)

0.8

1

1.2

Char

V_BUS= 5 V, 9 V, 12 V V_BAT= 3.8 V

Inductor 1µH, DCR =

V_BAT= 3.2 V, 3.8 V, 4.2 V_BUS= 5 V

V

Inductor 1µH, DCR =

14.6 mΩ

图 8-1. Charge Efficiency

图 8-2. Boost Efficiency

1

0.5

0

4.45

4.4

V_BATREG= 4.35 V

4.35

4.3

-0.5

-1

-1.5

4.25

0

0.5

1 1.5

Charge Current (A)

2

2.5

3

-40

-15

10

35

60

85

110 125

Junction Temperature (èC)

Char

图 8-3. Charge Current Accuracy

图 8-4. Battery Charge Voltage vs Junction

Temperature

1.6

1.4

1.2

1

4.6

ICHG = 500 mA

ICHG = 1000 mA

ICHG = 1380 mA

VINDPM = 4.1 V

VINDPM = 4.3 V

VINDPM = 4.4 V

VINDPM = 4.5 V

4.5

4.4

4.3

4.2

4.1

4

0.8

0.6

0.4

-40

-25

-10

5

20

35

50

65

8085

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

Char

VIND

图 8-5. Charge Current vs Junction Temperature

图 8-6. VINDPM vs Junction Temperature

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3.8

1.75

1.5

IINDPM = 0.5 A

INDPM = 0.9 A

INDPM = 1.5 A

3.75

3.7

1.25

1

0.75

0.5

3.65

3.6

0.25

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

-40

-25

-10

5

20

35

Junction Temperature (°C)

50

65

8085

VSYS

IIND

图 8-7. SYSMIN Voltage vs Junction Temperature

图 8-8. Input Current Limit vs Junction

(VSYS set at 3.5V)

Temperature

5.25

2.25

BOOSTV = 5.0 V

BOOSTV = 5.15 V

2

1.75

1.5

1.25

1

5.2

5.15

5.1

0.75

0.5

0.25

0

5.05

110 °C

90 °C

5

55

65

75

85

95

105

Junction Temperature (°C)

115

125

135

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

VOTG

图 8-10. Charge Current vs Junction Temperature

图 8-9. Boost Output Voltage vs Junction

Temperature

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9 Detailed Description

9.1 Overview

The BQ25611D device is a highly integrated 3.0-A switch-mode battery charger for single cell Li-Ion and Li-

polymer battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2),

low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate

drive.

9.2 Functional Block Diagram

VBUS

PMID

V_{VBUS_UVLOZ}

RBFET (Q1)

+

UVLO

SLEEP

ACOV

V_VBUS

Q1 Gate

Control

œ

I_IN

V_BAT+ V_SLEEP

+

VAC

REGN

BTST

EN_REGN

EN_HIZ

V_VBUS

REGN

LDO

œ

V_VBUS

+

V_VACOV

œ

FBO

V_VBUS

VBUS_OVP_BOOST

+

V_{BST_OVP}

œ

I_Q2

Q2_UCP_BOOST

Q3_OCP_BOOST

+

V_{OTG_HSZCP}

V_VBUS

œ

+

œ

+

œ

+

HSFET (Q2)

LSFET (Q3)

I_Q3

V_INDPM

SW

+

V_{OTG_BAT}

I_IN

CONVERTER

Control

œ

REGN

I_INDPM

V_BAT

+

BAT_OVP

UCP

104% × V_REG

IC T_J

T_REG

PGND

œ

I_{LSFET_UCP}

I_Q2

V_BATSNS

Q2_OCP

+

œ

+

œ

+

I_{HSFET_OCP}

I_Q3

V_SYS

V_REG

œ

V_{SYS_MIN}

V_BTST- V_SW

I_CHG

EN_HIZ

EN_CHARGE

EN_BOOST

+

REFRESH

V_{BTST_REFRESH}

I_{CHG_REG}

œ

SYS

I_CHG

V_{BAT_REG}

I_{CHG_REG}

BATFET

(Q4)

Q4 Gate

Control

BAT

REF

DAC

V_POORSRC

V_VBUS

+

POORSRC

TSHUT

Converter

Control State

Machine

œ

IC T_J

+

BATSNS

T_SHUT

œ

V_QON

D+

Input Source

Detection

USB

DÅ

Adapter

V_REG-V_RECHG

V_BATSNS

I_CHG

+

RECHRG

QON

œ

INT

+

TERMINATION

BATLOWV

I_TERM

œ

CHARGE

CONTROL

STATE

V_BATLOWV

STAT

+

V_BATSNS

V_SHORT

MACHINE

œ

BQ25611D

+

BATSHORT

SUSPEND

V_BATSNS

I2C

œ

Interface

Battery

Sensing

TS

Thermistor

SCL SDA

CE

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9.3 Feature Description

9.3.1 Power-On-Reset (POR)

The device powers internal bias circuits from the higher voltage of VBUS and BAT. When V_VBUSrises above

V_{VBUS_UVLOZ}or V_BATrises above V_{BAT_UVLOZ}, the sleep comparator, battery depletion comparator and BATFET

driver are active. I²C interface is ready for communication and all the registers are reset to default value. The

host can access all the registers after POR.

9.3.2 Device Power Up from Battery without Input Source

If only the battery is present and the voltage is above depletion threshold (V_{BAT _DPLZ}), the BATFET turns on and

connects the battery to the system. The REGN stays off to minimize the quiescent current. The low R_DSONof

BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.

The device always monitors the discharge current through BATFET. When the system is overloaded or shorted

(I_BAT> I_{SYS_OCP_Q4}), the device turns off BATFET immediately until the input source plugs in again.

With I²C, when the BATFET turns off due to over-current, the device sets the BATFET_DIS bit to indicate the

BATFET is disabled until the input source plugs in again or one of the methods described in the 节 9.3.7.2

section is applied to re-enable BATFET.

9.3.3 Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on the REGN LDO and

all the bias circuits. It detects and sets the input current limit before the buck converter is started. The power up

sequence from input source is as listed:

1. Power Up REGN LDO, see Power Up REGN LDOsection

2. Poor Source Qualification, see Poor Source Qualification section

3. Input Source Type Detection is based on D+/D– to set default input current limit (IINDPM threshold), see

Input Source Type Detection (IINDPPM Threshold) section

4. Input Voltage Limit Threshold Setting (VINDPM threshold), see Input Voltage Limit Thresholding Setting

(VINDPM Threshold) section

5. Power Up Converter, see Power Up Converter in Buck Mode section

9.3.3.1 Power Up REGN LDO

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. It also provides the

bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN LDO is

enabled when all the below conditions are valid:

• V_VBUS> V_{VBUS_UVLOZ}

• In buck mode, V_VBUS> V_BAT+ V_SLEEPZ

• In boost mode, V_VBUS< V_BAT+ V_SLEEPZ

• After 220-ms delay is completed

During high impedance mode when EN_HIZ bit is 1, REGN LDO turns off. The battery powers up the system.

9.3.3.2 Poor Source Qualification

After the REGN LDO powers up, the device starts to check current capability of the input source. The first step is

poor source detection.

• VBUS voltage above V_POORSRCwhen pulling I_BADSRC(typical 30 mA)

With I²C, once the input source passes poor source detection, the status register bit VBUS_GD is set to 1 and

the INT pin is pulsed to signal to the host.

If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.

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9.3.3.3 Input Source Type Detection (IINDPM Threshold)

After poor source detection, the device runs input source detection through D+/D– lines . The D+/D– detection

follows the USB Battery Charging Specification 1.2 (BC1.2) to detect standard (SDP/CDP/DCP) and non-

standard adapters through USB D+/D– lines.

With I²C, after input source type detection is completed, an INT pulse is asserted to the host. in addition, the

following register bits are updated:

The host can over-write the IINDPM register to change the input current limit if needed.

9.3.3.3.1 D+/D– Detection Sets Input Current Limit

The device contains a D+/D– based input source detection to set the input current limit when a 5-V adapter is

plugged-in. The D+/D– detection includes standard USB BC1.2 and non-standard adapters. When an input

source is plugged in, the device starts standard USB BC1.2 detection. The USB BC1.2 is capable of identifying

Standard Downstream Port (SDP), Charging Downstream Port (CDP) and Dedicated Charging Port (DCP). The

non-standard detection is used to distinguish vendor specific adapters (Apple and Samsung) based on their

unique dividers on the D+/D– pins. If an adapter is detected as DCP, the input current limit is set at 2.4-A. If an

adapter is detected as unknown, the input current limit is set at 0.5 A by ILIM pin.

The secondary detection is used to distinguish two types of charging ports (CDP and DCP). The protocol for

secondary detection is as follows:

Most of the time, a CDP requires the portable device (such as smart phone, tablet) to send back an enumeration

within 2.5 seconds of CDP plug-in. Otherwise, the port will power cycle back to SDP even the D+/D– detection

indicates CDP.

表 9-1. Non-Standard Adapter Detection

NON-STANDARD

D+ THRESHOLD

INPUT CURRENT LIMIT (A)

D– THRESHOLD

ADAPTER

Divider 1

Divider 2

Divider 3

Divider 4

V_D+within V_{D+/D- _2p8}

V_D+within V_{D+/D- _1p2}

V_D+within V_{D+/D- _2p0}

V_D+within V_{D+/D- _2p8}

V_D–within V_{D+/D- _2p0}

V_D–within V_{D+/D- _1p2}

V_D–within V_{D+/D- _2p8}

2.1

2

1

2.4

表 9-2. Input Current Limit Setting from D+/D– Detection

INPUT CURRENT LIMIT (IINLIM)

D+/D– DETECTION

USB SDP (USB500)

USB DCP

500 mA

2.4 A

1 A

Divider 3

Divider 1

2.1 A

2.4 A

2 A

Divider 4

Divider 2

Unknown 5-V Adapter

500 mA

9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device has two modes to set the VINDPM threshold.

• Fixed VINDPM threshold. The VINDPM is in default set at 4.5 V (programmable from 3.9 V to 5.4 V) .

• VINDPM threshold tracks the battery voltage to optimize the converter headroom between input and output.

When it is enabled in REG07[1:0], the actual input voltage limit is the higher of the VINDPM setting in register

and V_BAT+ offset voltage in VINDPM_BAT_TRACK[1:0] .

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9.3.3.5 Power Up Converter in Buck Mode

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. The

system voltage is powered from the converter instead of the battery. If battery charging is disabled, the BATFET

turns off. Otherwise, the BATFET stays on to charge the battery.

The device provides soft-start when system rail is ramping up. When the system rail is below V_{BAT_SHORT}, the

input current is limited to the lower of 200-mA or IINDPM register setting. The system load shall be appropriately

planned not to exceed the 200-mA IINDPM limit. After the system rises above V_{BAT_SHORTZ}, the device input

current limit is the value set by the IINDPM register .

As a battery charger, the device deploys a highly efficient 1.5-MHz step-down switching regulator. The fixed

frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery

voltage, charge current and temperature simplifying output filter design.

The converter supports PFM operation by default for fast transient response during system voltage regulation

and better light load efficiency. The PFM_DIS bit disables PFM operation if system voltage is not in regulation.

9.3.3.6 HIZ Mode with Adapter Present

By setting EN_HIZ bit to 1 with adapter, the device enters high impedance state (HIZ). In HIZ mode, the system

is powered from battery even with good adapter present. The device is in the low input quiescent current state

with Q1 RBFET, REGN LDO and the bias circuits off.

9.3.4 Boost Mode Operation From Battery

The device supports boost converter operation to deliver power from the battery to other portable devices

through a USB port. The output voltage is regulated at 5-V (programmable 4.6/4.75/5.0/5.15 V) and output

current is up to 1.2 A (programmable 0.5 A/1.2 A ) with constant current regulation. The user needs to have at

least 350 mV between V_BATand boost mode regulation voltage (V_BST) to power up boost mode reliably. For

example, BOOSTV[1:0] setting is recommended to be 4.75 V or higher if the battery voltage is 4.4 V.

The boost operation is enabled if the conditions below are valid:

1. Register setting: BATFET_DIS = 0, CHG_COFNIG = 0 and BST_CONFIG = 1

2. BAT above V_{BST_BAT}set by MIN_VBAT_SEL bit,

3. VBUS less than V_BAT+ V_SLEEP(in sleep mode) before converter starts.

4. Voltage at TS (thermistor) pin, as a percentage of V_REGN, is within acceptable range (V_{BHOT_RISE%}< V_TS%

V_{BCOLD_FALL%}

<

)

5. After 30-ms delay from boost mode enable .

During boost mode, the status register VBUS_STAT bits is set to 111 .

The converter supports PFM operation at light load in boost mode. The PFM_DIS bit can be used to disable

PFM operation in boost configuration.

9.3.5 Power Path Management

The device accommodates a wide range of input sources such as USB, wall adapter, or car charger. The device

provides automatic power path selection to supply the system (SYS) from the input source (VBUS), battery

(BAT), or both.

9.3.5.1 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The

minimum system voltage is set by SYS_Min bits. Even with a fully depleted battery, the system is regulated

above the minimum system voltage.

When the battery is below the minimum system voltage setting, the BATFET operates in linear mode (LDO

mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage

rises above the minimum system voltage, the BATFET is fully on and the voltage difference between the system

and battery is the V_DSof the BATFET.

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When battery charging is disabled and above the minimum system voltage setting or charging is terminated, the

system is always regulated at typically 50 mV above the battery voltage. The status register VSYS_STAT bit

goes to 1 when the system is in minimum system voltage regulation.

4.5

Minimum System Voltage

Charge Disabled

Charge Enabled

4.1

4.3

3.9

3.7

3.5

3.3

3.1

2.7

2.9

3.1

3.3

3.5

BAT (V)

3.7

3.9

4.1

4.3

D002

图 9-1. System Voltage vs Battery Voltage

9.3.5.2 Dynamic Power Management

To meet the maximum current limit in the USB specification and avoid overloading the adapter, the device

features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage.

When input source is overloaded, either the current exceeds the input current limit (IINDPM) or the voltage falls

below the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls

below the input current limit or the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to

drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement

mode where the BATFET turns on and the battery starts discharging so that the system is supported from both

the input source and battery.

During DPM mode, the status register bits VINDPM_STAT or IINDPM_STAT go to 1.

图 9-2 shows the DPM response with 9-V/1.2-A adapter, 3.2-V battery, 2.8-A charge current and 3.5-V minimum

system voltage setting.

Voltage

VBUS

9V

SYS

BAT

3.6V

3.4V

3.2V

3.18V

Current

4A

ICHG

3.2A

2.8A

ISYS

1.2A

1.0A

IIN

0.5A

-0.6A

DPM

Supplement

图 9-2. DPM Response

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9.3.5.3 Supplement Mode

When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is

regulated so that the minimum BATFET V_DSstays at 30 mV when the current is low. This prevents oscillation

from entering and exiting the supplement mode.

As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce R_DSONuntil

the BATFET is in full conduction. At this point onwards, the BATFET V_DSlinearly increases with discharge

current. 图 9-3 shows the V-I curve of the BATFET gate regulation operation. The BATFET turns off to exit

supplement mode when the battery is below battery depletion threshold.

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

5

10 15 20 25 30 35 40 45 50 55

V(BAT-SYS) (mV)

D001

Plot1

图 9-3. BAFET V-I Curve

9.3.6 Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5-

mΩ BATFET improves charging efficiency and minimizes the voltage drop during discharging.

9.3.6.1 Autonomous Charging Cycle

When battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously

completes a charging cycle without host involvement. The device default charging parameters are listed in 表

9-3. The host configures the power path and charging parameters by writing to the corresponding registers

through I²C.

表 9-3. Charging Parameter Default Setting

DEFAULT MODE

Charging voltage

Charging current

Pre-charge current

Termination current

Temperature profile

Safety timer

BQ25611D

4.20 V

1.02 A

180 mA

JEITA

10 hours

A new charge cycle starts when the following conditions are valid:

• Converter starts

• Battery charging is enabled (CHG_CONFIG bit = 1 and I_CHGregister is not 0 mA and CE is low)

• No thermistor fault on TS. (TS pin can be ignored by setting TS_IGNORE bit to 1)

• No safety timer fault

• BATFET is not forced to turn off (BATFET_DIS bit = 0)

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The device automatically terminates the charging cycle when the charging current is below the termination

threshold, the battery voltage is above the recharge threshold, and the device is not in DPM mode or thermal

regulation. When a fully charged battery is discharged below recharge threshold (selectable through VRECHG

bit), the device automatically starts a new charging cycle. After the charge is done, toggle CE pin or

CHG_CONFIG bit will initiate a new charging cycle. Adapter removal and replug will also restart a charging

cycle.

The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or

charging fault (blinking). The status register (CHRG_STAT) indicates the different charging phases: 00-charging

disable, 01-pre-charge, 10-fast charge (CC) and constant voltage (CV), 11-charging done. Once a charging

cycle is completed, an INT pulse is asserted to notify the host.

9.3.6.2 Battery Charging Profile

The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage

and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage

and regulates current and voltage accordingly.

Resistance between charger output and battery cell terminal such as board routing, connector, MOSFETs and

sense resistor can force the charging process to move from constant current to constant voltage too early and

increase charge time. To speed up the charging cycle, the device provides BATSNS pin to extend the constant

current charge time to delivery maximum power to battery. BATSNS pin is connected directly to battery cell

terminal to remotely sense battery cell voltage. BATSNS is by default enabled, and can be disabled through

BATSNS_DIS bit. If BATSNS is connected to GND or left floating, the charger regulates BAT pin instead.

表 9-4. Charging Current Setting

V_BAT

< 2.2 V

CHARGING CURRENT

DEFAULT SETTING

CHRG_STAT

I_{BAT_SHORT}

100 mA

01

10

2.2 V to 3 V

> 3 V

I_PRECHG

180 mA

I_CHG

1020 mA

Regulation Voltage

Charge Current

Battery Voltage

Charge Current

V_BATLOWV(3 V)

V_SHORTZ(2.2 V)

I_PRECHG

I_TERM

I_SHORT

Fast Charge and Voltage Regulation

Trickle Charge

Pre-charge

Safety Timer

Expiration

Top-off Timer

图 9-4. Battery Charging Profile

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9.3.6.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above the recharge threshold, and the current

is below termination current. After the charging cycle is completed, the BATFET turns off. The STAT is asserted

HIGH to indicate charging done. The converter keeps running to power the system, and BATFET can turn on

again to engage Supplement Mode.

If the device is in IINDPM/VINDPM regulation, or thermal regulation, the actual charging current will be less than

the termination value. In this case, termination is temporarily disabled.

When termination occurs, STAT pin goes HIGH. The status register CHRG_STAT is set to 11, and an INT pulse

is asserted to the host. Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.

The termination current is set in REG03[3:0]. Due to the termination current accuracy, the actual termination

current may be higher than the termination target. In order to compensate for termination accuracy, a

programmable top-off timer can be applied after termination is detected . The top-off timer will follow safety timer

constraints, such that if safety timer is suspended, so will the top-off timer. Similarly, if safety timer is doubled, so

will the termination top-off timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The host

can read CHRG_STAT and TOPOFF_ACTIVE to find out the termination status. STAT pin stays HIGH during

top-off timer counting cycle.

Top-off timer gets reset at one of the following conditions:

1. Charge disable to enable

2. Charger enters termination

3. REG_RST register bit is set

The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer

value (01, 10, 11) after termination will have no effect unless a recharge cycle is initiated. The top-off timer will

immediately stop if it is disabled (00). An INT is asserted to the host when entering top-off timer segment as well

as when top-off timer expires.

9.3.6.4 Thermistor Qualification

The device provides a single thermistor input for battery temperature monitoring.

9.3.6.4.1 JEITA Guideline Compliance During Charging Mode

To improve the safety of charging Li-ion batteries, the JEITA guideline was released on April 20, 2007. The

guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low

and high temperature ranges.

To initiate a charge cycle, the voltage on TS pin, as a percentage of V_REGN, must be within the V_{T1_FALL%}to

V_{T5_RISE%}thresholds. If the TS voltage percentage exceeds the T1-T5 range, the controller suspends charging,

a TS fault is reported and waits until the battery temperature is within the T1 to T5 range.

At cool temperature (T1-T2), the charge current is reduced to a programmable fast charge current (0%, 20%

default, 50%, 100% of I_CHG, by JEITA_ISET). At warm temperature (T3-T5), the charge voltage is reduced to 4.1

V or kept at V_REG(JEITA_VSET). and the charge current can be reduced to a programmable level (0%, 20%,

50%, 100% default). Battery termination is disabled in T3-T5. The charger provides more flexible settings on T2

and T3 threshold as well to program the temperature profile beyond JEITA. When the T1 is set to 0°C and T5 is

set to 60°C, T2 can be programmed to 5.5°C/10°C(default)/15°C/20°C, and T3 can be programmed to 40°C/

45.5°C(default)/50.5°C/54.5°C.

When charger does not need to monitor the NTC, host sets TS_IGNORE bit to 1 to ignore the TS pin condition

during charging and boost mode. If TS_IGNORE bit is set to 1, TS pin is ignored and the charger ignore TS pin

input. In this case, NTC_FAULT bits are 000 to report normal TS status.

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JEITA_WARM_ISET

100% of ICHG

(default)

(0%, 20%, 50%, 100%)

JEITA_VSET

4.1V (default)

(VREG or 4.1V)

JEITA_COOL_ISET

20% of ICHG

(default)

(0%,20%,50%,100%)

T1

0

T2

10 15 20

T3

T5

60

5

25

30 35

40

45 50

Battery Thermistor Temperature (°C)

图 9-5. JEITA Profile

方程式 1 through 方程式 2 describe how to calculate resistor divider values on Ts pin.

REGN

RT1

TS

NTC

103AT

RT2

图 9-6. TS Pin Resistor Network

%

(1)

(2)

%

In the equations above, R_{NTC, T1}is NTC thermistor resistance value at temperature T1 and R_{NTC, T5}is NTC

thermistor resistance values at temperature T5. Select 0°C to 60°C range for Li-ion or Li-polymer battery then

• R_NTC,T1= 27.28 KΩ (0°C)

• R_NTC,T5= 3.02 KΩ (60°C)

• RT1 = 5.3 KΩ

• RT2 = 31.14 KΩ

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9.3.6.4.2 Boost Mode Thermistor Monitor During Battery Discharge Mode

For battery protection during boost mode, the device monitors the battery temperature to be within the V_BCOLD

and V_BHOTthresholds. When RT1 is 5.3 KΩ and RT2 is 31.14 KΩ, T_BCOLDdefault is -19.5°C and T_BHOTdefault

is 64°C. When temperature is outside of the temperature thresholds, the boost mode is suspended. In addition,

VBUS_STAT bits are set to 000 and NTC_FAULT is reported. Once temperature returns within thresholds, boost

mode is recovered and NTC_FAULT is cleared.

9.3.6.5 Charging Safety Timer

The device has a built-in safety timer to prevent extended charging cycle due to abnormal battery conditions.

The safety timer is 2 hours when the battery is below V_BATLOWVthreshold and 10 hours (10/20 hours in

REG05[2] ) when the battery is higher than V_BATLOWVthreshold. When the safety timer expires, STAT pin is

blinking at 1 Hz to report a safety timer expiration fault.

The user can program the fast charge safety timer through I²C (CHG_TIMER bit REG05[2]). When safety timer

expires, the fault register CHRG_FAULT bits (REG09[5:4]) are set to 11 and an INT is asserted to the host. The

safety timer (both fast charge and pre-charge) can be disabled through I²C by setting EN_TIMER bit.

During IINDPM/VINDPM regulation, thermal regulation, or JEITA cool/warm when fast charge current is

reduced,the safety timer counts at a half clock rate, because the actual charge current is likely below the setting.

For example, if the charger is in input current regulation (IINDPM_STAT = 1) throughout the whole charging

cycle, and the safety time is set to 10 hours, the safety timer will expire in 20 hours. This half clock rate feature

can be disabled by writing 0 to the TMR2X_EN bit.

During faults of BAT_FAULT, NTC_FAULT that lead to charging suspend, safety timer is suspended as well.

Once the fault goes away, timer resumes. If user stops the current charging cycle, and start again, timer gets

reset (toggle CE pin or CHG_CONFIG bit).

9.3.7 Ship Mode and QON Pin

9.3.7.1 BATFET Disable (Enter Ship Mode)

To extend battery life and minimize power when the system is powered off during system idle, shipping, or

storage, the device turns off BATFET so that the system voltage is floating to minimize the battery leakage

current. When the host sets the BATFET_DIS bit, the charger can turn off the BATFET immediately or delay by

t_{BATFET_DLY}as configured by the BATFET_DLY bit. To set the device into ship mode with the adapter present, the

host has to first set BATFET_RST_VBUS to 1 and then BATFET_DIS to 1. The charger will turn off the BATFET

(no charging, no supplement) while the adapter is still attached. When the adapter is removed, the charger will

enter ship mode.

9.3.7.2 BATFET Enable (Exit Ship Mode)

When the BATFET is disabled (in ship mode) as indicated by setting BATFET_DIS, one of the following events

can enable the BATFET to restore system power:

1. Plug in adapter

2. Clear BATFET_DIS bit

3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)

4. A logic high to low transition on QON pin with t_SHIPMODEdeglitch time to enable BATFET to exit ship mode.

EN_HIZ bit is set to 1 (regardless of adapter present or not). Host has to set EN_HIZ bit to 0 before boost

mode enable. Once adapter plugs in, EN_HIZ will be cleared.

9.3.7.3 BATFET Full System Reset

The BATFET functions as a load switch between battery and system when input source is not plugged–in.

When BATFET_RST_EN=1 and BATFET_DIS=0, BATFET full system reset function is enabled. By changing the

state of BATFET from on to off, systems connected to SYS can be effectively forced to have a power-on-reset.

The QON pin supports push-button interface to reset system power without host by changing the state of

BATFET. Internally, it is pulled up to the V_QONvoltage through a 200-kΩ resistor.

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When the QON pin is driven to logic low for t_{QON_RST}, BATFET reset process starts. The BATFET is turned off

for t_{BATFET_RST}and then it is re-enabled to reset system power. This function can be disabled by setting

BATFET_RST_EN bit to 0.

BATFET full system reset functions either with or without adapter present. If BATFET_RST_WVBUS=1, the

system reset function starts after t_{QON_RST}when QON pin is pushed to LOW. Once the reset process starts, the

device first goes into HIZ mode to turn off the converter, and then power cycles BATFET. If

BATFET_RST_WVBUS=0, the system reset function doesn't start till t_{QON_RST}after QON pin is pushed to LOW

and adapter is removed.

After BATFET full system reset is complete, the device will power up again if EN_HIZ is not set to 1 before the

system reset.

Adapter

SYS

Q4

Control

/QON

VQON

tBATFET_DLY

tSHIPMODE

ON

BATFET Q4

OFF

/QON

Enter Shipmode

after BATFET_DIS=1

Exit Shipmode

with /QON

BATFET_RS

T_WVBUS

Adapter

/QON

Q4

tQON_RST

ON

OFF

tBATFET_RST

Enter HIZ tBATFET_RST

Enter HIZ

tBATFET_RST

BATFET Reset with

BATFET_RST_WVBUS=0

BATFET Reset with

BATFET_RST_WVBUS=1

图 9-7. QON Timing

9.3.8 Status Outputs ( STAT, INT )

9.3.8.1 Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED.

表 9-5. STAT Pin State

CHARGING STATE

STAT INDICATOR

LOW

Charging in progress (including recharge)

Charging termination (top off timer may be running)

Sleep mode, charge disable, boost mode

HIGH

Charge suspend (input over-voltage, TS fault, safety timer fault or system over-voltage)

Blinking at 1 Hz

9.3.8.2 Interrupt to Host ( INT)

In some applications, the host does not always monitor the charger operation. The INT pulse notifies the host on

the device operation. The following events will generate a 256-μs INT pulse.

• Good input source detected

– V_VBUSabove battery (not in sleep)

– V_VBUSbelow V_ACOVthreshold

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– V_VBUSabove V_POORSRC(typical 3.8 V) when I_BADSRC(typical 30 mA) current is applied (not a poor source)

• Input adapter removed

• USB/adapter source identified during Input Source Type Detection (IINDPM Threshold).

• Charge complete

• Any FAULT event in REG09

• VINDPM / IINDPM event detected (REG0A[1:0], maskable)

• Top off timer starts and expires

REG09[7:0] and REG0A[6:4] report charger operation faults and status change to the host. When a fault/status

change occurs, the charger sends out an INT pulse and keeps the state in REG09[7:0]/REG0A[6:4] until the host

reads the registers. Before the host reads REG09[7:0]/REG0A[6:4] and all the ones are cleared, the charger

would not send any INT upon new fault/status change. To read the current status, the host has to read REG09/

REG0A two times consecutively. The first read reports the pre-existing register status and the second read

reports the current register status.

9.3.9 Protections

9.3.9.1 Voltage and Current Monitoring in Buck Mode

9.3.9.1.1 Input Over-Voltage Protection (ACOV)

The input voltage is sensed via the VAC pin. The default OVP threshold is 14.2-V, and can be programmed at

5.7 V/6.4 V/11 V/14.2 V via OVP[1:0] register bits . ACOV event will immediately stop converter switching

whether in buck or boost mode. The device will automatically resume normal operation once the input voltage

drops back below the OVP threshold. During ACOV, REGN LDO is on, and the device doesn't enter HIZ mode.

During ACOV, the fault register CHRG_FAULT bits are set to 01. An INT pulse is asserted to the host.

9.3.9.1.2 System Over-Voltage Protection (SYSOVP)

The charger device clamps the system voltage during a load transient so that the components connected to the

system are not damaged due to high voltage. V_{SYS_OVP}threshold is about 300-mV above battery regulation

voltage when battery charging is terminated. Upon SYSOVP, converter stops switching immediately to clamp the

overshoot. The charger pulls 30-mA I_{SYS_LOAD}discharge current to bring down the system voltage.

9.3.9.2 Voltage and Current Monitoring in Boost Mode

9.3.9.2.1 Boost Mode Over-Voltage Protection

When the PMID voltage rises above regulation the target and exceeds V_{BST_OVP}, the device stops switching

immediately and the device exits boost mode and PMID_GOOD is pulled low as well after the boost mode OVP

lasts for 12 ms. Meanwhile, if VAC (and VBUS when shorted to VAC) voltage exceed V_ACOV, the device will exit

boost mode as well. BST_CONFIG bit is set to 0. During boost mode over-voltage, the fault register bit

BOOST_FAULT is set tot 1 to indicate fault in boost operation. An INT is asserted to the host.

9.3.9.3 Thermal Regulation and Thermal Shutdown

9.3.9.3.1 Thermal Protection in Buck Mode

Besides the battery temperature monitor on TS pin, the device monitors the internal junction temperature T_Jto

avoid overheating the chip and limits the IC junction temperature in buck mode. When the internal junction

temperature exceeds thermal regulation limit (110°C), the device lowers down the charge current. During thermal

regulation, the actual charging current is usually below the programmed battery charging current. Therefore,

termination is disabled, the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes

high.

Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface

temperature exceeds T_SHUT150°C. The BATFET and converter is enabled to recover when IC temperature is

130°C. The fault register CHRG_FAULT is set to 10 during thermal shutdown and an INT is asserted to the host.

9.3.9.3.2 Thermal Protection in Boost Mode

Besides the battery temperature monitor on TS pin, The device monitors the internal junction temperature to

provide thermal shutdown during boost mode. When IC junction temperature exceeds T_SHUT150°C, the boost

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mode is disabled by setting BST_CONFIG bit low . When IC junction temperature is below 145°C, the host can

re-enable boost mode.

9.3.9.4 Battery Protection

9.3.9.4.1 Battery Over-Voltage Protection (BATOVP)

The battery over-voltage limit is clamped at 4% above the battery regulation voltage. When battery over-voltage

occurs, the charger device immediately stops switching. The fault register BAT_FAULT bit goes high and an INT

is asserted to the host.

9.3.9.4.2 Battery Over-Discharge Protection

When battery is discharged below V_{BAT_DPL_FALL}, the BATFET will latch off to protect battery from over

discharge. To recover from over-discharge latch-off, an input source plug-in is required at VAC/VBUS.

9.3.9.4.3 System Over-Current Protection

I_{SYS_OCP_Q4}sets battery discharge current limit. Once I_BAT> I_{SYS_OCP_Q4}, charger will latch off Q4 and put the

device into ship mode. All methods to exit ship mode are valid to bring the part out of Q4 latch off.

9.3.10 Serial Interface

The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device

status reporting. I²C^TMis a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP

Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices

can be considered as masters or slaves when performing data transfers. A master is the device which initiates a

data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device

addressed is considered a slave.

The device operates as a slave device with address 6BH , receiving control inputs from the master device like

micro controller or a digital signal processor through REG00-REG0C. Register read beyond REG0C returns

0xFF. The I²C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).

connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines

are HIGH. The SDA and SCL pins are open drain.

9.3.10.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each

data bit transferred.

SDA

SCL

Data line stable;

Data valid

Change of data

allowed

图 9-8. Bit Transfer on the I²C Bus

9.3.10.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the

SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The

bus is considered busy after the START condition, and free after the STOP condition.

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SDA

SCL

SDA

SCL

START (S)

STOP (P)

图 9-9. TS START and STOP conditions

9.3.10.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant

Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some

other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data

transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

Acknowledgement

signal from slave

Acknowledgement

signal from receiver

MSB

1

SDA

SCL

2

7

8

9

1

2

8

9

S or Sr

P or Sr

START or

Repeated

START

STOP or

Repeated

START

ACK

图 9-10. Data Transfer on the I²C Bus

9.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter

that the byte was successfully received and another byte may be sent. All clock pulses, including the

acknowledge ninth clock pulse, are generated by the master. The transmitter releases the SDA line during the

acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH

period of this clock pulse.

When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The master can then

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

9.3.10.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction

bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

SDA

1 - 7

8

9

1-7

8

9

1-7

8

9

S

P

SCL

START

ADDRESS

R / W

ACK

DATA

ACK

DATA

ACK

STOP

图 9-11. Complete Data Transfer

9.3.10.6 Single Read and Write

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

1

7

1

0

1

8

1

8

1

S

Slave Address

ACK

Reg Addr

ACK

Data to Addr

ACK

P

图 9-12. Single Write

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1

7

1

0

1

8

1

7

1

S

Slave Address

ACK

Reg Addr

ACK

S

Slave Addr

ACK

8

1

Data

NCK

P

图 9-13. Single Read

9.3.10.7 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG0C.

1

7

1

0

1

8

1

S

Slave Address

ACK

Reg Addr

ACK

8

1

8

1

8

1

Data to Addr

ACK

Data to Addr + N

ACK

Data to Addr + N

ACK

P

图 9-14. Multi-Write

1

7

1

8

1

7

1

S

Slave Address

0

ACK

Reg Addr

ACK

S

Slave Address

ACK

8

1

8

1

8

1

Data @ Addr

ACK

Data @ Addr + 1

ACK

Data @ Addr + N NCK

P

图 9-15. Multi-Read

REG09[7:0]/REG0A[6:4] are fault/status change register. They keep all the fault/status information from last read

until the host issues a new read. For example, if Charge Safety Timer Expiration fault occurs but recovers later,

the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the

second time. In order to get the fault information at present, the host has to read REG09/REG0A for the second

time.

9.4 Device Functional Modes

9.4.1 Host Mode and Default Mode

The device is a host controlled charger, but it can operate in default mode without host management. In default

mode, the device can be used an autonomous charger with no host or while host is in sleep mode. When the

charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode,

WATCHDOG_FAULT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the

registers are in the default settings.

All the device parameters can be programmed by the host. To keep the device in host mode, the host has to

reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT

bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.

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POR

watchdog timer expired

Reset registers

I2C interface enabled

Host Mode

Start watchdog timer

Host programs registers

Y

I2C Write?

N

Default Mode

Reset watchdog timer

Reset selective registers

Y

WD_RST bit = 1?

N

Y

N

I2C Write?

Watchdog Timer

Expired?

图 9-16. Watchdog Timer Flow Chart

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9.5 Register Maps

I²C Slave Address: 6BH

Default I²C Slave Address: 0x6B (1101 011B + R/ W)

表 9-6. I²C Registers

Address

00h

Access Type

Acronym

REG00

REG01

REG02

REG03

REG04

REG05

REG06

REG07

REG08

REG09

REG0A

REG0B

REG0C

Register Name

Section

Go

R/W

R

Input Current Limit

Charger Control 0

Charge Current Limit

pre-charge and Termination Current Limit

Battery Voltage Limit

Charger Control 1

Charger Control 2

Charger Control 3

Charger Status 0

01h

Go

02h

Go

03h

Go

04h

Go

05h

Go

06h

Go

07h

Go

08h

Go

09h

R

Charger Status 1

Go

0Ah

0Bh

0Ch

R

Charger Status 2

Go

R

Part Information

Go

R/W

Charger Control 4

Go

Complex bit access types are encoded to fit into small table cells. 表 9-7 shows the codes that are used for

access types in this section.

表 9-7. I²C Access Type Codes

Access Type

Code

Description

Read Type

R

Read

Write Type

W

Write

Reset Value

-n

Value after reset

Undefined value

-X

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9.5.1 Input Current Limit Register (Address = 00h) [reset = 17h]

图 9-17. REG00 Register

7

0

6

0

5

0

4

3

2

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-8. REG00 Field Descriptions

Bit

Field

POR

Type

R/W

Reset

Description

HIZ mode enable in buck mode.

0 – Disable (default)

1 – Enable

by REG_RST

by Watchdog

7

EN_HIZ

0

When charger does not monitor the NTC, host sets this bit to 1 to

ignore the TS pin condition during charging and boost mode.

0 – Include TS pin into charge and boost mode enable

6

TS_IGNORE

0

by REG_RST conditions. (default)

1 – Ignore TS pin. Always consider TS is good to allow charging

and boost mode. NTC_FAULT bits are 000 to report normal

status.

R/W

Select either BATSNS pin or BAT pin to regulate battery voltage.

0 – Enable BATSNS in battery CV regulation. If the device fails

by REG_RST BATSNS open/short detection (BATSNS_STAT = 1). Battery

voltage is regulated through BAT pin. (default)

5

BATSNS_DIS

0

1 – Disable BATSNS. Use BAT pin in battery CV regulation.

4

3

2

1

IINDPM[4]

IINDPM[3]

IINDPM[2]

IINDPM[1]

1

0

1

R/W

by REG_RST 1600 mA

by REG_RST 800 mA

by REG_RST 400 mA

by REG_RST 200 mA

Input current limit setting (maximum limit, not

typical)

Offset: 100 mA

Range: 100 mA (000000) – 3.2 A (11111)

Default: 2400 mA (10111)

IINDPM bits are changed automatically after

Onput Source Type Detection (IINDPM

Threshold) is completed

USB SDP = 500 mA

USB CDP = 1.5 A

USB DCP = 2.4 A

0

IINDPM[0]

1

R/W

by REG_RST 100 mA

Unknown Adapter = 500 mA

Non-Standard Adapter = 1 A, 2 A, 2.1 A, or

2.4

Host can reprogram IINDPM register bits after

input source detection is completed.

LEGEND: R/W = Read/Write; R = Read only

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9.5.2 Charger Control 0 Register (Address = 01h) [reset = 1Ah]

图 9-18. REG01 Register

7

0

6

0

5

0

4

3

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-9. REG01 Field Descriptions

Bit Field

POR Type Reset

Description

PFM disable in both buck and boost mode.

by REG_RST 0 – PFM enable (default)

1 – PFM disable

R/W

7

6

PFM_DIS

0

I²C Watchdog timer reset. Back to 0 after watchdog timer reset

0 – Normal (default)

1 – Reset

by REG_RST

by Watchdog

WD_RST

Boost mode enable. In charging case application, based on adapter

plug-in or removal, the charger will automatically transit between

charging mode and boost mode by setting BST_CONFIG bit and

CHG_CONFIG bit both to 1.

by REG_RST

by Watchdog

5

BST_CONFIG

0

0 – Boost mode disable (default)

1 – Boost mode enable

R/W

Battery charging buck mode enable. Charging is enabled when CE pin

is pulled low, CHG_CONFIG bit is 1 and charge current is not zero.

by REG_RST

4

CHG_CONFIG

1

by Watchdog 0 – Charge Disable

1 – Charge Enable (default)

3

2

SYS_MIN[2]

SYS_MIN[1]

1

0

R/W by REG_RST System minimum voltage setting.

000 – 2.6 V

001 – 2.8 V

R/W by REG_RST

R/W

010 – 3 V

011 – 3.2 V

100 – 3.4 V

101 – 3.5 V (default)

110 – 3.6 V

1

0

SYS_MIN[0]

1

0

by REG_RST

111 – 3.7 V

R/W

Minimum battery voltage when exiting boost mode. The rising threshold

allows the device to start boost mode if other conditions are valid.

0 – 2.8V V_BATfalling, 3 V rising (default)

MIN_VBAT_SEL

by REG_RST

1 – 2.5V V_BATfalling, 2.8V rising

LEGEND: R/W = Read/Write; R = Read only

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9.5.3 Charge Current Limit Register (Address = 02h) [reset = 91h]

图 9-19. REG02 Register

7

1

6

0

5

0

4

3

2

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-10. REG02 Field Descriptions

Bit

Field

POR

Type

Reset

Description

R/W

Boost mode current regulation limit (minimum current limit, not

typical).

0 – 0.5 A

by REG_RST

by Watchdog

7

BOOST_LIM

1

1 – 1.2 A (default)

R/W

In buck mode, charger will fully turn on Q1 RBFET according

to this bit setting when IINDPM is below 700 mA. When

IINDPM is over 700 mA, Q1 is always fully on. In boost mode ,

Q1 is always fully on too, regardless of this bit setting.

0 – Partially turn on Q1 for better regulation accuracy when

IINDPM is below 700 mA. (default)

6

Q1_FULLON

0

by REG_RST

1 – Fully turn on Q1 for better efficiency when IINDPM is

below 700 mA.

R/W

by REG_RST

by Watchdog

5

4

3

2

1

0

ICHG[5]

ICHG[4]

ICHG[3]

ICHG[2]

ICHG[1]

ICHG[0]

0

1

0

1

1920 mA

by REG_RST

by Watchdog

960 mA

Fast charge current setting

Default: 1020 mA (010001)

Range: 0 mA (0000000) –

3000 mA (110010)

I_CHG0 mA disables charge.

I_CHG> 3000 mA is clamped to

3000 mA (110010)

by REG_RST

by Watchdog

R/W

480 mA

by REG_RST

by Watchdog

240 mA

120 mA

60 mA

R/W

by REG_RST

by Watchdog

by REG_RST

by Watchdog

LEGEND: R/W = Read/Write; R = Read only

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9.5.4 Pre-charge and Termination Current Limit Register (Address = 03h) [reset = 12h]

图 9-20. REG03 Register

7

0

6

0

5

0

4

3

2

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-11. REG03 Field Descriptions

Bit Field

POR Type Reset

Description

by REG_RST

by Watchdog

7

6

5

4

3

2

1

0

IPRECHG[3]

0

1

0

1

0

R/W

480 mA

Pre-charge current setting

Default: 180 mA (0010)

Range: 60 mA (0000) – 780 mA

(1100)

Offset: 60 mA

Note: I_PRECHG> 780 mA is

clamped to 780 mA (1100)

by REG_RST

by Watchdog

IPRECHG[2]

IPRECHG[1]

IPRECHG[0]

ITERM[3]

240 mA

120 mA

60 mA

by REG_RST

by Watchdog

by REG_RST

by Watchdog

by REG_RST

by Watchdog

480 mA

240 mA

120 mA

60 mA

by REG_RST

by Watchdog

Termination current setting

Default: 180 mA (0010)

Range: 60 mA – 780 mA (1100)

Offset: 60 mA

ITERM[2]

by REG_RST

by Watchdog

ITERM[1]

by REG_RST

by Watchdog

ITERM[0]

LEGEND: R/W = Read/Write; R = Read only

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9.5.5 Battery Voltage Limit Register (Address = 04h) [reset = 40h]

图 9-21. REG04 Register

7

0

6

1

5

0

4

3

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-12. REG04 Field Descriptions

Bit Field

POR Type Reset

Description

by REG_RST Battery voltage setting, also called V_REG

by Watchdog Default: 4.190 V (01000)

.

7

6

5

4

VBATREG[4]

0

1

0

R/W

00000 – 3.494 V

00001 – 3.590 V

00010 – 3.686 V

00011 – 3.790 V

by REG_RST

by Watchdog

VBATREG[3]

VBATREG[2]

VBATREG[1]

by REG_RST

by Watchdog

00100 – 3.894 V

by REG_RST

by Watchdog

00101 – 3.990 V

00110 – 4.090 V

00111 – 4.140 V

01000 – 4.190 V

by REG_RST

3

VBATREG[0]

0

R/W

by Watchdog 01001 - 11111 – 4.290 V - 4.510 V, 10 mV/step

01110 4.340 V, 10011 4.390V, 11000 4.440 V, 11101 4.490 V

by REG_RST Top-off timer setting.

2

1

TOPOFF_TIMER[1]

TOPOFF_TIMER[0]

0

R/W

by Watchdog

00 – Disabled (Default)

01 – 15 minutes

by REG_RST

by Watchdog

10 – 30 minutes

11 – 45 minutes

by REG_RST Battery recharge threshold setting.

by Watchdog

0

VRECHG

0

R/W

0 – 120 mV (default)

1 – 210 mV

LEGEND: R/W = Read/Write; R = Read only

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9.5.6 Charger Control 1 Register (Address = 05h) [reset = 9Eh]

图 9-22. REG05 Register

7

1

6

0

5

0

4

3

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-13. REG05 Field Descriptions

Bit

Field

POR

Type

Reset

Description

Battery charging termination enable.

0 – Disable

1 – Enable (default)

by REG_RST

by Watchdog

7

EN_TERM

1

R/W

by REG_RST

by Watchdog

6

5

Reserved

0

R/W

Reserved

by REG_RST Watchdog timer setting.

by Watchdog

WATCHDOG[1]

00 – Disable timer

01 – 40 s (default)

10 – 80 s

by REG_RST

by Watchdog

4

3

WATCHDOG[0]

EN_TIMER

1

R/W

11 – 160 s

Battery charging safety timer enable, including both fast

charge and pre-charge timers. Pre-charge timer is 2 hours.

Fast charge timer is set by REG05[2]

0 – Disable

by REG_RST

by Watchdog

1 – Enable timer (default)

Battery fast charging safety timer setting.

0 – 20 hrs

1 – 10 hrs (default)

by REG_RST

by Watchdog

2

1

CHG_TIMER

TREG

1

R/W

Thermal Regulation Threshold:

0 – 90°C

1 – 110°C (default)

by REG_RST

by Watchdog

Battery voltage setting during JEITA warm (T3 - T5,

typically 45C - 60C)

by Watchdog 0 – Set Charge Voltage to 4.1 V (max) (default)

by REG_RST

0

JEITA_VSET (45C-60C)

0

R/W

1 – Set Charge Voltage to V_REG

LEGEND: R/W = Read/Write; R = Read only

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9.5.7 Charger Control 2 Register (Address = 06h) [reset = E6h]

图 9-23. REG06 Register

7

1

6

1

5

1

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-14. REG06 Field Descriptions

Bit Field

POR Type Reset

Description

7

6

5

4

OVP[1]

1

0

R/W by REG_RST V_ACOVthreshold during buck mode and boost mode.

00 – 5.85 V

01 – 6.4 V (5-V input)

10 – 11 V (9-V input)

OVP[0]

R/W by REG_RST

11 – 14.2 V (12-V input) (default)

BOOSTV[1]

BOOSTV[0]

R/W by REG_RST Boost regulation voltage setting

00 – 4.6 V

01 – 4.75 V

10 – 5.0 V (default)

R/W by REG_RST

11 – 5.15 V

3

2

1

0

VINDPM[3]

VINDPM[2]

VINDPM[1]

VINDPM[0]

0

1

0

R/W by REG_RST 800 mV

R/W by REG_RST 400 mV

R/W by REG_RST 200 mV

R/W by REG_RST 100 mV

VINDPM threshold setting

Default: 4.5 V (0110)

Range: 3.9 V (0000) – 5.4 V

(1111)

Offset: 3.9 V

LEGEND: R/W = Read/Write; R = Read only

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9.5.8 Charger Control 3 Register (Address = 07h) [reset = 4Ch]

图 9-24. REG07 Register

7

0

6

1

5

0

4

3

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-15. REG07 Field Descriptions

Bit Field

POR Type Reset

Description

Force input source type detection. After the detection is complete, this

bit returns to 0.

by Watchdog 0 – Not in input current limit detection. (default)

1 – Force input current limit detection when adapter is present.

by REG_RST

7

6

IINDET_EN

0

1

R/W

Safety timer is slowed by 2X during input DPM, JEITA cool/warm or

thermal regulation.

by REG_RST

TMR2X_EN

0 – Disable. Safety timer duration is set by REG05[2].

by Watchdog

1 – Safety timer slowed by 2X during input DPM (both V and I) or

JEITA cool/warm (except I_CHG=100%), or thermal regulation. (default)

BATFET Q4 ON/OFF control. Set this bit to 1 to enter ship mode. To

reset the device with adapter present, the host shall set

BATFET_RST_WVBUS to 1 and then BATFET_DIS to 1.

0 – Turn on Q4. (default)

1 – Turn off Q4 after t_{BATFET_DLY}delay time (REG07[3])

5

4

3

BATFET_DIS

0

1

R/W by REG_RST

Start BATFET full system reset with or without adapter present.

0 – Start BATFET full system reset after adapter is removed from

VBUS. (default)

BATFET_RST_WVBUS

BATFET_DLY

1 – Start BATFET full system reset when adapter is present on VBUS.

Delay from BATFET_DIS (REG07[5]) set to 1 to BATFET turn off during

ship mode.

R/W by REG_RST 0 – Turn off BATFET immediately when BATFET_DIS bit is set.

1 – Turn off BATFET after t_{BATFET_DLY}(typ 10 s) when BATFET_DIS bit

is set. (default)

Enable BATFET full system reset. The time to start of BATFET full

system reset is based on the setting of BATFET_RST_WVBUS bit.

by REG_RST

by Watchdog 0 – Disable BATFET reset function

1 – Enable BATFET reset function when REG07[5] is also 1. (default)

2

1

BATFET_RST_EN

1

0

R/W

VINDPM_BAT_TRACK[1]

R/W by REG_RST Sets VINDPM to track BAT voltage. Actual VINDPM is higher of register

value and V_BAT+ VINDPM_BAT_TRACK.

00 – Disable function (VINDPM set by register) (default)

01 – V_BAT+ 200 mV

10 – V_BAT+ 250 mV

11 – V_BAT+ 300 mV

0

VINDPM_BAT_TRACK[0]

0

R/W by REG_RST

LEGEND: R/W = Read/Write; R = Read only

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9.5.9 Charger Status 0 Register (Address = 08h)

图 9-25. REG08

7

x

6

x

5

x

4

3

2

x

1

x

0

x

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-16. REG08 Field Descriptions

Bit Field

POR Type

Reset

Description

7

6

5

4

VBUS_STAT[2]

x

R

NA

VBUS Status register

Software current limit is reported in IINDPM register

VBUS_STAT[1]

VBUS_STAT[0]

CHRG_STAT[1]

NA

Charging status:

00 – Not Charging

01 – Pre-charge or trickle charge (< V_BATLOWV

10 – Fast Charging

)

3

CHRG_STAT[0]

x

R

NA

11 – Charge Termination

2

1

Reserved

x

R

NA

Reserved

0 – Not in thermal regulation

1 – In thermal regulation

THERM_STAT

0 – Not in SYS_MIN regulation (V_BAT> V_{SYS_MIN}

)

0

VSYS_STAT

x

R

NA

1 – In SYS_MIN regulation (V_BAT< V_{SYS_MIN}

)

LEGEND: R/W = Read/Write; R = Read only

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9.5.10 Charger Status 1 Register (Address = 09h)

图 9-26. REG09 Register

7

1

6

x

5

x

4

3

2

x

1

x

0

x

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-17. REG09 Field Descriptions

Bit Field

POR Type Reset

Description

0 – Normal, device is in host mode,

7

WATCHDOG_FAULT

1

R

NA

1 – Watchdog timer expiration, device is in default mode.

0 – Normal

1 – Fault detected in boost mode (any conditions that are not valid for

boost operation), including VBUS overloaded (BST_OVP) or battery is

too low (BST_BAT)

6

BOOST_FAULT

x

5

4

CHRG_FAULT[1]

CHRG_FAULT[0]

x

R

NA

00 – Normal

01 – Input fault

10 – Thermal shutdown

11 – Charge safety timer expiration

0 – Normal,

1 – Battery over voltage.

3

BAT_FAULT

x

R

NA

2

1

NTC_FAULT[2]

NTC_FAULT[1]

x

R

NA

TS fault in buck mode

000 – Normal

010 – Warm

011 – Cool

101 – Cold

110 – Hot

0

NTC_FAULT[0]

x

R

NA

TS fault in boost mode

000 – Normal

101 – Cold

110 – Hot

LEGEND: R/W = Read/Write; R = Read only

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9.5.11 Charger Status 2 Register (Address = 0Ah)

图 9-27. REG0A Register

7

x

6

x

5

x

4

3

2

x

1

0

x

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-18. REG0A Field Descriptions

Bit Field

POR Type Reset

Description

0 – VBUS does not pass poor source detection

1 – VBUS passes poor source detection

7

6

5

VBUS_GD

x

R

NA

0 – Not in VINDPM

1 – In VINDPM

VINDPM_STAT

IINDPM_STAT

0 – Not in IINDPM

1 – In IINDPM

0 – BATSNS pin is in good connection. Regulation battery voltage

through BATSNS pin.

1 – BATSNS pin is open/short. Regulate battery voltage through BAT

4

BATSNS_STAT

x

R

NA

pin.

0 – Top off timer not counting.

1 – Top off timer counting

3

2

TOPOFF_ACTIVE

ACOV_STAT

x

R

NA

0 – Not in ACOV

1 – In ACOV

Allow or block INT pulse assertion to host during VINDPM.

1

0

VINDPM_INT_ MASK

IINDPM_INT_ MASK

0

R/W by REG_RST 0 – INT is asserted to host during VINDPM (default)

1 – No INT pulse asserted to host during VINDPM

Allow or block INT pulse assertion to host during IINDPM

R/W by REG_RST 0 – INT is asserted to host during IINDPM (default)

1 – No INT pulse asserted to host during IINDPM

LEGEND: R/W = Read/Write; R = Read only

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9.5.12 Part Information Register (Address = 0Bh)

图 9-28. REG0B Register

7

0

6

1

5

0

4

3

2

1

0

1

0

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-19. REG0B Field Descriptions

Bit Field

POR Type Reset

Description

Register reset

0 – Keep current register setting (default)

1 – Reset to default register value and reset safety timer. This bit

7

REG_RST

0

R/W NA

returns to 0 after register reset is completed.

6

5

4

3

2

PN[3]

1

0

1

0

1

R

NA

PN[2]

BQ25611D: 1010

PN[1]

PN[0]

Reserved

1

0

R

NA

Reserved

LEGEND: R/W = Read/Write; R = Read only

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9.5.13 Charger Control 4 Register (Address = 0Ch) [reset = 75h]

图 9-29. REG0C

7

0

6

1

5

1

4

3

2

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9-20. REG0C Field Descriptions

Bit Field

POR Type Reset

Description

by REG_RST Fast charge current setting during cool temperature range (T1 - T2), as

by Watchdog percentage of I_CHGin REG02[5:0].

00 – No Charge

7

6

5

4

JEITA_COOL_ISET [1]

0

1

R/W

01 – 20% of I_CHG(default)

10 – 50% of I_CHG

11 – 100% of I_CHG(safety timer does not become 2X)

by REG_RST

by Watchdog

JEITA_COOL_ISET [0]

JEITA_WARM_ISET [1]

JEITA_WARM_ISET [0]

by REG_RST Fast charge current setting during warm temperature range (T3 - T5), as

by Watchdog percentage of I_CHGin REG02[5:0].

00 – No Charge

01 – 20% of I_CHG

10 – 50% of I_CHG

11 – 100% of I_CHG(safety timer does not become 2X) (default)

by REG_RST

by Watchdog

by REG_RST

by Watchdog

00 – VT2% = 70.75% (5.5°C)

01 – VT2% = 68.25% (10°C) (default)

10 – VT2% = 65.25% (15°C)

11 – VT2% = 62.25% (20°C)

3

2

1

0

JEITA_VT2 [1]

JEITA_VT2 [0]

JEITA_VT3 [1]

JEITA_VT3 [0]

0

1

0

1

R/W

by REG_RST

by Watchdog

by REG_RST

by Watchdog

00 – VT3% = 48.25% (40°C)

01 – VT3% = 44.75% (44.5°C) (default)

10 – VT3% = 40.75% (50.5°C)

11 – VT3% = 37.75% (54.5°C)

by REG_RST

by Watchdog

LEGEND: R/W = Read/Write; R = Read only

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

A typical application consists of the device configured as an I²C controlled Power Path management device and

a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smart phones and other

portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),

low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The

device also integrates a bootstrap diode for the high-side gate drive.

10.2 Typical Application

VAC

SYSTEM

INPUT

1µH

3.5V œ 4.52V

3.9V œ 14V

SW

VBUS

Q1

1µF

Q2

10µF

BTST

47nF

Q3

REGN

PMID

4. 7µF

10µF

PGND

SYS

Q4

STAT

VREF

BAT

10µF

BATSNS

SDA

SCL

INT

REGN

Host

TS

+

CE

QON

D+

D-

USB

Optional

BQ25611D

图 10-1. BQ25611D Application Diagram

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10.2.1 Design Requirements

For this design example, use the parameters shown in the table below.

表 10-1. Design Parameters

PARAMETER

VALUE

4 V to 13.5 V

2.4 A

V_VBUSvoltage range

Input current limit (REG00[4:0] )

Fast charge current limit (REG02[5:0] )

Minimum system voltage (REG01[3:1])

Battery regulation voltage (REG04[7:3] )

1.024 A

3.5 V

4.2 V

10.2.2 Detailed Design Procedure

10.2.2.1 Inductor Selection

The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor

saturation current higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

I_SAT≥ I_CHG+ (1/2) I_RIPPLE

(3)

The inductor ripple current depends on the input voltage (V_VBUS), the duty cycle (D = V_BAT/V_VBUS), the switching

frequency (f_S) and the inductance (L).

V_IN´D ´ (1- D)

=

I_RIPPLE

fs ´ L

(4)

The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually

inductor ripple is designed in the range between 20% and 40% maximum charging current as a trade-off

between inductor size and efficiency for a practical design.

10.2.2.2 Input Capacitor and Resistor

Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The

worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not

operate at 50% duty cycle, then the worst case capacitor RMS current I_CINoccurs where the duty cycle is closest

to 50% and can be estimated using 方程式 5.

I_CIN= I_CHG´ D ´ (1- D)

(5)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage

rating of the capacitor must be higher than normal input voltage level. A rating of 25-V or higher capacitor is

preferred for 12-V input voltage. Capacitance of minimum 10 μF is suggested for typical of 3-A charging current.

During high current output over 700 mA in boost mode, a 10-kΩ pull-down resistor on VBUS is recommended to

keep VBUS low in case Q1 RBFET leakage gets high.

10.2.2.3 Output Capacitor

Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.

方程式 6 shows the output capacitor RMS current I_COUTcalculation.

I_RIPPLE

I_COUT

=

» 0.29 ´ I_RIPPLE

2 ´

3

(6)

The output capacitor voltage ripple can be calculated as follows:

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æ

ç

è

ö

V_OUT

8LCfs²

V_OUT

V

DV_O=

1-

÷

^INø

(7)

At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the

output filter LC.

The charger device has internal loop compensation optimized for > 10-μF ceramic output capacitance. The

preferred ceramic capacitor is 10-V rating, X7R or X5R.

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10.3 Application Curves

V_VBUS= 5 V

V_BAT= 3.2 V

V_VBAT= 3.2 V

图 10-2. Power Up

图 10-3. System Reset by QON without VBUS

Present

I_CHG= 0.5 A

V_VBUS= 5 V

V_BAT= 3.2 V

I_SYS= 0 - 2 A

I_CHG= 1.5 A

V_VBUS= 5 V

V_BAT= 3.7 V

IINDPM = 1 A

图 10-4. System Reset by QON with VBUS Present

图 10-5. System Load Transient Response

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V_VBUS= 5 V

V_BAT= 3.7 V

IINDPM = 2 A

V_VBUS= 5 V

V_BAT= 3.7 V

IINDPM = 1 A

I_SYS= 0 – 2 A

I_SYS= 0 – 4 A

I_CHG= 1 A

I_CHG= 1.5 A

图 10-6. System Load Transient Respose

图 10-7. System Load Transient Response

V_VBUS= 5 V

V_BAT= 3.7 V

IINDPM = 2 A

I_SYS= 0 – 4 A

I_CHG= 1.5 A

图 10-8. System Load Transient Response

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11 Power Supply Recommendations

In order to provide an output voltage on SYS, the battery charger requires a power supply between 4-V and

13.5-V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion battery with battery

voltage greater than V_{BAT_UVLOZ}connected to BAT. The source current rating needs to be at least 3-A in order

for the buck converter of the charger to provide maximum output power to SYS.

12 Layout

12.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see 图 12-1) is important to prevent electrical and

magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the

proper layout.

1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper

trace connection or GND plane. Add 1 nF small size (such as 0402 or 0201) decoupling cap for high

frequency noise filter and EMI improvement.

2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower

electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not

use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other

trace or plane.

3. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC ground

with a short copper trace connection or GND plane.

4. Route analog ground separately from power ground. Connect analog ground and connect power ground

separately. Connect analog ground and power ground together using thermal pad as the single ground

connection point. Or using a 0-Ω resistor to tie analog ground to power ground.

5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the

device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.

6. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.

7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB

ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on

the other layers.

8. Ensure that the number and sizes of vias allow enough copper for a given current path.

See the BQ25619 BMS025 Evaluation Module EVM User's Guide for the recommended component placement

with trace and via locations. For the VQFN information, refer to Quad Flatpack No-Lead Logic Packages

Application Report and QFN and SON PCB Attachment Application Report.

12.2 Layout Example

+

œ

图 12-1. High Frequency Current Path

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图 12-2. Layout Example

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13 Device and Documentation Support

13.1 Device Support

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

• BQ25619 BMS025 Evaluation Module User's Guide

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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15-Sep-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ25611DRTWR

BQ25611DRTWT

WQFN

RTW

24

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Sep-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ25611DRTWR

BQ25611DRTWT

WQFN

RTW

24

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RTW 24

4 x 4, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224801/A

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ25611DRTWT
厂家：	TEXAS INSTRUMENTS
描述：	具有 USB 检测功能和 1.2A 升压操作的 I2C 控制型单节 3A 降压型电池充电器 \| RTW \| 24 \| -40 to 85 电池
文件：	总63页 (文件大小：3561K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ25611DRTWT [TI]

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