BQ25886RGET [TI]
具有电源路径且适用于 USB 输入的独立型 2 节 2A 升压电池充电器 | RGE | 24 | -40 to 85;
| 型号： | BQ25886RGET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源路径且适用于 USB 输入的独立型 2 节 2A 升压电池充电器 | RGE | 24 | -40 to 85 电池 |
| 文件： | 总43页 (文件大小：4093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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BQ25886
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
具备 PowerPath、USB BC1.2 检测和 USB On-the-Go (OTG) 升压式的
BQ25886 独立式 2 节电池、2A 升压模式电池充电器
1 特性
2 应用
1
•
高效的 2A、1.5MHz 开关模式升压充电器
•
•
•
•
•
无线扬声器
智能扬声器
–
在 5V 适配器、7.6V 电池、充电电流为 1A 下
的充电效率为 93.4%
EPOS 打印机
便携式 POS
IP 网络摄像头
–
针对 USB 输入和 2 节锂离子电池进行了优化
•
单个输入，支持 USB 输入适配器
–
–
–
支持 4.3V 至 6.2V 的输入电压范围，绝对最大
输入电压额定值为 20V
3 说明
输入电流限制（500mA 至 3.3A），支持
USB2.0、USB3.0 标准适配器
BQ25886 是一款高度集成的 2A 升压式开关模式电池
充电管理以及能实现即时通电并提供精确终端控制的系
统 PowerPath 管理器件，适用于 2 节 (2s) 锂离子和锂
聚合物电池。 BQ25886 是具有 PowerPath 和 OTG
功能的独立解决方案。
集成式 USB D+/D- 自动检测 USB SDP、
CDP、DCP 以及非标准适配器
•
独立功能，具有 PowerPath 管理功能
–
采用 17mΩ 电池放电 MOSFET，具有较高的电
池放电效率
器件信息(1)
器件型号
BQ25886
封装
封装尺寸（标称值）
–
窄 VDC (NVDC) PowerPath 管理
VQFN (24)
4.00mm x 4.00mm
–
–
无需电池或深度放电的电池即可瞬时启动
电池充电模式下实现理想的二极管运行
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
–
–
–
通过 VSET 引脚可调的充电电压支持 8.2V、
8.4V、8.7V 和 8.8V
简化原理图
通过 ICHGSET 引脚可调的充电电流支持 100
至 2200mA
5V @ 3A
VREF
STAT
/PG
VBUS
PMID
通过 ILIM 引脚可调的输入电流限制
SYSTEM
LOAD
•
输入电流优化器 (ICO)，无需过载适配器即可最大
限度地提高输入功率
6.0V to 8.8V
SYS
BAT
SW
ICHG=2A
•
•
高集成度包括所有 MOSFET、电流检测和环路补偿
BTST
高精度
REGN
–
–
–
±0.5% 充电电压调节
±5% 充电电流调节
±7.5% 输入电流调节
D+
D-
VREGN
Host
OTG
/CE
•
安全
TS
–
–
在充电下的电池温度检测
热调节和热关断
BQ25886
ILIM
`
VSET
GND
ICHGSET
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSD88
BQ25886
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 24
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 25
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements.............................................. 10
7.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
9
10 Power Supply Recommendations ..................... 31
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 32
12 器件和文档支持 ..................................................... 33
12.1 器件支持 ............................................................... 33
12.2 文档支持................................................................ 33
12.3 接收文档更新通知 ................................................. 33
12.4 社区资源................................................................ 33
12.5 商标....................................................................... 33
12.6 静电放电警告......................................................... 33
12.7 Glossary................................................................ 33
13 机械、封装和可订购信息....................................... 34
8
4 修订历史记录
Changes from Original (March 2019) to Revision A
Page
•
已更改 将“预告信息”更改为“生产数据”.................................................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
BQ25886
www.ti.com.cn
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
5 Device Comparison Table
Table 1. Device Comparison
PART NUMBER
VBUS Operating Range
USB Detection
PowerPath
BQ25882
BQ25883
3.9 to 6.2 V
D+/D-
BQ25886
4.3 to 6.2 V
D+/D-
BQ25887
3.9 to 6.2 V
PSEL
3.9 to 6.2 V
D+/D-
Yes
Yes
Yes
No
Cell Balancing
OTG
No
No
No
Yes
Up to 2 A
Yes
Up to 2 A
Yes
Up to 2 A
No
No OTG
Yes
16 bit ADC
Control Interface
Status Pin
I2C
I2C
Standalone
STAT, /PG
4x4 QFN-24
I2C
/PG
STAT, /PG
4x4 QFN-24
STAT, /PG
4x4 QFN-24
Package
2.1x2.1 WCSP-25
Copyright © 2019, Texas Instruments Incorporated
3
BQ25886
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
www.ti.com.cn
6 Pin Configuration and Functions
RGE Package (Standalone)
24-Pin VQFN
Top View
24
23
22
21
20
19
1
18
17
16
15
14
13
D-
SW
SW
SYS
SYS
2
STAT
3
/CE
BQ25886
RGE, 4x4
4
GND
5
OTG
BAT
BAT
VSET
6
7
8
9
10
11
12
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Positive USB data line – D+/D– based USB host/charging port detection. The detection includes
data contact detection (DCD) and secondary detection in BC1.2.
D+
24
AIO
AIO
Negative USB data line – D+/D– based USB host/charging port detection. The detection includes
data contact detection (DCD) and secondary detection in BC1.2.
D–
1
2
Open drain charge status indicator – Connect to the pull-up rail via 10-kΩ resistor. LOW indicates
charge in progress. HIGH indicates charge complete or charge disabled. When any fault occurs, the
STAT pin blinks at 1Hz.
STAT
DO
Active Low Charge Enable Pin – Battery charging is enabled when CE pin is LOW. CE pin is
internally pulled low with 900k-Ω resistor.
CE
3
5
DI
DI
OTG – USB On-The-Go Enable input. Pull high to enable OTG function. Pull low to disable OTG
function.
OTG
Battery Charge Voltage Limit – VSET pin sets battery charge voltage. Program battery regulation
voltage with a resistor pull-down from VSET to GND as follows:
RVSET< 18kΩ (short to GND) = 8.2 V
RVSET= 39kΩ (±10%) = 8.8 V
RVSET= 75kΩ (±10%) = 8.7 V
VSET
TS
6
7
8
AI
AI
AI
RVSET> 150kΩ (floating) = 8.4 V
Temperature Qualification Voltage – Connect a negative temperature coefficient thermistor.
Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends
when TS pin is out of range. Recommend 103AT-2 thermistor.
Input Current Limit (IINDPM) – ILIM pin sets the maximum input current and can be used to
monitor input current. IINDPM loop regulates ILIM pin voltage at 0.8V. When ILIM pin is less than
0.8V, the input current can be calculated by IIN = KILIM x VILIM / (RILIM x 0.8V). A resistor
connected from ILIM pin to ground sets the input current limit as maximum (IINMAX = KILIM /
RILIM). When ILIM pin is short to GND, the input current limit is set to maximum by ILIM. Input
current limit less than 500mA is not supported on ILIM pin. Do not float this pin.
ILIM
4
Copyright © 2019, Texas Instruments Incorporated
BQ25886
www.ti.com.cn
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Open drain active low power good indicator – Connect to the pull up rail via 10-kΩ resistor. LOW
indicates a good input source if the input voltage is within VVBUS_OP (3.9 V), and can provide more
than IPOORSRC (30 mA).
PG
9
DO
Charge Current Limit – A resistor from ICHGSET to GND is used to program the charge current.
The acceptable programming range on ICHGSET pin is 30mA (114Ω) – 2.2A (8kΩ). Pre-charge and
termination current is 1/10 of the fast charge current. The minimum pre-charge current is clamped at
30mA (typ). Minimum termination current is clamped at 10mA (typ). ICHGSET short to GND clamps
charge current to minimum setting 30mA (typ). Floating ICHGSET disables charge.
ICHGSET
10
AI
Gate Drive Supply – Bias supply for internal MOSFETs driver and IC. Bypass REGN to GND with a
4.7-µF ceramic capacitor. REGN current limit is 50 mA.
REGN
BTST
BAT
11
12
P
P
P
PWM High-side Driver Supply – Internally, BTST is connected to the cathode of the boot-strap
diode. Connect a 47nF bootstrap capacitor from SW to BTST.
Battery Power Connection – Connect minimum recommended 10-µF capacitance after derating
closely to the BAT pin and GND.
13, 14
System Connection – The internal BATFET is connected between SYS and BAT. When the battery
falls below the minimum system voltage, the switch-mode converter keeps SYS above the minimum
system voltage. Connect a 2x22-µF capacitance after derating closely to the SYS pin and PGND.
SYS
15, 16
P
SW
17, 18
P
Inductor Connection – Connect to the switched side of the external inductor.
GND
19, 20, 4
–
Ground Return
Blocking MOSFET Connection – The minimum recommended total input low-ESR capacitance on
VBUS and PMID, after applied derating, is 10 uF. At least 1-uF is recommended at VBUS with the
remainder at PMID. Typical value for PMID is 10 uF.
PMID
21, 22
P
Input Supply – VBUS is connected to the external DC supply. Bypass VBUS to GND with at least 1-
µF ceramic capacitor, placed as close to the IC as possible.
VBUS
NC
23
1
P
–
No Connect – Leave these pins floating or tie to ground.
Copyright © 2019, Texas Instruments Incorporated
5
BQ25886
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
-0.3
-0.3
MAX
20
8.5
12
13
19
6
UNIT
V
VBUS (converter not switching)
PMID (converter not switching)
BAT, SYS (converter not switching)
SW
V
-0.3
V
(2)
-0.3
V
Voltage Range (with respect to GND unless otherwise
specified)
BTST
-0.3
-0.3
-0.3
-0.3
-0.3
V
REGN, STAT, /PG, TS
ILIM
V
5
V
BTST to SW
6
V
D+, D-, ICHGSET, VSET, /CE
STAT, /PG
6
V
Output Sink Current
6
mA
°C
°C
Junction Temperature, TJ
Storage temperature, Tstg
–40
–40
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
(2) -2V for 50ns
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
6.2
3.3
2.2
5
UNIT
VVBUS
IVBUS
Input Voltage
4.3
V
A
A
A
Average input current (VBUS)
Average charge current (IBAT)
RMS discharging current with internal MOSFET
IBAT
IBAT_RMS
9 (up to
1us)
IBAT_PK
Peak discharging current with internal MOSFET
A
VBAT
TA
Battery Voltage
9.2(1)
V
Operating free-air temperature range
-40
85
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on SW pin. A tight layout minimizes
switching noise.
6
版权 © 2019, Texas Instruments Incorporated
BQ25886
www.ti.com.cn
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
BQ25886
THERMAL METRIC(1)
RGE (VQFN)
24-PIN
18
UNIT
RΘJA
Junction-to-ambient thermal resistance (EVM(2)
)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJA
Junction-to-ambient thermal resistance (JEDEC (1)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
)
32.4
RΘJC(top)
RΘJB
26.7
10.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ΨJB
10.6
RΘ JC(bot)
3.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Measured on 35µm thick copper, 4-layer board
7.5 Electrical Characteristics
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
QUIESCENT CURRENTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBAT = 9 V, No VBUS, SCL, SDA = 0 V
or 1.8 V, TJ=25C, ADC Disabled
12
12
30
30
1.5
3
14 µA
20 µA
IBAT
Battery discharge current (BAT)
Input supply current (VBUS) in HIZ
Input supply current (VBUS)
VBAT = 9 V, No VBUS, SCL, SDA = 0 V
or 1.8 V, TJ < 85C, ADC Disabled
VBUS = 5 V, High-Z Mode, no battery,
25℃
48 µA
IVBUS_HIZ
VBUS = 5 V, High-Z Mode, no battery,
<85℃
55.2 µA
VBUS = 5 V, VBAT = 7.6 V, converter not
switching
3
mA
mA
IVBUS
VBUS = 5 V, VBAT = 7.6 V, converter
switching, ISYS = 0A
VBUS/VBAT POWER UP
VVBUS_OP
VBUS operating range
4.3
6.2
3.68
6.6
V
V
VVBUS_UVLO_RISING VBUS rising, no battery
VBUS rising
3.3
VBUS over-voltage rising threshold
VBUS over-voltage falling threshold
VPOORSRC_FALLING Bad adapter detection threshold
VBUS rising
6.2
5.9
V
VVBUS_OV
VBUS falling
6.4
V
VBUS falling below VPOORSRC_FALLING
3.7
15
V
IPOORSRC
Bad adapter detection current source
mA
POWER-PATH
ISYS = 0A, VBAT = 8.80 V > SYS_MIN,
Charge Disabled
100
mV
VSYS
Typical System Regulation Voltage
System Regulation Voltage
ISYS = 0A, VBAT < SYS_MIN, Charge
Disabled
200
6.4
mV
V
VSYS_MIN
VBAT < SYS_MIN, Charge Disabled
6.2
BATTERY CHARGER
RVSET < 18 kΩ, VREG = 8.20 V, TJ =
-40℃ - 85℃
VREG_ACC
VREG_ACC
VREG_ACC
VREG_ACC
Charge voltage
8.159
8.756
8.656
8.358
8.2
8.8
8.7
8.4
8.241
8.844
8.744
8.442
V
V
V
V
RVSET = 39 kΩ (±10%), VREG = 8.80 V,
TJ = -40℃ - 85℃
Charge voltage
Charge voltage
Charge voltage
RVSET = 75 kΩ (±10%), VREG = 8.70 V,
TJ = -40℃ - 85℃
RSET > 150kΩ,VREG = 8.40 V, TJ =
-40℃ to 85℃
Copyright © 2019, Texas Instruments Incorporated
7
BQ25886
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
www.ti.com.cn
Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Charge current regulation setting
ratio
ICHG = RICHGSET/KICHGSET. ICHG = 1000
mA
KICHGSET
ICHG_RANGE
ICHG_ACC
3810
Ω/A
Charge current regulation range
30
2200 mA
Fast Charge current regulation
accuracy
ICHG = 1000 mA, VBAT = 6.2 V or 7.6 V,
TJ = 0°C to 85°C
-7.5
7.5
15
25
%
%
%
Fast Charge current regulation
accuracy
ICHG = 500mA, VBAT = 6.2 V or 7.6 V, TJ
= 0°C to 85°C
ICHG_ACC
-15
Fast Charge current regulation
accuracy
ICHG = 250 mA, VBAT = 6.2 V or 7.6 V,
TJ = 0°C to 85°C
ICHG_ACC
-25
30
IPRECHG_RANGE
Precharge current range
Precharge current accuracy
Termination current range
800 mA
237 mA
VBAT = 5.2 V, IPRECHG = 200 mA, TJ =
25°C
170
IPRECHG_ACC
VBAT = 5.2 V, IPRECHG = 200 mA, TJ =
0°C to 85°C
150
245 mA
ITERM_RANGE
ITERM_ACC
10
800 mA
159 mA
ICHG = 1.5A, ITERM = 150 mA, TJ = 25°C
143
ICHG = 1.5A, ITERM = 150 mA, TJ = 0°C
to 85°C
ITERM_ACC
ITERM_ACC
ITERM_ACC
120
42
180 mA
60 mA
75 mA
Termination current accuracy
ICHG = 1.5A, ITERM = 50 mA, TJ = 25°C
ICHG = 1.5A, ITERM = 50 mA, TJ = 0°C to
85°C
18
Short Battery Voltage rising threshold
to start pre-charging
VBAT_SHORT_RISING
VBAT rising
4.1
3.7
4.4
4
4.7
4.3
V
V
Short Battery Voltage falling
threshold to stop pre-charging
VBAT_SHORT_FALLIN
G
VBAT falling
Low Battery Voltage trickle charging
current
IBAT_SHORT
VBAT < 4.4 V
100
6
mA
V
VBAT LOWV Rising threshold to
start fast-charging
VBAT_LOWV_RISING
VBAT rising, VBATLOWV = 6.0 V
VBAT falling, VBATLOWV = 6.0 V
5.7
5.3
6.3
5.9
VBAT LOWV Falling threshold to
stop fast-charging
VBAT_LOWV_FALLING
VRECHG
5.6
V
Recharge threshold below VREG
VBAT falling
TJ = 25°C
200
32
mV
High-side switching MOSFET on-
resistance between SW and
SYS (Q2)
35 mΩ
47 mΩ
46 mΩ
63 mΩ
RON_QHS (Q2)
TJ = – 40°C to 125°C
TJ = 25°C
32
42
42
Low-side switching MOSFET on-
resistance between SW and GND
(Q3)
RON_QLS (Q3)
RON_QBAT (Q4)
TJ = – 40°C to 125°C
MOSFET on-resistance between
SYS and BAT (Q4)
TJ = 25°C
18
19 mΩ
MOSFET on-resistance between
SYS and BAT (Q4)
RON_QBAT (Q4)
IBAT_DISCHG
TJ = – 40°C - 85°C
18
23 mΩ
BAT Discharge current source
VBAT = 8V, EN_BAT_DISCHG = 1
8
11.5
16 mA
INPUT VOLTAGE / CURRENT REGULATION
VINDPM
Input voltage regulation range
4.171
4.3
4.429
V
A x
Ω
KILIM
IINMAX = KILIM/RILIM
Input Current regulation by ILIM pin
1110
Input Current regulation by ILIM pin = 0.5A
Input Current regulation by ILIM pin = 0.9A
Input Current regulation by ILIM pin = 1.5A
TJ = 25°C
457
839
505
909
1518
33
553 mA
980 mA
1624 mA
37 mΩ
Input current regulation limit, IINMAX
KILIM/RILIM
=
IINDPM
1413
Blocking MOSFET on-resistance
between VBUS and PMID (QBLK)
RON_QBLK (Q1)
TJ = – 40°C to 125°C
33
51 mΩ
8
Copyright © 2019, Texas Instruments Incorporated
BQ25886
www.ti.com.cn
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
D + /D- DETECTION
VD+D-_600MVSRC
ID+_10UASRC
D+/D- Voltage Source (600 mV)
D+ Current Source (10 µA)
D+/D- Current Sink (100 µA)
500
7
600
10
700 mV
14 µA
ID+D-_100UASNK
50
100
150 µA
D+/D- Comparator Threshold for
Secondary Detection
VD+D-_0P325
RD-_19K
250
400 mV
24.8 kΩ
800 mV
D- Resistor to Ground (19 kΩ)
14.25
D+ Comparator Threshold for Data
Contact Detection
VD+_0P8
D+/D- Threshold for Non-standard
adapter
VD+D-_1P2
VD+D-_2P0
VD+D-_2P8
ID+D-_LKG
1.05
1.85
1.35
2.15
V
V
D+/D- Comparator Threshold for
Non-standard adapter
D+/D- Threshold for Non-standard
adapter
2.55
-1
2.85
1
V
D+/D- Leakage Current
HiZ
µA
BATTERY OVER-VOLTAGE PROTECTION
VBAT_OVP_RISING
VBAT_OVP_FALLING
Battery over-voltage rising threshold VBAT rising, as percentage of VREG
Battery over-voltage falling threshold VBAT falling, as percentage of VREG
102.5
101
104
102
105
%
%
103.3
THERMAL REGULATION AND THERMAL SHUTDOWN
Junction temperature regulation
accuracy
TREG
TREG = 120°C
120
°C
Thermal Shutdown Rising threshold
TSHUT_RISING
Temperature Increasing
150
120
°C
°C
Thermal Shutdown Falling threshold Temperature Decreasing
JEITA THERMISTOR COMPARATOR (BOOST MODE)
TS pin voltage rising. T1 (0°C)
VT1
threshold, Charge suspended below As Percentage to REGN
this temperature.
72.75
67.75
44.25
73.25
1.3
73.75
68.75
45.25
%
%
%
%
%
%
%
%
TS pin voltage falling. Charge re-
enabled to ICHG/2 and VREG above As Percentage to REGN
this temperature
VT1_HYS
TS pin voltage rising. T2 (10°C)
threshold, charge set to ICHG/2 and As Percentage to REGN
VREG below this temperature
VT2
68.25
1.2
TS pin voltage falling. Charge set to
VT2_HYS
ICHG and VREG above this
temperature
As Percentage to REGN
As Percentage to REGN
As Percentage to REGN
TS pin voltage falling. T3 (45°C)
threshold, charge set to ICHG and
8.1 V above this temperature.
VT3
44.75
1
TS pin voltage rising. Charge set to
ICHG and VREG below this
temperature
VT3_HYS
TS pin voltage falling. T5 (60°C)
threshold, charge suspended above As Percentage to REGN
this temperature.
VT5
33.875 34.375 34.875
1.35
TS pin voltage rising. Charge set to
VT5_HYS
ICHG and 8.1 V below this
temperature
As Percentage to REGN
COLD/HOT THERMISTOR COMPARATOR (OTG BUCK MODE)
Cold Temperature Threshold, TS pin As Percentage to REGN (Approx. – 10°C
VBCOLD0
76.5
77
1
77.5
%
%
Voltage Rising Threshold
w/ 103AT)
Cold Temperature Threshold, TS pin
Voltage Falling Threshold
VBCOLD0_HYS
As Percentage to REGN
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Electrical Characteristics (continued)
VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Hot Temperature Threshold, TS pin
Voltage falling Threshold
As Percentage to REGN (Approx. 60°C w/
103AT)
VBHOT1
33.875 34.375 34.875
3
%
%
Hot Temperature Threshold, TS pin
Voltage rising Threshold
VBHOT1_HYS
As Percentage to REGN
BOOST MODE CONVERTER
FSW
PWM switching frequency
Oscillator frequency
1.35
1.5
5.1
1.65 MHz
OTG BUCK MODE CONVERTER
OTG Buck mode voltage regulation
accuracy
VOTG_ACC
VOTG_ACC
IOTG_ACC
VOTG_OVP
IVBUS = 0A, OTG_VLIM = 5.1V
IVBUS = 0A, OTG_VLIM = 5.1 V
OTG_ILIM = 2A
4.947
-3
5.253
V
%
%
V
OTG Buck mode voltage regulation
accuracy
3
0
OTG Buck mode current regulation
accuracy
-15
5.8
-7.5
6
OTG Buck mode over-voltage
threshold
REGN LDO
VREGN
REGN LDO output voltage
REGN LDO current limit
VVBUS = 5 V, IREGN = 20 mA
VVBUS = 5 V, VREGN = 3.8 V
4.7
50
4.8
5.15
0.4
V
IREGN
mA
LOGIC I/O PIN (/CE)
VIH_CEZ
Input high threshold level, /CE
Input low threshold level, /CE
High level leakage current, /CE
1.3
V
V
VIL_CEZ
IIN_BIAS_CEZ
Pull-up rail 1.8 V
2.5 uA
LOGIC O PIN (/INT, /PG, STAT)
VOL
Output low threshold level
High level leakage current
Sink current = 5 mA
Pull-up rail 1.8 V
0.4
1
V
IOUT_BIAS
µA
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
VBUS/BAT POWER UP
VBUS rising above VBUS_OV threshold to
converter turn off
tVBUS_OV
VBUS OVP reaction time
Bad adapter detection duration
200
30
ns
tPOORSRC
BATTERY CHARGER
ms
tTERM_DGL
Deglitch time for charge termination
Charge current falling below ITERM
250
250
ms
ms
BAT voltage falling below VRECHG = 100
mV
tRECGH_DGL
Deglitch time for recharge threshold
Deglitch time for battery over-voltage
to disable charge
tBAT_OVP_DGL
tSAFETY
1
µs
Charge Safety Timer Accuracy
CHG_TIMER = 12 hours
10.8
12
13.2 hr
DIGITAL CLOCK AND WATCHDOG TIMER
fLPDIG
fDIG
Digital low power clock
Digital clock
REGN LDO disabled
REGN LDO enabled
18
30
45 kHZ
1.35
1.5
1.65 MHz
10
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ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
7.7 Typical Characteristics
CVBUS = 1µF, CPMID= 10µF, CSYS= 44µF, CBAT = 10µF, L = 1µH (DFE252012F-1R0) (unless otherwise specified)
95
94
93
92
91
90
89
88
87
86
85
95
94
93
92
91
90
89
88
87
86
85
VBAT = 7.6 V
VBAT = 8.0 V
VBAT = 7.6 V
VBAT = 8.0 V
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Charge Current (A)
Charge Current (A)
D001
D001
VBUS = 5V
图 1. Charge Efficiency vs. Charge Current
VBUS = 5V
L = 1µH (IHLP2525CZER1R0k01)
图 2. Charge Efficiency vs. Charge Current
95
90
85
80
75
70
65
60
55
95
90
85
80
75
70
65
60
55
PFM En, OOA En
0.2 0.3 0.5 0.7
PFM En, OOA En
0.01
0.02 0.03 0.050.07 0.1
System Current (A)
1
0.01
0.02 0.03 0.050.07 0.1
0.2 0.3
0.5 0.7
1
System Current (A)
D016
D017
VBUS = 5V
VBAT = 8.4V
VBUS = 5V VBAT = 8.4V
L = 1µH (IHLP2525CZER1R0k01)
图 3. System Efficiency vs. System Current
图 4. System Efficiency vs. System Current
95
90
85
80
75
70
65
60
55
96
91
86
81
76
71
66
61
56
PFM En, OOA En
PFM En, OOA En
0.01
0.02 0.03 0.050.07 0.1
IBUS (A)
0.2 0.3
0.5 0.7
1
0.01
0.02 0.03 0.050.07 0.1
IBUS (A)
0.2 0.3
0.5 0.7
1
D018
D019
VBUS = 5V
VBAT = 7.6V
VBUS = 5V VBAT = 7.6V
L = 1µH (IHLP2525CZER1R0k01)
图 5. OTG Efficiency vs. VBUS Output Current
图 6. OTG Efficiency vs. VBUS Output Current
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Typical Characteristics (接下页)
CVBUS = 1µF, CPMID= 10µF, CSYS= 44µF, CBAT = 10µF, L = 1µH (DFE252012F-1R0) (unless otherwise specified)
10
7.5
5
10
7.5
5
VBAT = 6.6 V
VBAT = 7.6 V
VBAT = 6.6 V
VBAT = 7.6 V
2.5
0
2.5
0
-2.5
-5
-2.5
-5
-7.5
-10
-7.5
-10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
ICHG Setting (A)
ICHG Setting (A)
D004
D004
VBUS = 5V
VBUS = 5V
L = 1µH (IHLP2525CZER1R0k01)
图 7. Charge Current Accuracy vs. ICHG Setting
图 8. Charge Current Accuracy vs. ICHG Setting
225
200
175
150
125
100
75
8.56
8.55
8.54
8.53
8.52
8.51
8.5
8.49
8.48
8.47
8.46
8.45
50
25
0
0.8
1.0
1.2
1.4
1.6
1.8
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
System Current (A)
System Current (A)
D006
D007
VBUS = 5V
VBAT = 6V, EN_CHG = 0
SYSMIN = 7V
VBUS = 5V
VBAT = 8.4V
EN_CHG = 0
图 9. SYSMIN Load Regulation
图 10. System Load Regulation After Charge Done
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3.0
2.5
ICHG = 0.5A
ICHG = 1.0A
ICHG = 1.4A
-40°C
0°C
25°C
85°C
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
6
6.3
6.6
6.9
7.2
7.5
7.8
8.1
8.4
8.7
90
95
100
105
110
115
120
125
130
VBAT Voltage (V)
Die Temperature (°C)
D010
D015
VBUS = 5.1V
IBUS = 1A
VBUS = 5V
VBAT = 7.6V
ICHG = 0.5A, 1.0A, 1.4A
Measured on 35-µm thick copper, 4-layer board
图 11. OTG Voltage Regulation vs. VBAT Voltage
图 12. Max Current Temperature Profile
12
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8 Detailed Description
8.1 Overview
The BQ25886 device is a highly integrated 2-A switch-mode battery charger for 2s Li-Ion and Li-polymer battery.
It integrates the input blocking FET (Q1, QBLK), high-side switching FET (Q2, QHS), low-side switching FET
(Q3, QLS), and battery FET (Q4, QBAT). The device also integrates the boot-strap diode for high-side gate drive.
8.2 Functional Block Diagram
VBUS
PMID
VVBUS_UVLO_RISING
QBLK
(Q1)
+
+
UVLO
QBLK
CONTROL
REGN
BTST
REGN
REGN
LDO
EN_HIZ
VBUS_OVP
VVBUS_OV
VOREF
SYS
OTG_OVP(1)
VVBUS
+
VOTG_OVP
QHS
(Q2)
OTG_Q2_OCP(1)
+
IQ2
IHSOCP
VVBUS
VINDPM
SNS
6.2V
+
+
+
+
SW
BAT_OVP
BAT
IIN
BAT
+
+
+
QLS
(Q3)
VBAT_OVP
REGN
DC-DC
CONTROL
VBAT_REG
IINDPM
IC_TJ
TREG
ICHG
GND
ICHG_REG
EN_CHARGE
IQ3
+
+
Q3_OCP
GND
EN_HIZ
ILSOCP
EN_OTG
VBTST
œ VSW
REFRESH
SYS
VBTST_REFRESH
VPOORSRC
CONVERTER
CONTROL
STATE
+
+
POORSRC
VVBUS
IC_TJ
TSHUT
MACHINE
REF
DAC
TSHUT
ICHG
ILIM
VSET
QBAT
(Q4)
VBAT_REG
ICHG_REG
ICHGSET
QBAT
CONTROL
D+
D-
BAT
USB
DETECTION
VREG - VRECHG
RECHRG
+
BAT
/PG
ICHG
ITERM
TERMINATION
+
+
CHARGE
CONTROL
STATE
VBAT_LOWV
BAT
BATLOWV
MACHINE
STAT
VBAT_UVLO_RISING
BATUVLO
+
BAT
BATTERY
SENSING
THERMISTOR
VTS
TS_SUSPEND
TS
OTG
/CE
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8.3 Feature Description
8.3.1 Device Power-On-Reset
The internal bias circuits are powered from either VBAT or VBUS when it rises above VVBUS_UVLO_RISING or
VBAT_UVLO_RISING. When VBUS rises above VVBUS_UVLO_RISING or BAT rises above VBAT_UVLO_RISING, the BATFET
driver is active.
8.3.2 Device Power Up from Battery without Input Source
If only the battery is present and the voltage is above UVLO threshold (VBAT_UVLO_RISING), the BATFET turns on
and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) of
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
8.3.3 Device Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the boost converter is started. The power up
sequence from input source is as listed:
1. Poor Source Qualification
2. Input Source Type Detection based on D+/D- to set default Input Current Limit (IINDPM) and input source
type
3. Power Up REGN LDO
4. Converter Power-up
8.3.3.1 Poor Source Qualification
After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements in order to start the boost converter.
1. VBUS voltage below VVBUS_OVP
2. VBUS voltage above VPOORSRC when pulling IPOORSRC (typical 15mA)
If VBUS_OVP is detected (condition 1 above), the device automatically retries detection once the over-voltage fault
goes away. If a poor source is detected (condition 2 above), the device repeats poor source qualification routine
every 2 seconds. After 7 consecutive failures, the device goes to HIZ mode. The battery powers up the system
when the device is in HIZ. On BQ25886, adapter re-plugin is required to restart device operation. If the fault is
not removed, the part will enter HIZ mode again after the 7 consecutive failures.
8.3.3.2 Input Source Type Detection
After input source is qualified, the charger device runs input source type detection.
The BQ25886 sets input current limit through D+/D- pin. After input source type detection, /PG pin is pulled LOW.
The charger input current is always limited by the lower of ILIM pin or input source detection (500mA or 900mA),
Input Current Optimizer (ICO) setting if a DCP is detected.
8.3.3.2.1 D+/D– Detection Sets Input Current Limit
The BQ25886 contains a D+/D- based input source detection to program the input current limit. The D+/D-
detection has three major steps: Data Contact Detect (DCD), Primary Detection, and Secondary Detection.
14
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Feature Description (接下页)
Unknown/500mA
Divider 3/1A
Divider 1/2.1A
Divider 4/2.4A
Non-Standard
Adapter
Data Detection
Contact
Adapter Plug-in
Secondary
DCP
Primary
Detection
VBUS Detection
or
Detection
(3000mA)
(DCD)
FORCE_INDET
USB BC1.2 Standard
CDP
SDP
(1500mA)
(500mA)
图 13. D+/D- Detection Flow
表 2. Non-Standard Adapter Detection
NON-STANDARD
ADAPTER
D+ THRESHOLD
D– THRESHOLD
INPUT CURRENT LIMIT
Divider 1
Divider 3
Divider 4
VD+ within V2P8_VTH
VD+ within V2P0_VTH
VD+ within V2P8_VTH
VD– within V2P0_VTH
VD– within V2P8_VTH
VD– within V2P8_VTH
2.1 A
1 A
2.4 A
表 3. Input Current Limit Setting from D+/D– Detection
D+/D– DETECTION
INPUT CURRENT LIMIT (IINDPM)
USB SDP (USB500)
USB CDP
500 mA
1.5 A
3.0 A
1 A
USB DCP
Divider 3
Divider 1
2.1 A
2.4 A
500 mA
Divider 4
Unknown 5V Adapter
8.3.3.3 Power Up REGN Regulator (LDO)
The REGN LDO supplies internal bias circuits as well as the QHS and QLS gate drive. The LDO also provides
bias rail to TS external resistors. The pull-up rail of STAT and PG can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid.
1. VBUS above VVBUS_UVLO_RISING in boost mode or VBUS below VVBUS_UVLO_RISING in buck mode
2. Poor Source Qualification detects a valid input source
3. Input Source Type Detection completes and sets appropriate input current limit
4. After 220-ms delay is complete
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device
is in HIZ.
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8.3.3.4 Converter Power Up
After the input current limit is set, the PG pin is pulled LOW, and the converter is enabled, allowing the QHS and
QLS to start switching.Before charging begins, the battery discharge source (IBAT_DISCHG) is enabled
automatically to detect the presence of battery. BATFET stays on to charge the battery. The device provides soft-
start when system rail is ramped up.
As a battery charger, the device deploys a highly efficient 1.5-MHz boost switching regulator. The fixed frequency
oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,
charge current and temperature, simplifying output filter design.
In order to improve light-load efficiency, the device switches to PFM (Pulse Frequency Modulation) control at light
load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation,
the switching duty cycle is set by the ratio of SYS and VBUS.
8.3.4 Input Current Optimizer (ICO)
The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without
overloading the input source. The algorithm automatically identifies maximum input current limit of a power
source without staying in VINDPM to avoid input source overload.
On BQ25886, ICO starts automatically when DCP type of input source is detected. When other input source typs
are detected, ICO is disabled. The actual input current limit used by the Dynamic Power Management circuitry is
limited by the lower value of current limit identified by the ICO algorithm or the current limit set by the ILIM pin.
When the algorithm is enabled, it runs continuously to adjust input current limit of Dynamic Power Management
(IINDPM) using ICO algorithm. When optimal input current is identified, the input current limit set by ICO will not
be changed until the algorithm is forced to run by the following event:
1. A new input source is plugged-in
2. VINDPM is entered
3. VBUS_OVP event
表 4. Input Current Optimizer Automatic Operation
INPUT CURRENT LIMIT
(IINDPM)
AUTOMATIC START ICO
ALGORITHM
DEVICE
INPUT SOURCE
USB SDP (USB500)
USB CDP
500 mA
1.5 A
3.0 A
1 A
Disable
Disable
Enable
Disable
Disable
Disable
Disable
USB DCP
BQ25886 (D+/D–)
Divider 3
Divider 1
2.1 A
2.4 A
500 mA
Divider 4
Unknown 5V Adapter
8.3.5 Buck Mode Operation from Battery (OTG)
The device supports buck converter operation to deliver power from the battery to other portable devices through
USB port. The buck mode output current rating meets the USB On-The-Go 500-mA output requirement. The
maximum output is 2.0 A. The buck operation is enabled when the following conditions are valid:
1. BAT above VOTG_BAT
2. VBUS less than VVBUS_PRESENT
3. Buck mode operation is enabled (OTG pin is pulled high)
4. Voltage at TS (thermistor) pin is within range BHOT and BCOLD
5. After 30-ms delay from buck mode enable
16
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8.3.6 PowerPath Management
The device accommodates a wide range of input sources from USB, to wall adapter, to power bank. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.3.6.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. Even with a
fully depleted battery, the system is regulated above the minimum system voltage (fixed 6.2 V (typ)).
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is typically 200 mV above the minimum system voltage setting. As the battery voltage rises
above the minimum system voltage, the BATFET is fully on and the voltage difference between the system and
battery is the the BATFET's drain to source voltage drop.
When the battery charging is disabled and VBAT is above minimum system voltage setting or charging is
terminated, the system is always regulated at typically 50mV above battery voltage.
9.0
8.6
Charge Enabled
8.2
7.8
Charge Disabled
7.4
7.0
Minimum System Voltage
6.6
6.2
5.4
5.8 6.2 6.6 7.0 7.4 7.8 8.2 8.6
BAT (V)
图 14. System Voltage vs. Battery Voltage
8.3.6.2 Dynamic Power Management
To meet the maximum current limit in the USB spec and avoid over loading the adapter, the device features
Dynamic Power Management (DPM), which continuously monitors the input current and input voltage. As the
charger's system load plus charge current increases with constant input voltage, the charger's input current must
increase. If this current exceeds the charger's preset input current limit or causes the input source voltage to
droop near the input voltage limit (VINDPM fixed at 4.3 V typical), the device then reduces the charge current
until the input current is regulated to the input current limit or the input voltage is regulated to the VINDPM
threshold.Note that if the D+/D- algorithm detected a DCP port and VINDPM triggered, the ICO algorithm lowers
the input current limit.
If the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop.
Once the system voltage falls below the battery voltage, the device automatically enters the Supplement Mode
where the BATFET turns on and battery starts discharging so that the system is supported from both the input
source and battery.
The figure shows the DPM response with 5-V/3-A adapter, 6.4-V battery, 1.5-A charge current and 6.8 V
minimum system voltage setting.
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VSYS
VBAT
7.0V
6.8V
6.4V
6.0V
VBUS
5.0V
4.0V
3A
2A
IBUS
IBAT
1A
0A
ISYS
-1A
DPM
CC
DPM
CC
Supplement
图 15. DPM Response
8.3.6.3 Supplement Mode
When the voltage falls below the battery voltage, the BATFET turns on.
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the
BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current.
The figure shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit Supplement
Mode when the battery is below battery depletion threshold (VBAT_UVLO_RISING).
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IBAT(A)
D001
图 16. BATFET I-V Curve
18
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8.3.7 Battery Charging Management
The BQ25886 charges 2-cell Li-Ion battery with up to 2.2-A charge current for high capacity battery. The low
RDS(ON) BATFET improves charging efficiency and minimize the voltage drop during discharging.
8.3.7.1 Autonomous Charging Cycle
When battery charging is enabled (CE pin is LOW), the device autonomously completes a charging cycle without
host involvement. The device default charging parameters are listed in 表 5 below.
表 5. Charging Parameter Default Settings
DEFAULT MODE
Charging Voltage
Charging Current
Pre-Charge Current
Termination Current
Temperature Profile
Safety Timer
BQ25886
Set by VSET
Set by ICHGSET
1/10 of ICHG
1/10 of ICHG
JEITA
12 hours
A new charge cycle starts when the following conditions are valid:
1. Converter starts
2. No thermistor fault on TS
3. No safety timer fault
The charger automatically terminates the charging cycle when the charging current is below termination
threshold, charge voltage is above recharge threshold, and device is not in DPM mode or thermal regulation.
When a full battery voltage is discharged below recharge threshold (threshold fixed at 200 mV for BQ25886), the
device automatically starts a new charging cycle. After the charge is done, toggle CE pin can initiate a new
charging cycle.
The STAT output indicates the charging status of: charging (LOW), charging complete or charge disable (HIGH)
or charging fault (Blinking). If no battery is connected, the STAT pin blinks as capacitance connected at BAT
charges, discharges, then recharges.
8.3.7.2 Battery Charging Profile
The device charges the battery in five phases: trickle charge, pre-charge, constant current, constant voltage, and
top-off timer charging. At the beginning of a charging cycle, the device checks the battery voltage and regulates
current/voltage accordingly.
If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will
be less than the programmed value. In this case, termination is temporarily disabled and the charging safety
timer is counted at half the clock rate, as explained in the Charging Safety Timer section.
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VREG
Battery Voltage
Charge Current
ICHG
VBATLOWV
VBAT_SHORT
IPRECHG
I
图 17. Battery Charging Profile
8.3.7.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
When termination occurs, the STAT pin goes HIGH. Termination is temporarily disabled when the charger device
is in input current, voltage or thermal regulation. On the BQ25886, termination threshold is 1/10 of the fast
charge current setting.
8.3.7.4 Thermistor Qualification
The charger device provides a single thermistor input for battery temperature monitor.
8.3.7.4.1 JEITA Guideline Compliance in Charge Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds
the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range. At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge
current or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V / cell.
On the BQ25886, at cool temperature (T1-T2), the charge current is reduced to 20% of the fast charge current,
ICHG. At warm temperature (T3 - T5), the charge voltage is set to 8.0 V. Whenever the charger detectes "warm"
or "cool" temperature, termination is automatically disabled.
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REGN
TS
BQ2588x
图 18. TS Resistor Network
100
%
VREG
80%
60%
40%
20%
8.3V
8.0V
T2
10°
C
T3
45°
C
T5
60°
C
T2
10°
C
T3
45°
C
T5
60°
C
T1
0°C
T1
0°C
TS Temperature
TS Temperature
图 19. TS Charging Values
Assuming a 103AT NTC (Negative Temperature Coefficient) thermistor on the battery pack as shown above, the
value of RT1 and RT2 can be determined by:
≈
∆
«
’
÷
◊
1
1
RNTC,T1 ì RNTC,T 5
ì
-
VT 5 VT1
RT2 =
RT1=
≈
∆
«
’
≈
∆
«
’
÷
◊
1
1
RNTC,T1
ì
-1 - R
ì
-1
÷
NTC,T 5
VT1
VT 5
◊
(1)
(2)
1
-1
VT1
1
1
+
RT 2 RNTC,T1
Select 0°C to 60°C range for Li-ion or Li-polymer battery:
RNTC,T1 = 27.28 kΩ
RNTC,T5 = 3.02 kΩ
RT1 = 5.24 kΩ
RT2 = 30.31 kΩ
8.3.7.5 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions.
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During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the setting. For example, if the charger is in input current regulation throughout the
whole charging cycle, and the safety timer is set to 12 hours, then the timer will expire in 24 hours.
During faults which disable charging, or supplement mode, timer is suspended. Once the fault goes away, safety
timer resumes. If the charging cycle is stopped and started again, the timer gets reset.
The safety timer is reset for the following events:
1. Charging cycle stop and restart (toggle CE pin, or charged battery falls below recharge threshold).
2. BAT voltage changes from pre-charge to fast-charge or vice versa.
The precharge safety timer (fixed 2hr counter that runs when VBAT < VBAT_LOWV), follows the same rules as the
fast-charge safety timer in terms of getting suspended, reset, and counting at half-rate.
8.3.8 Status Outputs
8.3.8.1 Power Good Indicator (PG)
The open drain PG pin goes low to indicate a good input source when:
1. VBUS above VVBUS_UVLO_RISING
2. VBUS below VVBUS_OV threshold
3. VBUS above VPOORSRC (typ. 3.7 V) when IPOORSRC (typ. 30 mA) current is applied (not a poor source)
4. Input Source Type Detection is completed
8.3.8.2 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED.
表 6. STAT Pin State
CHARGING STATE
STAT INDICATOR
Charging in progress (including trickle charge, pre-charge, fast-
charge, recharge)
LOW
Charging complete
HIGH
HIGH
Sleep mode, charge disable
Charge suspend (Input over-voltage, TS fault, timer fault or battery
over-voltage) OTG Buck Mode suspend (due to TS fault)
Blinking at 1Hz
8.3.9 Input Current Limit on ILIM Pin
For safe operation, the BQ2588x has an additional hardware pin on ILIM to limit maximum input current. The
maximum input current is set by a resistor from ILIM pin to ground as:
KILIM
=
I
INMAX
RILIM
(3)
The actual input current limit is the lower value between ILIM pin setting and current limit set by D+/D- detection.
The device regulates ILIM pin at 0.8 V. If ILIM voltage exceeds 0.8 V, the device enters input current regulation
(refer to Dynamic Power Management section).
The ILIM pin can also be used to monitor input current. The voltage on ILIM pin is proportional to the input
current. ILIM can be used to monitor input current with the following relationship:
KILIM ìVILIM
RILIM ì0.8V
IIN
=
(4)
For example, if ILIM pin is set with 820-Ω resistor, and the ILIM voltage 0.5V, the actual input current is 0.795 A
to 0.973 A. If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 0.8 V.
8.3.10 Voltage and Current Monitoring
The device closely monitors the input voltage, as well as internal FET currents for safe boost and buck mode
operation.
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8.3.10.1 Voltage and Current Monitoring in Boost Mode
8.3.10.1.1 Input Over-Voltage Protection
The valid input voltage range for boost mode operation is VVBUS_OP. If VBUS voltage exceeds VVBUS_OV, the
device stops switching immediately to protect the power FETs. The device automatically starts switching again
when the over-voltage condition goes away.
8.3.10.1.2 Input Under-Voltage Protection
The valid input voltage range for boost mode operation is VVBUS_OP. If VBUS voltage falls below VPOORSRC during
operation, the device stops switching. The device automatically attempts to restart switching when the under-
voltage condition goes away.
8.3.10.1.3 System Over-Voltage Protection
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. SYSOVP threshold is 350 mV above system regulation voltage.
Upon SYSOVP, converter stops immediately to clamp the overshoot.
8.3.10.1.4 System Over-Current Protection
The charger device continually monitors and compares VBUS to VSYS to protect against a system short-circuit
event. In the event that VSYS drops to within 250 mV of VBUS during operation, a short circuit event is flagged
and the converter stops switching. The device attempts to recover from this condition automatically.
8.3.10.2 Voltage and Current Monitoring in OTG Buck Mode
The device closely monitors the VBUS voltage, as well as RBFET (Q1, QBLK) and LSFET (Q3, QLS) current to
ensure safe buck mode operation.
8.3.10.2.1 VBUS Over-voltage Protection
When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters over-voltage
protection which stops switching, and exits buck mode.
8.3.10.2.2 VBUS Over-Current Protection
The device monitors output current to provide output short protection. The OTG buck mode has built-in constant
current regulation to allow OTG to adapt to various types of loads. If short circuit is detected on VBUS, the OTG
turns off and retries 7 times. If the retries are not successful, OTG is disabled.
8.3.11 Thermal Regulation and Thermal Shutdown
8.3.11.1 Thermal Protection in Boost Mode
The device monitors internal junction temperature, TJ, to avoid overheating and limits the IC surface temperature
in boost mode. When the internal junction temperature exceeds the thermal regulation limit (120°C), the device
reduces charge current.
During thermal regulation, the actual charging current is usually below the programmed value. Therefore,
termination is disabled, and the safety timer runs at half the clock rate.
Additionally, the device has thermal shutdown to turn off the converter when IC surface temperature exceeds
TSHUT. The converter turns back on when IC temperature is below TSHUT_HYS
.
8.3.11.2 Thermal Protection in OTG Buck Mode
The BQ2588x monitors the internal junction temperature to provide thermal shutdown during OTG buck mode.
8.3.12 Battery Protection
8.3.12.1 Battery Over-Voltage Protection (BATOVP)
The battery over-voltage limit is clamped at 4% above the battery regulation voltage while charging. When
battery over-voltage occurs, the charger device immediately disables charge.
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8.4 Device Functional Modes
The BQ25886 is a standalone device and therefore does not include any functional modes for I2C operations.
24
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application consists of the BQ25886 configured as a standalone device and a 2s battery charger for Li-
Ion and Li-Polymer batteries used in a wide range of portable devices. It integrates an input blocking FET (QBLK,
Q1), high-side switching FET (QHS, Q2), and low-side switching FET (QLS, Q3). The device also integrates a
bootstrap diode for the high-side gate drive.
9.2 Typical Application
5V @ 3A
2.2K ꢁ VREF
VBUS
PMID
STAT
/PG
1 ꢀF
2.2K ꢁ
Q1
30 ꢀF
10 ꢀF
(optional)
1ꢀH
SYSTEM
LOAD
Q2
SYS
BAT
6.4V
SW
47nF
44 ꢀF
BTST
ICHG=2A
Q4
10 ꢀF
4.7ꢀF
REGN
Q3
D+
D-
Host
VREGN
OTG
/CE
TS
383Ω
ILIM
BQ25886
150kΩ
5.7kΩ
VSET
`
ICHGSET
GND
图 20. BQ25886 (Stand-Alone) Typical Application Diagram
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Typical Application (接下页)
9.2.1 Design Requirements
For this design example, use the parameters shown in 表 7 below.
表 7. Design Parameters
PARAMETER
VBUS voltage range
VALUE
4.3 V to 6.2 V
2.4 A
Input current limit (ILIM)
Fast charge current limit (ICHGSET)
Minimum System Voltage
Battery Regulation Voltage (VSET)
1.5 A
6.2 V
8.4 V
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The device has 1.5-MHz switching frequency to allow the use of small inductor and capacitor values. The
inductor saturation current should be higher than the input current (IIN) plus half the ripple current (IRIPPLE):
I
RIPPLE
ISAT í IIN +
(5)
The inductor ripple current (IRIPPLE) depends on input voltage (VVBUS), duty cycle (D = VBAT/VBUS), switching
frequency (fSW) and inductance (L):
V
BUS ì(VSYS-VBUS)
IRIPPLE
=
VSYS ì fSW ì L
(6)
The maximum inductor ripple current happens in the vicinity of D = 0.5. Usually inductor ripple is designed in the
range of (20 – 40%) maximum charging current as a trade-off between inductor size and efficiency for a practical
design.
9.2.2.2 Input (VBUS / PMID) Capacitor
The input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst
case RMS ripple current occurs when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then
the worst case capacitor RMS current IPMID occurs where the duty cycle is closest to 50% and can be estimated
by
I
RIPPLE
IPMID
=
ö 0.29ì IRIPPLE
2ì 3
(7)
A low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed close to the PMID and GND pins of the IC. Voltage rating of the capacitor must be higher than normal
input voltage level. 25-V rating or higher capacitor is preferred for up to 5-V input voltage. A minimum 10-μF
capacitor is suggested for up to 3.3-A input current. Keep in mind, long impedance cable would cause significant
voltage drop with higher inrush current. For optimal performance, 44-uF cap on PMID is recommended. In
addition, a minimum 1-μF capacitor is suggested at VBUS pin.
9.2.2.3 Output (VSYS) Capacitor
The SYS capacitor is the boost converter output capacitor and should also have enough ripple current rating to
absorb output switching ripple current. The output capacitor RMS current ICOUT is given:
D
ICSYS, rms = IOUT ì
1- D
(8)
The output capacitor voltage ripple is a function of the boost output current (IOUT), and can be calculated as
follows:
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I
OUT ì D
DVSYS
=
f
SW ìCSYS
(9)
A low ESR ceramic capacitor such as X7R or X5R is preferred for SYS decoupling capacitor and should be
placed close to the SYS and GND pins of the IC. Voltage rating of the capacitor must be higher than normal
output voltage level. 16-V rating or higher capacitor is preferred. Minimum 44-μF capacitor is suggested for up to
2.2-A boost converter output current.
9.2.2.4 ILIM resistor
The ILIM resistor sets the maximum input current limit and can be used to monitor input current. The maximum
input current is set by a resistor from ILIM pin to ground as:
KILIM
=
I
INMAX
RILIM
(10)
Using maximum input current limit 900mA as an example. The KLIM is 1110. If the maximum input current limit
cannot exceed 900mA, then IINMAX used in the calculation should be 819.9mA as regulation accuracy at
900mA (typ) setting is around +/-8.9%. Resistor accuracy should also be taken into consideration when setting
input current limit. When ILIM pin is short to GND, the input current limit is set to maximum by ILIM. Input current
limit less than 500mA is not supported on ILIM pin. Do not float this pin.
9.2.2.5 ICHGSET resistor
A resistor from ICHGSET to GND is used to program the charge current. Pre-charge and termination current is
1/10 of the fast charge current. The minimum pre-charge current is clamped at 30mA (typ). Minimum termination
current is clamped at 10mA (typ). ICHGSET short to GND clamps charge current to minimum setting 30mA (typ).
Floating ICHGSET disables charge. RICHGSET can be calculated as:
R
ICHGSET
ICHGSET
ICHGSET
=
K
(11)
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9.2.3 Application Curves
CVBUS = 1 µF, CPMID= 10 µF, CBAT = 10 µF, CSYS = 44 µF, L = DFE252012F-1R0 (1 µH) (unless otherwise specified)
VBUS = 5 V
VBAT = 6.0 V
ICHG = 1 A
VBUS = 5 V
VBAT = 7.4 V
ICHG = 1 A
图 21. Adapter Power Up with Charge Enabled
图 22. Charge Enable
VBUS = 5 V
VBAT = 7.4 V
ICHG = 1 A
VBUS = 5 V
VBAT = Open
Charge enabled
图 23. Charge Disabled
图 24. Adapter Plug-in with No Battery
VBAT = 7.6 V
VBUS = 5.1 V
No IBUS load
VBAT = 7.6 V
Adapter removed
with OTG = HIGH
RBUS = 25 Ω
图 26. Buck Mode Startup After Adapter Removal
图 25. Buck Mode (OTG) Startup
28
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ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
CVBUS = 1 µF, CPMID= 10 µF, CBAT = 10 µF, CSYS = 44 µF, L = DFE252012F-1R0 (1 µH) (unless otherwise specified)
VBAT = 7.6 V
VBUS = 5.1 V
IBUS = 1 A
VBAT = 7.6 V
VBUS = 5.1 V
IBUS = 0 mA
图 27. Buck Mode (OTG) PWM Switching
图 28. Buck Mode (OTG) PFM Switching
VBUS = 5 V
VBAT = 7.6 V
ICHG = 1 A
VBUS = 5 V
VBAT = 8.4 V
Charge disabled
图 29. Boost Mode PWM Switching
图 30. Boost Mode PFM Switching
DCP Adapter
VBAT = 8.0 V
Charge enabled
VBUS = 5 V
VBAT = 8.4 V
Charge disabled
图 32. VINDPM Transient Response
图 31. System Load Transient Response
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BQ25886
ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
www.ti.com.cn
CVBUS = 1 µF, CPMID= 10 µF, CBAT = 10 µF, CSYS = 44 µF, L = DFE252012F-1R0 (1 µH) (unless otherwise specified)
DCP Adapter
VBAT = 8.0 V
Charge enabled
VBAT = 7.6 V
VBUS = 5.1 V
图 33. IINDPM Transient Response
图 34. Buck Mode (OTG) Load Transient Response
30
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ZHCSJI9A –MARCH 2019–REVISED JUNE 2019
10 Power Supply Recommendations
In order to provide an output voltage on SYS, the device requires a power supply between 3.9-V and 6.2-V input
with at least 500-mA current rating connected to VBUS or a 2-cell Li-Ion battery with voltage > VBAT_UVLO
connected to BAT. The source current rating needs to be at least 3-A in order for the boost converter of the
charger to provide maximum output power to SYS.
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loops is important to prevent electrical and magnetic field
radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB
according to this specific order is essential.
1. Put SYS output capacitor as close to SYS and GND pins as possible. Ground connections need to be tied to
the IC ground with a short copper trace connection or GND plane.
2. Place PMID input capacitor as close as possible to PMID pins and PGND pins and use shortest copper trace
connection or GND plane.
3. Place inductor input terminal to SW pins as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the input current. Minimize
parasitic capacitance from this area to any other trace or plane.
4. Decoupling capacitors should be placed on the same side of and next to the IC and make trace connection
as short as possible.
5. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0-Ω resistor to tie analog ground to power ground.
6. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on
the other layers.
7. Via size and number should be enough for a given current path.
Refer to the EVM design and the Layout Example below for the recommended component placement with trace
and via locations.
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11.2 Layout Example
图 35. PCB Layout Example
32
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12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
《BQ2588x 升压电池充电器评估模块用户指南》
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
34
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25886RGER
BQ25886RGET
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ25886
BQ25886
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25886RGER
BQ25886RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25886RGER
BQ25886RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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