BQ27742YZFR-G1 [TI]
具有集成保护功能的单节锂离子电池电量监测计 | 电池电量监测计 | YZF | 15 | -40 to 85;
| 型号： | BQ27742YZFR-G1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成保护功能的单节锂离子电池电量监测计 | 电池电量监测计 | YZF | 15 | -40 to 85 电池 |
| 文件： | 总46页 (文件大小：1680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq27742-G1
ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
bq27742-G1 具有可编程硬件保护功能的单节锂离子
电池电量监测计
1 特性
3 说明
1
•
•
单节锂离子电池电量监测计和保护器 应用
微控制器外设提供：
德州仪器 (TI) bq27742-G1 器件是一款电量监测计，
适用于单节锂离子电池组。此电量计使用已获专利的
Impedance Track™技术，可预测剩余电池电量和系统
运行的速率、温度和老化补偿并且具有最高精度。此器
件还含有一个完全集成的高侧保护器，无需单独的锂离
子保护电路即可对是否存在过压、欠压、充电过流、放
电过流和放电短路条件进行全套高精度故障检测。硬件
保护功能提供了内置数据闪存可编程功能，方便针对不
同的终端设备需求重新配置现有器件。
–
具有低值感应电阻（5mΩ 至 20mΩ）的
精密 16 位高侧库仑计数器
–
–
–
–
用于报告电池温度的外部和内部温度传感器
使用寿命和电流数据记录
64 字节非易失性暂用闪存
通过 SHA-1 认证
•
基于已获专利的 Impedance Track™技术的电池电
量计量
这款电量监测计可提供剩余电池电量 (mAh)、充电状
态 (%)、续航时间（分钟）、电池电压 (mV)、电流
(mA) 和温度 (°C) 等信息，以及整个电池使用寿命期间
记录的重要参数。此器件还支持中断主机，指示检测到
各种重要的故障条件并汇报给系统。
–
–
用于电池续航能力精确预测的电池放电模拟曲线
针对电池老化、自放电和温度以及额定引入效应
的自动调节
•
•
集成高侧 NMOS 保护场效应晶体管 (FET) 驱动
基于硬件的安全与防护功能：
DSBGA 是 15 焊球封装 (2.78mm × 1.96mm)，非常适
合空间受限的 应用。
–
–
–
–
–
过压保护 (OVP)
欠压保护 (UVP)
充电过流 (OCC)
放电过流 (OCD)
放电短路 (SCD)
器件信息(1)
器件型号
封装
封装尺寸（标称值）
BQ27742YZFR-G1
BQ27742YZFT-G1
•
•
采用 I2C 和 HDQ 通信接口格式，用于与主机系统
YZF (15)
2.78mm x 1.96mm
通信
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
超紧凑 15 焊球 NanoFree™DSBGA
2 应用
简化原理图
VBAT
VPACK
RSENSE
•
•
•
•
•
智能手机
RSRN
RSRP
平板电脑
CSRN
CSRP
手持式终端
RCHG
RDSG
RPACKP
CDIFF
MP3 和多媒体播放器
便携式游戏机
RVPWR
RBAT
VPWR
BAT
SRN
SRP
CVPWR
CBAT
REG25 PACKP
TS
CHG
DSG
SDA
SCL
HDQ
CPACKP
CREG25
RTHERM
NC
RC2
VSS
SDA
SCL
CTHERM
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSBV9
bq27742-G1
ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
www.ti.com.cn
目录
6.21 Timing Requirements............................................ 11
6.22 Typical Characteristics.......................................... 13
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 18
7.5 Battery Parameter Measurements .......................... 21
7.6 Communications ..................................................... 22
7.7 Standard Data Commands ..................................... 24
7.8 Extended Data Commands..................................... 26
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 27
Power Supply Recommendation........................ 35
9.1 Power Supply Decoupling....................................... 35
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Power-On Reset........................................................ 7
6.6 2.5-V LDO Regulator ............................................... 7
6.7 Charger Attachment and Removal Detection ........... 8
6.8 CHG and DSG FET Drive......................................... 8
6.9 Overvoltage Protection (OVP) .................................. 8
6.10 Undervoltage Protection (UVP)............................... 8
6.11 Overcurrent in Discharge (OCD)............................. 9
6.12 Overcurrent in Charge (OCC)................................. 9
6.13 Short-Circuit in Discharge (SCD)............................ 9
6.14 Low Voltage Charging............................................. 9
6.15 Internal Temperature Sensor Characteristics ......... 9
6.16 High-Frequency Oscillator..................................... 10
6.17 Low-Frequency Oscillator ..................................... 10
7
8
9
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 37
11 器件和文档支持 ..................................................... 38
11.1 文档支持................................................................ 38
11.2 接收文档更新通知 ................................................. 38
11.3 社区资源................................................................ 38
11.4 商标....................................................................... 38
11.5 静电放电警告......................................................... 38
11.6 Glossary................................................................ 38
12 机械、封装和可订购信息....................................... 38
6.18 Integrating ADC (Coulomb Counter)
Characteristics ......................................................... 10
6.19 ADC (Temperature and Cell Voltage)
Characteristics ......................................................... 10
6.20 Data Flash Memory Characteristics...................... 11
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (February 2016) to Revision D
Page
•
•
•
Changed Detailed Description ............................................................................................................................................. 15
Changed Standard Commands ........................................................................................................................................... 25
已添加 接收文档更新通知 ..................................................................................................................................................... 38
Changes from Revision B (August 2015) to Revision C
Page
•
•
已更改 封装标签“CSP”全部改为“DSBGA” ............................................................................................................................. 1
Changed Integrating ADC (Coulomb Counter) Characteristics ........................................................................................... 10
Changes from Revision A (December 2014) to Revision B
Page
•
•
•
•
•
•
Changed Pin Functions ......................................................................................................................................................... 3
Changed Absolute Maximum Ratings ................................................................................................................................... 6
Changed Recommended Operating Conditions..................................................................................................................... 7
Changed Functional Block Diagram .................................................................................................................................... 15
Changed VVPWR to VBAT in Figure 15 .................................................................................................................................... 19
Changed "VPWR" to "VBAT" in OVERVOLTAGE Mode and UNDERVOLTAGE Mode........................................................... 20
2
Copyright © 2014–2018, Texas Instruments Incorporated
bq27742-G1
www.ti.com.cn
ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
5 Pin Configuration and Functions
1
2
3
A
B
C
D
E
SRP
CHG
DSG
SRN
VPWR
VSS
NC
BAT
HDQ
TS
PACKP
SDA
RC2
REG25
SCL
Not to scale
Pin Functions
NUMBER
NAME
I/O
DESCRIPTION
Analog input pin connected to the internal coulomb counter where SRP is nearest the PACK+
connection. Connect to a sense resistor.
A1
SRP
I
A2
A3
CHG
DSG
O
O
External high side N-channel charge FET driver
External high side N-channel discharge FET driver
Analog input pin connected to the internal coulomb counter where SRN is nearest the CELL+
connection. Connect to a sense resistor.
B1
SRN
I
B2
B3
C1
C2
NC
IO
I
Not used. Reserved for future GPIO. It is recommended to connect to GND.
Pack voltage measurement input for protector operation
PACKP
VPWR
BAT
—
I
Power input. Decouple with 0.1-µF ceramic capacitor to VSS
.
Cell-voltage measurement input. ADC input
Slave I2C serial communications data line for communication with system. Open-drain I/O.
Use with a 10-kΩ pullup resistor (typical).
C3
SDA
IO
D1
D2
D3
VSS
HDQ
RC2
—
I/O
IO
Device ground
HDQ serial communications line. Open-drain
General purpose IO. Push-pull output
Regulator output and bq27742-G1 processor power. Decouple with 1.0-µF ceramic capacitor
E1
E2
E3
REG25
TS
—
I
to VSS
.
Pack thermistor voltage sense (use 103AT-type thermistor). ADC input
Slave I2C serial communications clock input line for communication with system. Use with a
10-kΩ pullup resistor (typical).
SCL
IO
Copyright © 2014–2018, Texas Instruments Incorporated
3
bq27742-G1
ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
www.ti.com.cn
Table 1. Hardware Protection Thresholds(1)
OVERVOLTAGE
UNDERVOLTAGE
OVERCURRENT IN
OVERCURRENT IN
SHORT-CIRCUIT IN
PROTECTION (VOVP
)
PROTECTION (VUVP
)
CHARGE (VOCC
)
DISCHARGE (VOCD
14 mV
24 mV
34 mV
44 mV
53 mV
63 mV
73 mV
83 mV
13 mV
23 mV
33 mV
43 mV
53 mV
63 mV
72 mV
83 mV
13 mV
23 mV
33 mV
43 mV
52 mV
62 mV
72 mV
82 mV
13 mV
23 mV
33 mV
42 mV
52 mV
62 mV
72 mV
82 mV
13 mV
23 mV
32 mV
42 mV
52 mV
62 mV
71 mV
81 mV
)
DISCHARGE (VSCD)
6 mV
73 mV
13 mV
18 mV
28 mV
6 mV
4.450 V
4.425 V
4.400 V
4.375 V
4.350 V
2.438 V
2.422 V
2.409 V
2.395 V
2.381 V
148 mV
73 mV
13 mV
18 mV
28 mV
6 mV
148 mV
72 mV
13 mV
18 mV
28 mV
6 mV
147 mV
72 mV
13 mV
18 mV
28 mV
6 mV
146 mV
71 mV
13 mV
18 mV
28 mV
145 mV
(1) Production tested in the following configuration: VOVP = 4.450 V, VUVP = 2.438 V, VOCC = 28 mV, VOCD = 83 mV, and VSCD = 148 mV.
4
Copyright © 2014–2018, Texas Instruments Incorporated
bq27742-G1
www.ti.com.cn
ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
Table 1. Hardware Protection Thresholds(1) (continued)
OVERVOLTAGE
UNDERVOLTAGE
OVERCURRENT IN
OVERCURRENT IN
SHORT-CIRCUIT IN
PROTECTION (VOVP
)
PROTECTION (VUVP
)
CHARGE (VOCC
)
DISCHARGE (VOCD
13 mV
22 mV
32 mV
42 mV
52 mV
61 mV
71 mV
81 mV
13 mV
22 mV
32 mV
42 mV
51 mV
61 mV
70 mV
80 mV
13 mV
22 mV
32 mV
41 mV
51 mV
60 mV
70 mV
80 mV
)
DISCHARGE (VSCD)
6 mV
71 mV
13 mV
18 mV
27 mV
6 mV
4.325 V
2.368 V
2.354 V
2.340 V
144 mV
71 mV
13 mV
18 mV
27 mV
6 mV
4.300 V
143 mV
70 mV
13 mV
18 mV
27 mV
4.275 V
143 mV
Table 2. Hardware Protection Delays
OVERVOLTAGE
UNDERVOLTAGE
PROTECTION DELAY
(tUVP
OVERCURRENT IN
CHARGE DELAY (tOCC)
OVERCURRENT IN
DISCHARGE DELAY
(tOCD
SHORT-CIRCUIT IN
DISCHARGE DELAY
PROTECTION DELAY
(tOVP
)
)
)
(tSCD
)
1.00 s
31.25 ms
7.81 ms
31.25 ms
312.50 µs
Copyright © 2014–2018, Texas Instruments Incorporated
5
bq27742-G1
ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
5.5
UNIT
VVPWR
VREG25
Power input range
Supply voltage range
PACKP input pin
V
V
V
2.75
5.5
VPACKP
PACK+ input when external 2-kΩ resistor is in series with PACKP input pin (see
Figure 19 and Figure 20)
–0.3
28
V
VOUT
VIOD1
VIOD2
VBAT
VI
Voltage output pins (DSG, CHG)
Push-pull IO pins (RC2)
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
10
2.75
5.5
V
V
Open-drain IO pins (SDA, SCL, HDQ, NC)
BAT input pin
V
5.5
V
Input voltage range to all other pins (SRP, SRN)
Input voltage range for TS
5.5
V
VTS
TA
2.75
85
V
Operating free-air temperature
Functional temperature
°C
°C
°C
TF
–40
100
150
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
No operating restrictions
No FLASH writes
MIN
2.8
NOM
MAX
5.0
UNIT
VVPWR
CVPWR
Supply voltage
V
2.45
2.8
External input capacitor for internal
LDO between VPWR and VSS
0.1
1.0
µF
µF
Nominal capacitor values
specified. Recommend a 5%
ceramic X5R type capacitor
located close to the device
External output capacitor for
internal LDO between REG25 and
VSS
CREG25
0.47
Fuel gauge in NORMAL mode
ILOAD > Sleep Current with charge
pumps on (FETs on)
NORMAL operating mode
current(1)(2) (VPWR)
ICC
167
88
µA
µA
µA
Fuel gauge in SLEEP+ mode.
ISLP
SLEEP mode current(1)(2) (VPWR) ILOAD < Sleep Current with charge
pumps on (FETs on)
Fuel gauge in SLEEP mode.
FULLSLEEP mode current(1)(2)
ILOAD < Sleep Current with charge
(VPWR)
IFULLSLP
40
pumps on (FETs on)
(1) All currents are specified with charge pump on (FETs on).
(2) All currents are continuous average over 5-second period.
6
Copyright © 2014–2018, Texas Instruments Incorporated
bq27742-G1
www.ti.com.cn
ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
Recommended Operating Conditions (continued)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
NOM
MAX
UNIT
Fuel gauge in SHUTDOWN mode.
UVP tripped with fuel gauge and
protector turned off (FETs off)
VVPWR = 2.5 V
SHUTDOWN mode current(1)(2)
(VPWR)
0.1
0.2
µA
ISHUTDOWN
TA = 25°C
TA = –40°C to 85°C
0.5
0.4
µA
V
Output voltage low (SCL, SDA,
HDQ, NC, RC2)
VOL
IOL = 1 mA
Output voltage high (SDA, SCL,
HDQ, NC, RC2)
External pullup resistor connected
to VREG25
VOH(OD)
VIL
VREG25 – 0.5
–0.3
V
V
V
Input voltage low (SDA, SCL,
HDQ, NC)
0.6
5.5
Input voltage high (SDA, SCL,
HDQ, NC)
VIH(OD)
1.2
VA1
VA2
Input voltage range (TS)
Input voltage range (BAT)
VSS – 0.125
VSS – 0.125
2
5
V
V
VVPWR
–
VVPWR
+
VA3
Input voltage range (SRP, SRN)
V
0.125
0.125
Ilkg
Input leakage current (I/O pins)
Power-up communication delay
0.3
µA
ms
tPUCD
250
6.4 Thermal Information
bq27742-G1
THERMAL METRIC(1)
YZF (DSBGA)
UNIT
15 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
70
17
20
1
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
18
NA
RθJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Power-On Reset
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.09
45
TYP
2.20
115
MAX
2.31
185
UNIT
V
VIT+
Increasing battery voltage input at VREG25
Power-on reset hysteresis
VHYS
mV
6.6 2.5-V LDO Regulator(1)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.8 V ≤ VVPWR ≤ 4.5 V,
2.3
2.5
2.6
V
IOUT(1) ≤ 16 mA
TA = –40°C to
85°C
VREG25
Regulator output voltage
2.45 V ≤ VVPWR < 2.8 V (low
battery),
2.3
V
IOUT(1) ≤ 3 mA
(1) LDO output current, IOUT, is the sum of internal and external load currents.
Copyright © 2014–2018, Texas Instruments Incorporated
7
bq27742-G1
ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
www.ti.com.cn
2.5-V LDO Regulator(1) (continued)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = –40°C to
85°C
MIN
TYP
MAX
UNIT
(2)
ISHORT
Short-circuit current limit VREG25 = 0 V
250
mA
(2) Assured by characterization. Not production tested.
6.7 Charger Attachment and Removal Detection
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage threshold for charger attachment
detection
VCHGATT
VCHGREM
2.7
3.0
V
Voltage threshold for charger removal
detection
0.5
1.0
V
6.8 CHG and DSG FET Drive
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2 × VVPWR
0.2
UNIT
V
IL = 1 µA
TA = –40°C to 85°C
VFETON
CHG and DSG FETs on
CHG and DSG FETs off
CHG and DSG FETs on
2 × VVPWR – 0.4
2 × VVPWR – 0.2
VFETOFF
VFETRIPPLE
TA = –40°C to 85°C
V
IL = 1 µA
TA = –40°C to 85°C
(1)
0.1
VPP
CL = 4 nF
TA = –40°C to 85°C
No series resistance
FET gate rise time
(10% to 90%)
tFETON
67
10
140
30
218
60
μs
μs
CL = 4 nF
TA = –40°C to 85°C
No series resistance
FET gate fall time
(90% to 10%)
tFETOFF
(1) Assured by characterization. Not production tested.
6.9 Overvoltage Protection (OVP)
TA = 25°C and CREG25 = 1.0 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOVP – 0.016
VOVP – 0.033
VOVP – 0.028
VOVP – 0.063
VOVPREL – 0.022
VOVPREL – 0.033
VOVPREL – 0.028
VOVPREL – 0.063
tOVP – 5%
TYP
VOVP
VOVP
VOVP
VOVP
MAX
VOVP + 0.016
VOVP + 0.030
VOVP + 0.024
VOVP + 0.045
UNIT
TA = 25°C
TA = 0°C to 25°C
TA = 25°C to 50°C
TA = –40°C to 85°C
TA = 25°C
OVP detection voltage
threshold
VOVP
V
VOVP – 0.215
VOVP – 0.215
VOVP – 0.215
VOVP – 0.215
tOVP
VOVPREL + 0.022
VOVPREL + 0.030
VOVPREL + 0.024
VOVPREL + 0.045
tOVP + 5%
TA = 0°C to 25°C
TA = 25°C to 50°C
TA = –40°C to 85°C
TA = –40°C to 85°C
VOVPREL
OVP release voltage
OVP delay time
V
s
tOVP
6.10 Undervoltage Protection (UVP)
TA = 25°C and CREG25 = 1.0 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VUVP – 0.022
VUVP – 0.030
VUVP – 0.050
TYP
VUVP
VUVP
VUVP
MAX
VUVP + 0.022
VUVP + 0.030
VUVP + 0.050
UNIT
TA = 25°C
UVP detection voltage
threshold
VUVP
TA = –5°C to 50°C
TA = –40°C to 85°C
V
8
Copyright © 2014–2018, Texas Instruments Incorporated
bq27742-G1
www.ti.com.cn
ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
Undervoltage Protection (UVP) (continued)
TA = 25°C and CREG25 = 1.0 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VUVPREL – 0.022
VUVPREL – 0.030
VUVPREL – 0.050
tUVP – 5%
TYP
VUVP + 0.105
VUVP + 0.105
VUVP + 0.105
tUVP
MAX
VUVPREL + 0.022
VUVPREL + 0.030
VUVPREL + 0.050
tUVP + 5%
UNIT
V
TA = 25°C
VUVPREL
UVP release voltage
UVP delay time
TA = –5°C to 50°C
TA = –40°C to 85°C
TA = –40°C to 85°C
tUVP
ms
6.11 Overcurrent in Discharge (OCD)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
TA = 25°C
VSRN – VSRP
VOCD – 3
VOCD
VOCD + 3
OCD detection voltage
threshold
TA = –20°C to 60°C
VSRN – VSRP
0.98 * VOCD
–
1.02 * VOCD +
VOCD
VOCD
3.125
0.98 * VOCD – 3.5
tOCD – 5%
3.125
1.02 * VOCD + 3.5
tOCD + 5%
TA = –40°C to 85°C
VSRN – VSRP
VOCD
tOCD
tOCD
OCD delay time
TA = –40°C to 85°C
ms
6.12 Overcurrent in Charge (OCC)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
TA = 25°C
VSRP – VSRN
VOCC – 3
VOCC
VOCC + 3
OCC detection voltage
threshold
TA = –20°C to 60°C
VSRP – VSRN
0.98 * VOCC
–
1.02 * VOCC +
VOCC
VOCC
3.125
0.98 * VOCC – 3.5
tOCC – 5%
3.125
1.02 * VOCC + 3.5
tOCC + 5%
TA = –40°C to 85°C
VSRP – VSRN
VOCC
tOCC
tOCC
OCC delay time
TA = –40°C to 85°C
ms
6.13 Short-Circuit in Discharge (SCD)
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VSCD
VSCD
VSCD
tSCD
MAX
UNIT
mV
µs
TA = 25°C
VSRN – VSRP
VSCD – 3
VSCD + 3
SCD detection voltage
threshold
TA = –20°C to 60°C
VSRN – VSRP
0.98 * VSCD
–
1.02 * VSCD
+
VSCD
3.125
3.125
TA = –40°C to 85°C
VSRN – VSRP
0.98 * VSCD
–
1.02 * VSCD
+
3.5
3.5
tSCD
SCD delay time
TA = –40°C to 85°C
tSCD – 30%
tSCD + 30%
6.14 Low Voltage Charging
TA = 25°C, CREG25 = 1.0 µF, and VVPWR = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage threshold for low-voltage charging
detection
VLVDET
TA = –40°C to 85°C
1.4
1.55
1.7
V
6.15 Internal Temperature Sensor Characteristics
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G(TEMP)
Temperature sensor voltage gain
–2
mV/°C
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6.16 High-Frequency Oscillator
2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
8.389
0.38%
0.38%
0.38%
2.5
MAX
UNIT
fOSC
Operating frequency
MHz
TA = 0°C to 60°C
–2.0%
–3.0%
-4.5%
2.0%
3.0%
4.5%
5
fEIO
Frequency error(1) (2)
Start-up time(3)
TA = –20°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 85°C
tSXO
ms
(1) The frequency error is measured from 2.097 MHz.
(2) The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25°C.
(3) The startup time is defined as the time it takes for the oscillator output frequency to be ±3% of the typical oscillator frequency.
6.17 Low-Frequency Oscillator
2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
32.768
0.25%
0.25%
0.25%
500
MAX
UNIT
f(LOSC)
f(LEIO)
t(LSXO)
Operating frequency
kHz
TA = 0°C to 60°C
–1.5%
–2.5%
-4.0%
1.5%
2.5%
4.0%
Frequency error(1) (2)
Start-up time(3)
TA = –20°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 85°C
μs
(1) The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA = 25°C.
(2) The frequency error is measured from 32.768 kHz.
(3) The startup time is defined as the time it takes for the oscillator output frequency to be ±3% of the typical oscillator frequency.
6.18 Integrating ADC (Coulomb Counter) Characteristics
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VSR_IN
Input voltage range, VSRN and VSRP VSR = VSRP – VSRN
VVPWR – 0.125
VVPWR + 0.125
tSR_CONV
Conversion time
Single conversion
1
s
Resolution
14
7
15
±0.034%
0.3
bits
μV
VSR_OS
INL
Input offset
10
Integral nonlinearity error
Effective input resistance(1)
Input leakage current(1)
±0.007%
FSR
MΩ
μA
ZSR_IN
ISR_LKG
(1) Assured by design. Not production tested.
6.19 ADC (Temperature and Cell Voltage) Characteristics
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VSS – 0.125
VSS – 0.125
TYP
MAX
5
UNIT
V
VADC_IN
Input voltage range (VBAT channel)
Input voltage range (other channels)
Conversion time
1
V
tADC_CONV
125
15
ms
bits
mV
MΩ
MΩ
kΩ
μA
Resolution
14
VADC_OS
ZADC1
Input offset
1
(1)
Effective input resistance (TS)
55
55
Not measuring cell voltage
Measuring cell voltage
ZADC2
Effective input resistance (BAT)(1)
Input leakage current(1)
100
IADC_LKG
0.3
(1) Assured by design. Not production tested.
10
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6.20 Data Flash Memory Characteristics
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
PARAMETER
Data retention(1)
TEST CONDITIONS
MIN
10
TYP
MAX
UNIT
years
cycles
ms
tDR
(1)
Flash programming write-cycles
Word programming time(1)
Flash-write supply current(1)
20,000
tWORDPROG
ICCPROG
2
5
10
mA
(1) Assured by design. Not production tested.
6.21 Timing Requirements
TA = –40°C to 85°C, 2.4 V < VREG25 < 2.6 V; typical values at TA = 25°C and VREG25 = 2.5 V (unless otherwise noted)
MIN
NOM
MAX UNIT
I2C-Compatible Interface Timing Characteristics (see Figure 1)
tR
SCL or SDA rise time
SCL or SDA fall time
SCL pulse width (high)
SCL pulse width (low)
Setup for repeated start
Start to first falling edge of SCL
Data setup time
300
300
ns
ns
ns
μs
tF
tw(H)
600
1.3
600
600
100
0
tw(L)
tsu(STA)
td(STA)
tsu(DAT)
th(DAT)
tsu(STOP)
tBUF
ns
ns
ns
ns
ns
μs
Data hold time
Setup time for stop
600
66
Bus free time between stop and start
Clock frequency
fSCL
400
kHz
HDQ Communication Timing Characteristics (see Figure 2)
t(CYCH)
t(CYCD)
t(HW1)
t(DW1)
t(HW0)
t(DW0)
t(RSPS)
t(B)
Cycle time, host to fuel gauge
Cycle time, fuel gauge to host
Host sends 1 to fuel gauge
Fuel gauge sends 1 to host
Host sends 0 to fuel gauge
Fuel gauge sends 0 to host
Response time, fuel gauge to host
Break time
190
190
0.5
32
μs
μs
μs
μs
μs
μs
μs
μs
μs
s
205
250
50
50
86
145
145
950
80
190
190
40
t(BR)
Break recovery time
t(RST)
t(RISE)
HDQ reset
1.8
2.2
HDQ line rise time to logic 1 (1.2 V)
950
ns
t
t
t
t
t
f
t
r
(BUF)
SU(STA)
w(H)
w(L)
SCL
SDA
t
t
t
d(STA)
su(STOP)
f
t
r
t
t
su(DAT)
h(DAT)
REPEATED
START
STOP
START
Figure 1. I2C-Compatible Interface Timing Diagrams
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1.2V
t(BR)
t(RISE)
t(B)
(b) HDQ line rise time
(a) Break and Break Recovery
t(DW1)
t(HW1)
t(DW0)
t(CYCD)
t(HW0)
t(CYCH)
(d) Gauge Transmitted Bit
(c) Host Transmitted Bit
7-bit address
1-bit
R/W
8-bit data
Break
t(RSPS)
(e) Gauge to Host Response
t(RST)
(f) HDQ Reset
a. HDQ Breaking
b. Rise time of HDQ line
c. HDQ Host to fuel gauge communication
d. Fuel gauge to Host communication
e. Fuel gauge to Host response format
f . HDQ Host to fuel gauge reset
A. HDQ Breaking
B. Rise time of HDQ line
C. HDQ Host to fuel gauge communication
D. Fuel gauge to Host communication
E. Fuel gauge to Host response format
F. HDQ Host to fuel gauge reset
Figure 2. HDQ Communication Timing Diagrams
12
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6.22 Typical Characteristics
4.500
4.490
4.480
4.470
4.460
4.450
4.440
4.430
4.420
4.410
4.400
2.490
2.480
2.470
2.460
2.450
2.440
2.430
2.420
2.410
2.400
2.390
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
œ40 œ30 œ20 œ10
œ40 œ30 œ20 œ10
Temperature (°C)
Temperature (°C)
C001
C001
UVP threshold shown assumes an overvoltage setting of 4.450 V
Figure 3. Overvoltage Detection Threshold vs Temperature
Figure 4. Undervoltage Detection Threshold vs Temperature
30
28
85
80
[OCD2, OCC1, OCD0] = 111
75
26
70
[OCC1, OCC0] = 11
[OCD2, OCC1, OCD0] = 110
24
65
22
60
[OCC1, OCC0] = 10
[OCD2, OCC1, OCD0] = 101
55
20
50
18
[OCD2, OCC1, OCD0] = 100
45
16
40
[OCC1, OCC0] = 01
[OCD2, OCC1, OCD0] = 011
14
35
30
12
[OCD2, OCC1, OCD0] = 010
25
10
[OCC1, OCC0] = 00
20
8
[OCD2, OCC1, OCD0] = 001
15
6
4
10
[OCD2, OCC1, OCD0] = 000
5
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
œ40 œ30 œ20 œ10
œ40 œ30 œ20 œ10
Temperature (°C)
Temperature (°C)
C001
C001
OCC thresholds shown assume an overvoltage setting of 4.450 V
OCD thresholds shown assume an overvoltage setting of 4.450 V
Figure 5. Overcurrent in Charge Detection Threshold vs
Temperature
Figure 6. Overcurrent in Discharge Detection Threshold vs
Temperature
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
150
145
[SCD] = 1
140
135
130
125
120
115
110
105
100
95
90
85
80
[SCD] = 0
75
70
0
10 20 30 40 50 60 70 80
œ40 œ30 œ20 œ10
0
10 20 30 40 50 60 70 80
œ40 œ30 œ20 œ10
Temperature (°C)
Temperature (°C)
C001
C001
SCD thresholds shown assume an overvoltage setting of 4.450 V
Figure 8. Overvoltage Delay Time
Figure 7. Short-Circuit in Discharge Detection Threshold vs
Temperature
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Typical Characteristics (continued)
34.00
33.50
33.00
32.50
32.00
31.50
31.00
30.50
30.00
29.50
29.00
9.00
8.80
8.60
8.40
8.20
8.00
7.80
7.60
7.40
7.20
7.00
6.80
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
œ40 œ30 œ20 œ10
œ40 œ30 œ20 œ10
Temperature (°C)
Temperature (°C)
C001
C001
Figure 9. Undervoltage Delay Time
Figure 10. Overcurrent in Charge Delay Time vs
Temperature
34.00
33.50
33.00
32.50
32.00
31.50
31.00
30.50
30.00
29.50
29.00
350
345
340
335
330
325
320
315
310
305
300
295
290
285
280
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
œ40 œ30 œ20 œ10
œ40 œ30 œ20 œ10
Temperature (°C)
Temperature (°C)
C001
C001
Figure 11. Overcurrent in Discharge Delay vs Temperature
Figure 12. Short-Circuit in Discharge Delay vs Temperature
170
39
165
160
155
150
145
38
37
36
35
34
140
VPWR = 2.8V
VPWR = 2.8V
33
135
VPWR = 3.7V
VPWR = 3.7V
VPWR = 4.2V
VPWR = 4.2V
130
32
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (°C)
Temperature (°C)
C020
C021
Performance with CL = 4 nF
Figure 13. FET Gate Rise Time vs Temperature
Performance with CL = 4 nF
Figure 14. FET Gate Fall Time vs Temperature
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7 Detailed Description
7.1 Overview
The bq27742-G1 fuel gauge accurately predicts the battery capacity and other operational characteristics of a
single Li-based rechargeable cell. It can be interrogated by a system processor to provide cell information, such
as state-of-charge (SOC) and time-to-empty (TTE).
7.2 Functional Block Diagram
CC
+
0.3 V
SCD
Delay
Wake
Comparator
POR
–
HFO/128
+
–
+
VSCD
–
+
VUVP
VPWR
SRN
LDO
+
–
+
UVP
Delay
VOCD
+
OCD
Delay
BAT
+
SRP
OVP
Delay
VPWR
+
–
HFO
VOVP
–
+
20 kΩ
VOCC
4R
2.5 V
OCC
Delay
Protector
FSM
REG25
PACKP
CHG
DSG
SDA
HFO
LFO
+
R
360 kΩ
HFO/128
ADC
TS
MUX
CHG Drive
VPWR
5 kΩ
Internal
Temp
Sensor
NC
DSG Drive
HFO/4
RC2
22
22
Instruction
ROM
I2C Engine
CPU
VSS
SCL
I/O
Controller
Instruction
FLASH
HDQ
HDQ
Engine
8
8
Wake
and
GP Timer
and
PWM
Data
SRAM
Data
FLASH
Watchdog
Timer
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7.3 Feature Description
7.3.1 Configuration
Cell information is stored in the fuel gauge in non-volatile flash memory. Many of these data flash locations are
accessible during application development. They cannot, generally, be accessed directly during end-equipment
operation. Access to these locations is achieved by either use of the companion evaluation software, through
individual commands, or through a sequence of data-flash-access commands. To access a desired data flash
location, the correct data flash subclass and offset must be known.
The fuel gauge provides 64 bytes of user-programmable data flash memory, partitioned into two 32-byte blocks:
Manufacturer Info Block A and Manufacturer Info Block B. This data space is accessed through a data flash
interface.
7.3.2 Fuel Gauging
The key to the high-accuracy gas gauging prediction is Texas Instruments proprietary Impedance Track
algorithm. This algorithm uses cell measurements, characteristics, and properties to create state-of-charge
predictions that can achieve less than 1% error across a wide variety of operating conditions and over the
lifetime of the battery.
See Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm Application Note
(SLUA364) for further details.
7.3.3 Power Modes
To minimize power consumption, the fuel gauge has different power modes: NORMAL, SLEEP, and
FULLSLEEP. The fuel gauge passes automatically between these modes, depending upon the occurrence of
specific events, though a system processor can initiate some of these modes directly.
7.3.3.1 NORMAL Mode
The fuel gauge is in NORMAL mode when not in any other power mode. During this mode, AverageCurrent(),
Voltage(), and Temperature() measurements are taken, and the interface data set is updated. Decisions to
change states are also made. This mode is exited by activating a different power mode.
Because the fuel gauge consumes the most power in NORMAL mode, the Impedance Track algorithm minimizes
the time the fuel gauge remains in this mode.
7.3.3.2 SLEEP Mode
SLEEP mode performs AverageCurrent(), Voltage(), and Temperature() less frequently which results in reduced
power consumption. SLEEP mode is entered automatically if the feature is enabled (Pack Configuration
[SLEEP] = 1) and AverageCurrent() is below the programmable level Sleep Current. Once entry into SLEEP
mode has been qualified, but prior to entering it, the fuel gauge performs an ADC autocalibration to minimize
offset.
During the SLEEP mode, the fuel gauge periodically takes data measurements and updates its data set.
However, a majority of its time is spent in an idle condition.
The fuel gauge exits SLEEP if any entry condition is broken, specifically when either:
•
•
AverageCurrent() rises above Sleep Current or
A current in excess of IWAKE through RSENSE is detected.
7.3.3.3 FULLSLEEP Mode
FULLSLEEP mode turns off the high-frequency oscillator and performs AverageCurrent(), Voltage(), and
Temperature() less frequently which results in power consumption that is lower than that of the SLEEP mode.
FULLSLEEP mode can be enabled by two methods:
•
Setting the [FULLSLEEP] bit in the Control Status register using the FULL_SLEEP subcommand and Full
Sleep Wait Time (FS Wait) in data flash is set as 0.
•
Setting the Full Sleep Wait Time (FS Wait) in data flash to a number larger than 0. This method is disabled
when the FS Wait is set as 0.
16
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Feature Description (continued)
FULLSLEEP mode is entered automatically when it is enabled by one of the methods above. When the first
method is used, the gauge enters the FULLSLEEP mode when the fuel gauge is in SLEEP mode. When the
second method is used, the FULLSLEEP mode is entered when the fuel gauge is in SLEEP mode and the timer
counts down to 0.
The fuel gauge exits the FULLSLEEP mode when there is any communication activity. Therefore, the execution
of SET_FULLSLEEP sets the [FULLSLEEP] bit. The FULLSLEEP mode can be verified by measuring the
current consumption of the gauge.
During FULLSLEEP mode, the fuel gauge periodically takes data measurements and updates its data set.
However, a majority of its time is spent in an idle condition.
The fuel gauge exits SLEEP if any entry condition is broken, specifically when either:
•
•
AverageCurrent() rises above Sleep Current, or
A current in excess of IWAKE through RSENSE is detected.
While in FULLSLEEP mode, the fuel gauge can suspend serial communications by as much as 4 ms by holding
the comm line(s) low. This delay is necessary to correctly process host communication, because the fuel gauge
processor is mostly halted in SLEEP mode.
7.3.4 Li-Ion Battery Protector Description
The battery protector controls two external high-side N-channel FETs in a back-to-back configuration for battery
protection. The protector uses two voltage doublers to drive the CHG and DSG FETs on.
7.3.4.1 High-Side NFET Charge and Discharge FET Drive
These FETs are automatically turned off by the protector based on the detected hardware protection faults or by
the fuel gauge based on detected firmware protection faults. This enables the gauge to be configured with
effectively two levels of safety: the first level employing conservative protection settings to keep the cell within a
safe operating area and the second level set to act as a fail-safe measure to prevent cell damage. Once the
protection fault(s) is deemed to be cleared, the protector or fuel gauge will re-enable the applicable FET(s).
Additionally, the FET drivers can be manually tested at production using the FETTest(0x74/0x75) extended
command if needed.
7.3.4.2 Protector Configuration
The integrated Li-Ion hardware protector includes full programmability of its fault detection thresholds, eliminating
the need to order several part variants to accommodate different system safety threshold needs. Configuration of
the thresholds is provided in the form of data flash parameters, Prot OV Config and Prot OC Config, which are
bit-mapped to two simple lookup tables that determine the protector safety thresholds. Table 3 through Table 6
detail the protection settings available for hardware overvoltage, overcurrent in charge, overcurrent in discharge,
and short-circuit in discharge, respectively. An added degree of flexibility is made possible in combining the
programmable thresholds with changes to the selected sense resistor value, enabling a wide variety of Li-Ion
protection options in a single device.
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Feature Description (continued)
Table 3. Hardware Overvoltage Protection Configuration
Prot OV Config
OVERVOLTAGE (VOVP) SETTING
[OVP2]
[OVP1]
[OVP0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4.275 V
4.300 V
4.325 V
4.350 V
4.375 V
4.400 V
4.425 V
4.450 V (default)
Table 4. Hardware Overcurrent in Charge Configuration
Prot OC Config
OVERCURRENT IN CHARGE (VOCC) SETTING
[OCC1]
[OCC0]
0
0
1
1
0
1
0
1
6 mV
13 mV
18 mV (default)
28 mV
Table 5. Hardware Overcurrent in Discharge Configuration
Prot OC Config
OVERCURRENT IN DISCHARGE (VOCD) SETTING
[OCD1]
[OCD0]
[OCD0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
14 mV
24 mV
34 mV (default)
44 mV
53 mV
63 mV
73 mV
83 mV
Table 6. Hardware Short-Circuit in Discharge Configuration
Prot OC Config
SHORT-CIRCUIT IN DISCHARGE (VSCD) SETTING
[SCD]
0
1
73 mV (default)
148 mV
7.4 Device Functional Modes
7.4.1 Operating Modes
The battery protector has several operating modes depending on a variety of conditions. These modes are
described below:
•
•
•
•
•
NORMAL Mode
OVERVOLTAGE Mode
UNDERVOLTAGE Mode
OVERCURRENT IN CHARGE Mode
OVERCURRENT IN DISCHARGE and SHORT-CIRCUIT IN DISCHARGE Mode
18
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ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
Device Functional Modes (continued)
•
SHUTDOWN WAIT Mode
–
–
ANALOG SHUTDOWN State
LOW VOLTAGE CHARGING State
The relationships among these modes are shown in Figure 15.
UVP Fault
(POR State)
CHG FET on
DSG FET off
Fuel Gauge on
LDO is on
Normal
FW(ROM) turns
FETs off briefly
Fuel Gauge in
(VSRP – VSRN) > VOCC
Normal, SLEEP,
FULLSLEEP Modes
CHG FET on
OCC Fault
CHG FET off
DSG FET on
Fuel Gauge on
LDO on
Fault recovery:
DSG FET on
Fuel Gauge on
LDO is on
Charger removed
POR
(Force UVP set)
Low Voltage Charging
(VSRN – VSRP) > VOCD
OR
(VSRN – VSRP) > VSCD
CHG FET control shorted to
Charger removed
AND
PACKP pin
DSG FET off
Protection off
Fuel Gauge off
LDO is off
V
BAT < Shutdown V
VBAT > VOVP
Shutdown bit
cleared
Charger removed
AND
VBAT
< Shutdown V
Fault recovery:
load removed
Shutdown Bit
set
Charger attached
AND
VBAT < VOVPREL
AND
OCD/SCD Fault
VBAT > VLVDET
Fault recovery:
Charger removed
Analog Shutdown
CHG FET on
DSG FET off
Fuel Gauge on
LDO on
Shutdown Wait
CHG FET off
DSG FET off
Fuel Gauge off
LDO is off
OVP Fault
CHG FET off
DSG FET off
Fuel Gauge on
LDO is on
CHG FET off
DSG FET on
Fuel Gauge on
LDO on
Charger removed
Virtual Shutdown
Figure 15. Operating Modes
7.4.1.1 NORMAL Mode
In this mode, the protector is fully powered and operational. Both CHG and DSG FETs are closed and the
protector continuously checks for fault conditions.
FET enable override capability is available to the fuel gauge to force the CHG or DSG FET open based on
firmware instruction. It is useful for firmware-defined safety features or other special functionality that requires
one or both FETs to be opened based on specific conditions. It cannot, however, be used to enforce FET turn-on
when the hardware protector is one of the protection fault modes, as the latter has ultimate authority over the
FET drive control circuitry.
Firmware can also command the fuel gauge to go into SHUTDOWN mode based on a dedicated Control()
subcommand from the host. In this case, firmware sets the shutdown bit, [SHUTDWN], to indicate intent to go
into SHUTDOWN mode. The fuel gauge then transitions to SHUTDOWN WAIT mode and waits for charger
removal prior to disabling the internal LDO and fully powering down the entire device.
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Device Functional Modes (continued)
7.4.1.2 OVERVOLTAGE Mode
In this mode, an overvoltage protection (OVP) fault mode is entered when the voltage on the VBAT pin
continuously exceeds the VOVP threshold for longer than the tOVP delay time. At this point, the fuel gauge enables
the fault recovery detection circuitry, which monitors the PACKP pin for charger removal. The OVP fault is
cleared once the pack voltage drops below the cell voltage by more than 300 mV and the cell voltage drops
below VOVPREL, which causes the fuel gauge to transition to NORMAL mode.
7.4.1.3 UNDERVOLTAGE Mode
In this mode, an undervoltage protection (UVP) fault mode is entered when the voltage on the VBAT pin
continuously falls below the VUVP threshold for longer than the tUVP delay time. The fuel gauge then enables the
charger attachment detection circuitry and, if no charger is found, sends the fuel gauge into ANALOG
SHUTDOWN mode to minimize power consumption and avoid further discharge of the battery. The UVP fault is
cleared once charger attachment is detected and the cell voltage rises above VUVPREL, which causes the fuel
gauge to transition to NORMAL mode.
The fuel gauge can enter this mode from LOW VOLTAGE CHARGING mode when the battery pack is being
charged from a deeply discharged state or from NORMAL mode when the battery pack is being discharged past
the UVP threshold.
7.4.1.4 OVERCURRENT IN CHARGE Mode
In this mode, an OVERCURRENT IN CHARGE (OCC) fault mode is entered when the voltage across the sense
resistor continuously exceeds the VOCC threshold for longer than the configured tOCC delay time. Recovery occurs
when the PACKP voltage drops to more than 300 mV below the cell voltage, indicating charger removal.
7.4.1.5 OVERCURRENT IN DISCHARGE and SHORT-CIRCUIT IN DISCHARGE Mode
In this mode, a short-circuit in discharge (SCD) or overcurrent in discharge (OCD) protection fault is detected
when the voltage across the sense resistor continuously exceeds the VOCD or VSCD thresholds for longer than the
tOCD or tSCD delay times. Recovery occurs when the PACKP voltage rises to within 300 mV of the cell voltage,
indicating load removal.
7.4.1.6 SHUTDOWN WAIT Mode
A transition to this mode occurs when the host sends the SET_SHUTDOWN command and the fuel gauge
subsequently initiated the shutdown sequence.
The shutdown sequence is as follows:
1. Open both CHG and DSG FETs.
2. Determine if any faults are set. If any faults are set, then go back to NORMAL mode.
3. Wait for charger removal. Once the charger is removed, turn off the LDO, which puts the fuel gauge into
ANALOG SHUTDOWN mode.
7.4.1.6.1 ANALOG SHUTDOWN State
In this mode, the fuel gauge is completely powered down and no portions of the device are functional. Once the
charger is connected, the fuel gauge will transition into either LOW VOLTAGE CHARGING mode (if below the
power-on reset voltage) or NORMAL mode (if above the POR voltage and no faults are detected).
7.4.1.7 LOW VOLTAGE CHARGING State
In this mode, the fuel gauge shorts the CHG FET gate to PACKP pin if the cell voltage is above the VLVDET
threshold, allowing the battery to be trickle charged with the CHG FET biased in the ohmic region. If below the
aforementioned threshold, low voltage charging is prohibited for safety reasons and the cell will likely be
permanently unrecoverable due to being dangerously depleted.
7.4.2 Firmware Control of Protector
The firmware has control to open the CHG FET or DSG FET independently by overriding hardware control.
However, it has no control to close the CHG FET or DSG FET and can only disable the FET override.
20
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Device Functional Modes (continued)
7.4.3 OVERTEMPERATURE FAULT Mode
Gauging firmware monitors temperature every second and will open either the CHG FET if Temperature() > OT
Chg for OT Chg Time in CHARGING mode or open the DSG FET if Temperature() > OT Dsg for OT Dsg Time
in DISCHARGING mode. Gauge determination of charge or discharge mode is based on Current() > Chg
Current Threshold for Quit Relax Time or Current() < Dsg Current Threshold for Quit Relax Time. Recovery
from the given overtemperature fault occurs when Temperature() < OT Chg Recovery or < OT Dsg Recovery,
depending on if a charge overtemperature or discharge overtemperature fault is present.
7.4.4 Wake-Up Comparator
The wake-up comparator indicates a change in cell current while the fuel gauge is in SLEEP mode. Wake
comparator threshold can be configured in firmware and set to the thresholds in Table 7. An internal event is
generated when the threshold is breached in either charge or discharge directions.
Table 7. IWAKE Threshold Settings(1)
RSNS1
RSNS0
IWAKE
Vth(SRP-SRN)
Disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
1.0 mV or –1.0 mV
2.2 mV or –2.2 mV
2.2 mV or –2.2 mV
4.6 mV or –4.6 mV
4.6 mV or –4.6 mV
9.8 mV or –9.8 mV
(1) The actual resistance value versus the setting of the sense resistor is not important just the actual voltage threshold when calculating
the configuration. The voltage thresholds are typical values under room temperature.
7.5 Battery Parameter Measurements
7.5.1 Charge and Discharge Counting
The integrating delta-sigma ADC measures the charge or discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SRP and SRN pins. The integrating ADC measures bipolar
signals and detects charge activity when VSR = VSRP – VSRN is positive and discharge activity when VSR = VSRP
VSRN is negative. The fuel gauge continuously integrates the signal over time using an internal counter.
–
7.5.2 Voltage
The fuel gauge updates cell voltages at 1-second intervals when in NORMAL mode. The internal ADC of the fuel
gauge measures the voltage, and scales and calibrates it appropriately. Voltage measurement is automatically
compensated based on temperature. This data is also used to calculate the impedance of the cell for Impedance
Track fuel gauging.
7.5.3 Current
The fuel gauge uses the SRP and SRN inputs to measure and calculate the battery charge and discharge
current using a 5-mΩ to 20-mΩ typical sense resistor.
7.5.4 Auto-Calibration
The fuel gauge provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The fuel gauge performs auto-calibration before entering the SLEEP
mode.
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Battery Parameter Measurements (continued)
7.5.5 Temperature
The fuel gauge external temperature sensing is optimized with the use of a high-accuracy negative temperature
coefficient (NTC) thermistor with R25 = 10 kΩ ± 1% and B25/85 = 3435 kΩ ± 1% (such as Semitec 103AT for
measurement). The fuel gauge can also be configured to use its internal temperature sensor. The fuel gauge
uses temperature to monitor the battery-pack environment, which is used for fuel gauging and cell protection
functionality.
NOTE
Formatting Conventions in This Document:
Commands: italics with parentheses and no breaking spaces, for example,
RemainingCapacity()
Data Flash: italics, bold, and breaking spaces; for example, Design Capacity
Register Bits and Flags: brackets only; for example, [TDA]
Data Flash Bits: italic and bold; for example, [XYZ1]
Modes and States: ALL CAPITALS; for example, UNSEALED mode
7.6 Communications
7.6.1 HDQ Single-Pin Serial Interface
The HDQ interface is an asynchronous return-to-one protocol where a processor sends the command code to
the fuel gauge. With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted
first. The DATA signal on pin 12 is open-drain and requires an external pullup resistor. The 8-bit command code
consists of two fields: the 7-bit HDQ command code (bits 0 through 6) and the 1-bit RW field (MSB bit 7). The
RW field directs the fuel gauge either to:
•
•
Store the next 8 bits of data to a specified register, or
Output 8 bits of data from the specified register
The HDQ peripheral can transmit and receive data as either an HDQ master or slave.
HDQ serial communication is normally initiated by the host processor sending a break command to the fuel
gauge. A break is detected when the DATA pin is driven to a logic low state for a time t(B) or greater. The DATA
pin then is returned to its normal ready logic high state for a time t(BR). The fuel gauge is now ready to receive
information from the host processor.
The fuel gauge is shipped in the I2C mode. TI provides tools to enable the HDQ peripheral.
7.6.2 I2C Interface
The fuel gauge supports the standard I2C read, incremental read, one-byte write quick read, and functions. The
7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit
device address is therefore 0xAA or 0xAB for write or read, respectively.
22
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Communications (continued)
GG Generated
Host Generated
A
CMD[7:0]
DATA[7:0]
A P
A
S
ADDR[6:0]
1
A
S
ADDR[6:0]
0
DATA[7:0]
N P
N P
(a)
(b)
Sr
S
ADDR[6:0] 0 A
CMD[7:0]
A
ADDR[6:0]
1
A
DATA[7:0]
( c)
Sr
. . .
S
ADDR[6:0] 0 A
CMD[7:0]
A
ADDR[6:0]
1
A
DATA[7:0]
A
DATA[7:0]
N P
(d)
A. 1-byte write; b. Quick read; c. 1-byte read; Incremental read (S = Start, Sr = Repeated Start, A = Acknowledge, N =
No Acknowledge, and P = Stop)
Figure 16. Supported I2C Formats
The quick read returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I2C communication engine, increments whenever data is acknowledged by the fuel gauge or the
I2C master. Quick writes function in the same manner and are a convenient means of sending multiple bytes to
consecutive command locations (such as two-byte commands that require two bytes of data).
Attempt to write a read-only address (NACK after data sent by master):
A
CMD[7:0]
A
S
ADDR[6:0]
0
DATA[7:0]
P
N
Attempt to read an address above 0x7F (NACK command):
P
N
A
0
CMD[7:0]
S
ADDR[6:0]
Attempt at incremental writes (NACK all extra data bytes sent):
A
CMD[7:0]
. . .
N P
A
S
ADDR[6:0]
0
DATA[7:0]
A
DATA[7:0]
N
Incremental read at the maximum allowed read address:
A
CMD[7:0]
A
Sr
S
ADDR[6:0]
0
ADDR[6:0]
1
A
DATA[7:0]
A
DATA[7:0]
N P
Data from
addr 0x74
Data from
addr 0x00
Address
0x7F
Figure 17. I2C Interfaces
The I2C engine releases both SDA and SCL if the I2C bus is held low for t(BUSERR). If the fuel gauge was holding
the lines, releasing them frees the master to drive the lines. If an external condition is holding either of the lines
low, the I2C engine enters the low-power SLEEP mode.
7.6.2.1 I2C Time Out
The I2C engine releases both SDA and SCL lines if the I2C bus is held low for about 2 seconds. If the fuel gauge
was holding the lines, releasing them frees the master to drive the lines.
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Communications (continued)
7.6.2.2 I2C Command Waiting Time
To ensure the correct results of a command with the 400-kHz I2C operation, a proper waiting time must be added
between issuing a command and reading the results. For subcommands, the following diagram shows the
waiting time required between issuing the control command and reading the status with the exception of the
checksum command. A 100-ms waiting time is required between the checksum command and reading the result.
For read-write standard commands, a minimum of 2 seconds is required to get the result updated. For read-only
standard commands, there is no waiting time required, but the host must not issue any standard command more
than two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the
watchdog timer.
S
S
ADDR[6:0] 0 A
ADDR[6:0] 0 A
CMD[7:0]
CMD[7:0]
A
A
DATA[7:0]
A
DATA[7:0]
DATA[7:0]
A P
66ms
DATA[7:0]
Sr
ADDR[6:0] 1 A
A
N P
66ms
Waiting time between control subcommand and reading results
S
ADDR[6:0] 0 A
CMD[7:0]
DATA[7:0]
A
Sr
ADDR[6:0]
66ms
1
A
DATA[7:0]
A
DATA[7:0]
A
DATA[7:0]
A
N P
Waiting time between continuous reading results
Figure 18. I2C Command Waiting Time
The I2C clock stretch could happen in a typical application. A maximum 80-ms clock stretch could be observed
during the flash updates. There is up to a 270-ms clock stretch after the OCV command is issued.
7.7 Standard Data Commands
The fuel gauge uses a series of 2-byte standard commands to enable system reading and writing of battery
information. Each standard command has an associated command-code pair, as indicated in Table 8. Each
protocol has specific means to access the data at each Command Code. Data RAM is updated and read by the
gauge only once per second. Standard commands are accessible in NORMAL operation mode.
Table 8. Standard Commands
COMMAND NAME
COMMAND CODE
0x00 and 0x01
0x02 and 0x03
0x04 and 0x05
0x06 and 0x07
0x08 and 0x09
0x0A and 0x0B
0x0C and 0x0D
0x0E and 0x0F
0x10 and 0x11
0x12 and 0x13
0x14 and 0x15
0x16 and 0x17
0x18 and 0x19
0x1A and 0x1B
0x1C and 0x1D
0x1E and 0x1F
0x20 and 0x21
0x22 and 0x23
UNIT
—
SEALED ACCESS
Control()
RW
RW
R
AtRate()
mA
UnfilteredSOC()
Temperature()
Voltage()
%
0.1°K
mV
R
R
Flags()
—
R
NomAvailableCapacity()
FullAvailableCapacity()
RemainingCapacity()
FullChargeCapacity()
AverageCurrent()
TimeToEmpty()
FilteredFCC()
mAh
mAh
mAh
mAh
mA
R
R
R
R
R
min
mAh
—
R
R
SafetyStatus()
R
UnfilteredFCC()
Imax()
mAh
mA
R
R
UnfilteredRM()
mAh
mAh
R
FilteredRM()
R
24
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ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
Standard Data Commands (continued)
Table 8. Standard Commands (continued)
COMMAND NAME
COMMAND CODE
0x24 and 0x25
0x26 and 0x27
0x28 and 0x29
0x2A and 0x2B
0x2C and 0x2D
0x2E and 0x2F
0x30 and 0x31
0x32 and 0x33
0x34 and 0x35
0x36 and 0x37
0x38 and 0x39
UNIT
mAh
mAh
0.1°K
Counts
%
SEALED ACCESS
BTPSOC1Set()
RW
RW
R
BTPSOC1Clear()
InternalTemperature()
CycleCount()
R
StateofCharge()
StateofHealth()
ChargingVoltage()
ChargingCurrent)
PassedCharge()
DOD0()
R
%/num
mV
R
R
mA
R
mAh
hex
R
R
SelfDischargeCurrent()
mA
R
7.7.1 Control(): 0x00 and 0x01
Issuing a Control() command requires a subsequent 2-byte subcommand. These additional bytes specify the
particular control function desired. The Control() command allows the system to control specific features of the
fuel gauge during normal operation and additional features when the fuel gauge is in different access modes, as
described in Table 9.
Table 9. Control() Subcommands
SUBCOMMAND
CODE
SEALED
ACCESS
SUBCOMMAND NAME
DESCRIPTION
CONTROL_STATUS
DEVICE_TYPE
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0007
0x0008
0x0009
0x000A
0x000C
0x0010
0x0013
0x0014
0x0017
0x0018
0x0019
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Reports the status of DF Checksum, Impedance Track, and so on.
Reports the device type of 0x0742 (indicating bq27742-G1).
Reports the firmware version on the device type.
Reports the hardware version on the device type.
Reports the hardware protector version on the device type.
Returns reset data.
FW_VERSION
HW_VERSION
PROTECTOR_VERSION
RESET_DATA
PREV_MACWRITE
CHEM_ID
Returns previous Control() subcommand code.
Reports the chemical identifier of the Impedance Track configuration.
Forces the device to measure and store the board offset.
Forces the device to measure the CC offset.
BOARD_OFFSET
CC_OFFSET
No
DF_VERSION
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Reports the data flash version of the device.
SET_FULLSLEEP
SET_SHUTDOWN
CLEAR_SHUTDOWN
STATIC_CHEM_CHKSUM
ALL_DF_CHKSUM
STATIC_DF_CHKSUM
Sets the CONTROL_STATUS[FULLSLEEP] bit to 1.
Sets the CONTROL_STATUS[SHUTDWN] bit to 1.
Clears the CONTROL_STATUS[SHUTDWN] bit to 1.
Calculates chemistry checksum.
Reports checksum for all data flash excluding device specific variables.
Reports checksum for static data flash excluding device specific variables.
Reports checksum for protector configuration data flash excluding device
specific variables.
PROTECTOR_CHKSUM
0x001A
Yes
SEALED
0x0020
0x0021
0x0023
No
No
Places the fuel gauge in SEALED access mode.
Enables the Impedance Track algorithm.
IT_ENABLE
IMAX_INT_CLEAR
Yes
Clears an Imax interrupt that is currently asserted on the RC2 pin.
Starts FET Test based on data entered in FETTest() register. Sets and
clears the [FETTST] bit in CONTROL_STATUS.
START_FET_TEST
0x0024
No
CAL_ENABLE
RESET
0x002D
0x0041
No
No
Toggle CALIBRATION mode.
Forces a full reset of the fuel gauge.
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Table 9. Control() Subcommands (continued)
SUBCOMMAND
CODE
SEALED
ACCESS
SUBCOMMAND NAME
EXIT_CAL
DESCRIPTION
0x0080
0x0081
0x0082
No
No
No
Exit CALIBRATION mode.
Enter CALIBRATION mode.
ENTER_CAL
OFFSET_CAL
Reports internal CC offset in CALIBRATION mode.
7.8 Extended Data Commands
Extended commands offer additional functionality beyond the standard set of commands. They are used in the
same manner; however unlike standard commands, extended commands are not limited to 2-byte words. The
number of command bytes for a given extended command ranges in size from single to multiple bytes, as
specified in Table 10. For details on the SEALED and UNSEALED states, see the Access Modes section in the
bq27742-G1 Technical Reference Manual (SLUUAX0).
Table 10. Extended Commands
NAME
COMMAND CODE
UNIT
SEALED
UNSEALED
ACCESS(1)(2)
ACCESS(1)(2)
PackConfiguration()
DesignCapacity()
DataFlashClass()(2)
DataFlashBlock()(2)
BlockData()/Authenticate()(3)
BlockData()/AuthenticateCheckSum()(3)
BlockData()
0x3A and 0x3B
0x3C and 0x3D
0x3E
Hex
mAh
NA
R
R
R
R
NA
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
R
0x3F
NA
0x40 to 0x53
0x54
NA
NA
0x55 to 0x5F
0x60
NA
BlockDataCheckSum()
BlockDataControl()
DODatEOC()
NA
RW
NA
R
0x61
NA
0x62 and 0x63
0x64 and 0x65
0x66 and 0x67
0x68 to 0x6C
0x6D
NA
Qstart()
mAh
mAh
NA
R
R
FastQmax()
R
R
Reserved
R
R
ProtectorStatus()
Reserved
Hex
NA
R
R
0x6E and 0x6F
0x70 and 0x71
0x72 and 0x73
0x74 and 0x75
0x76 and 0x77
0x78
R
R
SimultaneousCurrent()
Reserved
mA
R
R
NA
R
R
FETTest()
Hex
mW or cW
Hex
R
RW
R
AveragePower()
ProtectorState()
AN_COUNTER
AN_CURRENT_LSB
AN_CURRENT_MSB
AN_VCELL_LSB
AN_VCELL_MSB
AN_TEMP_LSB
AN_TEMP_MSB
R
R
R
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
(1) SEALED and UNSEALED states are entered via commands to Control() 0x00 and 0x01
(2) In SEALED mode, data flash cannot be accessed through commands 0x3E and 0x3F.
(3) The BlockData() command area shares functionality for accessing general data flash and for using Authentication. See Authentication in
the bq27742-G1 Technical Reference Manual (SLUUAX0) for more details.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The bq27742-G1 is a single-cell fuel gauge with integrated Li-Ion protection circuitry for highly accurate detection
of overvoltage, undervoltage, overcurrent in charge, overcurrent in discharge, and short-circuit in discharge fault
conditions. If the detected fault continues to be present for a specific delay time (preconfigured in the device), the
protection front-end will disable the applicable charge pump circuit, resulting in opening of the FET until the
provoking safety condition resolves. The integrated 16-bit delta-sigma converters provide accurate, high precision
measurements for voltage, current, and temperature in order to accomplish effective battery monitoring,
protection, and gauging. To allow for optimal performance in the end application, special considerations must be
taken to ensure minimization of measurement error through proper printed circuit board (PCB) board layout and
correct configuration of battery characteristics in the fuel gauge data flash. Such requirements are detailed in
Design Requirements.
8.2 Typical Applications
8.2.1 Pack-Side, Single-Cell Li-Ion Fuel Gauge and Protector
0.1 µF 0.1 µF
5 mΩ
PACK+
200 Ω
200 Ω
0.1 µF 0.1 µF
0.1 µF
0.1 µF
0.1 µF
1 kΩ
1 kΩ
2 kΩ
10 Ω
10 Ω
VPWR
BAT
SRN
SRP
0.1 µF
0.1 µF
REG25
TS
PACKP
CHG
DSG
0.1 µF
1 µF
10 kΩ
(25°C)
NC
100 Ω
100 Ω
100 Ω
100 Ω
SDA
SCL
RC2
VSS
SDA
0.47 µF
SCL
HDQ
PACK–
Copyright © 2017, Texas Instruments Incorporated
Figure 19. I2C Mode Schematic
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Typical Applications (continued)
0.1 µF 0.1 µF
5 mΩ
PACK+
200 Ω
200 Ω
0.1 µF 0.1 µF
0.1 µF
0.1 µF
1 kΩ
1 kΩ
2 kΩ
0.1 µF
10 Ω
VPWR
BAT
SRN
SRP
10 Ω
0.1 µF
0.1 µF
REG25
TS
PACKP
CHG
DSG
0.1 µF
1 µF
10 kΩ
(25°C)
NC
RC2
VSS
SDA
0.47 µF
SCL
100 Ω
100 Ω
HDQ
HDQ
4.7 kΩ
–
PACK
Copyright © 2017, Texas Instruments Incorporated
Figure 20. HDQ Mode Schematic
8.2.2 Design Requirements
Several key parameters must be updated to align with a given application's battery characteristics. For highest
accuracy gauging, it is important to follow-up this initial configuration with a learning cycle to optimize resistance
and maximum chemical capacity (Qmax) values prior to sealing and shipping packs to the field. Successful and
accurate configuration of the fuel gauge for a target application can be used as the basis for creating a "golden"
gas gauge (.GG) file that can be written to all production packs, assuming identical pack design and Li-Ion cell
origin (chemistry, lot, and so on). Calibration data can be included as part of this golden GG file to cut down on
battery pack production time. If going this route, it is recommended to average the calibration data from a large
sample size and use these in the golden file. Ideally, it is recommended to calibrate all packs individually as this
will lead to the highest performance and lowest measurement error in the end application on a per-pack basis. In
addition, the integrated protection functionality should be correctly configured to ensure activation based on the
fault protection needs of the target pack design, or else accidental trip could be possible if using defaults.
Table 11, Key Data Flash Parameters for Configuration, shows the items that should be configured to achieve
reliable protection and accurate gauging with minimal initial configuration.
Table 11. Key Data Flash Parameters for Configuration
NAME
DEFAULT
UNIT
RECOMMENDED SETTING
Set based on the nominal pack capacity as interpreted from cell manufacturer's
datasheet. If multiple parallel cells are used, should be set to N * Cell Capacity.
Design Capacity
1000
mAh
Set based on the nominal pack energy (nominal cell voltage * nominal cell
capacity) as interpreted from the cell manufacturer's datasheet. If multiple parallel
cells are used, should be set to N * Cell Energy.
Design Energy
3800
mWh
28
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ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
Typical Applications (continued)
Table 11. Key Data Flash Parameters for Configuration (continued)
NAME
DEFAULT
UNIT
RECOMMENDED SETTING
Set to 10 to convert all power values to cWh or to 1 for mWh. Design Energy is
divided by this value.
Design Energy Scale
1
—
Set to desired runtime remaining (in seconds/3600) * typical applied load
between reporting 0% SOC and reaching Terminate Voltage, if needed.
Reserve Capacity
0
mAh
Design Voltage
3800
900
mV
Set to nominal cell voltage per manufacturer datasheet.
Cycle Count Threshold
mAh
Set to 90% of configured Design Capacity
Should be configured using TI-supplied Battery Management Studio software.
Default open-circuit voltage and resistance tables are also updated in conjunction
with this step. Do not attempt to manually update reported Device Chemistry as
this does not change all chemistry information! Always update chemistry using
the appropriate software tool (that is, BMS).
Device Chemistry
0354
hex
Load Mode
Load Select
1
1
—
—
Set to applicable load model, 0 for constant current or 1 for constant power.
Set to load profile which most closely matches typical system load.
Set to initial configured value for Design Capacity. The gauge will update this
parameter automatically after the optimization cycle and for every regular Qmax
update thereafter.
Qmax Cell 0
1000
4350
mAh
mV
Set to nominal cell voltage for a fully charged cell. The gauge will update this
parameter automatically each time full charge termination is detected.
V at Chg Term
Set to empty point reference of battery based on system needs. Typical is
between 3000 and 3200 mV.
Terminate Voltage
Ra Max Delta
3000
43
mV
mΩ
Set to 15% of Cell0 R_a 4 resistance after an optimization cycle is completed.
Set based on nominal charge voltage for the battery in normal conditions (25°C,
for example). Used as the reference point for offsetting by Taper Voltage for full
charge termination detection.
Charging Voltage
Taper Current
4350
100
100
60
mV
mA
mV
mA
mA
mA
mA
Set to the nominal taper current of the charger + taper current tolerance to ensure
that the gauge will reliably detect charge termination.
Sets the voltage window for qualifying full charge termination. Can be set tighter
to avoid or wider to ensure possibility of reporting 100% SOC in outer JEITA
temperature ranges that use derated charging voltage.
Taper Voltage
Sets threshold for gauge detecting battery discharge. Should be set lower than
minimal system load expected in the application and higher than Quit Current.
Dsg Current Threshold
Chg Current Threshold
Quit Current
Sets the threshold for detecting battery charge. Can be set higher or lower
depending on typical trickle charge current used. Also should be set higher than
Quit Current.
75
Sets threshold for gauge detecting battery relaxation. Can be set higher or lower
depending on typical standby current and exhibited in the end system.
40
Current profile used in capacity simulations at onset of discharge or at all times if
Load Select = 0. Should be set to nominal system load. Is automatically updated
by the gauge every cycle.
Avg I Last Run
–299
Power profile used in capacity simulations at onset of discharge or at all times if
Load Select = 0. Should be set to nominal system power. Is automatically
updated by the gauge every cycle.
Avg P Last Run
Sleep Current
–1131
15
mW
mA
Sets the threshold at which the fuel gauge enters SLEEP Mode. Take care in
setting above typical standby currents else entry to SLEEP may be
unintentionally blocked.
If auto-shutdown of fuel gauge is required prior to protect against accidental
discharge to undervoltage condition, set this to desired voltage threshold for
completely powering down the fuel gauge. Recovery occurs when a charger is
connected.
Shutdown V
0
mV
Sets the boundary between charging inhibit/suspend and charging with T1-T2
parameters. Defaults set based on recommended values from JEITA standard.
T1 Temp
T2 Temp
T3 Temp
0
°C
°C
°C
Sets the boundary between charging with T1-T2 or T2-T3 parameters. Defaults
set based on recommended values from JEITA standard.
10
45
Sets the boundary between charging with T2-T3 or T3-T4 parameters. Defaults
set based on recommended values from JEITA standard.
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Typical Applications (continued)
Table 11. Key Data Flash Parameters for Configuration (continued)
NAME
DEFAULT
UNIT
RECOMMENDED SETTING
Sets the boundary between charging with T4-T5 or T4-T5 parameters. Also
serves as charge inhibit boundary if initiating new charging event. Defaults set
based on recommended values from JEITA standard.
T4 Temp
50
°C
Sets the boundary between charging suspend and charging with T4-T5
parameters. Refer to JEITA standard for compliance.
T5 Temp
60
1
°C
°C
mV
mV
mV
mV
%
Adds temperature hysteresis for boundary crossings to avoid oscillation if
temperature is changing by a degree or so on a given boundary.
Temp Hys
Sets reported charge voltage when inside of T1 Temp and T2 Temp range.
Defaults set based on recommended values from JEITA standard.
T1-T2 Chg Voltage
T2-T3 Chg Voltage
T3-T4 Chg Voltage
T4-T5 Chg Voltage
T1-T2 Chg Current
T2-T3 Chg Current
T3-T4 Chg Current
4350
4350
4300
4250
50
Sets reported charge voltage when inside of T2 Temp an d T3 Temp range.
Defaults set based on recommended values from JEITA standard.
Sets reported charge voltage when inside of T3 Temp and T4 Temp range.
Defaults set based on recommended values from JEITA standard.
Sets reported charge voltage when inside of T4 Temp and T5 Temp range.
Defaults set based on recommended values from JEITA standard.
Sets reported charge current when inside of T1 Temp and T2 Temp range.
Defaults set based on recommended values from JEITA standard.
Sets reported charge current when inside of T2 Temp and T3 Temp range.
Defaults set based on recommended values from JEITA standard.
80
%
Sets reported charge current when inside of T3 Temp and T4 Temp range.
Defaults set based on recommended values from JEITA standard.
80
%
Sets reported charge current when inside of T4 Temp and T5 Temp range.
Defaults set based on recommended values from JEITA standard.
T4-T5 Chg Current
OV Prot Threshold
OV Prot Delay
80
4390
1
%
mV
s
Set to maximum allowable cell voltage due to overcharge in normal operation.
Set to required OVP duration prior to fault detection and FET disable. Setting of 0
disables firmware-based OVP feature. Default of 1s is recommended.
Set to desired OVP recovery threshold. 100 to 200 mV below OVP trip threshold
is common.
OV Prot Recovery
OV Prot Threshold
OV Prot Delay
4290
2800
1
mV
mV
s
Set to minimum allowable cell voltage due to overdischarge in normal operation.
Set to required UVP duration prior to fault detection and FET disable. Setting of 0
disables firmware-based UVP feature. Default of 1s is recommended.
Set to desired UVP recovery threshold. 100 to 200 mV above UVP trip threshold
is common.
OV Prot Recovery
2900
mV
Varies based on FET selection. Use the max DC current for the forward-biased
body diode from the FET datasheet and derate based on the operating
temperature range to arrive at the minimum current value (and add some margin)
that the fuel gauge should use to re-enable FET when disabled during a fault
condition.
Body Diode Current
Threshold
60
mA
Set to desired temperature at which charging is prohibited to prevent cell damage
due to excessive ambient temperature.
OT Chg
55.0
5
°C
s
Set to desired time before CHG FET is disabled based on overtemperature.
Since temperature changes much more slowly than other fault conditions, the
default setting is sufficient for most application.
OT Chg Time
OT Chg Recovery
OT Dsg
50.0
60.0
°C
°C
Set to the temperature threshold at which charging is no longer prohibited.
Set to desired temperature at which discharging is prohibited to prevent cell
damage due to excessive ambient temperature.
Set to desired time before DSG FET is disabled based on overtemperature. Since
temperature changes much more slowly than other fault conditions, the default
setting is sufficient for most application.
OT Dsg Time
5
s
OT Dsg Recovery
55.0
°C
Set to the temperature threshold at which cell discharging is no longer prohibited.
Set based on required trip thresholds for overcurrent in charge, overcurrent in
discharge, and short-circuit in discharge. When setting this parameter, be sure to
account for charger tolerance and maximum load spikes expected in the end
system to avoid accidental trip of these fault conditions
Prot OC Config
0A
hex
30
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ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
Typical Applications (continued)
Table 11. Key Data Flash Parameters for Configuration (continued)
NAME
DEFAULT
UNIT
RECOMMENDED SETTING
Set to maximum tolerable cell voltage before cell is permanently damaged.
Serves as a second level OVP protection mechanism.
Prot OV Config
07
hex
Set to sum of Prot OC Config and Prot OV Config. Improper setting will cause
FETs to open and warning flag assertion in SafetyStatus(), until corrected.
Prot Checksum
CC Gain
11
5
hex
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines conversion of coulomb counter measured
sense resistor voltage to current.
mΩ
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines conversion of coulomb counter measured
sense resistor voltage to passed charge.
CC Delta
CC Offset
5.074
6.874
0.66
mΩ
mA
uA
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines native offset of coulomb counter hardware
that should be removed from conversions.
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines native offset of the printed circuit board
parasitics that should be removed from conversions.
Board Offset
Calibrate this parameter using TI-supplied BMS software and calibration
procedure in the TRM. Determines voltage offset between cell tab and ADC input
node to incorporate back into or remove from measurement, depending on
polarity.
Pack V Offset
0
mV
8.2.3 Detailed Design Procedure
8.2.3.1 BAT Voltage Sense Input
A ceramic capacitor at the input to the BAT pin is used to bypass AC voltage ripple to ground, greatly reducing
its influence on battery voltage measurements. It proves most effective in applications with load profiles that
exhibit high frequency current pulses (that is, cell phones) but is recommended for use in all applications to
reduce noise on this sensitive high impedance measurement node.
The series resistor between the battery and the BAT input is used to limit current that could be conducted
through the chip-scale package's solder bumps in the event of an accidental short during the board assembly
process. The resistor is not likely to survive a sustained short condition (depends on power rating), however, it
sacrifices the much cheaper resistor component over suffering damage to the fuel gauge die itself.
8.2.3.2 SRP and SRN Current Sense Inputs
The filter network at the input to the coulomb counter is intended to improve differential mode rejection of voltage
measured across the sense resistor. These components should be placed as close as possible to the coulomb
counter inputs and the routing of the differential traces length-matched in order to best minimize impedance
mismatch-induced measurement errors. The single-ended ceramic capacitors should be tied to the battery
voltage node (preferably to a large copper pour connected to the SRN side of the sense resistor) in order to
further improve common-mode noise rejection. The series resistors between the CC inputs and the sense
resistor should be at least 200 Ω in order to mitigate SCR-induced latch-up due to possible ESD events.
8.2.3.3 Sense Resistor Selection
Any variation encountered in the resistance present between the SRP and SRN pins of the fuel gauge will affect
the resulting differential voltage, and derived current, it senses. As such, it is recommended to select a sense
resistor with minimal tolerance and temperature coefficient of resistance (TCR) characteristics. The standard
recommendation based on best compromise between performance and price is a 1% tolerance, 50-ppm drift
sense resistor with a 1-W power rating.
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8.2.3.4 TS Temperature Sense Input
Similar to the BAT pin, a ceramic decoupling capacitor for the TS pin is used to bypass AC voltage ripple away
from the high-impedance ADC input, minimizing measurement error. Another helpful advantage is that the
capacitor provides additional ESD protection since most thermistors are handled and manually soldered to the
PCB as a separate step in the factory production flow. As before, it should be placed as close as possible to the
respective input pin for optimal filtering performance.
8.2.3.5 Thermistor Selection
The fuel gauge temperature sensing circuitry is designed to work with a negative temperature coefficient-type
(NTC) thermistor with a characteristic 10-kΩ resistance at room temperature (25°C). The default curve-fitting
coefficients configured in the fuel gauge specifically assume a 103AT-2 type thermistor profile and so that is the
default recommendation for thermistor selection purposes. Moving to a separate thermistor resistance profile (for
example, JT-2 or others) requires an update to the default thermistor coefficients in data flash to ensure highest
accuracy temperature measurement performance.
8.2.3.6 VPWR Power Supply Input Filtering
A ceramic capacitor is placed at the input to the fuel gauge's internal LDO in order to increase power supply
rejection (PSR) and improve effective line regulation. It ensures that voltage ripple is rejected to ground instead
of coupling into the device's internal supply rails.
8.2.3.7 REG25 LDO Output Filtering
A ceramic capacitor is also needed at the output of the internal LDO in order to provide a current reservoir for
fuel gauge load peaks during high peripheral utilization. It acts to stabilize the regulator output and reduce core
voltage ripple inside of the device.
8.2.3.8 Communication Interface Lines
A protection network composed of resistors and zener diodes is recommended on each of the serial
communication inputs to protect the fuel gauge from dangerous ESD transients. The Zener should be selected to
break down at a voltage larger than the typical pullup voltage for these lines but less than the internal diode
clamp breakdown voltage of the device inputs (~6 V). A zener voltage of 5.6 V is typically recommended. The
series resistors are used to limit the current into the Zener diode and prevent component destruction due to
thermal strain once it goes into breakdown. 100 Ω is typically recommended for these resistance values.
For HDQ-based designs, a pullup resistor is normally designed in on the battery pack PCB and can be
connected to the RC2 input since a 1.8-V pullup voltage is readily available and provided by the fuel gauge.
8.2.3.9 PACKP Voltage Sense Input
Inclusion of a 2-kΩ series resistor on the PACKP input allows it to tolerate a charger overvoltage event up to 28
V without device damage. The resistor also protects the device in the event of a reverse polarity charger input,
since the substrate diode will be forward biased and attempt to conduct charger current through the fuel gauge
(as well as the high FETs). An external reverse charger input FET clamp can be added to short the DSG FET
gate to its source terminal, forcing the conduction channel off when negative voltage is present at PACK+ input
to the battery pack and preventing large battery discharge currents. A ceramic capacitor connected at the
PACKP pin helps to filter voltage into the comparator sense lines used for checking charger and load presence.
In addition, in the Low Voltage Charging State, the minimal circuit elements that are operational are powered
from this input pin and require a stable supply.
8.2.3.10 CHG and DSG Charge Pump Voltage Outputs
The series resistors used at the DSG and CHG output pins serve to protect them from damaging ESD events or
breakdown conditions, allowing the resistors to be sacrificed in place of the fuel gauge itself. An added bonus is
that they also help to limit in-rush currents due to use of FETs with large gate capacitance, allowing smooth ramp
of power-path connection turn-on to the system.
32
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8.2.3.11 NFET Selection
The choice in NFETs for a single-cell battery pack design will depend on a variety of factors including package
type, size, and device cost as well as performance metrics such as drain-to-source resistance (rDS(on)), gate
capacitance, maximum current and power handling, and similar. At a bare minimum, it is recommended that the
selected FETs have a drain-to-source voltage (VDS) and gate-to-source (VGS) voltage tolerance of 12 V. Some
FETs can are designed to handle as much as 24 V between the drain and source terminals and this would
provide an increased safety margin for the pack design. Further, the DC current rating should be high enough to
safely handle sustained current in charge or discharge direction just below the maximum threshold tolerances of
the configured OCC and OCD protections and the lowest possible sense resistance value based on tolerance
and TCR considerations, or vice-versa. This ensures that there is sufficient power dissipation margin given a
worst case scenario for the fault detections. In addition, striving for minimal FET resistance at the expected gate
bias as well as lowest gate capacitance will help reduce conduction losses and increase power efficiency as well
as achieve faster turn-on and turn-off times for the FETs. Many of these FETs are now offered as dual, back-
back NFETs in wafer-chip scale (WCSP) packaging, decreasing both BOM count and shrinking necessary board
real estate to accommodate the components. Last, one should always refer to the safe operating area (SOA)
curves of the target FETs to ensure that the boundaries are never violated based on all possible load conditions
in the end application. The CSD83325L is an excellent example of a FET solution that meets all of the
aforementioned criteria, offering rDS(on) of 10.3 mΩ and VDS of 12 V with back-to-back NFETs in a chip-scale
package, a perfect fit for battery pack designs.
8.2.3.12 Additional ESD Protection Components
The additional capacitors placed across the CHG and DSF FET source pins as well as between PACK+ and
ground help to bolster and greatly improve the ESD robustness of the pack design. The former components
shunt damaging transients around the FETs and the latter components attempt to bypass such pulses to PACK–
before they couple further into the battery pack PCB. Two series capacitors are used for each of these protection
areas to prevent a battery short in the event of a single capacitor failure.
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8.2.4 Application Curves
2V / div
2V / div
2V / div
2V / div
5V / div
5V / div
5V / div
5V / div
500ms / div
50ms / div
Figure 21. Overvoltage Protection Set and Clear
Figure 22. Undervoltage Protection Set and Clear
2V / div
2V / div
2V / div
2V / div
5V / div
5V / div
5V / div
5V / div
20ms / div
20ms / div
Figure 23. Overcurrent in Charge Protection Set and Clear
Figure 24. Overcurrent in Discharge Protection Set and
Clear
34
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ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
2V / div
2V / div
5V / div
5V / div
100µs / div
Figure 25. Short-Circuit in Discharge Protection Set and Clear
9 Power Supply Recommendation
9.1 Power Supply Decoupling
Both the VPWR input pin and the REG25 output pin require low equivalent series resistance (ESR) ceramic
capacitors placed as closely as possible to the respective pins to optimize ripple rejection and provide a stable
and dependable power rail that is resilient to line transients. A 0.1-µF capacitor at the VPWR and a 1-µF
capacitor at REG25 will suffice for satisfactory device performance.
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10 Layout
10.1 Layout Guidelines
10.1.1 Li-Ion Cell Connections
For highest voltage measurement accuracy, it is critical to connect the BAT pin directly to the battery terminal
PCB pad. This avoids measurement errors caused by IR drops when high charge or discharge currents are
flowing. Connecting right at the positive battery terminal with a Kelvin connection ensures the elimination of
parasitic resistance between the point of measurement and the actual battery terminal. Likewise the low current
ground return for the fuel gauge and all related passive components should be star-connected right at the
negative battery terminal. This technique minimizes measurement error due to current-induced ground offsets
and also improves noise performance through prevention of ground bounce that could occur with high current
and low current returns intersecting ahead of the battery ground. The bypass capacitor for this sense line needs
to be placed as close as possible to the BAT input pin.
10.1.2 Sense Resistor Connections
Kelvin connections at the sense resistor are just as critical as those for the battery terminals themselves. The
differential traces should be connected at the inside of the sense resistor pads and not anywhere along the high
current trace path in order to prevent false increases to measured current that could result when measuring
between the sum of the sense resistor and trace resistance between the tap points. In addition, the routing of
these leads from the sense resistor to the input filter network and finally into the SRP and SRN pins needs to be
as closely matched in length as possible else additional measurement offset could occur. It is further
recommended to add copper trace or pour-based "guard rings" around the perimeter of the filter network and
coulomb counter inputs to shield these sensitive pins from radiated EMI into the sense nodes. This prevents
differential voltage shifts that could be interpreted as real current change to the fuel gauge. All of the filter
components need to be placed as close as possible to the coulomb counter input pins.
10.1.3 Thermistor Connections
The thermistor sense input should include a ceramic bypass capacitor placed as close to the TS input pin as
possible. The capacitor helps to filter measurements of any stray transients as the voltage bias circuit pulses
periodically during temperature sensing windows.
10.1.4 FET Connections
The battery current transmission path through the FETs should be routed with large copper pours to provide the
lowest resistance path possible to the system. Depending on package type, thermal vias can be placed in the
package land pattern's thermal pad to reduce thermal impedance and improve heat dissipation from the package
to the board, protecting the FETs during high system loading conditions. In addition, it is preferable to locate the
FETs and other heat generating components away from the low power pack electronics to reduce the chance of
temperature drift and associated impacts to data converter measurements. In the event of FET overheating,
keeping reasonable distance between the most critical components, such as the fuel gauge, and the FETs helps
to decrease the risk of thermal breakdown to the more fragile components.
10.1.5 ESD Component Connections
The ESD components included in the reference design that connect across the back-to-back FETs as well as
from PACK+ to ground require trace connections that are as wide and short as possible in order to minimize loop
inductance in their return path. This ensures impedance is lowest at the AC loop through the series capacitors
and makes this route most attractive for ESD transients such that they are conducted away from the vulnerable
low voltage, low power fuel gauge and passive components. The series resistors and Zener diodes connected to
the serial communications lines should be placed as close as possible to the battery pack connector to keep
large ESD currents confined to an area distant from the fuel gauge electronics. Further, all ESD components
referred to ground should be single-point connected to the PACK– terminal if possible. This reduces the
possibility of ESD coupling into other sensitive nodes well ahead of the PACK– ground return.
36
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ZHCSD75D –MARCH 2014–REVISED JANUARY 2018
Layout Guidelines (continued)
10.1.6 High Current and Low Current Path Separation
For best possible noise performance, it is extremely important to separate the low current and high current loops
to different areas of the board layout. The fuel gauge and all support components should be situated on one side
of the boards and tap off of the high current loop (for measurement purposes) at the sense resistor. Routing the
low current ground around instead of under high current traces will further help to improve noise rejection. Last,
the high current path should be confined to a small loop from the battery, through the FETs, into the PACK
connector, and back.
10.2 Layout Example
Use short and wide
traces to minimize
inductance
CESD1 CESD2
Use copper pours for
battery power path to
minimize IR losses
RSENSE
PACK+
S1
S2
G1
G2
S1
S2
RSRP
RSRN
SRP
CHG
DSG
CSRP
Keep differential
traces length
matched
CDIFF
RDSG
CESD3
CSRN
RCHG
Use short and wide
traces to minimize
inductance
PACK
P
SRN
NC
RPACKP
CESD4
RVPWR
VPWR
BAT
HDQ
TS
SDA
RC2
SCL
RBAT
CVPWR
CPACKP
VSS
CBAT
Kelvin connect BAT
sense line right at
positive battery
terminal
REG25
Star ground right at
negative battery
terminal for low current
return path
CREG25
RESD1
RESD3
RESD2
RESD4
RTHERM
SDA
SCL
Use short and wide
traces to minimize
inductance
CTHERM
Star ground right at PACK-
for ESD return path
PACK-
Via connects to Power Ground
Via connects between two layers
Figure 26. bq27742-G1 Board Layout
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
1. 《bq27742-G1 技术参考手册》(SLUUAX0)
2. 用户指南《bq27742EVM 单节电池 Impedance Track™ 技术评估模块》（文献编号：SLUUAH1）
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的“通知我”进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
Impedance Track, NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
38
版权 © 2014–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ27742YZFR-G1
BQ27742YZFT-G1
ACTIVE
ACTIVE
DSBGA
DSBGA
YZF
YZF
15
15
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ27742
BQ27742
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ27742YZFR-G1
BQ27742YZFT-G1
DSBGA
DSBGA
YZF
YZF
15
15
3000
250
180.0
180.0
8.4
8.4
2.06
2.06
2.88
2.88
0.69
0.69
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jan-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ27742YZFR-G1
BQ27742YZFT-G1
DSBGA
DSBGA
YZF
YZF
15
15
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZF0015
DSBGA - 0.625 mm max height
SCALE 6.500
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
0.35
0.15
BALL TYP
1 TYP
SYMM
E
D
SYMM
2
TYP
C
B
D: Max = 2.806 mm, Min =2.746 mm
E: Max = 1.986 mm, Min =1.926 mm
0.5
TYP
A
1
2
3
0.35
0.25
C A B
15X
0.5 TYP
0.015
4219381/A 02/2017
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. NanoFreeTM package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
15X ( 0.245)
(0.5) TYP
1
3
2
A
B
SYMM
C
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MAX
0.05 MIN
(
0.245)
METAL
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
(
0.245)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219381/A 02/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
15X ( 0.25)
1
2
3
A
B
(0.5)
TYP
METAL
TYP
SYMM
C
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219381/A 02/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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