BQ500101 [TI]

NexFET 功率级;


型号：	BQ500101
厂家：	TEXAS INSTRUMENTS
描述：	NexFET 功率级
文件：	总21页 (文件大小：595K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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bq500101

ZHCSEQ6 –MARCH 2016

bq500101 NexFET™功率级

1 特性

2 应用

•

5A 电流时系统效率达 98%

•

用于 15W 或 5W 系统的无线电源发射器，符合

WPC (Qi) 1.2 规范

最大额定持续电流 10A，峰值 15A

高频工作（高达 600kHz）

•

专用无线充电器和发射器

以无线方式供电的工业和医疗系统

更多相关信息，请访问 www.ti.com/wirelesspower

高密度小外形尺寸无引线 (SON) 3.5mm x 4.5mm

封装

•

超低电感封装

3 说明

系统已优化的印刷电路板 (PCB) 封装

3.3V 和 5V 脉宽调制 (PWM) 信号兼容

输入电压高达 24V

bq500101 NexFET™功率级针对涵盖 WPC v1.2 中等

功率规范的无线电源应用进行了优化。该器件既可用

于固定频率发射器类型中的电源轨电压控制，也可用于

固定频率和频率可变两种发射器类型中的线圈驱动器。

这个组合在小型 3.5mm x 4.5mm 外形尺寸封装中实现

具有高电流、高效率和高速开关功能的器件。此外，印

刷电路板 (PCB) 封装已经过优化，可帮助减少设计时

间并简化总体系统设计的完成。

集成型自举二极管

击穿保护

符合 RoHS 绿色环保标准-无铅引脚镀层

无卤素

包含高效栅极驱动器和场效应管 (FET) 的优化型功

率级

•

针对 15W 无线电源发射器设计进行了优化

器件信息⁽¹⁾

封装

订货编号

封装尺寸（标称值）

bq500101

DPC (9)

3.5mm x 4.5mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

空白

应用图表

典型功率级效率与功率损耗

100

3.2

2.8

2.4

bq500100

bq500101

19 V

(Current Sense

(Voltage Regulation)

Monitor)

V_DD= 5 V

V_IN= 10 V

L_SW= 6 mH

f_SW= 130 kHz

1.6

1.2

0.8

0.4

T_A= 25èC

Duty Cycle = 50%

bq501210

(Wireless Power

Transmitter Controller)

bq500101

Efficiency (%)

Power Loss (W)

V_SWCurrent (A)

D001

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLPS585

bq500101

ZHCSEQ6 –MARCH 2016

www.ti.com.cn

特性.......................................................................... 1

Application and Implementation .......................... 8

8.1 Application Information.............................................. 8

8.2 Typical Application ................................................... 8

8.3 System Example ..................................................... 11

Layout ................................................................... 13

9.1 Layout Guidelines ................................................... 13

9.2 Layout Example ...................................................... 13

9.3 Thermal Considerations.......................................... 14

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

Detailed Description .............................................. 6

7.1 Overview ................................................................... 6

7.2 Functional Block Diagram ......................................... 6

7.3 Feature Description................................................... 7

10 器件和文档支持 ..................................................... 15

10.1 商标....................................................................... 15

10.2 静电放电警告......................................................... 15

10.3 Glossary................................................................ 15

11 机械、封装和可订购信息....................................... 16

11.1 机械制图................................................................ 16

11.2 建议印刷电路板 (PCB) 焊盘图案........................... 17

11.3 建议模板开口......................................................... 17

4 修订历史记录

日期

修订版本

注释

2016 年 3 月

首次发布。

bq500101

www.ti.com.cn

ZHCSEQ6 –MARCH 2016

5 Pin Configuration and Functions

SON 3.5 × 4.5 mm

(Top View)

Pin Functions

DESCRIPTION

NO.

NAME

V_DD

Supply voltage to gate drivers and internal circuitry.

V_DD

P_GND

V_SW

Power ground, needs to be connected to Pin 9 and PCB

Voltage switching node – pin connection to the inductor.

Input voltage pin. Connect input capacitors close to this pin.

V_IN

BOOT_R

Bootstrap capacitor C_BOOTconnections. Connect a minimum 0.1 µF 16 V X5R, ceramic cap C_BOOTfrom BOOT to

BOOT_R pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is

BOOT

integrated. Boot_R is internally connected to V_SW

Pulse Width modulated tri-state input from external controller. Logic Low sets Control FET gate low and Sync FET

gate high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates

PWM

P_GND

low if greater than the tri-state shutdown hold-off time (t_3HT

)

Power ground

bq500101

ZHCSEQ6 –MARCH 2016

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

T_A= 25°C (unless otherwise noted)

MIN

–0.3

–7

MAX

UNIT

V_INto P_GND

V_SWto P_GND, V_INto V_SW

V_SWto P_GND, V_INto V_SW(<10 ns)

V_DDto P_GND

–0.3

–2

PWM

BOOT to P_GND

BOOT to P_GND(<10 ns)

BOOT to BOOT_R

BOOT to BOOT_R (duty cycle <0.2%)

–0.3

P_D

T_J

Power dissipation

°C

Operating temperature

Storage temperature

–40

–55

150

T_stg

(1) Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM)⁽¹⁾

Charged device model (CDM)⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

T_A= 25° (unless otherwise noted)

MIN

MAX UNIT

V_DD

V_IN

Gate drive voltage

4.5

5.5

Input supply voltage⁽¹⁾

Continuous V_SWcurrent

Peak V_SWcurrent⁽³⁾

Switching frequency

On time duty cycle

I_SW

V_IN= 10 V, V_DD= 5 V, Duty cycle = 50%,

ƒ_SW= 130 kHz, L_SW= 6 µH⁽²⁾

I_SW-PK

ƒ_SW

C_BOOT= 0.1 µF (min)

600

85%

kHz

Minimum PWM on time

Operating temperature

°C

–40

125

(1) Operating at high V_INcan create excessive AC voltage overshoots on the switch node (V_SW) during MOSFET switching transients. For

reliable operation, the switch node (V_SW) to ground voltage must remain at or below the Absolute Maximum Ratings.

(2) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_INto P_GNDpins.

(3) System conditions as defined in Note 2. Peak V_SWCurrent is applied for t_p= 10 ms, duty cycle ≤ 1%

6.4 Thermal Information

T_A= 25°C (unless otherwise noted)

THERMAL METRIC

Junction-to-case (top of package) thermal resistance⁽¹⁾

Junction-to-board thermal resistance⁽²⁾

MIN

TYP

MAX UNIT

R_θJC

R_θJB

22.8

°C/W

2.5

(1)

(2)

_θJCis determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inch x 1.5 inch, 0.06 inch

(1.52 mm) thick FR4 board.

_θJBvalue based on hottest board temperature within 1mm of the package.

bq500101

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ZHCSEQ6 –MARCH 2016

6.5 Electrical Characteristics

T_A= 25°C, V_DD= POR to 5.5 V (unless otherwise noted)

PARAMETER

P_LOSS

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN= 10 V, V_DD= 5 V, I_SW= 5 A, ƒ_SW= 130 kHz,

L_SW= 6 µH , T_J= 25°C, Duty Cycle = 50%

Power

loss⁽¹⁾

0.53

0.68

V_IN= 10 V, V_DD= 5 V, I_SW= 5 A, ƒ_SW= 130 kHz,

L_SW= 6 µH , T_J= 125°C, Duty Cycle = 50%

Power

loss⁽¹⁾

V_IN

I_Q

V_INquiescent current

PWM = Floating, V_DD= 5 V, V_IN= 24 V

µA

V_DD

I_DD

Standby supply current

Operating supply current

PWM = Float

130

µA

PWM = 50% Duty cycle, ƒ_SW= 130 kHz

POWER-ON RESET AND UNDERVOLTAGE LOCKOUT

V_DDRising Power-on reset

V_DDFalling UVLO

Hysteresis

PWM I/O SPECIFICATIONS

4.15

3.7

0.2

Pull up to V_DD

1700

800

R_I

Input impedance

kΩ

Pull down (to GND)

V_IH

V_IL

Logic level high

Logic level low

Hysteresis

2.65

1.3

0.6

V_IH

V_TS

0.2

Tri-state voltage

Tri-state activation time

(falling) PWM

t_THOLD(off1)

Tri-state activation time (rising)

PWM

t_THOLD(off2)

t_3RD(PWM)

(1)

Tri-state exit time PWM

100

BOOTSTRAP SWITCH

V_FBSTForward voltage

I_RLEAK

Reverse leakage⁽¹⁾

I_F= 10 mA

120

240

µA

V_BOOT– V_DD= 25 V

(1) Specified by design

bq500101

ZHCSEQ6 –MARCH 2016

www.ti.com.cn

7 Detailed Description

7.1 Overview

The bq500101 NexFET™ Power Stage is a highly optimized design for use in wireless power transmitter

designs. The bq500101 can also be used for synchronous buck applications.

7.2 Functional Block Diagram

VDD

BOOT

VIN

DRVL

Control

FET

DRVH

Level Shift

V_UVLO

BOOT_R

VSW

1 V

VDD

1 / 2 VDD

1 V

1.7Meg

Sync

FET

3-State

Logic

DRVL

PWM

800k

PGND

bq500101

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ZHCSEQ6 –MARCH 2016

7.3 Feature Description

7.3.1 Powering bq500101 And Gate Drivers

An external V_DDvoltage is required to supply the integrated gate driver device and provide the necessary gate

drive power for the MOSFETS. A 1-µF 10-V X5R or higher ceramic capacitor is recommended to bypass V_DDpin

to P_GND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap

supply to drive the Control FET is generated by connecting a 100-nF 16-V X5R ceramic capacitor C_BOOT

between BOOT and BOOT_R pins. An optional R_BOOTresistor in series with C_BOOTcan be used to slow down the

turn on speed of the Control FET and reduce voltage spikes on the V_SWnode. A typical 1 Ω to 4.7 Ω value is a

compromise between switching loss and V_SWspike amplitude.

7.3.2 Undervoltage Lockout Protection (UVLO)

The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As V_VDDrises, both the Control

FET and Sync FET gates hold actively low at all times until V_VDDreaches the higher UVLO threshold (V_{UVLO_H}).,

Then the driver becomes operational and responds to PWM command. If VDD falls below the lower UVLO

threshold (V_{UVLO_L}= V_{UVLO_H}– Hysteresis), the device disables the driver and drives the outputs of the Control

FET and Sync FET gates actively low. Figure 1 shows this function.

UVLO_H

UVLO_L

VDD

Driver On

UDG-12218

Figure 1. UVLO Operation

7.3.3 Integrated Boost-Switch

To maintain a BOOT-V_SWvoltage close to VDD (to get lower conduction losses on the high-side FET), the

conventional diode between the VDD pin and the BOOT pin is replaced by a FET which is gated by the DRVL

signal.

bq500101

ZHCSEQ6 –MARCH 2016

www.ti.com.cn

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The Power Stage bq500101 is a highly optimized design for wireless power transmitter applications using

NexFET devices with a 5-V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield

the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards

a more systems centric environment. The high-performance gate driver device integrated in the package helps

minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level

performance curves such as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict

the product performance in the actual application.

8.2 Typical Application

V_SENSE

+19V

VIN

VSW

BOOT

VDD

BOOT_R

PGND

+5V

IN+

IN-

V+

PWM

PAD

GND

bq500101

OUT

bq500100

I_SENSE

+3.3V

V33

PWM_RAIL

RAIL+

C15

+5V

C10

C12

VIN

VSW

BOOT

VSW

VIN

RAIL-

VDD

BOOT

VDD

DPWM-A

DPWM-B

V_SENSE

DPWM-A

DPWM-B

V_SENSE

I_SENSE

+5V

C14

BOOT_R

PGND

BOOT_R

PGND

PAD

I_SENSE

C11

C13

C16

AGND / DGND

bq501210

PWM

PAD

PWM

bq500101

DPWM-A

DPWM-B

Figure 2. Application Schematic

bq500101

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ZHCSEQ6 –MARCH 2016

Typical Application (continued)

8.2.1 Application Curves

T_J= 125°C, unless stated otherwise

2.5

1.1

0.9

0.8

0.7

0.6

0.5

1.5

0.5

Typ

Max

2.5

5.5

8.5

-50

-25

100

125

150

Output Current (A)

T_C- Junction Temperature (èC)

D002

D003

V_IN= 10 V

V_DD= 5 V

V_IN= 10 V

V_DD= 5 V

ƒ_SW= 130 kHz

L_SW= 6 µH

Duty Cycle = 50%

ƒ_SW= 130 kHz

L_SW= 6 µH

Duty Cycle = 50%

Figure 3. Power Loss vs Output Current

Figure 4. Power Loss vs Temperature

400 LFM

200 LFM

100 LFM

Nat. conv.

Min

Typ

100

120

140

Ambient Temperature (èC)

Board Temperature (èC)

D006

D004

V_IN= 10 V

V_DD= 5 V

V_IN= 10 V

V_DD= 5 V

ƒ_SW= 130 kHz

L_SW= 6 µH

Duty Cycle = 50%

ƒ_SW= 130 kHz

L_SW= 6 µH

Duty Cycle = 50%

(1)

Figure 6. Typical Safe Operating Area

Figure 5. Safe Operating Area – PCB Horizontal Mount

1.15

1.12

1.09

1.06

1.03

1.2

0.9

0.7

0.5

0.2

0.0

-0.2

1.15

1.1

1.2

0.8

1.05

0.4

0.0

0.95

0.9

-0.4

-0.8

-1.2

0.97

0.85

130

220

310

400

490

580

670

Switching Frequency (kHz)

Input Voltage (V)

D007

D008

V_IN= 10 V

I_SW= 5 A

V_DD= 5 V

I_SW= 5 A

ƒ_SW= 130 kHz

V_DD= 5 V

L_SW= 6 µH

Duty Cycle = 50%

L_SW= 6 µH

Duty Cycle = 50%

Figure 7. Normalized Power Loss vs Frequency

Figure 8. Normalized Power Loss vs Input Voltage

(1) LFM: Linear Feet per Minute (Air Flow Velocity)

bq500101

ZHCSEQ6 –MARCH 2016

www.ti.com.cn

Typical Application (continued)

T_J= 125°C, unless stated otherwise

1.15

1.2

0.8

0.4

0.0

-0.4

1.1

1.05

0.95

Output Inductance (mH)

D010

V_IN= 10 V

V_DD= 5 V

I_SW= 5 A

ƒ_SW= 130 kHz

Duty Cycle = 50%

Figure 9. Normalized Power Loss vs Output Inductance

1. The Typical bq500101 System Characteristic curves are based on measurements made on a PCB design

with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1-oz. copper

thickness. See the System Example section for detailed explanation.

bq500101

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ZHCSEQ6 –MARCH 2016

T_J= 125°C, unless stated otherwise

8.3 System Example

8.3.1 Power Loss Curves

MOSFET centric parameters such as ON-resistance and gate charges are primarily needed by engineers to

estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas

Instruments has provided measured power loss performance curves. Figure 3 plots the power loss of the

bq500101 as a function of load current. This curve is measured by configuring and running the bq500101 as the

circuit shown in Figure 10. The measured power loss is the bq500101 device power loss which consists of both

input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Power Loss = (V_INx I_IN) + (V_DDx I_DD) – (V_{SW_AVG}x I_OUT

)

(1)

The power loss curve in Figure 3 is measured at the maximum recommended junction temperature of

T_J= 125°C under isothermal test conditions.

bq500101

Input Current (I_IN

)

.ooꢁ

Gate Drive

Current (I_DD

Vin

)

V_DD

V_IN

V_DD

.{Ç

Cin

Input Voltage

C_Boot

/onꢁrol

C9Ç

(V_IN

)

I{gꢀꢁe

Gate Drive

Voltage (V_DD

5wëI

[[

)

.ooꢁ_w

L_O

V_O

Vsw

V_SW

{ync

C9Ç

tía

Output Current

[{gꢀꢁe

tía

(I_OUT

)

5wë[

Db5

P_GND

!verꢀging

/ircuiꢁ

Averaged Switched

Node Voltage

(V_{SW_AVG}

)

Figure 10. Power Loss Test Circuit

8.3.2 Safe Operating Area (SOA) Curves

The SOA curves in the bq500101 datasheet give engineers guidance on the temperature boundaries within an

operating system by incorporating the thermal resistance and system power loss. Figure 5 and Figure 6 outline

the temperature and airflow conditions required for a given load current. The area under the curve dictates the

safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4.0"

(W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1-oz. copper thickness.

8.3.3 Normalized Curves

The normalized curves in the bq500101 data sheet give engineers guidance on the Power Loss and SOA

adjustments based on their application specific needs. These curves show how the power loss and SOA

boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in

power loss and the secondary Y-axis is the change is system temperature required in order to comply with the

SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is

subtracted from the SOA curve.

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ZHCSEQ6 –MARCH 2016

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System Example (continued)

8.3.3.1 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example below).

Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the

following procedure will outline the steps engineers should take to predict product performance for any set of

system conditions.

8.3.3.1.1 Design Example

Operating Conditions: Output Current (l_SW) = 9 A, Input Voltage (V_IN) = 8 V, Switching Frequency (ƒ_SW) = 300

kHz, Output Inductor (L_SW) = 5 µH, Duty Cycle = 50%.

8.3.3.1.2 Calculating Power Loss

•

Typical Power Loss at 9 A = 1.78 W (Figure 3)

Normalized Power Loss for switching frequency ≈ 1.03 (Figure 7)

Normalized Power Loss for input voltage ≈ 0.96 (Figure 8)

Normalized Power Loss for output inductor ≈ 1.075 (Figure 9)

Final calculated Power Loss = 1.78 W × 1.03 × 0.96 × 1.075 ≈ 1.89 W

8.3.3.1.3 Calculating SOA Adjustments

•

SOA adjustment for switching frequency ≈ 0.20°C (Figure 7)

SOA adjustment for input voltage ≈ –0.30°C (Figure 8)

SOA adjustment for output inductor ≈ 0.60°C (Figure 9)

Final calculated SOA adjustment = 0.2 + (–0.3) + 0.6 ≈ 0.5°C

Figure 11. Power Stage bq500101 SOA, T_A= 25°C

In the design example above, the estimated power loss of the bq500101 would increase to 1.89 W. In addition,

the maximum allowable board and/or ambient temperature would have to decrease by 0.5°C. Figure 11

graphically shows how the SOA curve would be adjusted accordingly.

1. Start by drawing a horizontal line from the application current to the SOA curve.

2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.

3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient

temperature of 0.5°C. In the event the adjustment value is a negative number, subtracting the negative number

would yield an increase in allowable board/ambient temperature.

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ZHCSEQ6 –MARCH 2016

9 Layout

9.1 Layout Guidelines

9.1.1 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and

thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below

is a brief description on how to address each parameter.

9.1.2 Electrical Performance

The bq500101 has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be then taken

with the PCB layout design and placement of the input capacitors, inductor and switch capacitors (SW

capacitors).

•

The placement of the input capacitors relative to V_INand P_GNDpins of bq500101 device should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

the ceramic input capacitor C1 needs to be placed as close as possible to the V_INand P_GNDpins (see

Figure 12). Notice if there are input capacitors on both sides of the board, an appropriate amount of V_INand

GND vias need to be added to interconnect both layers..

•

The bootstrap cap C_BOOT0.1-µF 0603 16-V ceramic capacitor C4 in Figure 12 should be closely connected

between BOOT and BOOT_R pins.

The switching node of the inductor should be placed relatively close to the Power Stage bq500101 V_SWpins.

Minimizing the V_SWnode length between these two components will reduce the PCB conduction losses and

(1)

actually reduce the switching noise level.

9.2 Layout Example

GND

PWM

VDD

GND

BOOT

BOOT_R

VSW

bq500101

VIN

GND

Figure 12. Recommended PCB Layout (Top Down View)

(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

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ZHCSEQ6 –MARCH 2016

www.ti.com.cn

9.3 Thermal Considerations

The bq500101 has the ability to use the GND planes as the primary thermal path. As such, the use of thermal

vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids

and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of

solder attach that will wick down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

Use the smallest drill size allowed in your design. The example in Figure 12 uses vias with a 10 mil drill hole

and a 16 mil capture pad.

•

Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

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ZHCSEQ6 –MARCH 2016

10 器件和文档支持

10.1 商标

NexFET is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

10.2 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

10.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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ZHCSEQ6 –MARCH 2016

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11 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。

11.1 机械制图

ꢀ

0.300

(x45°)

毫米

英寸

标称值

DIM

最小值

0.800

0.000

0.150

2.000

0.150

3.850

4.400

3.400

2.000

标称值

0.900

0.000

0.200

2.200

0.200

3.950

4.500

3.500

2.100

最大值

1.000

0.080

0.250

2.400

0.250

4.050

4.600

3.600

2.200

最小值

0.031

0.000

0.006

0.079

0.006

0.152

0.173

0.134

0.079

最大值

0.039

0.003

0.010

0.095

0.010

0.160

0.181

0.142

0.087

0.035

0.000

0.008

0.087

0.008

0.156

0.177

0.138

0.083

0.400 典型值

0.300 典型值

0.400

0.016 典型值

0.012 典型值

0.016

0.300

0.180

0.00

0.500

0.280

—

0.012

0.007

0.00

0.020

0.011

—

0.230

0.009

—

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11.2 建议印刷电路板 (PCB) 焊盘图案

(0.006)

0.150

(0.016)

0.400

(0.010)

0.250

(x18)

(0.006)

0.150

(0.024)

0.600 (x 2)

(0.008)

0.200

(x2)

(0.087)

2.200

R0.100

0.225 ( x 2)

(0.009)

(0.088)

2.250

(0.012)

0.300

(0.159)

4.050

11.3 建议模板开口

(0.016)

0.400

(0.029)

0.738 (x 8)

(0.008)

0.200

(0.008)

0.200

(0.015)

0.390

(0.014)

0.350

0.300

R0.100

(0.012)

0.850 (x8)

(0.033)

(0.012)

0.300

R0.100

(0.004)

0.115

0.440 (0.017)

(0.008)

0.200

(0.009)

0.225

0.200

(0.008)

(0.087)

2.200

NOTE: 尺寸单位为 mm（英寸）。

模板厚度为 100µm。

重要声明

德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改，并有权根据

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TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使

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TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要

求，TI不承担任何责任。

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应用

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数字音频

www.ti.com.cn/audio

www.ti.com.cn/amplifiers

www.ti.com.cn/dataconverters

www.dlp.com

通信与电信

计算机及周边

消费电子

能源

放大器和线性器件

数据转换器

DLP® 产品

DSP - 数字信号处理器

时钟和计时器

接口

www.ti.com.cn/computer

www.ti.com/consumer-apps

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工业应用

医疗电子

安防应用

汽车电子

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www.ti.com.cn/medical

www.ti.com.cn/security

www.ti.com.cn/automotive

www.ti.com.cn/video

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www.ti.com.cn/microcontrollers

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www.ti.com/omap

微控制器 (MCU)

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2500

250

(1)

(2)

(3)

(4/5)

(6)

BQ500101DPCR

BQ500101DPCT

ACTIVE

VSON-CLIP

DPC

RoHS-Exempt

& Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

500101

ACTIVE

DPC

RoHS-Exempt

& Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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Addendum-Page 2

重要声明和免责声明

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BQ500101 [TI]

相关型号：

BQ500101DPCR

BQ500101DPCT

BQ500110

BQ500110RGZR

BQ500110RGZT

BQ500110_11

BQ500210

BQ500210RGZR

BQ500210RGZT

BQ500210_1108

BQ500211

BQ500211A