CDC930 [TI]
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER / DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS; 133 - MHz差分时钟合成器/驱动器，用于PC主板用3态输出
| 型号： | CDC930 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER / DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS |
| 文件： | 总17页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCAS641 – JULY 2000
DL PACKAGE
(TOP VIEW)
Generates Clocks for Pentium 4
Microprocessors
Uses a 14.318 MHz Crystal Input to
Generate Multiple Output Frequencies
GND
REF0/MultSel0
REF1/MultSel1
V
3.3V
DD
1
56
55
54
53
52
51
50
49
48
47
46
3VMREF
3VMREF
GND
2
Includes Spread Spectrum Clocking (SSC),
0.6% Downspread for Reduced EMI With
3
V
V
V
V
3.3V
XIN
4
DD
†
Theoretical EMI Damping of 7 dB
SPREAD
HCLK(1)
HCLK(1)
5
Power Management Control Terminals
XOUT
GND
PCI0
PCI1
3.3V
6
7
Low Output Skew and Jitter for Clock
Distribution
V
3.3V
8
DD
HCLK(2)
HCLK(2)
GND
9
Operates From Single 3.3-V Supply
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DD
Consumes Less Than 30-mA Power-Down
Current
PCI2
PCI3
GND
PCI4
PCI5
45 HCLK(3)
Generates the Following Clocks:
– 4 HCLK (Host) (Different Pairs–
100/133 MHz)
– 1 3VMREF Pair (3.3 V, 180 Shifted
50/66 MHz)
– 10 PCI (3.3 V, 33.3 MHz)
– 2 REF (3.3 V, 14.318 MHz)
– 4 3V66 MHz (3.3 V, 66 MHz)
– 2 3V48 MHz (3.3 V, 48 MHz)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
HCLK(3)
3.3V
V
DD
HCLK(4)
HCLK(4)
GND
3.3V
DD
PCI6
PCI7
GND
PCI8
PCI9
I_REF
V
3.3V
DD
GND
3.3V
V
DD
Packaged in 56-Pin SSOP Package
3.3V
3V66(0)
3V66(1)
GND
DD
SEL100/133
GND
description
3V48(0)/SelA
3V48(1)/SelB
GND
The CDC930 is a differential clock synthesizer/
driver that generates HCLK/HCLK, 3VMREF/
3VMREF, PCI, 3V66, 3V48, REF system clock
signals to support a computer system with a
3V66(2)
3V66(3)
V
3.3V
DD
PWRDWN
V
3.3V
DD
Pentium 4 microprocessor and
Rambus memory subsystem.
a
Direct
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided
at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies
and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external
components. Thehost, PCI clock and 48-MHzclockoutputsprovidelow-skew/low-jitter clock signalsfor reliable
clock operation. All outputs have 3-state capability, which can be selected using control inputs SEL133, SelA
and SelB.
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. When PWRDWN is set to
high, the device operates in normal mode. When PWRDWN is set low, the device transitions to a power-down
mode in which HCLK is driven at 2 I
, HCLK is not driven, and all others are set low.
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
This is system design dependant.
Intel and Pentium 4 are trademarks of Intel Corporation.
Rambus is a trademark of Rambus Corporation.
Copyright 2000, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
description (continued)
The HOST bus operates at 100 MHz or 133 MHz. The MREF bus operates at 50 MHz or 66 MHz. Output
frequency selection is accomplished with corresponding setting for SEL100/133 control input. The PCI bus
frequency is fixed to 33 MHz.
Since the CDC930 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up as well as changes to SEL inputs. With use of external
reference clock, this signal must be fixed-frequency and fixed-phase prior stabilization time starts.
functional block diagram
3-State/Low
Control
Logic
23
Test
SEL100/133
SEL 100/133
2
25
26
SELA
SELB
2*REF
14.318 MHz
(2,3)
Latched
5
6
2*3V48
48 MHz
(25,26)
XIN
48 MHz
PLL
Xtal
Oscillator
XOUT
10*PCI
33 MHz
(8,9,11,12,14,
15,17,18,20,21)
/3
/2
Spread
Logic
CPU
PLL
/2
52
28
SPREAD
/2
4*3V66
66 MHz
(30,31,34,35)
PWRDWN
1*3VMREF
50/66 MHz
(55)
180
Phase
Shift
1*3VMREF
50/66 MHz
(54)
2
3
MultSel0
MultSel1
Latched
2
4*HCLK
100/133 MHz
(42,45,48,51)
4*HCLK
100/133 MHz
(41,44,47,50)
39
I_REF
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
3V48(0)/SelA
3V48(1)/SelB
3V66[0–3]
3VMREF
25
I/O
I/O
O
Dual function 3.3 V, Type 3, 48-MHz clock output that latches the state of SelA during power up
Dual function 3.3 V, Type 3, 48-MHz clock output that latches the state of SelB during power up
3.3 V, Type 5, 66-MHz clock outputs
26
30, 31, 34, 35
55
54
O
3.3 V, Type 5, 50/66-MHz memory clock output
3VMREF
O
3.3 V, Type 5, 50/66-MHz memory clock output (180 out of phase with 3VMREF)
Ground for core and HCLK/HCLK, 3VMREF/3VMREF, 3V48, 3V66 and PCI outputs
GND
1, 7, 13, 19,
24, 32, 33, 37,
40, 46, 53
HCLK[1–4]
HCLK[1–4]
I_REF
42, 45, 48, 51
41, 44, 47, 50
39
O
O
Type X1, host clock outputs
Type X1, host complementary clock outputs
Special Current reference pin for the host clock pairs. I_REF uses a fixed precision resistor tied to ground
to establish the appropriate current.
PCI[0–9]
8, 9, 11, 12,
14, 15, 17, 18,
20, 21
O
3.3 V, Type 5, 33-MHz PCI clock outputs
PWRDWN
28
I
Power down for complete device with HOST at 2 I
forced low.
, HCLK not driven and all other outputs
REF
REF0/MultSel0
2
I/O
Dual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel0 is latched
during power up. MultSel0 configures the I
the HCLK pair outputs.
amplitude (and thus the V
swing amplitude) of
OH
OH
REF1/MultSel1
3
I/O
Dual function 3.3 V, Type 3, 14.318-MHz reference clock output. The state of MultSel1 is latched
during power up. MultSel1 configures the I
the HCLK pair outputs.
amplitude (and thus the V
swing amplitude) of
OH
OH
SEL100/133
SPREAD
23
52
I
I
I
Active low LVTTL level logic select. SEL100/133 is used for enabling 100/133 MHz. Low=100
MHz, high=133 MHz
LVTTL level logic select. SPREAD pin enables/disables the spread spectrum for the
HCLK/HCLK, 3VMREF/3VMREF, 3V66 and PCI outputs.
V
3.3V
4, 10, 16, 22,
27, 29, 36, 38,
43, 49, 56
3.3-V power for core and the HCLK/HCLK, 3VMREF/3VMREF, 3V48, 3V66, and PCI outputs.
DD
XIN
XOUT
5
6
I
Crystal input – 14.318 MHz
Crystal output – 14.318 MHz
O
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
Function Tables
SELECT FUNCTIONS
OUTPUTS
INPUTS
FUNCTION
SEL100/133 SelA
SelB
HOST, HCLK
100 MHz
Hi-Z
3VMREF, 3VMREF
PCI
33 MHz 66 MHz 48 MHz 14.318 MHz Active 100 MHz
Hi-Z Hi-Z Hi-Z Hi-Z All outputs 3-stated
33 MHz 66 MHz 48 MHz 14.318 MHz Active 133 MHz
TCLK/8 TCLK/4 TCLK/2 TCLK Test Mode
3V66
3V48
REF
0
0
1
1
0
1
0
1
0
1
0
1
50 MHz
Hi-Z
133 MHz
TCLK/2
66 MHz
TCLK/4
ENABLE FUNCTION
OUTPUTS
3VMREF, 3VMREF
INPUT
SEL100/133
HCLK
HCLK
PCI
L
3V66
L
3V48
REF
L
0
1
2 I
REF
Not driven
On
L
L
On
On
On
On
On
On
SPREAD SPECTRUM FUNCTION
OUTPUTS
INPUT
0
Spread spectrum clocking active, –0.6% at HCLK/HCLK, 3VMREF/3VMREF, 3V66, PCI
SPREAD
1
Spread spectrum clocking nonactive
OUTPUT BUFFER SPECIFICATIONS
V
DD
RANGE IMPEDANCE
BUFFER NAME
BUFFER TYPE
(V)
( )
3V48, REF
PCI, 3V66
3.135 – 3.465
3.135 – 3.465
3.135 – 3.465
20–60
12–65
12–55
TYPE 3
TYPE 5
TYPE 5
TYPE X1
3VMREF/3VMREF
HCLK/HCLK
OUTPUT BUFFER SPECIFICATIONS
REFERENCE R,
INPUTS
MultSel1
BOARD TARGET
TRACE/TERM Z
V
AT Z
OH
OUTPUT CURRENT
I
= VDD/3 R )
IREF = 2.32 mA
REF
r
MultSel0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
60
50
60
50
60
50
60
50
R = 475 1%, I
= 2.32 mA
= 2.32 mA
= 2.32 mA
= 2.32 mA
= 2.32 mA
= 2.32 mA
= 2.32 mA
= 2.32 mA
I
I
I
I
I
I
I
I
= 5 I
= 5 I
= 6 I
= 6 I
= 4 I
= 4 I
= 7 I
= 7 I
0.71 V at 60
0.59 V at 50
0.85 V at 60
0.71 V at 50
0.56 V at 60
0.47 V at 50
0.99 V at 60
0.82 V at 50
r
REF
REF
REF
REF
REF
REF
REF
REF
OH
OH
OH
OH
OH
OH
OH
OH
REF
REF
REF
REF
REF
REF
REF
REF
R = 475 1%, I
r
R = 475 1%, I
r
R = 475 1%, I
r
R = 475 1%, I
r
R = 475 1%, I
r
R = 475 1%, I
r
R = 475 1%, I
r
NOTE: The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DD
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
I
DD
Voltage range applied to any output in the high-impedance state or power-off state,
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
DD
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 rated I
O
OL
Input clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
(V < V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
I
DD
Output clamp current , I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
(V < V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
O
DD
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 C/W
Package thermal impedance,
JA
Maximum power dissipation at T = 55 C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
A
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 85 C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 150 C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,
which use a trace length of zero. The absolute maximum power dissipation allowed at T = 55 C (in still air) is 1.3 W.
A
3. The maximum package power dissipation is calculated using a junction temperature of 1505C and a board trace length of 750 mils.
Formoreinformation, refertothe
, literature number SCBD002.
application note in the
DISSIPATION RATING TABLE
‡
T
25 C
DERATING FACTOR
ABOVE T = 25 C
A
T
= 70 C
T = 85 C
A
POWER RATING
A
A
PACKAGE
POWER RATING
POWER RATING
DL
1558.6 mW
12.468 mW/ C
997.5 mW
810.52 mW
‡
This is the inverse ofthe traditional junction-to-case thermal resistance (R
at 74 C/W.
) and usesa board-mounted device
JA
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
recommended operating conditions (see Note 2)
†
MIN
NOM
MAX
UNIT
Supply voltage, V
3.135
3.465
V
DD
V
0.3 V
+
DD
High-level input voltage, V
2
V
IH
IL
GND –
0.3 V
Low-level input voltage, V
Input voltage, V
0.8
V
V
0
V
DD
I
HCLK/HCLK
–20
–15
–16
–15
5
3VMREF/3VMREF
48MHz, REFx
PCIx, 3V66x
High-level output current, I
mA
OH
HCLK/HCLK
A
3VMREF/3VMREF
48MHz, REFx
PCIx, 3V66x
10
Low-level output current, I
OL
10
mA
10
‡
Reference frequency, f
(XIN)
Test mode
14
MHz
MHz
C
§
Crystal frequency, f
Normal mode
13.8 14.318
0
14.8
85
(XTAL)
Operating free-air temperature, T
A
†
‡
All nominal values are measured at their respective nominal V
values.
DD
Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven
externally up to f = 16 MHz. If XIN is driven externally, XOUT is floating.
(XIN)
This is a series fundamental crystal with f = 14.31818 MHz.
§
O
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.
5. , V : All input levels referenced to V = 3.30 V.
V
IH IL DD
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
IK
V
V
V
= 3.135 V,
= 3.465 V,
= 3.135 V,
I = –18 mA
–1.2
DD
DD
DD
I
R
Input resistance
XIN-XOUT
XOUT
V = V
–0.5 V
–0.5 V
100
k
I
I
DD
DD
V = V
50
10
mA
I
MultSel0, MultSel1,
SelA, SelB
V
DD
= 3.465 V,
V = V
A
I
DD
DD
I
IH
High-level input current
SEL100/133
SPREAD, PWRDWN
V
V
V
= 3.465 V,
= 3.135 V,
= 3.465 V,
V = V
5
–5
A
mA
A
DD
DD
DD
I
XOUT
V
= 0 V
O
MultSel0, MultSel1,
SelA, SelB,
V = GND
–10
I
I
I
Low-level input current
IL
SEL100/133
SPREAD, PWRDWN
V
V
= 3.465 V,
= 3.465 V,
V = GND
–5
A
DD
I
I_REF
R = 221
r
–5.5
mA
DD
SELA, SELB = H,
SEL100/133 H
L
L
High-impedance-state output current
V
= 3.465 V
10
A
OZ
DD
V
= V
or GND
O
DD
PWRDWN = H
SELA, SELB = H,
SEL100/133 H
PWRDWN = H
I
I
High-impedance-state supply current
PWRDWN state supply current
V
V
= 3.465 V
= 3.465 V,
40
30
mA
mA
DD(Z)
DD
PWRDWN = L
PWRDWN = H,
DD(PD)
DD
HCLK = 133 MHz,
SSC = ON/OFF,
I
Dynamic supply current
V
= 3.465 V
250
5
mA
DD
DD
C
R
= MAX
L
= 475
,
ref
I
= 6
I
ref
OUT
‡
C
C
Input capacitance
V
V
= 3.3 V,
= 3.3 V,
V = V
or GND
2
pF
pF
I
DD
I
DD
Crystal terminal capacitance
V = 0.3 V
I
18
(XTAL)
DD
†
‡
All typical values are measured at their respective nominal V
values.
DD
These parameters are ensured by design and lab characterization, not 100% production tested.
Control SELx, PWRDWN, SPREAD threshold levels during FUNC w/c level tests.
C
C
C
= MAX = 5 pF, R = 33.2 , R = 49.9 at HCLK/HCLK (Type X1)
L
L
L
s p
= MAX = 20 pF, R = 500 at 48 MHz, REF (Type 3)
L
= MAX = 30 pF, R = 500 at PCIx, 3V66, 3VMREF, 3VMREF (Type 5)
L
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
HCLK/HCLK (Type X1)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
–10.5
–13.1
–15.7
–18.4
UNIT
V
V
V
V
V
V
V
V
= 3.135 V
= 3.465 V
= 3.135 V
= 3.465 V
= 3.135 V
= 3.465 V
= 3.135 V
= 3.465 V
–8.1
DD
DD
DD
DD
DD
DD
DD
DD
I
I
I
I
= 2.32 mA
= 2.32 mA
= 2.32 mA
= 2.32 mA
4
5
6
7
mA
ref
ref
ref
ref
–10.1
–12.1
–14.1
mA
mA
I
High-level output current
V
OH
at Z = 50
OH
mA
pF
‡
C
Output capacitance
V
= V or GND
DD
3.5
O
O
†
‡
All typical values are measured at their respective nominal V
These parameters are ensured by design and lab characterization, not 100% production tested.
values.
DD
48MHz, REFx (Type 3), C = 20 pF, R = 500
L
L
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
VDD –
V
= min to max,
I
= –1 mA
DD
OH
0.1 V
2.4
V
V
High-level output voltage
Low-level output voltage
V
OH
V
V
V
V
V
V
V
V
V
V
= 3.135 V,
= min to max,
= 3.135 V,
= 3.135 V,
= 3.3 V,
I
I
I
= –14 mA
= 1 mA
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OL
OL
0.1
0.4
V
OL
= 9 mA
V
V
V
V
V
V
V
= 1 V
–29
29
2
O
O
O
O
O
O
O
I
High-level output current
Low-level output current
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
–41
mA
OH
= 3.465 V,
= 3.135 V,
= 3.3 V,
–23
I
mA
pF
53
OL
= 3.465 V,
= 3.3 V,
27
5
‡
C
Output capacitance
= V
or GND
DD
O
†
‡
All typical values are measured at their respective nominal V
These parameters are ensured by design and lab characterization, not 100% production tested.
values.
DD
PCIx, 3V66x, MREF/MREF (Type 5), C = 20 pF, R = 500
L
L
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
VDD –
V
= min to max,
I
= –1 mA
DD
OH
0.1 V
2.4
V
V
High-level output voltage
V
OH
V
V
V
V
V
V
V
V
V
V
= 3.135 V,
= min to max,
= 3.135 V,
= 3.135 V,
= 3.3 V,
I
I
I
= –18 mA
= 1 mA
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OL
OL
0.1
0.4
Low-level output voltage
High-level output current
V
OL
= 12 mA
= 1 V
V
V
V
V
V
V
V
–33
30
2
O
O
O
O
O
O
O
I
mA
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
–53
OH
= 3.465 V,
= 3.135 V,
= 3.3 V,
–33
I
Low-level output current
70
mA
pF
OL
= 3.465 V,
= 3.3 V,
38
5
‡
C
Output capacitance
= V
or GND
DD
O
†
‡
All typical values are measured at their respective nominal V
These parameters are ensured by design and lab characterization, not 100% production tested.
values.
DD
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
switching characteristics, V
= MIN to MAX, T = 0 C to 85 C
A
DD
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
‡
v
v
v
v
Overshoot
V +200
OH
over
HCLK/HCLK 0.7 V ampli-
tude
mV
‡
Undershoot
V
–200
under
over
OL
‡
Overshoot
GND–0.7
Other clocks, C = Worst
L
case
V
‡
Undershoot
V
+0.7
100
under
DD
Output enable time to low
level
f
= 100 or 133 MHz,
(HCL)
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
PZL
PZH
PHZ
PLZ
PZL
PZH
PHZ
SELA, SELB = H,
SEL100/133 L
H,
Output enable time to high
level
100
10
10
10
10
10
R
= 475
ref
HCLK/
HCLK
SEL100/133
Output disable time from
high level
f
= 100 or 133 MHz,
(HCL)
SELA, SELB = H,
SEL100/133 H
L,
Output disable time from low
level
R
= 475
ref
Output enable time to low
level
f
= 100 or 133 MHz,
(HCL)
SELA, SELB = H,
SEL100/133 L
H,
Output enable time to high
level
REF, 3V48
3VMREF,
3VMREF,
3V66, PCI
R
= 475
ref
SEL100/133
Output disable time from
high level
f
= 100 or 133 MHz,
(HCL)
SELA, SELB = H,
SEL100/133 H
L,
Output disable time from low
level
t
t
10
3
ns
PLZ
R
= 475
ref
†
Stabilization time
After power up
ms
stab
†
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for
phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present a XIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time from when V
achieves its nominal operating level until the output frequency is stable and operating within specification.
These parameters are ensured by design and lab characterization, not 100% production tested.
DD
‡
HCLK/HCLK (Type X1) C = 2 pF, R > 500 k
L
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
10
TYP
MAX
UNIT
f
f
f
f
= 100 MHz
10.2
7.65
200
(HCLK)
(HCLK)
(HCLK
(HCLK)
†
t
ns
ps
HCLK clock period
c
= 133 MHz
7.5
t
Cycle to cycle jitter
Duty cycle
= 100 or 133 MHz
= 100 or 133 MHz crossing
jit(cc)
dc
t
45%
55%
150
point
f
= 100 or 133 MHz crossing
(HCLK)
point
t
t
HCLK bus skew
HCLKx
0.7 V
HCLKx
ps
ns
sk(o)
w
f
= 100 MHz
= 133 MHz
4.41
3.29
175
175
(HCLK
(HCLK
Pulse duration width
f
t
t
Rise time‡
Fall time‡
V
V
2
= 0.14 V to 0.56 V
= 0.14 V to 0.56 V
700
700
ps
ps
r
O
O
f
am litude
p
‡
t , t
r
Rise and fall time matching
(t – t )/(t + t )
20%
f
r
f
r
f
0.7 V
amplitude
f
= 100 or 133 MHz
40%
VOH
55%
VOH
(HCLK)
HCLK and HCLK
‡
v
V
Cross point voltages
cross
†
‡
The average over any 1– s period of time is greater than the minimum specified period.
These parameters are ensured by design and lab characterization, not 100% production tested.
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
switching characteristics, V
= 3.135 V to 3.465 V, T = 0 C to 85 C (continued)
A
DD
3VMREF/3VMREF (Type 5) C = 30 pF, R = 500
L
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
20
TYP
MAX
UNIT
f
f
= 50 MHz
20.4
15.3
ns
ns
3VMREF/3VMREF clock
(3VMREF/3VMREF)
(3VMREF/3VMREF)
(3VMREF/3VMREF)
t
c
†
period
= 66 MHz
15
f
f
V
= 66 MHz,
= 100 or 133 MHz,
= 3.3 V, Measured at 1.5 V
t
t
t
Cycle to cycle jitter
Duty cycle
250
55%
250
ps
jit(cc)
(HCLK)
DD
f
= 66 MHz
= 66 MHz,
= 100 or 133 MHz,
= 3.3 V, Measured at 1.5 V
45%
dc
(3VMREF/3VMREF)
(3VMREF/3VMREF)
f
f
V
3VMREF/3VMREF output
skew
3VMREF/
3VMREF
3VMREF/
3VMREF
ps
ns
sk(o)
(HCLK)
DD
f
= 66 MHz,
(3VMREF/3VMREF)
3VMREF/3VMREF clock
to PCI offset
3VMREF/
3VMREF
Measured points at 1.5 V,
Measured at rising edges
t
PCIx
3
(off)
t
t
Rise time
Fall time
V
V
= 0.4 V to 2.4 V
= 0.4 V to 2.4 V
0.5
0.5
2
2
ns
ns
r
O
O
f
†
The average over any 1– s period of time is greater than the minimum specified period.
3V66 (Type 5, No SSC), C = 30 pF, R = 500
L
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
†
t
t
t
t
3V66 clock period
f
= 66 MHz
= 66 MHz,
15.03
ns
c
(3V66)
f
f
V
(3V66)
Cycle to cycle jitter
Duty cycle
= 100 or 133 MHz,
= 3.3 V, Measured at 1.5 V
300
55%
250
ps
jit(cc)
dc
(HCLK)
DD
f
= 66 MHz
45%
1.5
(3V66)
f
f
V
= 66 MHz,
(3V66)
3V66 output skew
3V66x
3V66x
PCIx
= 100 or 133 MHz,
= 3.3 V, Measured at 1.5 V
ps
ns
sk(o)
(HCLK)
DD
f
= 66 MHz,
(3V66)
t
3V66 clock to PCI
3V66x
Measured points at 1.5 V,
Measured at rising edges
3.5
(off)
t
t
Rise time
Fall time
V
V
= 0.4 V to 2.4 V
= 0.4 V to 2.4 V
0.5
0.5
2
2
ns
ns
r
O
O
f
†
The average over any 1– s period of time is greater than the minimum specified period.
PCI (Type 5), C = 30 pF, R = 500
L
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
†
t
t
t
t
t
t
PCI clock period
f
f
f
f
= 33.3 MHz
30.06
ns
ps
c
(PCI)
Cycle to cycle jitter
Duty cycle
= 100 or 133 MHz
500
55%
500
2
jit(cc)
(HCLK)
= 33.3 MHz
= 33.3 MHz
45%
dc
(PCI)
(PCI)
PCI output skew
Rise time
PCIx
PCIx
ps
ns
ns
sk(o)
V
V
= 0.4 V to 2.4 V
= 0.4 V to 2.4 V
0.5
0.5
r
f
O
O
Fall time
2
†
The average over any 1– s period of time is greater than the minimum specified period.
10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
switching characteristics, V
= 3.135 V to 3.465 V, T = 0 C to 85 C (continued)
A
DD
3V48 (Type 3), C = 20 pF, R = 500
L
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
†
t
t
t
t
3V48 clock period
f
= 48 MHz
15.03
ns
c
(3V48)
(3V48)
f
f
V
= 48 MHz,
= 100 or 133 MHz,
= 3.3 V, Measured at 1.5 V
Cycle to cycle jitter
Duty cycle
350
55%
250
ps
jit(cc)
dc
(HCLK)
DD
f
= 48 MHz
45%
1.5
(3V48)
f
f
V
= 48 MHz,
(3V48)
= 100 or 133 MHz,
= 3.3 V, Measured at 1.5 V
3V48 output skew
3V48x
3V48x
PCIx
ps
ns
sk(o)
(HCLK)
DD
f
= 48 MHz,
(3V48)
t
3V48 clock to PCI
3V48x
Measured points at 1.5 V,
Measured at rising edges
3.5
(off)
t
t
Rise time
Fall time
V
V
= 0.4 V to 2.4 V
= 0.4 V to 2.4 V
1
1
4
4
ns
ns
r
O
O
f
†
The average over any 1– s period of time is greater than the minimum specified period.
REF (Type 3), C = 20 pF, R = 500
L
L
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
†
t
t
t
t
t
REF clock period
f
f
f
= 14.318 MHz
69.84
c
(REF)
Cycle to cycle jitter
Duty cycle
= 100 or 133 MHz
1
62%
4
ps
jit(cc)
(HCLK)
= 14.318 MHz
= 0.4 V to 2.4 V
= 0.4 V to 2.4 V
52%
dc
r
(REF)
Rise time
V
V
1
1
ns
ns
O
Fall time
4
f
O
†
The average over any 1– s period of time is greater than the minimum specified period.
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
R
= 500
V
L
S1
ref(O)
OPEN
GND
TEST
/t
S1
Open
From Output
Under Test
t
t
t
PLH PHL
C
L
R = 500
L
/t
V
PLZ PZL
/t
ref(OFF)
GND
(see Note A)
PHZ PZH
LOAD CIRCUIT of single-ended outputs for t
and t
sk
pd
t
w
From Output
Under Test
Test
Point
3 V
V
ref(IH)
Input
V
ref(T)
C
L
V
0 V
ref(IL)
(see Note A)
VOLTAGE WAVEFORMS
LOAD CIRCUIT of single-ended outputs for t and t
r
f
Output
Enable
(high-level
enabling)
V
3 V
DD
Input
V
V
ref(T)
V
V
ref(T)
ref(T)
ref(T)
0 V
0 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
OH
V
V
V
ref(IH)
ref(T)
ref(IL)
V
ref(T)
Output
V
+ 0.3 V
OL
(see Note B)
V
OL
V
OL
f
t
PZH
t
t
t
PHZ
r
Output
Waveform 2
S1 at GND
V
OH
0 V
t
V
– 0.3 V
w(H)
OH
V
ref(T)
t
w(L)
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
C includes probe and jig capacitance. C = 2 pF (HCLK, HCLK), C = 20 pF (48MHZ, REF), C = 30 pF (PCIx, 3VMREF, 3V66).
L
NOTES: A.
L
L
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
14.318 MHz, Z = 50 , t 2.5 ns,
O r
t
f
PARAMETER
3.3-V INTERFACE
2.5-V INTERFACE
UNIT
V
High-level reference voltage
2.4
2
V
ref(IH)
V
Low-level reference voltage
Input threshold reference voltage
Off-state reference voltage
0.4
1.5
6
0.4
1.25
4.6
V
V
V
ref(IL)
V
ref(T)
V
ref(OFF)
Figure 1. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
V
V
PCIx, 3V48x, 3V66x
PCIx, 3V48x, 3V66x
T_REF
t
c
T_REF
t
t
t
(high)
sk(o)
(low)
t
(low or high)
tdc
100
t
c
t
c
HCLKx
HCLKx
t
W
HCLKx
HCLKx
t
sk(o)
t
W
t
=
x 100
dc
t
c
3V66
PCIx
V _
T REF
V _
T REF
t
[3V66 to PCIx]
(off)
PARAMETER
Input threshold reference voltage
3.3-V INTERFACE
UNIT
V
1.5
V
T_REF
Figure 2. Waveforms for Calculation of Output Skew, Duty Cycle, and Offset
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
HCLK
HCLK
t
t
c (n)
c (n+1)
t
=
t
– t
jit(cc)
c(n)
c(n+1)
VT_REF
t
t
c(n)
c(n+1)
– t
c(n) c(n+1)
t
=
t
jit(cc)
PARAMETER
Input threshold reference voltage
3.3-V INTERFACE
UNIT
V
1.5
V
T_REF
Figure 3. Waveforms for Calculation of Cycle-Cycle Jitter
14
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
PARAMETER MEASUREMENT INFORMATION
0 ns
50 ns
100 ns
150 ns
200 ns
PWRDWN
HOST 100 MHz
HOST 100 MHz
3VMREF
3VMREF
3V66 MHz
PCI 33MHz
3V48 MHz
REF 14.318 MHz
Figure 4. Power DOWN Timing
V
DD
R
R
= 33
S1
S1
TLA
TLB
HCLK
Clock
Clock
MultSel0
CDC930
MultiSel1
= 33
R
HCLK
C
= 2 pF
L
C
= 2 pF
= 49.9
R
= 49.9
T1
L
T1
R
= 475
IREF
NOTE A:
Z
= Z
= 50 , L
(TLA)
= L
= 3.5’’, C represents probe and jig capacitance.
(TLB) L
(TLA)
(TLB)
Figure 5. Load Circuit for 0.7 V Amplitude HCLK/HCLK Bus
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SCAS641 – JULY 2000
MECHANICAL DATA
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48-PIN SHOWN
0.025 (0,635)
48
0.012 (0,305)
0.005 (0,13)
0.008 (0,203)
M
25
0.006 (0,15) NOM
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0 –8
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
0.110 (2,79) MAX
PINS **
28
48
56
DIM
0.380
(9,65)
0.630
(16,00) (18,54)
0.730
A MAX
0.370
(9,40)
0.620
(15,75) (18,29)
0.720
A MIN
4040048/D 08/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
16
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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