CDC960 [TI]
200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE; 200 - MHz的时钟合成器/驱动器,具有SPREAD SPECTURM能力建设与设备控制接口型号: | CDC960 |
厂家: | TEXAS INSTRUMENTS |
描述: | 200-MHz CLOCK SYNTHESIZER/DRIVER WITH SPREAD SPECTURM CAPABILITY AND DEVICE CONTROL INTERFACE |
文件: | 总38页 (文件大小:551K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢅ ꢄ ꢄ ꢆꢇꢈ ꢉ ꢀꢊ ꢋ ꢀꢌ ꢍꢎ ꢏꢐ ꢈꢑꢍꢒ ꢓ ꢑꢔ ꢕ ꢁꢔ ꢒ ꢖꢑ ꢔ
ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
DL PACKAGE
(TOP VIEW)
D
D
D
Generates Clocks for AMD-K8 Clawhammer
Desktop Systems
Uses a 14.318-MHz Crystal Input to
Generate Multiple Output Frequencies
FS0 & REF0
FS1 & REF1
GND
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
2
3
4
5
6
7
8
9
DD
Includes Spread Spectrum Clocking (SSC),
0.5% Downspread for Reduced EMI
XIN
XOUT
GND
V
DD
FS2 & REF2
SPREAD
D
Power Management Control Terminals
D
SMBus Serial Interface Provides Output
Enable and Control
PCI/LDT_SEL
PCI/LDT0
V
DDA
GNDA
CPU0
CPU0
GND
PCI/LDT1
D
Low-Output Skew and Low Jitter for Clock
Distribution
V
DD
GND
PCI/LDT2
LDT_Stop
PCI0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D
Operates From Single 3.3-V Supply
V
DD
D
Generates the Following Clocks:
– 2 CPU (3.3 V, 180° shifted pairs,
200/166/133/100 MHz)
CPU1
CPU1
PCI1
V
DD
– 6 PCI (3.3 V, 33 MHz)
GND
GND
– 1 PCI_F (3.3 V, 33 MHz)
– 3 REF (3.3 V, 14.318 MHz)
– 1 USB (3.3 V, 48 MHz)
V
GNDF
DD
PCI2
PCI3
V
DDF
USB
GND
– 1 FDC (3.3 V, 24 MHz or 48 MHz)
V
†
DD
– 3 PCI/LDT (3.3 V, 33 MHz or 66 MHz)
GND
PCI4
V
DD
D
Packaged in 48-Pin SSOP Package
24/48_SEL & FDC
GND
PCI5
description
PCI_F
SDATA
The CDC960 is a clock synthesizer/driver and
PCI_Stop
SCLK
buffer that generates CPU, PCI, PCI/LDT, USB,
FDC, and REF system clock signals to support
PCs with an AMD-K8 Clawhammer-class system.
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided
at the XIN input instead of a crystal. It is recommended to use the bypass mode of the internal oscillator in this
case. Two phase-locked loops (PLLs) are used to generate the host frequencies and 48-MHz clock frequencies.
On-chip loop filters and internal feedback eliminate the need for external components.
The device provides a standard mode (100 kbps) SMBus 1.1 serial interface for device control. The
implementation is as a slave with read and write capability. The device address is specified in the SMBus serial
interface device address table. Both SMBus inputs (SDATA and SCLK) provide integrated pullup resistors
(typically 150 kΩ).
Seven 8-bit SMBus registers provide individual enable control for each of the outputs. The controllable outputs
default to enabled at power up and can be placed in a disabled mode with a low-level output when a low-level
control bit is written to the control register. The registers must be accessed in sequential order (i.e., random
access of the registers not supported).
The CPU, PCI, PCI_F, LDT, FDC (24/48-MHz), and USB (48-MHz) clock outputs provide low-skew/low-jitter
clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control
inputs FS0, FS1, and FS2 at power-up preset condition.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
LDT is equivalent to HT66 shown on AMD specification.
Copyright 2002, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
description (continued)
The CPU bus is a 3.3-V differential push-pull output type. All others are single-ended CMOS buffers.
The host frequencies are fixed and are controlled by the FS0, FS1 and FS2 signals at power-up. The CPU bus
frequencies are 200, 166, 133 and 100 MHz.
Because the CDC960 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
With use of external reference clock, this signal must be fixed-frequency and fixed-phase prior stabilization time
starts.
FUNCTION TABLES
DEVICE FREQUENCY SELECT FUNCTIONS
SMBUS
INPUTS
OUTPUTS
CONTROLLED
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
200 MHz
200 MHz
200 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Xin
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
Xin/6
33 MHz
66 MHz
33 MHz
66 MHz
33/66 MHz
33/66 MHz
33/66 MHz
Xin/6
48 MHz
48 MHz
48 MHz
48 MHz
24 MHz
24 MHz
48 MHz
48 MHz
14.31818 MHz
14.31818 MHz
L
L
H
14.31818 MHz
L
L
L
14.31818 MHz
L
H/L
H/L
H/L
X
H/L
H/L
H/L
H
48 MHz 24/48 MHz
48 MHz 24/48 MHz
48 MHz 24/48 MHz
14.31818 MHz
L
H
L
14.31818 MHz
L
L
14.31818 MHz
L
L
H
H
H
H
H
H
L
L
L
L
f
f
= 0 to
(xin)
200 MHz
L
X
L
L
L
Xin
Xin/6
Xin/3
L
L
L
L
H
H
L
H
H
H
H
H
L
Xin
Xin/6
Xin/6
Xin/2
Xin/2
Xin/2
Xin/2
Xin/4
Xin/4
Xin/2
Xin/2
Xin
Xin
Xin
Xin
L
H
L
L
Xin
Xin/6
Xin/3
= 0 to
(xin)
16 MHz
L
L
H
L
Xin
Xin/6
Xin/6
L
L
L
L
Xin
Xin/6
Xin/3
L
X
X
L
Reserved for future use
Hi-Z Hi-Z
L
X
X
L
L
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
H
H
H
H
H
H
H
X
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H
H
H
H
L
H
H
L
H
L
90 MHz
119 MHz
30 MHz
30 MHz
30/60 MHz
30/60 MHz
48 MHz 24/48 MHz
48 MHz 24/48 MHz
14.31818 MHz
14.31818 MHz
14.31818 MHz
14.31818 MHz
14.31818 MHz
14.31818 MHz
14.31818 MHz
14.31818 MHz
–10%
–10%
–10%
–10%
10%
H
L
180 MHz 36.3 MHz 36.3/72.6 MHz 48 MHz 24/48 MHz
L
180 MHz
111 MHz
30 MHz
30/60 MHz
48 MHz 24/48 MHz
H
H
L
H
L
36.9 MHz 36.9/73.9 MHz 48 MHz 24/48 MHz
L
148 MHz 36.9 MHz 36.9/73.9 MHz 48 MHz 24/48 MHz
222 MHz 44.4 MHz 44.4/88.8 MHz 48 MHz 24/48 MHz
222 MHz 36.9 MHz 36.9/73.9 MHz 48 MHz 24/48 MHz
Not-yet-defined settings
10%
L
H
L
10%
L
L
10%
X
X
X
†
‡
If the REF, USB, and FDC outputs are disabled in by pass mode, the Xin-input can be driven with an external clock signal from 0 MHz to 200 MHz.
Otherwise the maximum input frequency is limited to 16 MHz.
24/48_SEL and PCI/LDT_SEL inputs operate independently from each other and the frequency of the corresponding bus, as shown in detail
for the 200-MHz configuration.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄ
ꢅ ꢄ ꢄ ꢆꢇꢈ ꢉ ꢀꢊ ꢋ ꢀꢌ ꢍꢎ ꢏꢐ ꢈꢑꢍꢒ ꢓ ꢑꢔ ꢕꢁ ꢔꢒ ꢖ ꢑ ꢔ
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SCAS675 – APRIL 2002
FUNCTION TABLES (Continued)
SPREAD SPECTRUM
INPUT
0
1
Spread spectrum disabled
Spread
Spread spectrum enabled, –0.5% at CPU/CPU, PCI/LDT, PCI_F, PCI
DEVICE ENABLE FUNCTIONS
SMBus
CONTROLLED
INPUTS
OUTPUTS
INTERNAL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
L
X
H
H
L
X
H
L
L
H
H
H
H
H
H
H
H
L
L
X
X
X
X
X
X
X
X
L
L
X
X
X
X
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Xtal
Xtal
Xtal
Xtal
Xtal
Xtal
Xtal
Xtal
Xtal
H
Hi-Z
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
H
Hi-Z
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
L
Hi-Z
↑↓
Hi-Z
↑↓
L
Hi-Z
↑↓
L
Hi-Z
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
L
Hi-Z
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
L
Hi-Z
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
L
Off
↑↓
Off
↑↓
↑↓
↑↓
↑↓
H
L
↑↓
↑↓
L
↑↓
L
↑↓
↑↓
L
↑↓
↑↓
↑↓
H
H
L
H
L
↑↓
↑↓
L
↑↓
↑↓
L
↑↓
↑↓
L
↑↓
↑↓
↑↓
L
H
L
↑↓
↑↓
L
↑↓
↑↓
L
L
↑↓
L
↑↓
↑↓
X
H
H
L
X
X
H
L
H
H
L
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
L
HL
HL
L
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
H
H
L
HL
L
L
L
L
L
L
H
H
H
L
L
L
L
L
H
HL
L
L
L
L
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
L
L
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
L
L
L
L
H
L
L
H
H
L
L
H
H
L
HL
HL
L
HL
HL
HL
L
L
L
L
L
H
H
L
L
L/H
L/H
L/H
L/H
L/H
L/H
H/L
H/L
H/L
L
H
L
L
HL
L
L
L
L
L
†
‡
SMBus bits set to their reset values
Hi-Z will have LOW state if external load circuit is applied, CPU and CPU are push-pull type outputs.
↑↓ Outputs toggle at the selected frequency according to the Device Frequency Select FunctionS table above.
HL device output state is undefined, either L or H. It is L if Xin is held static at L or H before the bypass mode is selected.
OUTPUT BUFFER SPECIFICATIONS
V
DD
RANGE
(V)
IMPEDANCE
BUFFER NAME
LUMPED TEST LOAD
(Ω)
CPU
3.135 – 3.465
3.135 – 3.465
3.135 – 3.465
40
25
35
10 pF
30 pF
20 pF
PCI, PCI_F, LDT
REF, USB, FDC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ
ꢅꢄ ꢄꢆꢇ ꢈꢉ ꢀ ꢊ ꢋꢀꢌ ꢍ ꢎꢏ ꢐꢈ ꢑꢍ ꢒ ꢓꢑ ꢔꢕ ꢁ ꢔꢒ ꢖ ꢑꢔ
ꢗ
ꢒ
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ꢈ
ꢍ
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ꢔ
ꢑ
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ꢁ
ꢍ
ꢘꢑ
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ꢔ
ꢚ
ꢇ
ꢀ
ꢙ
ꢘꢙ
ꢛ
ꢒ
ꢊꢒ
ꢐ
ꢎ
ꢙ
ꢏ
ꢁ
ꢁ
ꢑ
ꢖ
ꢒ
ꢀ
ꢑ
ꢀ
ꢋ
ꢏ
ꢐ
ꢔ
ꢋ
ꢊ
ꢒ
ꢏ
ꢐꢑ
ꢔ
ꢜ
ꢙ
ꢀ
ꢑ
SCAS675 – APRIL 2002
functional block diagram
25
SCLK
26
SMBus
SDATA
44
SPREAD
Control
Logic
V
DD
/2
1 x FDC
24/48 MHz
24/48_SEL
(28)
V
DD
@ Power Up
1 x USB
48MHz
(31)
48 MHz
PLL
V
DD
3
4
XIN
3 x REF
Xtal
Oscillator
14.318 MHz
FS0, FS1, FS2
(1, 45, 48)
XOUT
@ Power Up
CPU
PLL
/2
/2
/3
/4
2 x CPU
(200/166/133/100 MHz)
(37, 41)
SPREAD
SPECTRUM
2 x CPU
(200/166/133/100 MHz)
(36, 40)
V
DD
12
0
1
LDT_Stop
/5
/6
V
DD
3 x PCI/LDT
33/66 MHz
(7, 8, 11)
/2
6
PCI/LDT_SEL
PCI_Stop
24
6 x PCI
33 MHz
(13, 14, 17, 18, 21, 22)
1 x PCI_F
33 MHz
(23)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄ
ꢅ ꢄ ꢄ ꢆꢇꢈ ꢉ ꢀꢊ ꢋ ꢀꢌ ꢍꢎ ꢏꢐ ꢈꢑꢍꢒ ꢓ ꢑꢔ ꢕꢁ ꢔꢒ ꢖ ꢑ ꢔ
ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
CPU[0:1],CPU[0:1]
41, 37
40, 36
O
3.3-V, differential CPU clock outputs
CPU Clock Outputs 0 and 1: CPU push-pull true clock outputs of the differential pair
CPU Clock Outputs 0 and 1: CPU push-pull complementary clock outputs of the differential pair
FS[0:2] & REF[0:2]
1, 48, 45
I/O
G
3.3 V, 14.318-MHz clock outputs
Frequency Select inputs: Power–on strapping to set device operating frequency as described in
the Device Frequency Select Functions table. These inputs have 150-kΩ internal pullup resistors.
Low = 0, High = 1. 3.3-V reference clock outputs: Fixed clock output at 14.318 MHz
GND
5, 10, 15,
20, 27, 30,
34, 39, 47
Power Connection: Connected to V . Used to ground digital portions of the chip
SS
GNDA
GNDF
42
33
G
G
Analog GND: Connected to VSS through filter. Used to ground the main CPU-PLL on the chip
Analog GND for 48-MHz PLL: Connected to V
the chip
through filter. Used to ground the 48-MHz PLL on
SS
LDT_Stop
12
I
Control for 66-MHz PCI clocks: Active LOW control input to halt all 66-MHz PCI clocks except the
free-running clock. This input has a 150-kΩ internal pullup resistor. Once this input has been
asserted, PCI/LDT outputs if operating at 66-MHz must stop in the low state within 1 µs.
Low = stop, High = running
PCI[0:5]
PCI_F
13, 14, 17,
18, 21, 22
O
O
3.3-V PCI clock outputs divided down from CPU-PLL
3.3-V PCI clock outputs: PCI clocks operate at 33 MHz.
23
7, 8, 11
6
3.3-V, 33-MHz clocks divided down from CPU-PLL
3.3-V Free-Running PCI clock output: The free-running PCI clock pin operates at 33 MHz. The
free-running PCI clock is not turned off when PCI_Stop# is activated LOW.
PCI/LDT[0:2]
PCI/LDT_SEL
O
I
3.3-V PCI 33-MHz or LDT 66-MHz outputs: This group of outputs is selectable between 33 MHz
and 66 MHz based upon the state of PCI/LDT_SEL. When running at 66 MHz these outputs are for
use as reference clocks to LDT devices.
PCI 33-MHz/LDT 66-MHz Select: This input selects the output frequency of PCI/LDT outputs to
either 33 MHz or 66 MHz. This is a dedicated input pin to avoid corruption of the input state due to
PCI add-in cards that may have termination resistors on the input clocks. This input has a 150-kΩ
internal pullup resistor. Low = 66-MHz outputs, High = 33-MHz outputs
PCI_Stop
24
I
3.3-V LVTTL-compatible input for PCI_Stop active low
Control for 33-MHz PCI clocks: Active LOW control input to halt all 33-MHz PCI clocks except the
free-running clock. This input has a 150-kΩ internal pullup resistor. Once this input has been
asserted, the PCI outputs and PCI/LDT outputs operating at 33 MHz must stop in the low state
within 1 µs.
Low = stop, High = running
SCLK
25
26
I
SMBus compatible SCLK.
Clock pin for SMBus circuitry (SMBus revision 1.1). This input has an internal pull-up resistor of
150 kΩ. SCLK is a 3.6-V tolerant signal input. High impedance at power down is not supported.
SDATA
I/O
SMBus compatible SDATA
Data pin for SMBus circuitry (SMBus revision 1.1). This output is open drain and has an internal
pullup resistor of 150 kΩ. SDATA is a 3.6V tolerant signal IO. High impedance at power down is not
supported.
SPREAD
44
I
Spread Spectrum Clocking Enable: Power-on strapping to set spread spectrum clocking as
enabled or disabled. This input allows the default spread spectrum clocking mode to be enabled or
disabled upon power up. This input has a 150-kΩ internal pullup resistor.
Low = disable, High = enable. Note that all Athlon and Hammer systems are recommended to use
SSC; therefore, the default of this pin is enabled and should only be turned off for debug and test
purposes.
USB
31
O
P
3.3-V, fixed 48-MHz non-SSC clock output
3.3-V USB clock output: Fixed clock output at 48 MHz
V
DD
2, 9, 16,
19, 29, 35,
38, 46
Power Connection: Connected to 3.3-V power supply. Used to supply digital portions of the chip
5
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ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
V
V
43
P
Analog V : Connected to 3.3-V power supply through filter. Used to supply the main CPU-PLL
DD
DDA
on the chip
32
3
P
I
Analog V
48-MHz PLL on the chip
for 48-MHz PLL: Connected to 3.3-V power supply through filter. Used to supply the
DDF
DD
XIN
Crystal input – 14.318 MHz
Crystal Connection or External Reference: Reference crystal input or external reference clock
input. This pin includes an internal 36-pF load capacitance to eliminate the need for an external
load capacitor.
XOUT
4
O
Crystal output – 14.318 MHz
Crystal Connection: Reference crystal feedback. This output includes an internal 36-pF load
capacitance to eliminate the need for an external load capacitor.
24/48_SEL & FDC
28
I/O
3.3-V super I/O clock output: The super I/O clock can be strapped for 24 MHz or 48 MHz. This
input has a 150-kΩ internal pullup resistor.
Low = 48-MHz output, High = 24-MHz output
connecting SCLK and SDATA to 5-V SMBus signals
SCLK and SDATA of CDC960 have been designed to work within a 3.3-V supply voltage environment only. In
order to connect SCLK and SDATA to a 5-V SMBus configuration, external circuitry is required. A simple and
inexpensive solution is to use clamping diodes. Two approaches are recommended for this solution:
1. Using Zener diode to clamp to GND in reverse-biased direction
3.3 V
150 kΩ
SCLK
OR
R1
V
O
V
IO
SDATA
Driver
SCLK
or
SDATA
D1
CDC960
Figure 1. SCLK SDATA Connection to 5-V SMBus Using Zener Diode
Zener diode D1 in Figure 1 is chosen such that the Zener voltage (V ) cannot exceed 300 mV above V
of
DD
IH
ZK
the CDC960. The minimum value of V must be greater than 2.1 V to meet minimum requirement for V of
ZK
the CDC960. The value of R1 is chosen to satisfy requirements both for I
of the driver of SCLK and SDATA
OH
and for V and I of SDATA of CDC960.
OL
OL
V
* V
O
IO
I
(For the driver of SCLK and SDATA. RS is the source driver impedance.)
v ǒR1 ) RSǓ
OH
(1)
0.8 V
R1 ) Z
2 mA v
v 6 mA
(For a SDATA of CDC960, 25 W t Z t 47 W)
O
O
(2)
(3)
ǒR1 ) Z
Ǔ
1.75 mA t 0.4 V (For a SDATA of CDC960, 25 W t Z t 47 W)
O
O
6
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ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
connecting SCLK and SDATA to 5-V SMBus signals (continued)
There are many manufacturers making Zener diodes that can be used for this application. Panasonic MA8033
and Vishay BZX84C3V3 that have 3.1 V < V < 3.5 V can be used for this application. In this case R1 is
Z
recommended as 150 Ω.
The worst I
in equation (1) is 16 mA when V
= 5.5 V, R = 0 Ω and V = 3.1 V.
OH
OH S IO
The current in equation (2), between 4 mA and 4.6 mA, satisfies the requirement.
Equation (3) is also satisfied with the selected R1 and diode.
2. Clamping Diode to V
DD
3.3 V
3.3 V
D1
150 kΩ
SCLK
OR
R1
V
O
V
IO
SDATA
Driver
SCLK
or
SDATA
CDC960
Figure 2. SCLK SDATA Connection to 5-V SMBus Using Clamping Diode to V
DD
Diode D1 in Figure 2 should have a small forward voltage (V ). Ideally, we want V to be less than 300 mV to
F
F
meet the input voltage requirement of the CDC960. International IOR Rectifier has a device (part number
10BQ015) with maximum V of 350 mV at 1.0 A. Using the 10BQ015 with R1 = 150 Ω, the worst-case I
calculated using equation (4).
is
F
OH
5.5 V * (3.0 * 0.35) V
I
+
+ 14 mA
OH
150 W
(4)
The calculation for equations (2) and (3) is the same as in part 1.
When using the configuration in Figure 2, the power supply is required to have a capability of sinking current.
The total amount of sinking current is dependent on the overall load connected to that power supply.
Using the above interface circuitry with a high-impedance source, the available high-level voltage on the SMBus
is limited to about (Vzk) for the configuration in Figure 1 and (VDD
Figure 2. One has to choose which option best fits a given SMBus configuration.
+ V
) for the configuration in
(CDC960)
F(D1)
Actually, the typical SMBus configuration is an open-drain configuration with pullup resistors to the
corresponding power supply. It does not require a 5-V SMBus driver that has a low impedance to drive the
CDC960 SMBus ports with its additional components as shown in Figure 1 and Figure 2. The external
components are not needed if the pullup resistors of the SMBus are directly connected to a voltage equal to
the supply voltage of the CDC960 (typically 3.3 V). This pullup resistor connection is strongly recommended.
7
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ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
power-up sequences
Sampled inputs are: FS0, FS1, FS2 and 24/48_SEL.
State S1 is an analog controlled delay derived from internal reference voltages to ensure that a valid input state
is captured. There is no specific delay in this state after power up.
Figure 3 shows the symbolic sequence of the CDC960 during power up. States S0–S4 are required to ensure
proper configuration and operation of the device functions.
Outputs Disabled
S2
S1
V
DD
≤ 2 V
Sample
Input Straps
Delay
Outputs
Undefined
Enable
Outputs
S0
S4
S3
V
DD
= Off
Power Up
Wait
3 ms
Normal
Operation
Power Off
Figure 3. Power-Up State Transitions
SMBus serial interface
The following section describes the SMBus interface programming.
In general the CDC960 SMBus protocol supports only block write and block read operations.
SMBus device address
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
0
0 = write to CDC960
1 = read from CDC960
writing to the SMBus interface
1. Send the address D2
and validate the acknowledge from the slave.
(H)
2. Send the dummy byte as a command code and validate the acknowledge from the slave.
3. Send the number of data bytes to write and validate the acknowledge from the slave.
4. Write the desired data bytes to registers and validate the acknowledge from the slave for each data byte.
Clock Generator
Addr (7 bits)
+8 bits dummy
command code
+8 bits byte
count
ACK
ACK
ACK
Data byte 0
ACK
Data byte N
ACK
A(6:0) & R/W
D2
(H)
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ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
SMBus serial interface (continued)
reading the SMBus interface, using address pre-phase
1. Send the address D2 and validate the acknowledge from the slave.
(H)
2. Send dummy byte as command code and validate the acknowledge from the slave.
3. Send repeated start condition followed by address D3 and validate the acknowledge from the slave.
(H)
4. The slave returns the number of bytes it is going to send (byte count) and validates the acknowledge from
the master.
5. Read back the desired data bytes and validate the acknowledge sent by the master for each data byte.
Clock
Generator
Addr
Clock
Generator
Addr
+8 bits
dummy
command
code
(7 bits)
(7 bits)
Repeated
Start
+8 bit byte ACK by
count master
Data
byte 0
ACK by
master
Data
byte N
ACK by
master
ACK
ACK
ACK
A(6:0)&
R/W
A(6:0)&
R/W
D2
(H)
D3
(H)
reading the SMBus interface, using direct read
1. Send the address D3 and validate the acknowledge from the slave.
(H)
2. The slave returns the number of bytes it is going to send (byte count) and validates the acknowledge from
the master.
3. Read back the desired data bytes and validate the acknowledge sent by the master for each data byte.
Clock
Generator
+8 bit byte
Addr (7 bits)
A(6:0)& R/W
ACK
ACK by master
Data byte 0
ACK by master
Data byte N
ACK by master
count
D3
(H)
9
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SCAS675 – APRIL 2002
SMBus configuration command bitmap
Byte 0: Frequency and Spread Spectrum Control Register (see Note 1)
(H = Enable, L = Disable)
PIN AFFECTED
SOURCE PIN
(READ
†
BIT TYPE
PUD
DESCRIPTION
(WRITE
OPERATION)
OPERATION)
Write disable (write once). A 1 written to this bit after a 1 has been written to
Byte0, Bit0 disables modification of all configuration registers until the de-
vice has been powered off.
7
6
R/W
R/W
L
—
—
Register value
Spread spectrum enable. This bit provides a software programmable con-
trol forspread spectrum clocking. The truth table for SSC is as follows:
Spread (ext. Pin)
Byte0, Bit6
SSC Function
Disabled
L
L
L
H
L
L
Register value
Enabled
H
H
Enabled
H
Enabled
5
4
R/W
R/W
L
L
FS4 (corresponds to frequency selection table)
FS3 (corresponds to frequency selection table)
—
—
Register value
Register value
Externally FS2 (corresponds to frequency selection table). If write is enabled, this bit
3
2
1
R/W
R/W
R/W
—
—
—
45 at power up
48 at power up
1 at power up
‡
selected
can be set differently than the power-up condition.
Externally FS1 (corresponds to frequency selection table). If write is enabled, this bit
‡
selected
can be set differently than the power-up condition.
Externally FS0 (corresponds to frequency selection table). If write is enabled, this bit
‡
selected
can be set differently than the power-up condition.
Write Enable. A 1 written to this bit after power up enables modification of all
configuration registers and subsequent 0s written to this bit disable modifi-
cation of all configuration registers except this single bit. Note that when a 1
has been written to Byte0, Bit 7, all modification is permanently disabled un-
til the device power cycles. Note also, that block write transactions to the
interface are completed. However, unless the interface has been previously
unlocked, the writes have no effect.
0
R/W
L
—
Register value
†
‡
PUD = Power-up condition
The value of this bit is according to level applied to corresponding device pin at power up.
NOTE 1: Byte0, Bit0 controls the write enable status for the device SMBus. If a 1 is written to Byte0, Bit0, the SMBus registers are write enabled.
Once write has been enabled, a new block write protocol must be sent to the device to program the desired register values. Once after
power up a 1 is written to Byte0, Bit0, the device functionality is according to the settings of the different registers. E.g., the device function
table is according to setting of Bits[1…6] of Byte0 and other functions are according to corresponding SMBus register settings.
If a 0 is written to Byte0, Bit0, write is disabled and the device function is according to the previous settings of the last write cycle.
Byte 1: PCI Clock Control Register
(H = Enable, L = Disable)
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
†
BIT
TYPE
PUD
DESCRIPTION
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
H
H
H
H
H
H
H
H
PCI/LDT1 enable
PCI/LDT0 enable
PCI5 enable
PCI4 enable
PCI3 enable
PCI2 enable
PCI1 enable
PCI0 enable
8
Register value
Register value
Register value
Register value
Register value
Register value
Register value
Register value
7
22
21
18
17
14
13
†
PUD = Power-up condition
10
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ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
SMBus configuration command bitmap (continued)
Byte 2: PCI Clock USB FDC and REF Control Register
(H = Enable, L = Disable)
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
†
BIT
TYPE
PUD
DESCRIPTION
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
H
H
H
H
H
H
H
H
CPU1 enable‡
CPU0 enable‡
36, 37
40, 41
45
Register value
Register value
Register value
Register value
Register value
Register value
Register value
Register value
REF2 enable
REF1 enable
48
REF0 enable
1
FDC (24_48 MHz) enable
USB enable
28
31
PCI/LDT2 enable
11
†
‡
PUD = Power-up condition
If a CPU clock is disabled by setting its control bit (bit 6 or bit 7) low, both the CPU and CPU outputs for the disabled clock are set low.
Byte 3: PCI Clock Free Running Control Register
(H = Free running, L = controlled by PCI_Stop/LDT_Stop))
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
†
BIT
TYPE
PUD
DESCRIPTION
§
§
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
L
L
L
L
L
L
L
L
PCI/LDT1 free-running enable
8
Register value
Register value
Register value
Register value
Register value
Register value
Register value
Register value
PCI/LDT0 free-running enable
7
§
§
§
§
§
§
PCI5 free-running enable
PCI4 free-running enable
PCI3 free-running enable
PCI2 free-running enable
PCI1 free-running enable
PCI0 free-running enable
22
21
18
17
14
13
†
§
PUD = Power-up condition
The above individual free-running enable/disable controls are intended to allow individual clock outputs to be made free running. A clock output
that has its free-running bit enabled (set to H) is not turned off with the assertion of either PCI_Stop or LDT_Stop. If a particular bit is disabled
in Byte1, the Byte1 settings overwrite the Byte3 settings.
11
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SCAS675 – APRIL 2002
SMBus configuration command bitmap (continued)
Byte 4: Pin Latched/Real Time State Control Register (see Note 2)
(H = Enable, L = Disable)
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
†
BIT
7
TYPE
R/W
R
PUD
DESCRIPTION
PCI_F enable
H
23
Register value
44
Externally
‡§
6
SPREAD actual pin state
selected
Externally
5
4
3
2
R
R
R
R
24/48_SEL pin power up latched state
PCI/LDT_SEL actual pin state
FS2 power-up latched pin state
FS1 power-up latched pin state
FS0 power-up latched pin state
28 at power up
6
‡
selected
Externally
‡§
selected
Externally
selected
45 at power up
48 at power up
‡
Externally
selected
‡
Externally
selected
1
0
R
1 at power up
Register value
‡
¶
R/W
L
PCI/LDT2 free-running enable
11
†
‡
§
PUD = Power-up condition
The value of this bit is determined by the level applied to the corresponding device pin at power up.
If the SMBus is in read mode, and the byte-count byte is being sent, the device input pin is sampled again at the falling edge of SCLK at the same
state as the acknowledge state for the byte count that is initiated by SCLK↓.
The above individual free running enable/disable controls are intended to allow individual clock outputs to be made free running. A clock output
that has its free-running bit enabled (set to H) is not turned off with the assertion of either PCI_Stop or LDT_Stop. If a particular bit is disabled
in Byte2, the Byte2 settings overwrite the Byte4 settings.
¶
NOTE 2: Byte4 holds the power-up information for pins latched at power up. In the case that an unintentional write has been made to these bits
of Byte4, the SMBus write is ignored; the bits always return the power-up latched value during an SMBus read operation.
This does not relate to the bits which hold the actual (current) pin state. Those bits can not be overwritten by software in order to get
the hardware setting states back via software.
Byte 5: Vendor Identification Register
(H = Enable, L = Disable)
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
†
BIT
TYPE
PUD
DESCRIPTION
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
H
H
H
L
Manufacturer ID (MSB)
Manufacturer ID
–
–
–
–
–
–
–
–
Returns H
Returns H
Returns H
Returns L
Returns L
Returns L
Returns L
Returns H
Manufacturer ID, TI is shown for vendor ID = 111
Device revision ID (MSB)
L
Device revision ID
L
Device revision ID
L
Device revision ID
H
Device revision ID, device revision: 00001
†
PUD = Power-up condition
12
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ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
SMBus configuration command bitmap (continued)
Byte 6: Byte Count Control Register
(H = Enable, L = Disable)
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
†
BIT
TYPE
PUD
DESCRIPTION
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
L
L
Byte count bit, MSB
Byte count bit
–
–
–
–
–
–
–
–
Register value
Register value
Register value
Register value
Register value
Register value
Register value
Register value
L
Byte count bit
L
Byte count bit
L
Byte count bit
H
H
H
Byte count bit
Byte count bit
Byte count bit, LSB
†
PUD = Power-up condition
Byte 7: Vendor Specific Register (reserved)
(H = Enable, L = Disable)
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
†
BIT
TYPE
PUD
DESCRIPTION
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R
L
L
L
L
L
L
L
L
Must be set to L during the byte write
Must be set to L during the byte write
Must be set to L during the byte write
Must be set to L during the byte write
Must be set to L during the byte write
Must be set to L during the byte write
Must be set to L during the byte write
Must be set to L during the byte write
–
–
–
–
–
–
–
–
Register value
Register value
Register value
Register value
Register value
Register value
Register value
Register value
R
†
PUD = Power-up condition
13
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ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
SMBus configuration command bitmap (continued)
Byte 8: Vendor Specific Register (reserved)
(H = Enable, L = Disable)
PIN AFFECTED
(WRITE OPERATION)
SOURCE PIN
(READ OPERATION)
†
BIT
TYPE
PUD
DESCRIPTION
Trigger single pulse at the L-to-H transition of this bit
after an SMBus write cycle completes. This bit must be
written back to L in order to trigger a following pulse with
a new L-to-H transition at the completion of a write
protocol.
7
R/W
L
CPU, CPU
Register value
Single-pulse ARM bit
H = enable, L = disable single-pulse feature
6
R/W
L
–
Register value
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
L
L
L
L
L
L
Must set to L during the byte write
Must set to L during the byte write
Must set to L during the byte write
Must set to L during the byte write
Must set to L during the byte write
Must set to L during the byte write
–
–
–
–
–
–
Register value
Register value
Register value
Register value
Register value
Register value
†
PUD = Power-up condition
Single-pulse initialization
1. Device is in normal operating mode (frequencies selected by FS[4:0] as usual).
2. Put device into SMBus mode (set write enable bit according to specification).
3. Put device into required operating mode via the SMBus.
4. Set Byte8/Bit6 to H. Byte8 is a TI control byte, Bit6 is the ARM bit.
a. The device continues running as in the normal operating mode, but the CPUx/CPUx outputs are pulled
to low/high, respectively; i.e., the clock is low.
b. All other clocks (PCI, LDT66, USB, 48-MHz, REFCLOCK) continue running as long as they are not
disabled by the SMBus or other means.
5. Set Byte8/Bit7 to H. Byte8/Bit 7 is the SHOOT bit.
a. The device recognizes a rising edge on this bit and sends a single high pulse on CPUx. The CPUx
output is complementary (low). The pulse duration depends on frequency settings for the CPU-BUS
(half of the period).
b. CPU1 or CPU0 can still be enabled/disabled via the SMBus as usual.
6. Set Byte8/Bit7 back to L for the next shot.
a. Because the device only detects L! H transitions, this bit must be reset to L.
7. Now the device is ready for the next pulse (write H to Byte8/Bit7).
8. When setting the ARM bit to L, the single-shot feature is disabled and the device runs as usual.
14
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ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
spread spectrum clock (SSC) implementation for CDC960
Simultaneously switching at a fixed frequency generates a significant power peak at the selected frequency,
which in turn causes an EMI disturbance to the environment. The purpose of the internal frequency modulation
of the CPU-PLL is to distribute the energy to many different frequencies, thus reducing the power peak.
A typical characteristic for a single-frequency spectrum and a modulated-frequency spectrum is shown in
Figure 4.
Maximum Peak
∆
Non-SSC
SSC
δ of f
nom
f
nom
Figure 4. Frequency Power Spectrum With and Without the Use of SSC
The modulated spectrum has its distribution to the left side of the single-frequency spectrum, which indicates
a down-spread modulation.
The peak reduction depends on the modulation scheme and modulation profile. System performance and timing
requirements are the limiting factors for actual design implementations. The implementation is driven to keep
the average clock frequency close to its upper specification limit. The modulation amount is set to –0.5%.
In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation
signal is limited in order to minimize SSC-induced tracking skew jitter.
15
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SCAS675 – APRIL 2002
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DD
Input voltage range, V (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
I
DD
Voltage range applied to any output in the high-impedance state or power-off state,
V (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
DD
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 × rated I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
O
OL
Input clamp current:
Output clamp current:
I
I
I
I
(V < 0)
IK
IK
I
. .
DD
(V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
OK
O
(V > V
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
DD
Package thermal impedance, θ (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Maximum power dissipation at T = 55°C (in still air) (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Operating free-air temperature range, T
Storage temperature range, T
JA
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0°C to 70°C
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
4. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,
°
which use a trace length of zero. The absolute maximum power dissipation allowed at T = 55 C (in still air) is 1.0 W.
A
5. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
OPERATING FACTOR
T = 70°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DL
1.3 W
10.7 mW/°C
0.85 W
‡
This is the inverse of the traditional junction-to-case thermal resistance (R
board-mounted device at 95°C/W.
) and uses a
θJA
16
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ꢀ ꢁꢀ ꢂꢃ ꢄ
ꢖ
ꢅ
ꢄ
ꢎ
ꢄ
ꢆ
ꢙ
ꢇ
ꢏ
ꢈ
ꢁ
ꢉ
ꢀ
ꢊ
ꢋ
ꢀ
ꢀ
ꢌ
ꢑ
ꢍ
ꢀ
ꢎ
ꢋ
ꢏ
ꢏ
ꢐ
ꢐ
ꢈ
ꢔ
ꢑ
ꢋ
ꢍ
ꢊ
ꢒ
ꢓ
ꢒ
ꢑ
ꢏ
ꢔ
ꢐ
ꢕꢁ
ꢔꢒ
ꢑ
ꢔ
ꢗ
ꢒ
ꢐ
ꢈ
ꢍ
ꢘꢔ
ꢑꢙ
ꢁ
ꢍ
ꢘ
ꢑ
ꢀ
ꢐꢔ
ꢚ
ꢇ
ꢀ
ꢙ
ꢘꢙ
ꢛ
ꢒ
ꢊ
ꢒ
ꢐ
ꢁ
ꢑ
ꢖ
ꢒ
ꢑ
ꢔꢜꢙ
ꢀꢑ
SCAS675 – APRIL 2002
recommended operating conditions (see Notes 4 and 5)
†
MIN
NOM
MAX
UNIT
Supply voltages, V
DD
3.3 V
3.135
3.465
V
PCI_Stop, LDT_Stop, PCI/LDT_SEL, 24/48_SEL, FS0, FS1,
FS2, SPREAD
2
V
DD
+0.3
High-level input voltage, V
IH
V
V
SDATA, SCLK (see Note 6)
XIN
2.0
2.0
V
V
+0.3
+0.3
DD
DD
PCI_Stop, LDT_Stop, PCI/LDT_SEL, 24/48_SEL, FS0, FS1,
FS2, SPREAD
−0.3
0.8
Low-level input voltage, V
IL
SDATA, SCLK (see Note 6)
XIN
−0.3
−0.3
1.08
0.5
PCI_Stop, LDT_Stop, PCI/LDT_SEL, 24/48_SEL, FS0, FS1,
FS2, SPREAD
−0.3
−0.3
V
V
+0.3
DD
Input Voltage, V
V
I
SDATA, SCLK (see Note 6)
CPU
+0.3
−18
−12
−12
18
9
DD
USB, FDC, REF
PCI, LDT
High-level output current, I
mA
OH
CPU
USB, FDC, REF
PCI, LDT
Low-level output current, I
mA
OL
9
SDATA
4
PCI_Stop, LDT_Stop, PCI/LDT_SEL, 24/48_SEL, FS0, FS1,
FS2, SPREAD
100
220
Input resistance to V
DD,
R
I
kΩ
SDATA, SCLK
100
0
220
200
16
‡
Reference frequency, f
PLL BY–PASS MODE
NORMAL MODE
MHz
MHz
kHz
µs
(XIN)
§
Crystal frequency, f
(XTAL)
10 14.31818
¶
SCLK frequency, f
100
(SCLK)
¶
Bus free time, t
(BUS)
4.7
4.7
4.0
4.7
4.0
¶
START setup time, t
µs
su(START)
¶
START hold time, t
µs
h(START)
¶
SCLK low pulse duration, t
w(SCLL)
µs
¶
SCLK high pulse duration, t
µs
w(SCLH)
¶
SDATA input rise time, t
r(SDATA)
1000
300
ns
¶
SDATA input fall time, t
f(SDATA)
ns
¶
SDATA setup time, t
su(SDATA)
250
5
ns
SDATA hold time, th(SDATA)
ns
¶
STOP setup time, t
su(STOP)
4
µs
Operating free–air temperature, T
0
70
°C
A
†
‡
All typical values are measured at their respective nominal V
.
DD
Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven
externally up to f = 0 MHz to 200 MHz. If XIN is driven externally, XOUT is floating.
(XIN)
§
¶
This is a fundamental crystal with f = 14.31818 MHz and 18 pF load in a parallel resonance application (Pierce-type oscillator)
O
This conforms to SMBus Specification, Version 1.1.
NOTES: 4. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,
°
which use a trace length of zero. The absolute maximum power dissipation allowed at T = 55 C (in still air) is 1.0 W.
A
°
5. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
6. The CMOS-level inputs fall within these limits: V min = 0.7 × V
IH DD
and V max = 0.3 × V .
IL DD
17
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ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
IK
V
V
= 3.135 V,
= 3.465 V,
I = –18 mA
–0.7
−1.2
V
DD
I
XIN
V = 2.0
I
2.5
DD
PCI/LDT_SEL, PCI_Stop,
LDT_Stop, SPREAD
V
= 3.465 V,
V = V
5
DD
I
DD
High-level input
current
I
IH
µA
FS0, FS1, FS2, 24/48_SEL
SDATA, SCLK
XIN
V
DD
V
DD
V
DD
= 3.465 V,
= 3.465 V,
= 3.465 V,
V = V
5
5
I
DD
V = V
I
DD
V = GND
I
−1.5
mA
PCI/LDT_SEL, PCI_Stop,
LDT_Stop, SPREAD
V
= 3.465 V,
V = GND
−50
DD
I
Low-level input
current
‡
I
IL
µA
FS0, FS1, FS2, 24/48_SEL
SDATA, SCLK
V
DD
V
DD
V
DD
V
DD
= 3.465 V,
= 3.465 V,
= 3.465 V,
= 3.465 V,
V = GND
I
–50
−50
±5
V = GND
I
I
I
High-impedance-state output current
V
= V
= V
or GND
µA
µA
OZ
O
O
DD
High-impedance-state output current, SDATA
V
5
OZ
DD
Static supply
All outputs open,
current
All outputs = low or high,
I
4.5
mA
DD
TEST MODE,
V
= 3.465 V
= 3.465 V
DD
DD
SSC = ON/OFF,
C
= MAX,
CPU = 166 MHz,
V
180
L
LDT = 66 MHz,
CPU outputs: TEST LOAD
All others loaded with
corresponding load
capacitance only.
Dynamic supply
current
I
mA
DD
CPU = 200 MHz,
V
DD
= 3.465 V
185
CPU =166 MHz/ 200 MHz,
= 3.465 V
All outputs disabled (LOW)
45
38
55
50
V
DD
High-impedance-
state supply
current
All outputs open, and out-
puts are in 3-state
I
CPU = 200 MHz,
V
DD
= 3.465 V
mA
DD(Z)
C
V = V
DD
or GND
2.3
29
15
2.7
31
pF
pF
pF
I
I
Input capacitance to GND
V
V
= 3.3 V
= 3.3 V,
XIN,
XOUT
DD
V = 1.5 V
I
27
C
Cryatal terminal capacitance (see Note 7)
V = 1.5 V
I
XTAL
DD
†
‡
All typical values are measured at their respective nominal V
DD.
I
IL
is caused by internal pullup resistors.
NOTE 7: This is the corresponding electrical capacitive load for the crystal in this oscillator application (Pierce-type oscillator). Parasitic pin-to-pin
capacitance = 2 pF.
18
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ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CPU (200/166/133/100 MHz)
†
PARAMETER
TEST CONDITIONS
MIN
– 0.1
TYP
MAX
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
= MIN to MAX,
= 3.135 V,
= MIN to MAX,
= 3.135 V,
= 3.465 V,
= 3.3 V,
I
I
I
I
= –1 mA
= –18 mA
= 1 mA
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OH
OL
OL
V
V
High-level output voltage
V
OH
2.3
0.05
0.6
Low-level output voltage
High-level output current
V
OL
= 18 mA
= 2.0 V
V
V
V
V
V
V
V
–43
–43
–14
32
O
O
O
O
O
O
O
= 1.65 V
= 2.735 V
= 0.8 V
–27
–56
I
mA
OH
= 3.135 V,
= 3.465 V,
= 3.3 V,
= 1.55 V
= 0.4 V
29
41
52
I
Low-level output current
mA
OL
= 3.135 V,
= 3.3 V,
17
C
Output capacitance
Output impedance
= V
DD
or GND
2.7
40
3.0
55
55
pF
O
High state
Low state
= 0.5 V
,
,
Z
V
/I
25
25
O
O
DD
O = O OH
Z
O
Ω
= 0.5 V
Z
V
/I
40
DD
O = O OL
†
All typical values are measured at their nominal V
DD
values.
REF (14.318 MHz)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
= MIN to MAX,
= 3.135 V,
= MIN to MAX,
= 3.135 V,
= 3.465 V,
= 3.3 V,
I
I
I
I
= –1 mA
= –12 mA
= 1 mA
V
DD
– 0.1
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OH
OL
OL
V
V
High-level output voltage
Low-level output voltage
V
OH
2.5
0.1
0.4
V
OL
= 9 mA
V
V
V
V
V
V
V
= 2.0 V
–46
–47
–15
33
O
O
O
O
O
O
O
= 1.65 V
= 2.735 V
= 0.8 V
–29
–61
I
High-level output current
Low-level output current
mA
OH
= 3.135 V,
= 3.465 V,
= 3.3 V,
= 1.65 V
= 0.4 V
30
42
52
I
mA
OL
= 3.135 V,
= 3.3 V,
17
C
Output capacitance
Output impedance
= V
DD
or GND
3.2
35
3.7
52
52
pF
O
High state
Low state
= 0.5 V
,
,
Z
V
/I
22
22
O
O
DD
O = O OH
Z
O
Ω
= 0.5 V
Z
V
/I
35
DD
O = O OL
†
All typical values are measured at their nominal V
DD
.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ
ꢅꢄ ꢄꢆꢇ ꢈꢉ ꢀ ꢊ ꢋꢀꢌ ꢍ ꢎꢏ ꢐꢈ ꢑꢍ ꢒ ꢓꢑ ꢔꢕ ꢁ ꢔꢒ ꢖ ꢑꢔ
ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
USB (48 MHz), FDC (24 MHz or 48 MHz)
†
PARAMETER
TEST CONDITIONS
MIN
– 0.1
TYP
MAX
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
= MIN to MAX,
= 3.135 V,
= MIN to MAX,
= 3.135 V,
= 3.465 V,
= 3.3 V,
I
I
I
I
= –1 mA
= –16 mA
= 1 mA
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OH
OL
OL
V
V
High-level output voltage
V
OH
2.4
0.1
0.4
Low-level output voltage
High-level output current
V
OL
= 9 mA
V
V
V
V
V
V
V
= 2.0 V
–46
–47
–15
33
O
O
O
O
O
O
O
= 1.65 V
= 2.735 V
= 0.8 V
–29
–61
I
mA
OH
= 3.135 V,
= 3.465 V,
= 3.3 V,
= 1.65 V
= 0.4 V
30
42
52
I
Low-level output current
mA
OL
= 3.135 V,
= 3.3 V,
17
C
Output capacitance
Output impedance
= V
DD
or GND
3.2
35
3.7
52
52
pF
O
High state
Low state
= 0.5 V
,
,
Z
V
/I
22
22
O
O
DD
O = O OH
Z
O
Ω
= 0.5 V
Z
V
/I
35
DD
O = O OL
†
All typical values are measured at their nominal V
DD
.
PCI, PCI_F (33 MHz) and LDT (33 MHz or 66 MHz)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
= MIN to MAX,
= 3.135 V,
= MIN to MAX,
= 3.135 V,
= 3.465 V,
= 3.3 V,
I
I
I
I
= –1 mA
= –12 mA
= 1 mA
V
DD
– 0.1
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
OH
OH
OL
OL
V
V
High-level output voltage
Low-level output voltage
V
OH
2.4
0.1
0.4
V
OL
= 9 mA
V
V
V
V
V
V
V
= 2.V
–71
–71
–23
38
O
O
O
O
O
O
O
= 1.65 V
= 2.735 V
= 0.8 V
–40
–97
I
High-level output current
Low-level output current
mA
OH
= 3.135 V,
= 3.465 V,
= 3.3 V,
= 1.65 V
= 0.4 V
37
71
100
I
mA
OL
= 3.135 V,
= 3.3 V,
19
C
Output capacitance
Output impedance
= V
DD
or GND
3.2
25
3.7
37
37
pF
O
High state
Low state
= 0.5 V
,
,
Z
V
/I
12
22
O
O
DD
O = O OH
Z
O
Ω
= 0.5 V
Z
V
/I
25
DD
O = O OL
†
All typical values are measured at their nominal V
DD
.
SDATA
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.2
Unit
V
V
V
V
V
= MIN to MAX,
= 3.135 V,
= 3.465 V,
= 3.3 V,
I
I
= 4 mA
= 6 mA
= 0.8 V
= 1.65 V
= 0.4 V
DD
DD
DD
DD
DD
OL
V
OL
Low-level output voltage, SDATA
V
0.4
OL
V
V
V
35
46
19
36
4.5
O
O
O
33
25
57
I
Low-level output current, SDATA
mA
OL
= 3.135 V,
Z
O
Output impedance, low state
0.5 V
DD
,
Z
V
/I
47
Ω
O = O OL
C
Input/output capacitance, SDATA
V
DD
= 3.3 V,
V = V
O DD
or GND
5.1
pF
I/O
†
All typical values are measured at their nominal V
DD
.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄ
ꢅ ꢄ ꢄ ꢆꢇꢈ ꢉ ꢀꢊ ꢋ ꢀꢌ ꢍꢎ ꢏꢐ ꢈꢑꢍꢒ ꢓ ꢑꢔ ꢕꢁ ꢔꢒ ꢖ ꢑ ꢔ
ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
switching characteristics, V
= MIN to MAX, T = 0°C to 70°C
DD
A
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
v
/v
Overshoot/undershoot
All clocks
±0.7
(over) (under)
f
= 33/66 MHz to disable
(PCI/LDT)
PCI/LDT in next cycle (PCI/LDT = low)
t
t
t
t
PCI_Stop↓ or LDT_Stop↓ to PCI_F↑
PCI_Stop↓ or LDT_Stop↓ to PCI_F↑
PCI_Stop↑ or LDT_Stop↑ to PCI_F↑
PCI_Stop↑ or LDT_Stop↑ to PCI_F↑
10
0
ns
ns
ns
ns
su(disable)
h(disable)
su(enable)
h(enable)
f
= 33/66 MHz to disable
(PCI/LDT)
PCI/LDT in next cycle (PCI/LDT = low)
f
= 33/66 MHz to enable PCI/LDT
(PCI/LDT)
in next cycle (PCI/LDT = high)
10
0
f
= 33/66 MHz to enable PCI/LDT
(PCI/LDT)
in next cycle (PCI/LDT = high)
SSC(midx)
SSC spread amount
f
f
= 100 MHz to 200 MHz
= 100 MHz to 200 MHz
–0.5
31.4
0.03
0.13
%
(CPU)
f
SSC modulation frequency
kHz
(mod)
stab
(CPU)
FS0, FS1, FS2 or SMBus update
After power up
3
3
†
t
Stabilization time
ms
†
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for
phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at XIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time from when V
DD
achieves its nominal operating level until the output frequency is stable and operating within specification.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ
ꢅꢄ ꢄꢆꢇ ꢈꢉ ꢀ ꢊ ꢋꢀꢌ ꢍ ꢎꢏ ꢐꢈ ꢑꢍ ꢒ ꢓꢑ ꢔꢕ ꢁ ꢔꢒ ꢖ ꢑꢔ
ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
switching characteristics, V
= 3.135 V to 3.465 V, T = 0°C to 70°C
A
DD
CPU, C = 10 pF, R = Test Load
L
L
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
Unit
t
t
Propagation delay time
Propagation delay time
XIN
CPUx
CPUx
f
≥ 1 MHz, TEST MODE
3.5
15
ns
ns
pd1
(XIN)
Test mode
SCLK ↑
18
pd2
f
f
f
f
f
f
= 100 MHz
10.0
7.5
6.0
5.0
10.1
7.60
6.08
5.1
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
(CPU)
= 133 MHz
†
t
t
CPU clock period
ns
c
= 166 MHz
= 200 MHz
Cycle to cycle jitter
Duty cycle
Synthesizer mode
= 100 to 200 MHz
= 100 to 200 MHz
160
53
ps
%
jit(cc)
odc
47
t
Accumulated jitter, SSC = ON, see Note 8
f(CPU) = 100 to 200 MHz
–150
150
70
ps
ps
jit(acc)
tsk(b)
CPU bank skew ↑ edges
CPUx
CPUx
PCIx
f = 100 to 200 MHz
(CPU)
CPU x-point to ↑ edges
Output skew window
time independent (3.3 V)
CPUx
CPUx
CPUx
CPUx
f
= 33.3 MHz
= 66.7 MHz
= 33.3 MHz
= 66.7 MHz
500
500
200
200
(PCI)
(LDT)
(PCI)
(LDT)
↑ CPU
200 MHz
LDTx
PCIx
LDTx
f
f
f
tsk
ps
(ow)
CPU x-point to ↑ edges
Output skew window
time variant skew
↑ CPU
200 MHz
100
2.5
300
8.0
ps
V/ns
t
t
Rise time
Fall time
r
Test load at the ac coupling
node including CPU load.
V
= 0V "400 mV
ref
differential measured
100
2.5
300
8.0
ps
V/ns
f
Edge rate rising edge
(maintained during total
transition)
Test load at the ac coupling
node including CPU load.
V
= 0V "400 mV
ref
differential measured
v
v
2.0
2.0
8.0
8.0
V/ns
V/ns
r
f
Edge rate falling edge
(maintained during total
transition)
Test load at ac coupling
node
†
All typical values are measured at their nominal V
DD
values.
NOTE 8: Accumulated jitter is the sum of individual consecutive cycle-to-cycle jitter reads added for a at least 32 µs (one SSC modulation period).
The limit corresponds to the w/c cumulative shortest and longest jitter number found during evaluation time.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄ
ꢅ ꢄ ꢄ ꢆꢇꢈ ꢉ ꢀꢊ ꢋ ꢀꢌ ꢍꢎ ꢏꢐ ꢈꢑꢍꢒ ꢓ ꢑꢔ ꢕꢁ ꢔꢒ ꢖ ꢑ ꢔ
ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
CPU C = 10 pF, R = Test Load (see Note 9) (continued)
L
L
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
Unit
Test load at ac
coupling node
VOD
Differential output voltage
CPU to CPU
1.3
1.7
V
including CPU load.
Change in dc differential output
voltage
∆V
CPU to CPU
CPU to CPU
CPU to CPU
–15
1.3
15
1.4
10
mV
V
OD_DC
V
OCM
Common mode voltage
Change in common mode
voltage
∆V
–10
mV
OCM
Common mode voltages (MIN/
MAX)
VCM_AC
CPU to CPU
1.0
1.0
1.4
1.2
V
V
Test load at ac
coupling node
including CPU load.
Absolute cross point voltages
crosspoint (low and high)
v
CPU and CPU
cross
∆v
Variation of V
cross
, rising edge
, all edges
At ↑ CPU(x…n), (max-min)
At ↑ or ↓ CPU(x…n),(max-min)
90
mV
mV
cross
T∆v
Total variation V
cross
140
cross
†
The average over any 1-µs period of time is greater than the minimum specified period
NOTES: 9. This specification does not include variations caused by K8 input resistor network or K8
voltage variations.
VDD
+V )/2. See the measurement information section for details.
The common mode voltage is calculated as: (V
10. This applies also to CPU outputs.
OH OL
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ
ꢅꢄ ꢄꢆꢇ ꢈꢉ ꢀ ꢊ ꢋꢀꢌ ꢍ ꢎꢏ ꢐꢈ ꢑꢍ ꢒ ꢓꢑ ꢔꢕ ꢁ ꢔꢒ ꢖ ꢑꢔ
ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
switching characteristics, V
= 3.135 V to 3.465 V, T = 0°C to 70°C (continued)
A
DD
USB, FDC (48 MHz) and FDC (24 MHz), C = 20 pF, (USB) R = 500 Ω
L
L
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
≥ 1 MHz, TEST MODE
(XIN)
MIN TYP
MAX
UNIT
t
t
Propagation delay time
XIN
USB/FDC
f
2
15
ns
ns
pd1
Propagation delay time
SCLK↑
USB/FDC TEST MODE
18
pd2
‡
USB/FDC (48 MHz) clock period
f
f
f
f
f
f
f
= 48 MHz
20.8
41.6
20.84
41.68
200
180
160
55
(USB/FDC)
t
c
ns
‡
FDC (24 MHz) clock period
= 24 MHz
(FDC)
Cycle to cycle jitter FDC (48 MHz) or FDC (24 MHz)
Cycle to cycle jitter USB (48 MHz), FDC=24 or 48 MHz
Accumulated jitter USB (48 MHz), FDC=24 or 48 MHz
Duty cycle USB/FDC
= 100 to 200 MHz
= 100 to 200 MHz
= 100 to 200 MHz
(CPU)
t
t
ps
ps
jit(cc)
(CPU)
–160
45
jit(acc)
(CPU)
= 48 MHz
(USB/FDC)
odc
%
Duty cycle FDC
= 24 MHz
45
55
(FDC)
USB to FDC skew ↑ edges
time-independent and
time-variant skew combined
f
f
= 48 MHz
500
500
(USB/FDC)
t
USB
FDC
ps
sk(ow)
= 48 / 24 MHz
= 48 MHz
(USB/FDC)
(USB/FDC)
USB/FDC pulse skew
FDC pulse skew
USB/FDC USB/FDC
f
f
f
f
f
f
2
2
6.5
6.5
t
t
t
t
t
ns
ns
ns
sk(p)
w(H)
w(L)
r
FDC
FDC
= 24 MHz
(FDC)
= 48 MHz
7.5
18
(USB/FDC)
Pulse duration, high
Pulse duration, low
Rise time
= 24 MHz
(FDC)
= 48 MHz
11.5
22
(USB/FDC)
= 24 MHz
(FDC)
USB
FDC
USB
FDC
USB
FDC
USB
FDC
1.1
2
2.5
0.7
ns
V/ns
V
= 20% to 80% of V
= 20% to 80% of V
= 20% to 60% of V
= 20% to 60% of V
ref
O
1.1
2
2.5
0.7
ns
V/ns
Fall time
V
ref
f
O
Edge rate, rising edge (maintained during total
transition)
v
V
0.25
0.25
1.1
1.1
V/ns
V/ns
r
ref
DD
DD
Edge rate falling edge (maintained during total
transition)
v
V
f
ref
†
‡
All typical values are measured at their nominal V
values.
The average over any 1-µs period of time is greater than the minimum specified period
DD
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄ
ꢅ ꢄ ꢄ ꢆꢇꢈ ꢉ ꢀꢊ ꢋ ꢀꢌ ꢍꢎ ꢏꢐ ꢈꢑꢍꢒ ꢓ ꢑꢔ ꢕꢁ ꢔꢒ ꢖ ꢑ ꢔ
ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
switching characteristics, V
= 3.135 V to 3.465 V, T = 0°C to 70°C (continued)
A
DD
PCI, LDT (33 MHz), PCI_F and LDT (66 MHz), C = 30 pF, R = 500 Ω
L
L
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
t
t
Propagation delay time
Propagation delay time
XIN
PCIx,LDT
f
≥ 1 MHz, Test mode
2.0
15
ns
ns
pd1
(XIN)
SCLK↑
PCIx, LDT Test mode
18
pd2
f
= 33.3 MHz
= 66.7MHz
29.95
14.95
30.3
15.15
170
290
300
55
(PCI)
(LDT)
†
t
PCI clock period
ns
ps
c
f
Cycle-to-cycle jitter PCI/LDT (33 MHz), LDT (33 MHz)
Cycle-to-cycle jitter LDT (66 MHz), PCI (33 MHz)
Accumulated jitter PCI/LDT (33 MHz), LDT (66 MHz)
Duty cycle PCI (33 MHz)
t
t
f
= 100 to 200 MHz
= 100 to 200 MHz
jit(cc)
(CPU)
f
f
f
–300
45
ps
%
%
jit(acc)
(CPU)
odc
= 33.3 MHz
= 66.7 MHz
(PCI)
(LDT)
t
dc
Duty cycle LDT (66MHz)
45
55
PCI bank skew ↑ edges
time-independent (3.3 V)
500
200
500
200
500
200
500
200
t
PCIx
PCIx
f
f
f
f
= 33.3 MHz
= 33.3 MHz
= 66.7 MHz
= 66.7 MHz
ps
ps
ps
ps
sk(b)
(PCI)
(PCI)
(LDT)
(LDT)
PCI bank skew ↑ edges
time-variant skew
↑ edges to CPU x-point
time-independent (3.3 V)
t
t
t
PCIn
LDTx
CPUx
LDTx
sk(ow)
↑ edges to CPU x-point
time-variant skew
LDT bank skew ↑ edges
time-independent (3.3 V)
sk(b)
LDT bank skew ↑ edges
time-variant skew
↑ edges to CPU x-point
time-independent (3.3 V)
LDTx
LDTx
CPUx
CPUx
sk(ow)
↑ edges to CPU x-point tim-
variant skew
†
‡
All typical values are measured at their nominal V
The average over any 1-µs period of time is greater than the minimum specified period
values.
DD
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ
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SCAS675 – APRIL 2002
PCI, LDT (33 MHz), PCI_F and LDT (66 MHz), C = 30 pF, R = 500 Ω (continued)
L
L
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
500
200
500
200
Unit
↑ edges to LDT time
independent (3.3 V)
PCIx
PCIx
PCIx
PCIx
LDTx
f
f
= 33.3 MHz
(PCI/LDT)
↑ edges to LDT time variant
skew
LDTx
LDTx
LDTx
t
ps
sk(ow)
↑ edges to LDT time
independent (3.3)
= 33.3 MHz/66.7 MHz
(PCI/LDT)
↑ edges to LDT time variant
skew
PCI pulse skew
PCIn
LDTn
PCIn
LDTn
f
f
f
f
f
f
= 33.3 MHz
1.5
1.4
3.7
3.6
(PCI)
(LDT)
(PCI)
(LDT)
(PCI)
(LDT)
t
t
ns
ns
ns
sk(p)
LDT pulse skew
= 66.7 MHz
Pulse duration, high PCI (33 MHz)
Pulse duration, high LDT (66 MHz)
Pulse duration, low PCI (33 MHz)
Pulse duration, low LDT (66 MHz)
= 33.3 MHz
= 66.7 MHz
= 33.3 MHz
= 66.7 MHz
13.6
6.2
w(H)
16.0
8.4
t
t
t
w(L)
0.7
2.9
1.6
1.2
ns
V/ns
Rise time PCI/LDT (33 MHz), LDT (66 MHz)
Fall time PCI/LDT (33 MHz), LDT (66 MHz)
V
= 20% to 80% of V
r
f
ref
O
O
0.6
3.5
1.6
1.2
ns
V/ns
V
= 20% to 80% of V
ref
v
v
0.3
0.4
1.7
1.7
r
f
Edge rate rising edge (maintained during total transition)
V
ref
= 20% to 60% of V
V/ns
DD
†
All typical values are measured at their nominal V
DD
values.
26
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SCAS675 – APRIL 2002
switching characteristics, V
= 3.135 V to 3.465 V, T = 0°C to 70°C (continued)
A
DD
REF, C = 20 pF, R = 500 Ω
L
L
FROM
(INPUT) (OUTPUT)
TO
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
t
t
t
t
t
t
Propagation delay time
Propagation delay time
XIN
REF
REF
f
≥ 1 MHz, TEST MODE
2
10.0
ns
ns
ns
ps
ps
ps
%
pd1
(XIN)
TEST MODE
SCLK↑
18
pd2
†
REF clock period
f
f
f
f
f
f
f
f
f
= 14.318 MHz
= 100 to 200 MHz
= 100 to 200 MHz
= 100 to 200 MHz
= 14.318 MHz
= 14.318 MHz
= 14.318 MHz
= 14.318 MHz
= 14.318 MHz
69.8
–200
45
69.84
250
200
300
55
c
(REF)
(CPU)
(CPU)
(CPU)
(REF)
(REF)
(REF)
(REF)
(REF)
Cycle to cycle jitter
Accumulated jitter
Phase jitter
jit(cc)
jit(acc)
jit(
)
odc
Duty cycle
t
t
t
t
REF bank skew ↑ edges
REF pulse skew
REFx
REF
REFx
REF
500
5.8
ps
ps
ns
ns
sk(b)
sk(p)
w(H)
w(L)
2
27
32
Pulse duration width, high
Pulse duration width, low
1.1
2
2.7
0.7
ns
V/ns
t
Rise time
Fall time
V
= 20% to 80% of Vo
r
f
ref
1.1
2
2.7
0.7
ns
V/ns
t
V
ref
= 20% to 80% of Vo
v
v
Edge rate rising edge (maintained during total transition)
Edge rate falling edge (maintained during total transition)
V
ref
= 20% to 60% of VDD
0.25
0.25
1.1
1.1
V/ns
V/ns
r
f
†
‡
All typical values are measured at their nominal V
values.
The average over any 1-µs period of time is greater than the minimum specified period
DD
SDATA, C = 10 pF to 400 pF, R = 1 kΩ
L
L
FROM
(INPUT)
TO
(OUTPUT)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
‡
‡
‡
t
t
t
Propagation delay time
Propagation delay time
Propagation delay time
SCLK↓
SCLK↓
SCLK↓
Data acknnowledge See Figure 6
0.375
0.375
0.375
2
2
µs
µs
µs
PHL
PLH
PHL
Data valid
Data valid
See Figure 6
See Figure 6
2
C
C
= 10 pF
86
250
250
L
L
t
f
Fall time
ns
= 400 pF
115
†
‡
All typical values are measured at their nominal V
This is a digital controlled delay. It equals to 6 REF clock cycles plus the internal gate delay (20 ns).
values.
DD
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ꢗ
ꢒ
ꢐ
ꢈ
ꢍ
ꢘ
ꢔ
ꢑ
ꢙ
ꢁ
ꢍ
ꢘꢑ
ꢀ
ꢐ
ꢔ
ꢚ
ꢇ
ꢀ
ꢙ
ꢘꢙ
ꢛ
ꢒ
ꢊ
ꢒ
ꢐ
ꢎ
ꢙ
ꢏ
ꢁ
ꢁ
ꢑ
ꢖ
ꢒ
ꢀ
ꢑ
ꢀ
ꢋ
ꢏ
ꢐ
ꢔ
ꢋ
ꢊ
ꢒ
ꢏ
ꢐꢑ
ꢔ
ꢜꢙ
ꢀ
ꢑ
SCAS675 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
R
= 500 Ω
V
L
S1
O_REF(OFF)
OPEN
From Output
Under Test
TEST
/t
S1
GND
t
t
t
Open
PLH PHL
C
L
R = 500 Ω
L
/t
V
PLZ PZL
/t
O_REF(OFF)
GND
(see Note A)
PHZ PZH
LOAD CIRCUIT for t and t
pd
sk
t
w
From Output
Under Test
Test
Point
3 V
V
V
V
IH_REF
T_REF
IL_REF
Input
C
L
0 V
(see Note A)
VOLTAGE WAVEFORMS
LOAD CIRCUIT FOR t and t
r
f
Output
Enable
(high-level
enabling)
V
3 V
0 V
DD
Input
V
V
T_REF
V
V
T_REF
T_REF
T_REF
0 V
t
PZL
t
t
PLH
PHL
V
t
PLZ
Output
Waveform 1
S1 at 6 V
≈3 V
V
V
OH
IH_REF
V
Output
V
T_REF
IL_REF
T_REF
V
+ 0.3 V
OL
(see Note B)
V
V
OL
V
OL
t
PZH
t
t
t
f
PHZ
r
Output
Waveform 2
S1 at GND
OH
t
V
OH
– 0.3 V
w_high
V
T_REF
t
w_low
(see Note B)
≈0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 14.318 MHz, Z = 50 Ω, t ≤ 2.5 ns,
C includes probe and jig capacitance. C = 10 pF (CPU), C = 20 pF (USB, FDC, REF), C = 30 pF (PCI, LDC)
L L L L
O
r
t ≤ 2.5 ns.
f
D. The outputs are measured one at a time with one transition per measurement.
PARAMETER
3.3-V INTERFACE
UNIT
V
V
V
V
High-level reference voltage
Low-level reference voltage
Input threshold reference voltage
Off-state reference voltage
2.4
0.4
1.5
6
V
V
V
V
IH_REF
IL_REF
T_REF
O_REF
Figure 5. Load Circuit and Voltage Waveforms
28
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ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
V
O
= 3.3 V
R
= 1 kΩ
L
DUT
C
C
= 10 pF or
= 400 pF
L
L
GND
TEST CIRCUIT
4 to N Bytes for Complete Device Programming
Start
Condition
(S)
Bit 0
Stop
Condition
(P)
Bit 7
MSB
Acknowledge
(A)
LSB
Bit 6
(R/W)
t
t
t
w(SCLL)
w(SCLH)
su(START)
0.7 V
0.3 V
CC
SCLOCK
t
CC
t
t
PHL
su(START)
r
t
PLH
t
t
f
(BUS)
0.7 V
CC
SDATA
0.3 V
CC
t
t
t
t
h(SDATA)
f(DATA)
t
su(STOP)
Stop Condition
r(SDATA)
t
su(SDATA)
h(START)
Start or
Repeat Start Condition
Repeat Start Condition
(see Note A)
VOLTAGE WAVEFORMS
NOTE A: The repeat start condition is supported, but not clock stretching.
BYTE
DESCRIPTION
1
SMBus address
2
3
Command (dummy value, ignored)
Byte count
4
SMBus data byte 0
SMBus data byte 1 – N
5 – N
Figure 6. Propagation Delay Times, t and t
r
f
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SCAS675 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
PCI_F
t
t
su
su
LDT or PCI_Stop
PCI or LDT
PCI/LDT_SEL
(High)
PCI_F
t
t
h
h
LDT or PCI_Stop
PCI or LDT
PCI/LDT_SEL
(High)
NOTE: Assertion and deassertion of PCI_STOP or LDT_STOP maintain signals duty cycle.
t
t
is the time at which no pulse exists in following period.
is the time at which a pulse exists in following period.
su(disable)
su(enable)
Figure 7. PCI_Stop or LDT_Stop ↓↑ to PCI (LDT)
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ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
V
T_REF
Bus Clock
Bus Clock
(n)
t
c
V
IH_REF
V
T_REF
(n+1)
V
IL_REF
t
t
t
w(h)
(sk_0)
w(l)
t
t
(high)
(low)
t
(sk_0)
t
(low or high)
+ Ťt
Ť
t
* t
Duty Cycle +
100
(sk_p)
w(l)
w(h)
t
c
Refer to Figure 4
Bus
Bus
Clock
Clock
V
(A)
(x)
T_REF
V
T_REF
(B)
(x)
t
t
= Bus
(B)
Clock – Bus
(x) (A)
Clock
(x)
(sk_0)
(sk_0)
a) Single-Ended Outputs
V
(cross_H)
(cross_L)
CPU Clock
(n)
V
t
t
(sk_b)
c
CPU Clock
(n+1)
t
t
t
w(h)
(sk_b)
w(l)
t
w(Low or High)
Duty Cycle =
x 100
t
c
V
V
(cross_H)
(cross_L)
CPU Clock
(x)
V
Bus
(B)
Clock
T_REF
(x)
t
t
= Bus
(B)
Clock – CPU Clock
(x)
(sk_0)
(sk_0)
(x)
b) Differential Ouput
Figure 8. Waveforms for Calculation of Skew and Offset
31
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ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
Bus Clock
(n)
V
T_REF
t
t
c(n+1)
c(n)
3
3
Cycle-to-Cycle Jitter
Mean Cycle Time
t
= | t
– t
|
n > 2 x 10
jit(cc)
c(n) c(n+1)
n
t
Σ
c(n)
t
=
n > 2 x 10
0
n = 1
n
a) Single-Ended Output
t
t
c(n+1)
c(n)
V
V
(cross_H)
(cross_L)
CPU Clock
(n)
t
t
t
w(n+2)
w(n)
w(n+1)
3
3
Cycle-to-Cycle Jitter
Mean Cycle Time
t
= | t
– t
|
n > 2 x 10
jit(cc)
c(n) c(n+1)
n
t
Σ
c(n)
t
=
0
n = 1
n > 2 x 10
n
b) Differential Output
Figure 9. Waveforms for Calculation of Jitter
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SCAS675 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
V
DD
= 2.5 V
V
DD
= 2.5 V
Differential Impedance = 100 Ω
250 Ω
1%
3900 pF
R
R
= 15 Ω
S1
S1
CPU
CDC960
CPU
TLA
TLB
TLC
TLD
TLD
250 Ω
1%
C
= 5 pF
= 5 pF
1%
L
NPO 10%
169 Ω
1%
200 Ω
1%
3900 pF
= 15 Ω
TLC
C
L
1%
200 Ω
NPO 10%
1%
Test Node
Clock
Test Node
Clock
R
= 50 Ω
R
= 50 Ω
T2
T1
TLA = TLB: Z = 60 Ω, L = 12.7 cm (750 ps)
O
TLC: Z = 60 Ω, L = 1.27 cm (75 ps)
O
TLD: Z = 60 Ω, L = ~3.43 cm (~180 ps)
O
Figure 10. Load Circuit and Voltage Waveforms for CPU Bus
correction for measurements at 50 Ω nodes
Voltage levels and readings are scaled for the voltage divider 200 Ω to 50 Ω versus all reads and reference levels
must be multiplied/divided by the fixed scale of five.
t
sk(ow2)
t
sk(ow1)
t
sk(ow5)
Bank1
t
sk(ow3)
1
Bank2
Bank2
2
Bank2
3
Bank2
4
t
sk(ow4)
5
Bank2
6
Bank2
t
sk(ow6)
MIN to MAX Output Skew
Figure 11. Bank and Output Skew; t
: Output Skew Window and MIN-to-MAX Phase
sk(owx)
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ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
The common mode voltage is measured single-ended and is the result of the following calculation:
Vocm = [Vo(CPUT) + Vo(CPUC) ]/2
(t)
(t)
(t)
t
w(h)
t
w(l)
Avg.
Avg.
CPUx
CPUx
V
cm(Max)
V
cm(Min)
0 V (GND)
V
cm0
V
cm1
45%
of
45%
of
t
t
w(h)
w(l)
75%
of
75%
of
t
t
w(h)
w(l)
V
is calculated from the average of Vocm within 45%–75% (region without switching noise) of the pulse while CPUx is in the
cm0
LOW state.
is calculated from the average of Vocm within 45%–75% (region without switching noise) of the pulse while CPUx is in the
V
cm1
HIGH state.
= (V
V
+ V )/2
cm1
– V
cm0 cm1
ocm
∆V
cm0
= V
ocm
a) Static
t
w(h)
t
w(l)
CPUx
CPUx
V
cm(Max)
V
cm(Min)
0 V (GND)
V
cm0
V
cm1
t = 0 to t
w(l)
t = 0 to t
w(h)
∆V
ocm(t)
= MAX (V
) – MIN (V
) and
cm1(t)
)
cm1(t)
cm0(t)
∆V
ocm(t)
= MIN (V
) – MAX (V
cm0(t)
b) Dynamic
Figure 12. Common Mode Voltage
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄ
ꢅ ꢄ ꢄ ꢆꢇꢈ ꢉ ꢀꢊ ꢋ ꢀꢌ ꢍꢎ ꢏꢐ ꢈꢑꢍꢒ ꢓ ꢑꢔ ꢕꢁ ꢔꢒ ꢖ ꢑ ꢔ
ꢗ ꢒ ꢐꢈ ꢍ ꢘꢔ ꢑꢙ ꢁ ꢍ ꢘꢑ ꢀ ꢐꢔ ꢚꢇ ꢀꢙꢘꢙꢛꢒ ꢊ ꢒꢐ ꢎ ꢙꢏꢁ ꢁꢑ ꢖꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙ ꢀꢑ
SCAS675 – APRIL 2002
PARAMETER MEASUREMENT INFORMATION
The differential voltage is measured single-ended and is the result of the following calculation:
Vod = Vo(CPUx) – Vo(CPUx)
(t)
(t)
(t)
t
w(h)
t
w(l)
CPUx
CPUx
V
o(Max)
V
dif
V
o(Min)
0 V (GND)
Avg.
Avg.
|V
dif(Max)
|
|
|V
dif
|
|V
dif(Min)
0 V (GND)
V
od_0
V
od_1
45%
of
45%
of
t
t
w(h)
w(l)
75%
75%
of
of
t
t
w(h)
w(l)
Vod_0 is calculated from the average of Vod within 45%–75% (region without switching noise) of the pulse while CPUx is in the
LOW state.
Vod_1 is calculated from the average of Vod within 45%–75% (region without switching noise) of the pulse while CPUx is in the
HIGH state.
Vod = (Vod_0 + Vod_1/2
∆Vod_DC = Vod_0 – Vod_1
∆Vod_AC = |Vdif(max0| – |Vdif(min)|
Figure 13. Differential Output Voltage
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ
ꢅꢄ ꢄꢆꢇ ꢈꢉ ꢀ ꢊ ꢋꢀꢌ ꢍ ꢎꢏ ꢐꢈ ꢑꢍ ꢒ ꢓꢑ ꢔꢕ ꢁ ꢔꢒ ꢖ ꢑꢔ
ꢗꢒ ꢐ ꢈ ꢍꢘ ꢔꢑ ꢙ ꢁ ꢍ ꢘꢑ ꢀꢐ ꢔꢚ ꢇ ꢀꢙ ꢘꢙꢛ ꢒ ꢊꢒ ꢐ ꢎ ꢙꢏꢁ ꢁꢑꢖ ꢒꢀ ꢑ ꢀꢋ ꢏꢐ ꢔꢋ ꢊ ꢒꢏ ꢐꢑ ꢔꢜꢙꢀꢑ
SCAS675 – APRIL 2002
MECHANICAL DATA
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.005 (0,13)
M
0.008 (0,203)
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SSOP
SSOP
Drawing
CDC960DL
ACTIVE
ACTIVE
DL
48
48
25
None
None
Call TI
Call TI
Level-1-220C-UNLIM
Level-1-220C-UNLIM
CDC960DLR
DL
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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