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CDCE6214

SNAS811 –JULY 2020

CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs,

Two Inputs, and Internal EEPROM

1 Features

–

Integrated EEPROM with two pages and

external select pin. In-situ programming

allowed.

1

•

Configurable high performance, low-power, frac-N

PLL with RMS jitter with spurs (12 kHz – 20 MHz,

F_out> 100 MHz) as:

•

Supports 100-Ω systems

Low electromagnetic emissions

Small footprint: 24-pin VQFN (4 mm × 4 mm)

–

Integer mode:

–

Differential output: 350 fs typical, 600 fs

maximum

2 Applications

–

LVCMOS output: 1.05 ps typical, 1.5 ps

maximum

•

PCIe Gen 1 - Gen 5 clocking

Data Center & Enterprise Computing, PC &

Notebook

Fractional mode:

–

Differential output: 1.7 ps typical, 2.1 ps

maximum

•

Enterprise Machine - Multi-Function Printer

Test & Measurement, Handheld Equipment

–

LVCMOS output: 2.0 ps typical, 4.0 ps

maximum

3 Description

•

Supports PCIe Gen1/2/3/4 with SSC and Gen

1/2/3/4/5 without SSC

The CDCE6214 is a four-channel, ultra-low power,

medium grade jitter, clock generator that can

generate five independent clock outputs selectable

between various modes of drivers. The input source

could be a single-ended or differential input clock

source, or a crystal. The CDCE6214 features a frac-N

PLL to synthesize unrelated base frequency from any

input frequency. The CDCE6214 can be configured

through the I²C interface. In the absence of the serial

interface, the GPIO pins can be used in Pin Mode to

configure the product into distinctive configurations.

•

2.335-GHz to 2.625-GHz internal VCO

Typical power consumption: 65 mA for 4-output

channel, 23 mA for 1-output channel.

•

Universal clock input, two reference inputs for

redundancy

–

Differential AC-coupled or LVCMOS: 10 MHz

to 200 MHz

–

Crystal: 10 MHz to 50 MHz

Flexible output clock distribution

Device Information⁽¹⁾

–

4 channel dividers: Up to 5 unique output

frequencies from 24 kHz to 328.125 MHz

PART NUMBER

PACKAGE

BODY SIZE (NOM)

CDCE6214

VQFN (24)

4.00 mm × 4.00 mm

Combination of LVDS-like, LP-HCSL or

LVCMOS outputs on OUT0 – OUT4 pins

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Glitchless output divider switching and output

channel synchronization

Application Example CDCE6214

Individual output enable through GPIO and

register

Voltage Domain

1.8V / 2.5V / 3.3V

FPGA

•

Frequency margining options

–

DCO mode: frequency increment/decrement

with 10ppb or less step-size

Crystal

D_DA_AC_C

Voltage Domain

1.8V / 2.5V / 3.3V

CDCE6214

•

Fully-integrated, configurable loop bandwidth: 100

kHz to 1.6 MHz

MCU

Single or mixed supply for level translation: 1.8

V/2.5 V/3.3 V

Ethernet

LVCMOS

Crystal Copy

PCIe

Voltage Domain

1.8V / 2.5V / 3.3V

Configurable GPIOs and flexible configuration

options

–

I²C-compatible interface: up to 400 kHz

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

CDCE6214

SNAS811 –JULY 2020

www.ti.com

Table of Contents

7.25 Typical Characteristics.......................................... 12

Parameter Measurement Information ................ 14

8.1 Reference Inputs..................................................... 14

8.2 Outputs.................................................................... 14

8.3 Serial Interface........................................................ 15

8.4 PSNR Test .............................................................. 15

8.5 Clock Interfacing and Termination .......................... 16

Detailed Description ............................................ 18

9.1 Overview ................................................................. 18

9.2 Functional Block Diagram ....................................... 18

9.3 Feature Description................................................. 18

9.4 Device Functional Modes........................................ 30

9.5 Programming........................................................... 30

1

2

3

4

5

6

7

Features.................................................................. 1

8

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (cont.) ................................................. 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 EEPROM Characteristics.......................................... 6

7.6 Reference Input, Single-Ended Characteristics........ 6

7.7 Reference Input, Differential Characteristics ............ 6

7.8 Reference Input, Crystal Mode Characteristics ........ 6

7.9 General-Purpose Input Characteristics..................... 6

7.10 Triple Level Input Characteristics............................ 7

7.11 Logic Output Characteristics................................... 7

7.12 Phase Locked Loop Characteristics ....................... 7

7.13 Closed-Loop Output Jitter Characteristics .............. 7

7.14 Input and Output Isolation....................................... 8

7.15 Buffer Mode Characteristics.................................... 8

7.16 PCIe Spread Spectrum Generator.......................... 8

7.17 LVCMOS Output Characteristics ............................ 9

7.18 LP-HCSL Output Characteristics ............................ 9

7.19 LVDS Output Characteristics ................................ 10

7.20 Output Synchronization Characteristics................ 10

7.21 Power-On Reset Characteristics........................... 10

7.22 I²C-Compatible Serial Interface Characteristics.... 10

9

10 Application and Implementation........................ 38

10.1 Application Information.......................................... 38

10.2 Typical Application ............................................... 39

11 Power Supply Recommendations ..................... 40

11.1 Power-Up Sequence............................................. 40

11.2 Decoupling ............................................................ 40

12 Layout................................................................... 41

12.1 Layout Guidelines ................................................. 41

12.2 Layout Examples................................................... 41

13 Device and Documentation Support ................. 43

13.1 Device Support .................................................... 43

13.2 Receiving Notification of Documentation Updates 43

13.3 Support Resources ............................................... 43

13.4 Trademarks........................................................... 43

13.5 Electrostatic Discharge Caution............................ 43

13.6 Glossary................................................................ 43

7.23 Timing Requirements, I²C-Compatible Serial

Interface ................................................................... 11

14 Mechanical, Packaging, and Orderable

Information ........................................................... 43

7.24 Power Supply Characteristics ............................... 11

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

July 2020

*

Initial release.

2

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5 Description (cont.)

On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device

provides frequency margining options with glitch-free operation to support system design verification tests (DVT)

and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by

steering the fractional feedback divider in DCO mode.

Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and

complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V,

or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.

The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small

footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-

on clocking device with a low power consumption.

6 Pin Configuration and Functions

CDCE6214 RGE Package

24-Pin VQFN

Top View

SECREF_P

SECREF_N

VDD_REF

REFSEL

1

2

3

4

5

6

18

17

16

15

14

13

OUT2_P

OUT2_N

VDDO_12

VDDO_34

OUT3_P

OUT3_N

DAP

PRIREF_P

PRIREF_N

Not to scale

(1) (2) (3) (4) (5)

Pin Functions

I/O

DESCRIPTION

NAME

NO.

POWER

Die Attach Pad. The DAP is an electrical connection and provides a thermal dissipation path.

For proper electrical and thermal performance of the device, the DAP must be connected to

PCB ground plane.

DAP

—

G

VDD_REF

VDD_VCO

3

P

1.8 V/2.5 V/3.3 V Power Supply for Reference Input and Digital.

1.8 V/2.5 V/3.3 V Power Supply for PLL/VCO.

24

(1) G = Ground, P = Power

(2) I = Input, I/O = Input/Output, O = Output

(3) I, R_PUPD= Input with Resistive Pull-up and Pull-down

(4) I, R_PU= Input with Resistive Pull=up

(5) I/O, R_PU= Input/Output with resistive pull-up

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(1) (2) (3) (4)

Pin Functions

⁽⁵⁾(continued)

NAME

I/O

DESCRIPTION

NO.

16

VDDO_12

P

1.8 V/2.5 V/3.3 V Power Supply for OUT1 and OUT2 channels

VDDO_34

15

1.8 V/2.5 V/3.3 V Power Supply for OUT0, OUT3, and OUT4 channels

INPUT BLOCK

HW_SW_CT

RL

Manual selection pin for EEPROM pages (3-state). Weak Pullup/Pulldown. R_PU= 50 kΩ. R_PD

= 50 kΩ.

23

5

I, R_PUPD

I

PRIREF_P

Primary reference clock. Accepts a differential or single-ended input. Input pins need AC-

coupling capacitors and internally biased in differential mode. For LVCMOS, input should be

provided on PRIREF_P and the non-driven input pin should be pulled down to ground.

Internal biasing for differential mode is disabled in single-ended mode.

PRIREF_N

6

I

Manual selection pin of reference input (3-state). Weak Pullup/Pulldown. R_PU= 50 kΩ. R_PD

50 kΩ.

=

REFSEL

4

1

I, R_PUPD

I

SECREF_P

Secondary reference clock. Accepts a differential or single-ended input or XTAL. Input pins

need AC-coupling capacitors and internally biased in differential mode. For XTAL input,

connect crystal between SECREF_P and SECREF_N pin. SECREF_P is XOUT, SECREF_N

is XIN. This device do not need any power limiting resistor on XOUT. For LVCMOS input,

input should be provided on SECREF_P, and the non-driven input pin should be pulled down

to ground. Internal biasing for differential mode is disabled in single-ended and XTAL mode.

SECREF_N

2

I

OUTPUT BLOCK

OUT0

LVCMOS Output 0. Reference Input can be bypassed into this output. Output slew-rate

configurable on all LVCMOS outputs.

7

O

OUT1_P

OUT1_N

OUT2_P

OUT2_N

OUT3_P

OUT3_N

OUT4_P

OUT4_N

22

21

18

17

14

13

10

9

O

LVDS-like/LP-HCSL/LVCMOS Output Pair 1. Programmable driver with LVDS-like/LP-HCSL

or 2x LVCMOS outputs.

LVDS-like/LP-HCSL Output Pair 2. Programmable driver with LVDS-like/LP-HCSL outputs.

LVDS-like/LP-HCSL Output Pair 3. Programmable driver with LVDS-like/LP-HCSL outputs.

LVDS-like/LP-HCSL/LVCMOS Output Pair 4. Programmable driver with LVDS-like/LP-HCSL

or 2x LVCMOS outputs.

DIGITAL CONTROL / INTERFACES

STATUS output or GPIO1 input. Weak pullup resistor when configured as Input. R_PU= 50

kΩ. Pullup resistor disabled in output mode.

GPIO1

GPIO4

PDN

20

11

8

I/O, R_PU

I, R_PU

STATUS output or GPIO4 input. Weak pullup resistor when configured as Input. R_PU= 50

kΩ. Pullup resistor disabled in output mode.

Device Power-down/RESET (active low) or SYNCN. Weak pullup resistor. R_PU= 50 kΩ.

Pullup resistor disabled in output mode.

I²C Serial Data (bidirectional, open-drain) or GPIO2 input. Requires an external pullup

resistor to VDD_REF in I²C mode. I²C slave address is initialized from on-chip EEPROM.

Fail-safe Input.

I²C Serial Clock or GPIO3 input. Requires an external pullup resistor to VDD_REF in I²C

mode. Fail-safe Input.

SDA/GPIO2

SCL/GPIO3

19

12

I/O

I

4

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

VDD_REF, VDD_VCO, VDDO_12, VDDO_34

PRIREF_P, PRIREF_N, SECREF_P, SECREF_N

Supply Voltage

Input Voltage

-0.3

3.63

V

VDD_REF +

0.3

-0.3

V

GPIO1, SDA/GPIO2, SCL/GPIO3, GPIO4, REFSEL, HW_SW_CTRL,

PDN

VDD_REF +

0.3

VDDO_X⁽²⁾

+

Input Voltage

OUT0, OUT1_P, OUT1_N, OUT2_P, OUT2_N, OUT3_P, OUT3_N,

OUT4_P, OUT4_N⁽²⁾

Output Voltage

0.3

125

150

T_J

Junction Temperature

Storage temperature

ºC

T_stg

-65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) VDDO_X refers to the output supply for a specific output channel, where X denotes the channel index.

7.2 ESD Ratings

VALUE

2000

750

UNIT

V

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VDD_VCO

Core supply voltage

Output supply voltage

1.71

1.8, 2.5, 3.3

3.465

V

VDDO_12,

VDDO_34

1.71

1.8, 2.5, 3.3

3.465

V

VDD_REF

T_A

Reference supply voltage

1.71

-40

3.465

105

125

145

30

V

Ambient temperature

ºC

ms

T_J

Junction temperature

-40

T_LOCK

t_RAMP

Continuous lock over temperature (without VCO calibration)

Maximum supply voltage ramp time⁽¹⁾

0.1

(1) VDD pin should monotonically reach 95% of its final value within supply ramp time. All VDD pins were tied together for this evaluation.

For non-monotonic or slower power supply ramp, it is recommended to pull-down PDN pin until VDD pins have reached 95% of its final

value. PDN pin has a 50 kΩ pullup resistor. When PDN pin cannot be actively controlled, TI recommends to add a capacitor to GND on

PDN pin to delay the release of reset.

7.4 Thermal Information

CDCE6214-Q1

THERMAL METRIC⁽¹⁾

RGE (VQFN)

24 PINS

32.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

R_θJC(bot)

ψ_JT

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

32.5

12.2

Junction-to-case (bottom) thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

2.0

0.4

ψ_JB

12.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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7.5 EEPROM Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

cycles

years

n_EEcyc

t_EEret

EEPROM programming cycles

EEPROM data retention

each word

10

7.6 Reference Input, Single-Ended Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_{IN_Ref}

V_IH

Reference frequency

10

200

MHz

0.8 ×

VDD_REF

Input high voltage

Input low voltage

LVCMOS Input Buffer

V

0.2 ×

VDD_REF

V_IL

LVCMOS Input Buffer

20% - 80%

dV_IN/dT

IDC

Input slew rate

1

40

V/ns

%

Input duty cycle

60

100

5

I_{IN_LEAKAGE}

C_{IN_REF}

Input leakage current

Input capacitance

-100

µA

pF

at 25°C

7.7 Reference Input, Differential Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_{IN_Ref}

Reference frequency

10

200

MHz

Differential input voltage swing, peak-to-

peak

V_{IN_DIFF}

VDD_REF = 2.5 V/3.3 V

0.4

1.6

1.0

V

Differential input voltage swing, peak-to-

peak

V_{IN_DIFF}

VDD_REF = 1.8 V

20% - 80%

dV_IN/dT

IDC

Input slew rate

1

40

V/ns

%

Input duty cycle

60

I_{IN_LEAKAGE}

C_{IN_REF}

Input leakage current

Input capacitance

-100

100

µA

pF

at 25°C

5

7.8 Reference Input, Crystal Mode Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

Ω

f_{IN_Xtal}

Z_ESR

Crystal frequency

Fundamental mode

10

50

Crystal equivalent series resistance

f_XTAL= 10 MHz to 16 MHz

f_XTAL= 16 MHz to 30 MHz

f_XTAL= 30 MHz to 50 MHz

60

50

Ω

30

Ω

Using on-chip load capacitance. A

supported Crystal is within

C_L

Crystal load capacitance

5

3

12.8

pF

P_XTAL

Crystal tolerated drive power

On-Chip load capacitance

A supported crystal tolerates up to

Programmable in typ. 200 fF steps

200

9.1

µW

pF

C_{XIN_LOAD}

(1) For detailed application report on configuring the XTAL Input, please refer to SNAA331: CDCI6214 and CDCE6214-Q1 design with

crystal input.

7.9 General-Purpose Input Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.8 ×

VDD_REF

V_IH

Input high voltage

V

0.2 ×

VDD_REF

V_IL

I_IH

Input low voltage

V

Input high level current

V_IH= VDD_REF, GPIO[1:4], PDN

-5

5

µA

6

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General-Purpose Input Characteristics (continued)

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

Input low level current

Input slew rate

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µA

I_IL

V_IL= GND, GPIO[2:3]

-5

5

I_IL

V_IL= GND, GPIO[1], GPIO[4], PDN

20% - 80%

-100

0.5

100

µA

dV_IN/dT

V/ns

T_{PULSE_WIDT}

Pulse width for correct operation

10

30

ns

H

R_PU

C_IN

Pullup Resistance

Pin Capacitance

Pins PDN, GPIO[1], GPIO[4]

55

80

10

kΩ

pF

7.10 Triple Level Input Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.8 ×

VDD_REF

V_IH

V_IM

V_IL

Input high voltage

V

0.41 ×

VDD_REF

0.5 ×

VDD_REF

0.58 ×

VDD_REF

Input mid voltage

Input low voltage

Float pin

V

0.2 ×

VDD_REF

I_IH

I_IL

Input high level current

Input low level current

V_IH= VDD_REF

V_IL= GND

20

50

100

-20

µA

-100

-50

7.11 Logic Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.8 ×

VDD_REF

VOH

VOL

Output high voltage

V

0.2 ×

VDD_REF

Output low voltage

V

7.12 Phase Locked Loop Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

f_PFD

Phase Detector Frequency

Integer and Fractional PLL mode

1

100

f_VCO

f_BW

Voltage Controlled Oscillator Frequency

Configurable closed-loop PLL Bandwidth

Voltage-Controlled Oscillator Gain

2335

100

2625

1600

MHz

REF = 25 MHz

f_VCO= 2.4 GHz

f_VCO= 2.5 GHz

kHz

K_VCO

140

175

MHz/V

Allowable Temperature Drift for

Continuous Lock⁽¹⁾

^oC

|ΔT_CL

|

dT/dt ≤ 20 K / min

145

0.1

f_MAX-ERROR

Maximum frequency error with frac-N PLL

ppm

(1) The maximum allowable temperature drift for continuous lock: how far the temperature can drift in either direction from the value it was

at the time, when the On-Chip VCO was calibrated while the PLL stays in lock throughout the temperature drift. The internal VCO

calibration takes place: at device start-up, when the device is reset using the RESET pin and when REGISTER bit is changed. This

implies the device will work over the entire frequency range, but if the temperature drifts more than the 'maximum allowable temperature

drift for continuous lock', then it is necessary to re-calibrate the VCO, using the appropriate REGISTER bit, to ensure the PLL stays in

lock. Regardless of what temperature the part was initially calibrated at, the temperature can never drift outside the ambient temperature

range of -40° C to 105° C.

7.13 Closed-Loop Output Jitter Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RMS jitter with spurs from 12 kHz to 20

MHz , Input Crystal = 25 MHz, Differential

OUTx > 100 MHz, int-PLL

t_{RJ_CL}

RMS Phase Jitter

350

600

fs

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Closed-Loop Output Jitter Characteristics (continued)

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RMS jitter with spurs from 12 kHz to 20

MHz, Input Crystal = 25 MHz, Differential

OUTx > 100 MHz, frac-PLL

t_{RJ_CL}

RMS Phase Jitter⁽¹⁾

1600

2100

fs

PCIe Gen 3 Filter applied, XIN = Crystal

25 MHz, OUTx = 100 MHz, frac-N PLL

with and without SSC, LP-HCSL or LVDS

output

t_{RJ_CL, PCIE}

RMS Phase Jitter

475

1000

fs

(1) F_IN= 25MHz, F_OUT= 161.1328MHz, F_PFD= 25MHz, RMS Noise = 1.83ps. F_IN= 25MHz, F_OUT= 161.1328MHz, F_PFD= 50MHz, RMS

Noise = 1.33ps. F_IN= 25MHz, F_OUT= 148.5MHz, F_PFD= 25MHz, RMS Noise = 1.74ps. F_IN= 25MHz, F_OUT= 148.5MHz, F_PFD= 50MHz,

RMS Noise = 1.43ps. F_IN= 25MHz, F_OUT= 148.3516MHz, F_PFD= 25MHz, RMS Noise = 1.6ps. F_IN= 25MHz, F_OUT= 148.3516MHz,

F_PFD= 50MHz, RMS Noise = 1.5ps. F_IN= 25MHz, F_OUT= 106.5MHz, F_PFD= 25MHz, RMS Noise = 0.8ps. F_IN= 25MHz, F_OUT

=

106.5MHz, F_PFD= 50MHz, RMS Noise = 1.3ps.

7.14 Input and Output Isolation

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Crosstalk between reference inputs,

PRIREF = 27MHz LVCMOS, SECREF =

25MHz XTAL

P_ISOLATION

Reference input isolation

-64

dB

Crosstalk between reference inputs,

PRIREF = 100MHz LVDS, SECREF =

25MHz LVCMOS

Reference input isolation

Clock output isolation

-72

-65

-42

dB

Crosstalk between clock outputs, OUT1 =

100MHz LP-HCSL, OUT2 = 156.25MHz

LVDS, PFD = 25MHz, int-PLL

Crosstalk between clock outputs, OUT1 =

156.25MHz LVDS, OUT0 = 25MHz

LVCMOS

7.15 Buffer Mode Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

int. Range from 10 kHz to 20 MHz , REF

t_{RJ_ADD}

Additive RMS Phase Jitter, System Level = HCSL 100 MHz with 0.5 V/ns, OUTx =

100 MHz LP-HCSL

350

fs

t_PROP,

REF = LVCMOS 25 MHz, OUTx = 25

Input-to-output propagation delay

MHz LVCMOS

1

ns

LVCMOS

t_PROP,

REF = AC-LVDS 100 MHz, OUTx = 100

Input-to-output propagation delay⁽¹⁾

2.3

MHz. Measured on OUT0

Differential

ZDB mode, LVCMOS input = LVCMOS

t_PROP-

Input-to-output delay variation in ZDB

output = 25 MHz, PLL BW = 300 kHz to

mode

-400

400

ps

VARIATION

900 kHz across temperature

(1) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS

buffer. There is an additional skew 150 ps- 250 ps between OUT1/OUT4 and OUT2/OUT3.

7.16 PCIe Spread Spectrum Generator

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

31.5

6.8

MAX

UNIT

kHz

dB

f_SSC-RATE

P_AMPL-RED

f_SSC-STEP

SSC modulation rate

OUTx = 100 MHz

30

33

SSC amplitude reduction

Down and Center spread SSC step size

OUTx = 100 MHz, -0.25% Down spread

OUTx = 100 MHz, -0.50% Down spread

OUTx = 100 MHz

9.9

dB

0.25

%

t_{SSC_FREQ_DE}Down spread minimum/maximum

OUTx = 100 MHz. F_PFD= 25 MHz, 50

MHz, 100 MHz

-0.5

0

%

deviation

VIATION

t_{SSC_FREQ_DE}Center spread minimum/maximum

OUTx = 100 MHz. F_PFD= 25 MHz, 50

MHz, 100 MHz

0.5

deviation

VIATION

8

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7.17 LVCMOS Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_{O_LVCMOS}

Output frequency

2 pF to GND, normal mode

0.024

200

MHz

I_OH= 1 mA, VDDO_x is corresponding

supply voltage.

0.8 ×

VDDO_x

V_{OH_LVCMOS}Output high voltage

V

I_OL= 1 mA, VDDO_x is corresponding

supply voltage.

0.2 ×

VDDO_x

V_{OL_LVCMOS}

Output low voltage

I_OH

Output high current

Output low current

Output rise/fall time

Vout = 0.8 × VDDO_x, VDDO_x = 1.8 V

Vout = 0.8 × VDDO_x, VDDO_x = 2.5 V

Vout = 0.8 × VDDO_x, VDDO_x = 3.3 V

Vout = 0.2 × VDDO_x, VDDO_x = 1.8 V

Vout = 0.2 × VDDO_x, VDDO_x = 2.5 V

Vout = 0.2 × VDDO_x, VDDO_x = 3.3 V

20/80%, C_L= 5 pF, normal mode

-6

-8.5

-11.2

6

mA

ps

I_OH

I_OL

8.5

I_OL

11.2

500

T_RISE-FALL

300

700

20/80%, C_L= 5 pF, slow mode, measured

on OUT0

T_RISE-FALL

T_SKEW

Output rise/fall time

1000

100

ps

LVCMOS-to-LVCMOS outputs, same

divide value

Output-to-output skew⁽¹⁾

LVCMOS-to-Differential outputs, same

divide value

T_SKEW

ODC

Output-to-output skew⁽¹⁾

Output duty cycle

400

Not in PLL bypass mode

Normal mode

45

50

55

75

85

%

Ω

R_{ON_LVCMOS}Output impedance

60

65

Slow mode

(1) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS

buffer. OUT1/OUT4 is matched within T_OUT-SKEW. OUT2/OUT3 is matched within T_OUT-SKEW

.

7.18 LP-HCSL Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

0.024

660

TYP

MAX

328.125

850

UNIT

MHz

mV

Ω

f_{O_HCSL}

V_OH

Output frequency

Output high voltage⁽¹⁾

V_OL

Output low voltage

Differential Output Impedance⁽¹⁾

-150

90

150

Z_DIFF

100

110

12-in, 100 Ω ±10% diff. trace with 2

pF±5%/pin in FR4.

V_CROSS

ΔV_CROSS

dV/dt

Absolute crossing point

250

550

140

4

mV

Relative crossing point variation

Slew rate for rising and falling edge

with respect to average crossing point

differential, at V_CROSS+/-150 mV,

1

V/ns

(2)

f_{O_HCSL}=100 MHz

single-ended, at V_CROSS+/-75 mV,

f_{O_HCSL}=100 MHz

ΔdV/dt

Slew rate matching

20

%

(2)

Measured on differential output at 100

MHz and specifies minimum voltage from

zero crossing

Vrb

Output ringback voltage

-100

100

mV

Tstable

ODC

Time elapsed until ringback

Output duty cycle

Minimum time until ringback is allowed

Not in PLL bypass mode

500

45

ps

%

55

T_OUT-SKEW

Output skew⁽³⁾

Same divide value, LP-HCSL to LP-HCSL

100

ps

(1) Differential Output characteristic is trimmed in factory and trim settings are stored in EEPROM. Parameter not valid in Fall-back mode.

(2) PCIe test load slew rate

(3) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS

buffer. OUT1/OUT4 is matched within T_OUT-SKEW. OUT2/OUT3 is matched within T_OUT-SKEW. There is an additional skew 150 ps- 250 ps

between OUT1/OUT4 and OUT2/OUT3.

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7.19 LVDS Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

0.024

1.025

0.85

TYP

MAX

328.125

1.375

UNIT

MHz

V

f_{O_PRG_AC}

V_CM

Output frequency

Output common mode⁽¹⁾

VDDO_X = 2.5 V, 3.3 V

1.2

V_CM

VDDO_X = 1.8 V

0.95

1.05

V

VDDO_X = 1.8 V (F_out< 200 MHz), 2.5 V,

3.3 V.

V_OD

Differential output voltage⁽¹⁾

0.25

0.30

0.45

V

V_OD

Differential output voltage⁽¹⁾

Output rise/fall times

Output duty cycle

VDDO_X = 1.8 V & F_out> 200 MHz

LVDS (20% to 80%)

0.22

450

45

0.30

650

0.45

900

55

V

t_RF

ps

%

ps

ODC

T_OUT-SKEW

Not in PLL bypass mode

Output skew⁽²⁾

Same divide value, LVDS to LVDS output

100

(1) Output Common Mode voltage and Differential output swing is dependent upon register settings DIFFBUF_IBIAS_TRIM,

LVDS_CMTRIM_DEC and LVDS_CMTRIM_INC. Parameters defined for DIFFBUF_IBIAS_TRIM=6h, LVDS_CMTRIM_DEC=0h and

LVDS_CMTRIM_INC=0h. Output Common Mode tested at DC.

(2) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS

buffer. OUT1/OUT4 is matched within T_OUT-SKEW. OUT2/OUT3 is matched within T_OUT-SKEW. There is an additional skew 150 ps- 250 ps

between OUT1/OUT4 and OUT2/OUT3.

7.20 Output Synchronization Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

with respect to PLL reference rising edge

at 100 MHz with R=1

t_{SU_SYNC}

t_{H_SYNC}

Setup time SYNC pulse

3

ns

with respect to PLL reference rising edge

at 100 MHz with R=1

Hold time SYNC pulse

3

ns

With R = 1, at least 2 PFD periods + 24

feedback pre-scaler periods

t_{PWH_SYNC}

High pulse width for SYNC

60

6

t_{PWL_SYNC}

t_EN

Low pulse width for SYNC

With R = 1, at least 1 PFD period

tri-state to first valid rising edge

last valid falling edge to tri-state

ns

Individual output enable time⁽¹⁾

Individual output disable time⁽¹⁾

4

nCK

t_DIS

(1) Output clock cycles of respective output channel. Global output enable handled by digital logic, additional propagation will be added.

7.21 Power-On Reset Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_THRESHOLDPOR threshold voltage⁽¹⁾

0.875

1.275

V

Start-up time after VDD reaches 95% to

the time outputs are toggling with correct

frequency (input = crystal or external

clock)

t_STARTUP

Start-up time

9

ms

timing requirement for any VDD pin while

PDN=LOW

t_VDD

Power supply ramp time⁽²⁾

0.1

30

(1) POR threshold voltage is the power supply voltage at which the internal reset is deasserted. It is qualified internally with PDN.

(2) VDD pin should monotonically reach 95% of its final value within supply ramp time. Parameters specified by characterization. All VDD

pins were tied together for this evaluation. For non-monotonic or slower power supply ramp, it is recommended to pull-down PDN pin

until VDD pins have reached 95% of its final value. PDN pin has a 50 kΩ pullup resistor. When PDN pin cannot be actively controlled, TI

recommends to add a capacitor to GND on PDN pin to delay the release of reset.

7.22 I²C-Compatible Serial Interface Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.7 ×

VDD_REF

V_IH

Input Voltage, Logic High

V

0.3 ×

VDD_REF

V_IL

I_IH

Input Voltage, Logic Low

Input Leakage Current

V

VDD_REF ± 10%

-5

5

µA

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I²C-Compatible Serial Interface Characteristics (continued)

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

Low Level Output Voltage

Input Capacitance

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_OL

C_IN

at 3 mA sink current

0.4

10

pF

C_OUT

Output Capacitance

max bus capacitance per pin

400

pF

7.23 Timing Requirements, I²C-Compatible Serial Interface

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ns

t_{PW_G}

f_SCL

Pulse Width of Suppressed Glitches

SCL Clock Frequency

50

Standard

100

400

0.6

kHz

µs

f_SCL

SCL Clock Frequency

Fast-mode

t_{SU_STA}

Setup Time Start Condition

SCL=V_IHbefore SDA=V_IL

SCL=V_ILafter SCL=V_ILAfter this time, the

first clock edge is generated.

t_{H_STA}

Hold Time Start Condition

0.6

µs

t_{SU_SDA}

t_{H_SDA}

t_{VD_SDA}

t_{PWH_SCL}

t_{PWL_SCL}

t_IR

Setup Time Data

SDA valid after SCL=V_IL, f_SCL=100 kHz

SDA valid after SCL=V_IL, f_SCL=400 kHz

SDA valid before SCL=V_IH

f_SCL=100 kHz⁽³⁾

250

100

0⁽²⁾

ns

Setup Time Data

Hold Time Data⁽¹⁾

⁽³⁾µs

µs

ns

Valid Data or Acknowledge Time

Pulse Width High, SCL

Pulse Width Low, SCL

Input Rise Time

3.45

0.9

f_SCL=400 kHz⁽²⁾

f_SCL=100 kHz

4.0

0.6

4.7

1.3

f_SCL=400 kHz

f_SCL=100 kHz

f_SCL=400 kHz

300

250

t_IF

Input Fall Time

ns

t_OF

Output Fall Time

10 pF ≤ C_OUT≤ 400 pF

ns

t_{SU_STOP}

Setup Time Stop Condition

0.6

1.3

µs

Time between a Stop and a Start

condition

t_BUS

Bus-Free Time

µs

(1) t_{H_SDA}is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min)of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

(3) The maximum t_{H_SDA}could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of t_{VD_SDA}by

a transition time. This maximum must only be met if the device does not stretch the LOW period (t_{PWL_SCL}) of the SCL signal. If the

clock stretches the SCL, the data must be valid by the setup time before it releases the clock.

7.24 Power Supply Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_{DD_REF}

I_{DD_VCO}

VDD_REF supply current

25 MHz XTAL, DBL ON

8

mA

f_VCO=2400 MHz, PSA = PSB = 4 and N-

divider = 48

VCO and PLL current

14

22

mA

IOD=6, LP-HCSL, 100MHz on OUT3 and

OUT4, 25MHz on OUT0

I_{DD_OUT}

Output Channel Current

IOD = 6, LP-HCSL, 100 MHz on OUT1

and OUT2

I_{DD_OUT}

I_{DD_PDN}

I_{DD_TYP}

Output Channel Current

Power down current

Typical current

17.5

2.8

50

mA

using reset pin / bits

5

4 x 100 MHz LVDS case using crystal

input and doubler, SSC off

70

4 x 100 MHz LP-HCSL case using crystal

input and doubler, SSC off

I_{DD_TYP}

L_PSNR

Typical current

65

90

mA

dB

OUTx = 100 MHz differential, on one of

VDDx injected sine wave at f_INJ= 100 kHz

Power supply noise rejection

-61

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Power Supply Characteristics (continued)

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A= -40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTx = 100 MHz differential, on one of

VDDx injected sine wave at f_INJ= 1 MHz

L_PSNR

Power supply noise rejection

-57

dB

7.25 Typical Characteristics

Measured at room temperature

Reference: Crystal

Closed-Loop Phase

Input 25 MHz Noise from 2.4-GHz

VCO

100-MHz LP-HCSL

Reference: Crystal

Closed-Loop Phase

156.25-MHz LVDS

Input 25 MHz Noise from 2.5-GHz

VCO

Figure 2. 100-MHz LP-HCSL Output

Figure 1. 156.25-MHz LVDS Output

Reference: Crystal

Input 25 MHz

Closed-Loop Phase

Noise from 2.376-

GHz VCO

148.5-MHz LVDS

Reference: Crystal

Input 25 MHz

Closed-Loop Phase

Noise from 2.4576-

GHz VCO

24.576-MHz

LVCMOS

Figure 3. 148.5-MHz LVDS Output

Figure 4. 24.576-MHz LVCMOS Output

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Typical Characteristics (continued)

Measured at room temperature

Figure 6. All Power Supply = 3.3 V, VDD Ramp Time = 1 ms

Figure 5. All Power Supply = 1.8 V, VDD Ramp Time = 1 ms

Figure 8. All Power Supply = 3.3 V, VDD Ramp Time = 10 ms

Figure 7. All Power Supply = 1.8 V, VDD Ramp Time = 10 ms

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8 Parameter Measurement Information

8.1 Reference Inputs

Signal

< 2 V_PP

100 ꢀ

DUT

Generator

Figure 9. Differential AC-Coupled Input

8.2 Outputs

Scope

LVCMOS

50 ꢀ

DUT

GND

Figure 10. LVCMOS Output Test Configuration

Scope

50ꢀ

DUT

LVDS

50ꢀ

GND

Figure 11. LVDS Output Test Configuration, AC-Coupled

Scope

(50 Ω)

DUT

Balun

Figure 12. LP-HCSL Test Configuration, DC-Coupled

50 ꢀ

>1MΩ

CDCE6214

Scope

50 ꢀ

GND

Figure 13. LVDS Common Mode Voltage, DC-Coupled

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Outputs (continued)

QAx, QBx

V_OD

nQAx, nQBx

80%

0 V

V_{OUT,DIFF,PP = 2xVOD}

20%

t_f

Figure 14. Differential Output Voltage and Rise/Fall Time

8.3 Serial Interface

ACK

STOP

START

t_IR

t_IF

t_{PWL_SCL}t_{PWH_SCL}

V_IH

V_IL

SCL

t_{H_STA}

t_{SU_STA}

t_BUS

t_{SU_SDA}

t_IR

t_{H_SDA}

t_{SU_STOP}

t_IF

V_IH

V_IL

SDA

Figure 15. I²C Timing

8.4 PSNR Test

Sine

Wave

Modulator

Power Supply

Phase Noise/

Spectrum

Analyzer

Signal

Generator

DUT

Device Output

Balun

Reference

Input

Figure 16. PSNR Test Configuration

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8.5 Clock Interfacing and Termination

8.5.1 Reference Input

Rs

LVCMOS

Driver

CDCE6214

Figure 17. Single-Ended LVCMOS to Reference

Signal

Generator

100 ꢀ

< 2 V_PP

DUT

Figure 18. Differential Input to Reference

8.5.2 Outputs

Rs

CDCE6214

DUT

GND

Figure 19. LVCMOS Output

CDCE6214

DUT

Figure 20. LVDS Output - DC-Coupled. Place 100Ω close to the DUT

VCM

CDCE6214

DUT

VCM

Figure 21. LVDS Output - AC-Coupled

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Clock Interfacing and Termination (continued)

Rs

CDCE6214

DUT

Figure 22. LP-HCSL Output

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9 Detailed Description

9.1 Overview

The CDCE6214 clock generator is a Phase-Locked Loop (PLL) with integrated voltage controlled Oscillator

(VCO) and integrated loop filter with selectable input reference. Input reference supports XTAL, Differential and

single-ended LVCMOS inputs. The PLL consists of Frac-N PLL with integrated VCO range of 2335MHz -

2625MHz. The output of the VCO is connected to the clock distribution network, which includes multiple

frequency dividers and multiplexers. The output of these network is connected to four output channels with

configurable differential and single ended buffers. There are 4 power supply pins which can be independently

configured to 1.8V/2.5V/3.3V. CDCE6214 can be configured using the I²C serial interface or built-in EEPROM at

power up. This device supports various modes such as Digitally Controlled Oscillator (DCO) through GPIO/I2C

and Internal/external Zero Delay mode.

9.2 Functional Block Diagram

Outputs (1.8/2.5/3.3 V)

7

OUT0

LVCMOS

Inputs (1.8/2.5/3.3 V)

0

22

OUT1

LVDS,

LP-HCSL,

LVCMOS

Integer Div

14-b

1

21

2

5

6

PRIREF

Differential,

LVCMOS

APLL (1.8/2.5/3.3 V)

0

1

2

18

17

OUT2

LVDS,

LP-HCSL

x2

Integer Div

14-b

VCO: 2.335-2.625 GHz

R div

8-b

f

/4 - /6

1

2

SECREF

Differential,

XTAL, LVCMOS

XO

0

1

2

14

13

OUT3

LVDS,

LP-HCSL

Integer Div

14-b

N Div

MARGIN

/4 - /6

15-b int,

24-b frac

4

REFSEL

0

1

2

10

9

OUT4

LVDS,

LP-HCSL,

LVCMOS

Integer Div

14-b

Control (1.8/2.5/3.3 V)

Registers

EEPROM

Device Control

and Status

Power Conditioning

Figure 23. CDCE6214 Clock Generator With 2 Inputs, 1 Fractional-N PLL, and 4 Outputs

9.3 Feature Description

The following sections describe the individual blocks of the CDCE6214 ultra low power clock generator.

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Feature Description (continued)

9.3.1 Reference Block

A reference clock to the PLL is fed to pins 1 (SECREF_P) and 2 (SECREF_N) or to pins 5 (PRIREF_P) and 6

(PRIREF_N). There are multiple input stages to accommodate various clock references. Pins 1 and 2 can be

used to connect a XTAL across it or provide an external single-ended LVCMOS clock or a differential clock.

These modes are selectable through register programming. When differential mode is selected, appropriated

biasing is applied to the pin. In case of differential mode, external AC-coupling capacitor is needed. When XTAL

or LVCMOS mode is selected, biasing circuitry is disengaged. Pins 5 and 6 can be used to provide an external

single-ended LVCMOS clock or a differential clock.

The reference MUX selects the reference clock for the PLL. Setting REFSEL pin = L selects SECREF input,

while setting REFSEL pin = H selects PRIREF Input. Alternatively, this can be configured through the register

settings.

Table 1. Reference Input Selection

REGISTER BIT ADDRESS

REGISTER BIT FIELD NAME

VALUE

DESCRIPTION

Input Reference Mux controlled

through Pin 4 (REFSEL)

R2[1:0]

REFSEL_SW

0h or 1h

Pin1/Pin 2 SECREF Input

selected. This is independent of

Pin 4 status.

(Default: 0h)

2h

3h

Pin 5/Pin 6 PRIREF Input

selected. This is independent of

Pin 4 status.

XO enabled. Valid for SECREF

pins.

R24[1:0]

R24[15]

IP_SECREF_BUF_SEL

(Default: 0h)

0h

1h

LVCMOS Buffer enabled. Valid

for SECREF pins.

Differential Buffer enabled. Valid

for SECREF pins.

2h or 3h

0h

LVCMOS Buffer enabled. Valid

for PRIREF pins.

IP_PRIREF_BUF_SEL

(Default: 0h)

Differential Buffer enabled. Valid

for PRIREF pins.

1h

A reference divider or a clock-doubler can be engaged to further multiply (2x) or divide the reference clock to the

PLL. IP_RDIV[7:0] can be used to set the value of the divider. Setting this to 00h would enable the doubler.

The output clock from the reference block can be bypassed to the OUT0 and other output channels. The

bypassed clock is selectable between the Input clock or PFD clock. More details available in Table 9.

The SECREF_P and SECREF_N pins provide a crystal oscillator stage to drive a fundamental mode crystal in

the range of 10 MHz to 50 MHz. The crystal input stage integrates a tunable load capacitor array up to 9 pF and

programmable through R24[12:8]. The drive capability of the oscillator is programmable through R24[5:2].

The LVCMOS input buffer threshold voltage follows VDD_REF. This device can be used as a level shifter

because the outputs have separate supplies.

9.3.1.1 Zero Delay Mode, Internal and External Path

The CDCE6214 can operate in Zero Delay Mode with internal as well as external feedback. In Zero Delay Mode,

PRIREF clock is used as the reference clock to the PFD. SECREF input clock can be used to feed an external

source as feedback clock to the PFD. External feedback path is recommended for zero delay operation.

Moreover there is an additional internal feedback path which is sourced from output channel 2. It is expected that

the Input-output propagation delay would be higher in Internal zero-delay mode than external zero delay mode.

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(1) (2) (3)

Table 2. Zero Delay Operation

R24[1:0] -

IP_SECREF_B IP_PRIREF_B

R24[15] -

R0[10] -

ZDM_CLOCKS DESCRIPTION

EL

R2[1:0] -

REFSEL_SW

R0[8] -

ZDM_EN

OPERATION

REFSEL

UF_SEL

Normal

Operation,

XTAL Input

L

0h or 1h or 2h

0h

X

0h

Operation,

XTAL Input

Normal

Operation,

Differential

Input

SECREF/Differ

ential Input

L

2h or 3h

X

0h

Normal

Operation,

Differential

Input

PRIREF/Differe

ntial Input

H

0h or 1h or 3h

X

1h

0h

Normal

Operation,

LVCMOS Input

SECREF/LVCM

OS Input

L

0h or 1h or 2h

0h or 1h or 3h

1h

X

0h

Normal

Operation,

LVCMOS Input

PRIREF/LVCM

OS Input

H

0h

External Zero

Delay Mode,

Differential

Input

Input Clock on

PRIREF,

Feedback clock

on SECREF

H

0h or 1h or 3h

2h or 3h

1h

0h

1h

0h

1h

0h

Input Clock on

PRIREF,

Feedback clock

on SECREF

External Zero

Delay Mode,

LVCMOS Input

1h

X

Internal Zero

Delay Mode,

Differential

Input

Input clock on

PRIREF

Internal Zero

Delay Mode,

Differential

Input

Input clock in

PRIREF

X

(1) In zero delay mode, all dividers should be programmed such that PLL can lock. On power-up in zero-delay mode, PLL would lock

automatically

(2) For internal Zero delay mode, channel 2 is required. Channel 2 should not be powered down

(3) "X" allows any possible bit-field value. It has no impact on the functionality

Figure 24. Input/Output Alignment in External Zero Delay Mode for LVCMOS Output

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9.3.2 Phase-Locked Loop (PLL)

The CDCE6214 has a fully-integrated Phase-Locked Loop (PLL) circuit. The error between a reference phase

and an internal feedback phase is compared at the phase-frequency-detector. The comparison result is fed to a

charge pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes

an internal Voltage-Controlled Oscillator (VCO). The frequency of the VCO is fed through a feedback divider (N-

counter) back to the PFD.

•

Integer and Fractional-N PLL mode of operation.

First-, Second-, or Third-Order MASH operation in Fractional mode.

24-bit Numerator and Denominator can be used to generate fractional frequencies with 0 ppb frequency

accuracy.

•

PFD operates between 1 MHz and 100 MHz.

Live Lock Detector (R7[0] or PLL_LOCK in GPIO) provides PLL Lock status (in fractional mode and SSC

enabled, lock detect window need to be widened. R50[10:8] = 7h). Additionally, sticky bit lock detect (R7[1])

detects if there was any temporary loss of lock.

•

Integrated selectable loop filter components.

For a 25-MHz PFD frequency, PFD bandwidth between 100 kHz and 1.6 MHz can be achieved to optimize

PLL to input reference.

•

Voltage-controlled oscillator (VCO) ranges from 2335 MHz to 2615 MHz.

Supports 0.25% and 0.5% center and down spread Spread Spectrum Clocking (SSC) generation. Further,

VCO also supports up to 0.5% SSC references at 100 MHz for PCIe clocking.

Table 3. Common Clock Generator Loop Filter Settings

PHASE

MARGIN IN °

DAMPING

FACTOR

f_VCOIN MHz f_PFDIN MHz

BW IN MHz

I_CPIN mA

C_PcapIN pF

R_ResIN kΩ

C_ZcapIN pF

2400

2457.6

2500

2400

25

50

0.469

0.938

1.60

1.04

0.49

0.93

400

70

65

0.5

2

0.60

0.80

0.60

0.40

16.1

8.2

2.5

2.0

2.5

1.5

580

276

303

331

497

386

636

100

61.44

25

0.5

1.15

0.4

1.0

0.1

8.2

9.2

13.5

11.7

50

(1)

Table 4. Common PLL Divider Settings

INPUT

FREQUENCY

IN MHz

OUTPUT

FREQUENCY

IN MHz

N-COUNTER

DIVIDER VALUE

OUTPUT

DIVIDER

f_PFDIN MHz

f_VCO

NUMERATOR

DENOMINATOR

PSA

25

50

25

50

25

100

2400

2500

2400

2457.6

2376

48

96

50

96

98

95

NA

4

6

156.25

25

NA

4

NA

24

25

4

24.576

148.5

5071614

664983

16682942

16624579

(1) Fractional Mode settings are based on DCO mode step size of 0.1ppm

9.3.2.1 PLL Configuration and Divider Settings

f_PFD= F_in/F_factor

F_factoris determined by R25[7:0] - ip_ref_div. F_factor= 0.5 when ip_ref_div=0, F_factor= ip_ref_div, otherwise.

f_VCO= f_PFD× (N + Num/Den).

N is set by R30[14:0] - PLL_NDIV. Num is the numerator of the fraction, set by {R32[7:0],R31[15:0]}. Den is the

denominator of the fraction, set by R34[7:0],R33[15:0]. When {R34[7:0],R33[15:0]} = 0, Den=2²⁴.

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The sigma delta modulator supports different order of MASH to shape the quantization noise. For Integer mode,

R27[1:0] is set as 0h. For fractional mode, it can be set to 1h, 2h or 3h for first, second and third order,

respectively.

In integer mode, PLL is configured in single-ended PFD configuration by setting R51[6]=1h. In Fractional mode,

PLL should be configured in Differential PFD configuration by setting R51[6]=0h. Further, R51[10] is set as 1h in

fractional mode and 0h in Integer mode.

9.3.2.2 Spread Spectrum Clocking

The energy of the harmonics from the rectangular clock signal can be spread over a certain frequency range.

This frequency deviation leads to lowered average amplitude of the harmonics. This can help to mitigate

electromagnetic interference (EMI) challenges in a system when the receiver supports this mode of operation.

The modulation shape is triangular.

The SSC clock is generated through the fractional-N PLL. When SSC is enabled, SSC clock is available on all

clock sourced from the PLL. Reference clock or PFD clock is available on the OUT1–OUT4 pins.

Down spread and center spread are supported. The following modes are supported.

•

PFD frequencies: Either 25 MHz or 50 MHz.

Down spread: –0.25% and ±0.5%

Center spread: ±0.25% and ±0.5%

Pre-configured settings are available to select any of these combinations.

Using these pre-configured settings, fmod of 31.5 kHz is synthesized for 100-MHz output clock.

Center-Spread

Frequency

f_upper

f_{SSC_MOD}

f_nom

f_SPREAD

f_lower

Time

Down-Spread

Frequency

f_upper= f_nom

f_{SSC_MOD}

f_SPREAD

f_lower

Time

Figure 25. Spread Spectrum Clock

(1) (2)

Table 5. Spread Spectrum Settings

R41[15] - SSC_EN

0h

R42[5] - SSC_TYPE

R42[3:1] - SSC_SEL

DESCRIPTION

No SSC modulation at output

X

(1) X signifies that this bitfield can take any value

(2) For any other SSC spread and modulation rate, please contact TI representative.

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Table 5. Spread Spectrum Settings ⁽²⁾(continued)

R41[15] - SSC_EN

R42[5] - SSC_TYPE

R42[3:1] - SSC_SEL

DESCRIPTION

Down spread SSC modulation.

SSC spread is determined by

ssc_sel

1h

0h

X

Center spread SSC modulation.

SSC spread is determined by

ssc_sel

1h

X

25-MHz PFD, +/- 0.25% for

Center spread, -0.25% for Down

spread.

0h

1h

2h

25-MHz PFD, +/- 0.50% for

Center spread, -0.50% for Down

spread.

X

50-MHz PFD, +/- 0.25% for

Center spread, -0.25% for Down

spread.

X

50-MHz PFD, +/- 0.50% for

Center spread, -0.50% for Down

spread.

1h

X

3h

4h-7h

Do not use

Figure 26. 100 MHz With - 0.25% Down Spread With and

Without Trace

Figure 27. 100 MHz With +/- 0.25% Center Spread With and

Without Trace

Figure 28. 100 MHz With - 0.5% Down Spread With and

Without Trace

Figure 29. 100 MHz With +/- 0.5% Center Spread With and

Without Trace

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RESULT

Table 6. PCI Express Compliance Measurement

MEASURED

SCOPE

METHOD

MEASURED

PNA METHOD

NO.

CLASS

DATA RATE

ARCHITECTURE

SPEC LIMIT

1

2

3

4

Gen4

Gen5

16 Gb/s

32 Gb/s

CC

SRIS

CC

195 fs

260 fs

490 fs

111 fs

157 fs

500 fs

150 fs

*

PASS

*

-

87 fs

-

SRIS

9.3.2.3 Digitally-Controlled Oscillator/ Frequency Increment and Decrement - Serial Interface Mode and

GPIO Mode

In this mode, the output clock frequency can be incremented or decremented by a fixed frequency step. The

frequency step size is determined by the register R43[15:0]. This value is added or subtracted to the numerator

of the sigma-delta modulator. Various bit fields as shown in can be used to exercise this functionality. Every

rising edge of FREQ_INC signal increases the output frequency, while every rising edge of FREQ_DEC signal

decreases the output frequency. There are two ways to trigger the increment or decrement:

1. Appropriate configuration of the GPIOs and sending FREQ_INC/FREQ_DEC signal through an external

microcontroller or ASIC.

2. Using register bit fields controlled through serial interface.

Table 7. Register Settings for Frequency Increment/Decrement Functionality

REGISTER BIT ADDRESS

REGISTER BIT FIELD NAME

DESCRIPTION

R3[3]

FREQ_INC_DEC_EN

Enables/Disables DCO mode

Selects DCO trigger through GPIOs or Serial

Interface.

R3[4]

FREQ_INC_DEC_REG_MODE

Generates FREQ_INC/FREQ_DEC signal

through serial Interface

R3[6:5]

FREQ_DEC_REG, FREQ_INC_REG

FREQ_INC_DEC_DELTA

R43[15:0]

Frequency Increment/Decrement step size

Table 8. Computing Divider Settings in DCO Mode

PARAMETERS

VALUE (EXAMPLE)

DESCRIPTION

Input PFD Frequency (F_PFD

)

25 MHz

Set according to F_PFD.

F_VCOis set within the operating VCO range

of 2335 MHz - 2625 MHz. F_VCOis selected

such that PSA/PSB/Output Divider is Integer.

Expected VCO Frequency (F_VCO

)

2457.6 MHz

24.576 MHz

PSA = 4, IOD = 25. F_VCO= PSA × IOD ×

Expected Output Frequency (F_OUT

)

F_OUT

.

Every rising edge of FREQ_INC/FREQ_DEC

would change the output by this step size.

Expected step size (in ppm) (F_step

)

0.1

98

76

N-divider Value (N)

INT(F_VCO/F_PFD

)

Minimum Numerator value to meet 0ppb

accuracy (Num)

These values are computed to meet

accuracy requirement at output. Should be

less than 2²⁴

.

Minimum Denominator to meet 0ppb

accuracy (Den)

250

Minimum Denominator value to meet ppm

101725.26

500000

1/(F_step× 1e6) / (F_VCO/F_PFD)

step size (F_DEN,min

)

Final Denominator value (F_DEN,final

)

F_DEN,finalshould be greater than F_DEN,minand

less than 2²⁴. F_DEN,finaland F_NUM,finalshould

be integer multiple of Den and Num

respectively. F_DEN,final/Den = F_NUM,final/Num

This value should be less than 2¹⁶-1.

F_DEN,finalshould be closest integer multiple of

Final Numerator value (F_NUM,final

)

152000

5

Increment/ Decrement step size

F_DEN,min

.

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9.3.3 Clock Distribution

The VCO output connects to two individually configurable pre-scalar dividers sourcing the on-chip clock

distribution – PSA and PSB. PSA and PSB can be configured as division value of /4, /5 or /6 independently.

The clock distribution consists of four output channels. Each output channel contains an integer divider (IOD)

with glitchless switching and synchronization capabilities.

IOD can be sourced from either the PSA, the PSB, or the Reference Clock. IOD can be bypassed to provide a

Reference clock at the output.

There are five output channels – OUT0, OUT1, OUT2, OUT3, and OUT4.

The OUT0 is a slew-rate controllable LVCMOS output. Either the reference clock or PFD clock can be routed to

this output through the clock distribution network.

The OUT1 and OUT4 are identical output channels. The output buffers in this channel are compatible with

various signaling standards – LVCMOS, LP-HCSL, and LVDS-like.

The OUT2 and OUT3 are identical output channels. The output buffers in this channel are compatible with

various signaling standards – LP-HCSL and LVDS-like.

•

The LP-HCSL output buffer can be directly connected to the receiver without any termination resistor to GND.

The output impedance of LP-HCSL is trimmed to 50 Ω ± 10%. A series resistor can be used to adapt to the

trace impedance.

The LVDS-like requires a differential termination connected between the positive and negative polarity output

pins. The termination can be connected directly or through an AC-coupling capacitor. For a 50-Ω system, a

100-Ω differential termination is appropriate.

LVCMOS outputs are designed for capacitive loads only. The polarity of the positive and negative output pins

can be configured individually.

The differential buffers support wide range of output frequencies up to 328.125 MHz. LVCMOS supports up to

200 MHz.

(1)

Table 9. Configuring Input Reference/PFD/PLL Clock to Output

REGISTER BIT ADDRESS

REGISTER BIT FIELD NAME

DESCRIPTION

Enables Reference Clock/PFD Clock to

OUT0.

R25[10]

IP_BYP_OUT0_EN

Selects between PFD Clock or Input

Reference Clock

R25[9]

REF_CH_MUX

IP_REF_TO_OUT4_EN,

IP_REF_TO_OUT3_EN,

IP_REF_TO_OUT2_EN,

IP_REF_TO_OUT1_EN

R25[14:11]

Selects reference clock to OUT1-OUT4

R56[15:14]

R62[15:14]

R67[15:14]

R72[15:14]

CH1_MUX

CH2_MUX

CH3_MUX

CH4_MUX

Clock selection MUX control for OUT1

Clock selection MUX control for OUT2

Clock selection MUX control for OUT3

Clock selection MUX control for OUT4

(1) It is recommended to disable any clock when not in use to reduce crosstalk

Table 10. Configuring Clock Distribution Network

REGISTER BIT ADDRESS

R47[6:5]

REGISTER BIT FIELD NAME

PLL_PSB

DESCRIPTION

Programmable Pre-scalar divider PSB

Programmable Pre-scalar divider PSA

OUT1 Integer Divider value

R47[4:3]

PLL_PSA

R56[13:0]

CH1_DIV

R62[13:0]

CH2_DIV

OUT2 Integer Divider value

R67[13:0]

CH3_DIV

OUT3 Integer Divider value

R72[13:0]

CH4_DIV

OUT4 Integer Divider value

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Table 11. Configuring LVCMOS Output Buffer

REGISTER BIT ADDRESS

REGISTER BIT FIELD NAME

DESCRIPTION

Enables OUT0 LVCMOS Buffer

R78[12]

CH0_EN

Controls output slew rate of OUT0 LVCMOS

Buffer

R79[3:0]

CH0_CMOS_SLEW_RATE_CTRL

R59[14], R75[14]

R59[13], R75[13]

CH1_CMOSN_EN, CH4_CMOSP_EN

CH1_CMOSP_EN, CH4_CMOSN_EN

Enables OUT1N/OUT4P LVCMOS Buffer

Enables OUT1P/OUT4N LVCMOS Buffer

Sets output polarity of OUT1N/OUT4P

LVCMOS Buffer

R59[12], R75[12]

R59[11], R75[11]

R60[3:0], R76[3:0]

CH1_CMOSN_POL, CH4_CMOSP_POL

CH1_CMOSP_POL, CH4_CMOSN_POL

Sets output polarity of OUT1P/OUT4N

LVCMOS Buffer

CH1_CMOS_SLEW_RATE_CTRL,

CH4_CMOS_SLEW_RATE_CTRL

Controls output slew rate of OUT1/OUT4

LVCMOS Buffer

(1) Multiple output buffers should not be enabled at the same time

(2) Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8V,

safety_1p8v_mode should be set.

(1) (2) (3)

Table 12. Configuring LP-HCSL Output Buffer

REGISTER BIT ADDRESS

REGISTER BIT FIELD NAME

DESCRIPTION

CH1_HCSL_EN, CH2_HCSL_EN,

CH3_HCSL_EN, CH4_HCSL_EN

Enables LP-HCSL buffer on

OUT1/OUT2/OUT3/OUT4

R57[14] , R63[13], R68[13], R73[13]

(1) Multiple output buffers should not be enabled at the same time

(2) External termination not needed. Voltage mode driver.

(3) Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8V,

safety_1p8v_mode should be set.

(1) (2) (3)

Table 13. Configuring LVDS-Like Output Buffer

REGISTER BIT ADDRESS

REGISTER BIT FIELD NAME

DESCRIPTION

CH1_LVDS_EN, CH2_LVDS_EN,

CH3_LVDS_EN, CH4_LVDS_EN

Enables LVDS-like buffer on

OUT1/OUT2/OUT3/OUT4

R59[15], R65[11], R70[11], R75[15]

CH1_DIFFBUF_IBIAS_TRIM,

CH2_DIFFBUF_IBIAS_TRIM,

CH3_DIFFBUF_IBIAS_TRIM,

CH4_DIFFBUF_IBIAS_TRIM

Sets the output swing and output common

mode of OUT1/OUT2/OUT3/OUT4

R60[15:12], R66[3:0], R71[3:0], R76[9:6]

R60[11:10], R66[5:4], R71[5:4], R76[5:4]

R60[5:4], R65[14:13], R71[10:9], R77[1:0]

CH1_LVDS_CMTRIM_INC,

CH2_LVDS_CMTRIM_INC,

CH3_LVDS_CMTRIM_INC,

CH4_LVDS_CMTRIM_INC

Increases the output common mode of

OUT1/OUT2/OUT3/OUT4. 2.5 V/3.3 V mode

only.

CH1_LVDS_CMTRIM_DEC,

CH2_LVDS_CMTRIM_DEC,

CH3_LVDS_CMTRIM_DEC,

CH4_LVDS_CMTRIM_DEC

Decreases the output common mode of

OUT1/OUT2/OUT3/OUT4. 2.5 V/3.3 V mode

only.

(1) Multiple output buffers should not be enabled at the same time.

(2) 100 Ω differential termination needed in DC-coupled mode. 50 Ω single ended or 100 Ω differential termination needed in AC-coupled

mode

(3) Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8V,

safety_1p8v_mode should be set.

9.3.3.1 Glitchless Operation

The bit fields ch{x}_glitchless_en can be used to enable glitchless output divider update. This feature ensures

that the high pulse of a clock period is not cut off by the output divider update process. It also ensures that setup

and hold time of a receiver is not violated. The low pulse in the transition from earlier period to the new period is

extended accordingly.

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Glitch-Less Divider Disabled:

Glitch-Less Divider Enabled:

t_per1> t_per2

t_per1< t_per2

Figure 30. Glitchless Divider Update

9.3.3.2 Divider Synchronization

The output dividers can be reset in a deterministic way. This can be achieved using the sync bit or PDN pin. The

level of the pin is qualified internally using the reference frequency at the PFD input. A low level on the SYNCN

pin or sync bit will mute the outputs. A high level will synchronously release all output dividers to operation, so

that all outputs share a common rising edge. The first rising edge can be individually delayed in steps of the

respective pre-scalar period, up to 32 cycles using ch{x}_sync_delay. This allows the user to compensate

external delays like routing mismatch, cables, or inherent delays introduced by logic gates in an FPGA design.

Each channel can be included or excluded from the SYNC process. Divider synchronization can be enabled

individually by ch{x}_sync_en.

For a deterministic behavior over power-cycles seen from input to output the reference divider must be set to 1. It

should not divide the reference clock nor should the reference doubler be used.

VCO

Clock Distribution Pre-Scaler Dividers

PS[BA]=4

PS[BA]=5

PS[BA]=6

Output Channel Dividers

All clocks muted.

PS[BA]=4

IOD=4

PS[BA]=5

IOD=4

PS[BA]=6

IOD=4

Internal SYNC

(ä PFD qualified)

1

2

3

Internal synchronization start

All signals muted

Synchronized dividers released

Figure 31. Output Divider Synchronization

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9.3.3.3 Global and Individual Output Enable

The output enable functionality allows the user to enable or disable all or a specific output buffer. The bypass

copy on OUT0 is excluded from the global output enable signal. When an output is disabled, it drives a

configurable mute-state. When the serial interface is deactivated one can use all individual output enable signals

at the same time. The individual output enable signal controls the respective output channel integer divider to

gate the clock, therefore each integer divider must be active.

The individual output enable signal enables and disables the respective output in a deterministic way. Therefore

the high and low level of the signal is qualified by counting four cycles of the respective output clock.

1. The OE falling edge disables the output. The output is enabled for 4 cycles after asserting the Output Enable

of a channel. This will enable any further operation in the system after OE is asserted.

2. The OE rising edge enables the output. Outputs starts toggling after 4 internal clock cycles.

MUTE_SEL= Logic Low

OE

Y1P

1

2

3

4

1

2

3

4

Y1N

Y2P

Y2N

1

2

3

4

1

2

3

4

1

2

3

4

5

6

MUTE_SEL= Logic High

OE

Y1P

1

2

3

4

1

2

3

4

Y1N

Y2P

Y2N

1

2

3

4

1

2

3

4

1

2

3

4

5

6

Figure 32. Individual Output Enable and Disable

Table 14. Glitch-less Operation, Divider Synchronization and Global/Individual OE Settings

REGISTER BIT ADDRESS

REGISTER BIT FIELD NAME

DESCRIPTION

R0[14]

PDN_INPUT_SEL

Configures PDN pin as PDN or SYNCN

Generates SYNC signal through serial

interface

R0[5]

SYNC

CH1_GLITCHLESS_EN,

CH2_GLITCHLESS_EN,

CH3_GLITCHLESS_EN,

CH4_GLITCHLESS_EN

Enables Glitch-less switching for

OUT1/OUT2/OUT3/OUT4

R57[9], R63[9], R68[9], R73[9]

CH1_SYNC_EN, CH2_SYNC_EN,

CH3_SYNC_EN, CH4_SYNC_EN

R57[3], R63[3], R68[3], R73[3]

R57[1], R63[1], R68[1], R73[1]

R57[0], R63[0], R68[0], R73[0]

Enables SYNC for OUT1/OUT2/OUT3/OUT4

CH1_MUTESEL, CH2_MUTESEL,

CH3_MUTESEL, CH4_MUTESEL

Sets Output level when mute on

OUT1/OUT2/OUT3/OUT4

CH1_MUTE, CH2_MUTE, CH3_MUTE,

CH4_MUTE

Mutes output on OUT1/OUT2/OUT3/OUT4

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9.3.4 Power Supplies and Power Management

The CDCE6214 provides multiple power supply pins. Each of the power supplies supports 1.8 V, 2.5 V, or 3.3 V

individually. Internal low-dropout regulators (LDO) source the internal blocks and allow each pin to be supplied

with its individual supply voltage. The VDDREF pin supplies the control pins and the serial interface, therefore

any pullup resistors shall be connected to the same domain as VDDREF.

The device is very flexible with respect to internal power management. Each block offers a power-down bit and

can be disabled to save power when the block is not required. The available bits are illustrated in Table 15. The

bypass output Y0 is connected to the pdn_ch4 bit. Each output channel has a bit which should be adapted to the

applied supply voltage, ch[4:1]_1p8vdet.

Table 15. Power Management

VDDREF

VDDVCO

VDDO_12

R0[1] - POWERDOWN

R4[4] - CH1_PD

VDDO_34

R0[1] - POWERDOWN

R4[6] - CH3_PD

R0[1] - POWERDOWN

R5[8] - PLL_VCOBUFF_LDO_PD

R5[7] - PLL_VCO_LDO_PD

R5[6] - PLL_VCO_BUFF_PD

R5[5] - PLL_CP_LDO_PD

R5[4] - PLL_LOCKDET_PD

R5[3] - PLL_PSB_PD

R4[5] - CH2_PD

R4[7] - CH4_PD

R5[2] - PLL_PSA_PD

R5[1] - PLL_PFD_PD

R53[6] - PLL_NCTR_EN

R53[3] - PLL_CP_EN

9.3.5 Control Pins

The ultra-low power clock generator is controlled by multiple LVCMOS input pins.

HW_SW_CTRL pin acts as EEPROM page select. The CDCE6214 clock generator contains two pages of

configuration settings. The level of this pin is sampled after device power up. A low level selects page zero. A

high level selects page one. The HW_SW_CTRL pin is a tri-level input pin. This third voltage level is

automatically applied by an internal voltage divider. The mid-level is used to select an internal default where the

serial interface is enabled.

PDN/SYNCN (pin 8) , SCL (pin 12), and SDA (pin 19) have a secondary functionality and can act as general-

purpose inputs and outputs (GPIO). This means that either the serial interface or the GPIO functionality can be

active.

PDN/SYNCN resets the internal circuitry and is used in the initial power-up sequence. The pin can be

reconfigured to act as synchronization input. The differential outputs are kept in mute while SYNCN is low. When

SYNCN is high, outputs are active.

Table 16. Control and GPIO Pins

PIN NO.

23

NAME

HW_SW_CTRL

GPIO1

TYPE

Input

2-LEVEL INPUT

3-LEVEL INPUT

OUTPUT

TERMINATION

PUPD

-

Yes

-

20

Input/Output

Yes

PU (when Input)

Open-Drain I/O in

I²C mode, CMOS

(Input)

19

GPIO2

Input/Output

Yes

-

Yes

12

11

8

GPIO3

GPIO4

PDN

Input

Input/Output

Input

Yes

-

Yes

PU (when Input)

PUPD

-

4

REFSEL

Input

Yes

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Table 17. GPIO Input/Output Signal List

ABBREVIATION

TYPE

DESCRIPTION

Frequency Increment; Increments the MASH

numerator

FREQ_INC

FREQ_DEC

OE (global)

Input

Frequency Decrement; Decrements the

MASH numerator

Enables or disables all differential outputs

Y[4:1] (bypass not affected)

SSC_EN

OE1

Input

Enables or disables SSC.

Enables or disables OUT1

Enables or disables OUT2

Enables or disables OUT3

Enables or disables OUT4

OE2

OE3

OE4

PLL Lock Status. 0 = PLL out of lock; 1 =

indicates PLL in lock

PLL_LOCK

Output

9.4 Device Functional Modes

9.4.1 Operation Modes

The operating modes listed in Table 18 can be set, and the GPIOs configured. An operating mode change only

becomes effective when it is loaded from the EEPROM after a power cycle.

Table 18. Modes of Operations

DESCRIPTION

I²C + GPIO

OE

MODE

Fall-back

Pin Mode

REFSEL

M

HW_SW_CTRL

GPIO1

I/O

GPIO2

SDA

GPIO3

SCL

GPIO4

I/O

M

L/H

OE1

OE2

OE3

OE4

Serial Interface

Mode

I²C + GPIO

L/H

I/O

SDA

SCL

I/O

9.4.1.1 Fall-Back Mode

As the programming interface can be intentionally deactivated using the EEPROM, an accidental disabling of the

I²C blocks further access to the device. The serial interface can be forced using the fall-back mode. To enter this

mode, the user leaves pin 4 and pin 23 floating while the supply voltage is applied to VDDREF. In this mode,

EEPROM Read at power up is bypassed and device boots in default mode. In this mode, pin 11 is pre-

configured as an input and pin 20 is configured as an output. After powering up in fall-back mode, the device can

be re-programmed through serial interface and be re-configured for normal operation. EEPROM can also be re-

programmed. The PLL would not be auto-calibrated, however, and the I²C interface would be active. This mode

would allow the user to fully configure the device before re-locking the PLL.

9.4.1.2 Pin Mode

In pin mode, the pins 12 and 19 are input pins which act as individual output enable pins. Together with pins 11

and 20, this allows for one output enable pin per output channel.

9.4.1.3 Serial Interface Mode

In serial interface mode, pins 12 and 19 are configured as an I²C interface.

9.5 Programming

9.5.1 I²C Serial Interface

The CDCE6214 ultra-low power clock generator provides an I²C-compatible serial interface for register and

EEPROM access. The device is compatible to standard-mode I²C at 100 kHz and the fast-mode I²C at 400-kHz

clock frequency.

1. In fall-back mode, I²C slave address = 67h.

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Programming (continued)

2. In other modes, I²C slave address = 68h (Default).

3. The LSB bit of the device can be programmed in the EEPROM. For example, if I2C_A0 is programmed H in

Page 0 of EEPROM, setting HW_SW_CTRL=0 would set I²C address as 69h.

4. Two devices with EEPROM + 1 device in fall-back mode can be used on the same I²C bus with addresses

67h, 68h and 69h.

Table 19. I²C-Compatible Serial Interface, Slave Address Byte

(1) (2)

7

6

5

4

3

2

1

0

Slave Address [6:0]

R/W# Bit

(1) The slave address consists of two sections. The hardwired MSBs A[6:1] and the software-selectable LSBs A[0].

(2) The R/W# bit indicates a read (1) or a write (0) transfer.

Table 20. I²C-Compatible Serial Interface, Programmable Slave Address

(1) (2)

A6

A5

A4

A3

A2

A1

A0

HW_SW_SEL DESCRIPTION

1

0

1

MID

Fall-back Mode

EEPROM Page

0

1

0

1

0

I2C_A0

LOW

EEPROM Page

1

HIGH

(1) In EEPROM Page 0, Serial Interface is not available. Device configured in Pin Mode

(2) In EEPROM Page 1, I2C_A0 is programmed as 0, Expected Slave Address is 68h

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The serial interface uses the following protocol as shown in Figure 33. The slave address is followed by a word-

wide register offset and a word-wide register value.

Write Transfer

7

1

S

Slave Address

Wr

A

8

1

Register Address High

A

Register Address Low

A

8

1

Date Byte High

A

Date Byte Low

A

P

Read Transfer

7

1

S

Slave Address

Wr

A

8

1

Register Address High

A

Register Address Low

A

7

1

Sr

Slave Address

Rd

A

8

1

Date Byte High

A

Date Byte Low

N

P

Legend

S

Sr

Start condition sent by master device

Write bit = 0 sent by master device

Acknowledge sent by master device

Stop condition sent by master device

Not-acknowledge sent by master device

|

Repeated start condition sent by master device

Read bit = 1 sent by master device

Wr Rd

A

P

N

A

Acknowledge sent by slave device

N

|

Not-acknowledge sent by slave device

Data

Data sent by master | Data sent by slave

Figure 33. I²C-Compatible Serial Interface, Supported Protocol

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9.5.2 EEPROM

9.5.2.1 EEPROM - Cyclic Redundancy Check

The device contains a cyclic redundancy check (CRC) function for reads from the EEPROM to the device

registers. At start-up, the EEPROM will be read internally and a CRC value calculated. One of the EEPROM

words contains an earlier stored CRC value. The stored and the actual CRC value are compared and the result

transferred to register. The CRC calculation can be triggered again by writing a 1 to the update_crc bit. A

mismatch between stored and calculated CRC value is informational only and non-blocking to the device

operation. Just reading back the CRC status bit and the live CRC value can speed up in-system EEPROM

programming and avoid reading back each word of the EEPROM for known configurations.

The polynomial used is CCITT-CRC16: x¹⁶+ x¹²+ x⁵+ 1.

9.5.2.2 Recommended Programming Procedure

TI recommends programming the registers of the device in the following way:

1. Read-back factory default EEPROM page configuration. Each device will have different EEPROM base page

configuration.

2. Modify register bits.

3. Ensure that ee_lock is set to 5h (unlock) when overwriting the EEPROM.

4. Program register addresses in descending order from 0x53 to 0x00 including all register addresses with

reserved values.

9.5.2.3 EEPROM Access

NOTE

The EEPROM word write access time is typically 8 ms.

There are two methods to write into the internal EEPROM

1. Register Commit method.

2. EEPROM Direct Access Method

Use the following steps to bring the device into a good known configuration.

1. Power down all the supplies.

2. Apply PDN = LOW.

3. REFSEL and HW_SW_CTRL pins can be High, Low or High-Z. For factory programmed device, I²C interface

is not available when HW_SW_CTRL is LOW.

4. Apply power supplies to all VDD pins. When device operation is not required, apply power supply to

VDDREF.

5. Apply PDN = HIGH.

6. Use the I²C interface to configure the device.

9.5.2.3.1 Register Commit Flow

In the Register Commit flow, all bits from the device registers are copied into the EEPROM. The recommended

flow is:

1. Pre-configure the device as desired, except the serial interface using mode.

2. Write 1 to RECAL to calibrate the VCO in this operation mode.

3. Select the EEPROM page, to copy the register settings into, using REGCOMMIT_PAGE.

4. Unlock the EEPROM for write access with EE_LOCK = x5.

5. Start the register commit operation by writing 1 to REGCOMMIT.

6. Force a CRC update by writing a 1 to UPDATE_CRC.

7. Read back the calculated CRC in NVMLCRC.

8. Store the read CRC value in the EEPROM by writing 0x3F to NVM_WR_ADDR and then the CRC value to

NVM_WR_DATA.

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9.5.2.3.2 Direct Access Flow

In the EEPROM direct access flow, the EEPROM words are directly accessed using the address and the data

bit-fields. The recommended flow is:

1. Prepare an EEPROM image consisting of 64 words of 16 bits each.

2. Unlock the EEPROM for write access with EE_LOCK = 0x5.

3. Write the initial address offset to the address bit-field. Write a 0x00 to NVM_WR_ADDR.

4. Loop through the EEPROM image from address 0 to 63 by writing each word from the image to

NVM_WR_DATA. The EEPROM word address is automatically incremented by every write access to

NVM_WR_DATA.

Write Transfer

I²C register

offset

15

6

5

0

Reserved

NVM_WR_ADDR

0x0E

NVM_WR_DATA

0x0D

Read Transfer

I²C register

offset

15

6

5

0

Reserved

NVM_RD_ADDR

0x0B

0x0C

NVM_RD_DATA

Copyright

Figure 34. EEPROM Direct Access Using I²C

9.5.2.4 Register Bits to EEPROM Mapping

Register bits settings are mapped into EEPROM. EEPROM is divided into three segments:

•

EEPROM Base Page: Selectable by connecting HW_SW_CTRL pin either to Logic 0 to Logic 1.

EEPROM Page 0: Selectable by connecting HW_SW_CTRL pin to Logic 0.

EEPROM Page 1: Selectable by connecting HW_SW_CTRL pin to Logic 1.

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Table 21. EEPROM Mapping

15

14

1

13

1

12

1

11

10

9

8

7

6

5

4

3

2

1

0

1

2

3

0

R5[8] R5[7] R5[6] R5[5] R5[4] R5[1] R4[3] R4[2] R4[1] R4[0] R3[9] R0[3]

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R15[5]

1

0

1

0

R47[1 R47[1 R47[1

4

5

6

R48[4] R48[3] R48[2] R48[1] R48[0]

R47[9] R47[8] R47[7]

0

2]

1]

0]

R48[1 R48[1 R48[1 R48[1 R48[1

0

R49[4] R49[3] R49[2] R49[1] R49[0]

R48[9] R48[8] R48[7] R48[6] R48[5]

4]

1

3]

1

2]

0

1]

0

0]

0

R50[1

0]

0

R50[9] R50[8]

0

7

8

R55[6] R53[6]

1

0

R53[2] R53[1] R53[0]

1

0

1

0

1

0

R58[4] R58[3] R58[2] R58[1] R58[0]

R55[9] R55[8] R55[7]

R60[1 R60[1 R60[1 R60[1

9

0

1

R60[3] R60[2] R60[1] R60[0] R59[9] R59[8] R59[7] R59[6] R59[5] R59[4]

5]

4]

3]

2]

10

11

12

13

14

15

16

17

18

R65[8] R65[7] R65[6] R65[5] R65[4]

1

0

R64[9] R64[8] R64[7] R64[6] R64[5]

0

R69[9] R69[8] R69[7] R69[6] R69[5]

1

R66[3] R66[2] R66[1] R66[0] R65[9]

R74[5]

1

R71[3] R71[2] R71[1] R71[0] R70[9] R70[8] R70[7] R70[6] R70[5] R70[4]

1

0

R76[0] R75[9] R75[8] R75[7] R75[6] R75[5] R75[4]

1

0

R74[9] R74[8] R74[7] R74[6]

0

R79[3] R79[2] R79[1] R79[0] R76[9] R76[8] R76[7] R76[6] R76[3] R76[2] R76[1]

0

R81[3]

1

0

R80[3]

0

R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] R0[15] R0[14] R0[13] R0[12]

R0[10]

R0[8] R0[0]

R2[6] R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] R1[15] R1[14] R1[13] R1[12] R1[11] R1[10] R1[9] R1[8] R1[7]

R5[3] R5[2] R4[7] R4[6] R4[5] R4[4] R3[4] R3[3] R2[13] R2[12] R2[11] R2[10] R2[9] R2[8] R2[7]

R24[1 R24[1 R24[1 R24[1

0

19

20

21

R24[9] R24[8]

0

R24[5] R24[4] R24[3] R24[2] R24[1] R24[0]

0

5]

2]

1]

0]

R25[1 R25[1 R25[1 R25[1 R25[1

R27[0]

0

R25[9] R25[7] R25[6] R25[5] R25[4] R25[3] R25[2] R25[1] R25[0]

4]

3]

2]

1]

0]

R30[1 R30[1 R30[1 R30[1 R30[1

R30[9] R30[8] R30[7] R30[6] R30[5] R30[4] R30[3] R30[2] R30[1] R30[0] R27[1]

4]

3]

2]

1]

0]

R31[1 R31[1 R31[1 R31[1 R31[1 R31[1

22

23

24

R31[9] R31[8] R31[7] R31[6] R31[5] R31[4] R31[3] R31[2] R31[1] R31[0]

5]

4]

3]

2]

1]

0]

R33[7] R33[6] R33[5] R33[4] R33[3] R33[2] R33[1] R33[0] R32[7] R32[6] R32[5] R32[4] R32[3] R32[2] R32[1] R32[0]

R33[1 R33[1 R33[1 R33[1 R33[1 R33[1

R34[7] R34[6] R34[5] R34[4] R34[3] R34[2] R34[1] R34[0]

R43[1

R33[9] R33[8]

R41[1

5]

4]

3]

2]

1]

0]

25

26

27

28

29

30

31

32

R43[9] R43[8] R43[7] R43[6] R43[5] R43[4] R43[3] R43[2] R43[1] R43[0] R42[5] R42[3] R42[2] R42[1]

0]

5]

R51[1

0]

R43[1 R43[1 R43[1 R43[1 R43[1

0

1

R51[6]

0

R47[6] R47[5] R47[4] R47[3]

5]

4]

1

3]

0

2]

0

1]

0

R56[1

0]

R56[9] R56[8] R56[7] R56[6] R56[5] R56[4] R56[3] R56[2] R56[1] R56[0] R53[3]

R57[1 R57[1

R56[1 R56[1 R56[1 R56[1 R56[1

R57[9] R57[8] R57[7] R57[6] R57[5] R57[4] R57[3] R57[1] R57[0]

R60[1 R60[1

4]

2]

5]

4]

0]

3]

0]

3]

R62[9] R62[8] R62[7]

2]

1]

R59[1 R59[1 R59[1 R59[1 R59[1

R62[6] R62[5] R62[4] R62[3] R62[2] R62[1] R62[0]

R63[7] R63[6] R63[5] R63[4] R63[3] R63[1] R63[0]

R60[5] R60[4]

1]

0]

5]

1]

2]

1]

R62[1 R62[1 R62[1 R62[1 R62[1 R62[1

5]

4]

3]

2]

3]

2]

R65[1 R65[1 R65[1 R63[1 R63[1

R67[6] R67[5] R67[4] R67[3] R67[2] R67[1] R67[0] R66[5] R66[4]

R63[9] R63[8]

R67[9] R67[8] R67[7]

4]

R67[1 R67[1 R67[1 R67[1 R67[1 R67[1

2]

R68[7] R68[6] R68[5] R68[4] R68[3] R68[1] R68[0]

5]

4]

3]

(1) Address Locations 0-15: EEPROM Base Page

(2) Address Locations 16-39: EEPROM Page 0

(3) Address Locations 40-63: EEPROM Page 1

(4) Bit locations marked in Red may vary from device to device

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(1) (2) (3)

Table 21. EEPROM Mapping

⁽⁴⁾(continued)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R68[9] R68[8]

R72[9] R72[8] R72[7]

R71[1

0]

R70[1 R68[1 R68[1

1]

33

34

35

36

R72[6] R72[5] R72[4] R72[3] R72[2] R72[1] R72[0]

R73[7] R73[6] R73[5] R73[4] R73[3] R73[1] R73[0]

R71[9] R71[5] R71[4]

3]

2]

R72[1 R72[1 R72[1 R72[1 R72[1 R72[1

5]

4]

3]

2]

1]

0]

R75[1 R75[1 R75[1 R75[1 R75[1 R73[1 R73[1

0

R77[1] R77[0] R76[5] R76[4]

R73[9] R73[8]

5]

0

4]

0

3]

2]

1]

0

3]

0

2]

0

R78[1

2]

0

R79[9]

0

37

38

39

40

41

42

0

1

0

R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] R0[15] R0[14] R0[13] R0[12]

R0[10]

R0[8] R0[0]

R2[6] R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] R1[15] R1[14] R1[13] R1[12] R1[11] R1[10] R1[9] R1[8] R1[7]

R5[3] R5[2] R4[7] R4[6] R4[5] R4[4] R3[4] R3[3] R2[13] R2[12] R2[11] R2[10] R2[9] R2[8] R2[7]

R24[1 R24[1 R24[1 R24[1

0

43

44

45

R24[9] R24[8]

0

R24[5] R24[4] R24[3] R24[2] R24[1] R24[0]

0

5]

2]

1]

0]

R25[1 R25[1 R25[1 R25[1 R25[1

4]

R27[0]

0

R25[9] R25[7] R25[6] R25[5] R25[4] R25[3] R25[2] R25[1] R25[0]

3]

2]

1]

0]

R30[1 R30[1 R30[1 R30[1 R30[1

4]

R30[9] R30[8] R30[7] R30[6] R30[5] R30[4] R30[3] R30[2] R30[1] R30[0] R27[1]

3]

2]

1]

0]

R31[1 R31[1 R31[1 R31[1 R31[1 R31[1

46

47

48

R31[9] R31[8] R31[7] R31[6] R31[5] R31[4] R31[3] R31[2] R31[1] R31[0]

5]

4]

3]

2]

1]

0]

R33[7] R33[6] R33[5] R33[4] R33[3] R33[2] R33[1] R33[0] R32[7] R32[6] R32[5] R32[4] R32[3] R32[2] R32[1] R32[0]

R33[1 R33[1 R33[1 R33[1 R33[1 R33[1

R34[7] R34[6] R34[5] R34[4] R34[3] R34[2] R34[1] R34[0]

R33[9] R33[8]

5]

4]

3]

2]

1]

0]

R43[1

0]

R41[1

49

50

51

52

53

54

55

56

57

58

59

60

R43[9] R43[8] R43[7] R43[6] R43[5] R43[4] R43[3] R43[2] R43[1] R43[0] R42[5] R42[3] R42[2] R42[1]

5]

R43[1 R43[1 R43[1 R43[1 R43[1

R51[1

0]

0

1

R51[6]

0

R47[6] R47[5] R47[4] R47[3]

5]

4]

3]

2]

1]

R56[1

0]

R56[9] R56[8] R56[7] R56[6] R56[5] R56[4] R56[3] R56[2] R56[1] R56[0] R53[3]

1

0

R57[1 R57[1

4]

R56[1 R56[1 R56[1 R56[1 R56[1

R57[9] R57[8] R57[7] R57[6] R57[5] R57[4] R57[3] R57[1] R57[0]

R60[1 R60[1

2]

5]

4]

0]

3]

0]

3]

R62[9] R62[8] R62[7]

2]

1]

R59[1 R59[1 R59[1 R59[1 R59[1

R62[6] R62[5] R62[4] R62[3] R62[2] R62[1] R62[0]

R63[7] R63[6] R63[5] R63[4] R63[3] R63[1] R63[0]

R60[5] R60[4]

1]

0]

5]

1]

2]

1]

R62[1 R62[1 R62[1 R62[1 R62[1 R62[1

5]

4]

3]

2]

3]

2]

R71[9] R71[5] R71[4]

R65[1 R65[1 R65[1 R63[1 R63[1

R67[6] R67[5] R67[4] R67[3] R67[2] R67[1] R67[0] R66[5] R66[4]

R63[9] R63[8]

4]

R67[1 R67[1 R67[1 R67[1 R67[1 R67[1

5]

2]

R68[7] R68[6] R68[5] R68[4] R68[3] R68[1] R68[0]

R72[6] R72[5] R72[4] R72[3] R72[2] R72[1] R72[0]

R73[7] R73[6] R73[5] R73[4] R73[3] R73[1] R73[0]

R67[9] R67[8] R67[7]

4]

3]

1]

R71[1

0]

R70[1 R68[1 R68[1

1]

R68[9] R68[8]

3]

2]

R72[9] R72[8] R72[7]

R72[1 R72[1 R72[1 R72[1 R72[1 R72[1

5]

4]

3]

2]

1]

0]

R75[1 R75[1 R75[1 R75[1 R75[1 R73[1 R73[1

0

R77[1] R77[0] R76[5] R76[4]

R73[9] R73[8]

5]

0

4]

0

3]

2]

1]

0

3]

0

2]

0

R78[1

2]

0

R79[9]

0

61

62

0

SCRC SCRC SCRC SCRC SCRC SCRC SCRC SCRC SCRC SCRC SCRC SCRC SCRC SCRC SCRC SCRC

[15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

63

36

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Table 22. Register Defaults in Fall-Back Mode and EEPROM Mode

REGISTER

ADDRESSES

FALL-BACK

MODE

HW_SW_CTRL = HW_SW_CTRL =

REGISTER

ADDRESSES

FALL-BACK

MODE

HW_SW_CTRL = HW_SW_CTRL =

0

1

0

1

R85

R84

R83

R82

R81

R80

R79

R78

R77

R76

R75

R74

R73

R72

R71

R70

R69

R68

R67

R66

R65

R64

R63

R62

R61

R60

R59

R58

R57

R56

R55

R54

R53

R52

R51

R50

R49

R48

R47

R46

R45

R44

R43

x0000

x0004

x0000

x0008

x1000

x0000

x0008

xA181

x2000

x0006

x0000

x0008

xA181

x2000

x0006

x0000

x0008

xA181

x2000

x0006

x0000

x0008

x502C

x4000

x0006

x001E

x3400

x0069

x5000

x40C0

x01C0

x0013

x1A14

x0A00

x0000

x4F80

x0318

x0051

x0000

xFF00

x01C0

x0004

x0008

x0000

x0002

x0188

x0008

xA181

x2000

x0006

x0406

x0008

xA181

x2000

x0006

x4008

xA181

x2000

x0006

x0000

x0008

x502C

x4000

x0006

x001E

x3400

x0069

x5000

x40C0

x01C0

x0013

x1A05

x0280

x0000

x4F80

x0318

x0051

x0000

xFF00

x01C0

x0004

x0008

x0000

x0002

x0188

x8008

xA181

x0000

x0006

x0406

x0808

xA181

x0000

x0006

x4808

xA181

x0000

x0006

x0000

x6028

x8008

x502C

x0000

x0006

x001E

x3400

x0069

x5000

x40C0

x01C0

x0013

x1A05

x0280

x0000

x4F80

x0318

x0051

R42

R41

R40

R39

R38

R37

R36

R35

R34

R33

R32

R31

R30

R29

R28

R27

R26

R25

R24

R23

R22

R21

R20

R19

R18

R17

R16

R15

R14

R13

R12

R11

R10

R9

x0002

x0000

x0030

x0000

x0005

x0000

x0400

x0718

x0000

x06A2

x0000

x26C4

x921F

xA037

x0000

x0008

x0000

x2310

x0000

x0002

x0000

x0028

x0000

x0030

x0000

x0004

x0000

x0400

x091C

x2406

x06A2

x0590

x0000

x26C4

x921F

xA037

x0000

xA777

x7BFA

x0001

x0C2D

x0E6C

x0008

x0000

x0200

x0000

x7654

x0001

x0002

x0000

x0028

x0000

x0030

x0000

x0004

x0000

x0400

x091C

x2406

x06A2

x0513

x0000

x26C4

x921F

xA037

x0000

x7002

x003F

xA777

x0001

x0C0D

x0E6C

x0008

x0000

x0200

x0000

x7652

x2000

R8

R7

R6

R5

R4

R3

R2

R1

R0

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

A typical application using the I²C interface and a 25-MHz crystal input is shown in Figure 35. The two ends of

25-MHz XTAL are connected to pin 1 and 2. The REFSEL pin is pulled down to select a secondary input. The

HW_SW_CTRL can be pulled either low or high if EEPROM is used, or kept floating if EEPROM is unused. 1.8

V, 2.5 V, or 3.3 V can be supplied to the VDD_REF and VDD_VCO pins, as well as VDDO_12 and VDDO_34

pins with filtering. Data and clock lines of I2C must be pulled to VDD_REF using pullup resistors. The PDN can

be connected to the MCU if a hardware reset is required, otherwise it can be left floating. The GPIO1 and 4 pins

can be connected to the MCU if needed, otherwise they can be left floating. Unused outputs can be left floating.

1.8V

/ 2.5V

/ 3.3V

1.8V

/ 2.5V

/ 3.3V

1.8V

/ 2.5V

/ 3.3V

1.8V

/ 2.5V

/ 3.3V

VDD_REF

VDD_VCO

VDDO_12

VDDO_34

SECREF_P

OUT0

OUT1_P

OUT1_N

OUT2_P

OUT2_N

OUT3_P

OUT3_N

OUT4_P

OUT4_N

100 nF

25 MHz

SECREF_N

PDN

100 nF

MCU_GPIO

U1

CDCE6214

100 nF

REFSEL

HW_SW_CTRL

100 nF

VDD_REF

DAP

100 nF

GND

GPIO4

SCL/GPIO3

SDA/GPIO2

GPIO1

MCU_GPIO

MCU_I2C_SCL

MCU_I2C_SDA

MCU_GPIO

Figure 35. Typical Application Schematic With I²C Interface

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10.2 Typical Application

Figure 36 shows typical block diagram for eAVB system using CDCE6214.

25MHz

XTAL

PFD

Output

Divider

2.4576GHz

VCO

Audio CODEC

N Div

98.304

Output

Divider

CDCE6214

Processor

PTP

TS

PHY

CNT1

I²C

MAC

CMP

(freq inc/dec by

< 1ppm steps)

CNT1

Figure 36. eAVB System Block Diagram Using CDCE6214

10.2.1 Design Requirements

For designs with the CDCE6214, the designer must select:

•

a primary or secondary input

an input type

an input frequency

a device communication mode (I²C and/or EEPROM)

the required device operation modes to configure the connections of GPIO pins

a supply voltage (1.8 V, 2.5 V, or 3.3 V)

a digital reference (1.8 V, 2.5 V, or 3.3 V)

an output reference (1.8 V, 2.5 V, or 3.3 V)

an output format

10.2.2 Detailed Design Procedure

The CDCE6214 is designed for ease-of-use. To power up the device:

1. Either tie the power supply pin (VDD_REF, VDD_VCO, VDDO_12 and VDDO_34) together or independently

connect them to the 1.8-V, 2.5-V, or 3.3-V power supply.

2. Solder the GND Pin (DAP) to the PCB Plane.

3. Ensure that the REFSEL, HW_SW_CTRL, and PDN configuration pins are appropriately connected:

1. Internally connect the PDN pin to VDD_REF through a pullup resistor. When floating, the PDN pin would

automatically release device from PDN.

2. If PDN pin is low, the device will not respond to I2C commands.

3. REFSEL and HW_SW_CTRL are tri-level pins. If left floating, the device will start in fall-back mode.

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Typical Application (continued)

The device is factory-configured to provide:

•

100-MHz LVDS with 25-MHz XTAL when HW_SW_CTRL=L. The 25-MHz output on OUT0 is enabled.

100-MHz LP-HCSL with 25-MHz XTAL and HW_SW_CTRL = H. The 25-MHz output on OUT0 is enabled.

10.2.3 Application Curves

Reference: Crystal

Input 25 MHz

Closed-Loop

Phase Noise from

2.4-GHz VCO

100-MHz LP-HCSL

Reference: Crystal

Input 25 MHz

Closed-Loop

Phase Noise from

2.4576-GHz VCO

24.576-MHz

LVCMOS

Figure 37. 100-MHz LP-HCSL Output for PCIe Application

Figure 38. 24.576MHz LVCMOS Output for Audio Clocking

11 Power Supply Recommendations

The CDCE6214 provides multiple power supply pins. Each power supply supports 1.8 V, 2.5 V, or 3.3 V. Internal

low-dropout regulators (LDO) source the internal blocks and allow each pin to be supplied with its individual

supply voltage. The VDD_REF pin supplies the control pins and the serial interface. Therefore, any pullup

resistors shall be connected to the same domain as VDD_REF. VDD_VCO powers all PLL blocks. VDDO_12

powers outputs OUT1 and OUT2. VDDO_34 powers OUT0, OUT3, and OUT4.

VDD_REF and VDDO_34 can be used for level translation operation on OUT0.

11.1 Power-Up Sequence

There are no restrictions from the device for applying power to the supply pins. From an application perspective,

TI recommends to either apply all the VDDs at the same time or apply the VDDREF first. The digital core is

connected to VDDREF and thus the settings of the EEPROM are applied automatically.

11.2 Decoupling

TI recommends isolating all power supplies using a ferrite bead and provide decoupling for each of the supplies.

TI also recommends optimizing the decoupling for the respective layout, and consider the power supply

impedance to optimize for the individual frequency plan.

An example for a decoupling per supply pin: 1x 4.7 µF, 1x 470 nF, and 1x 100 nF.

40

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12 Layout

12.1 Layout Guidelines

For this example, follow these guidelines:

•

Isolate inputs and outputs using a GND shield. routes all inputs and outputs as differential pairs.

Isolate outputs to adjacent outputs when generating multiple frequencies.

Isolate the crystal area, connect the GND pads of the crystal package and flood the adjacent area. Figure 40

shows a foot print which supports multiple crystal sizes.

•

Try to avoid impedance jumps in the fan-in and fan-out areas when possible.

Use five VIAs to connect the thermal pad to a solid GND plane. Full-through VIAs are preferred.

Place decoupling capacitors with small capacitance values very close to the supply pins. Try to place them

very close on the same layer or directly on the backside layer. Larger values can be placed more far away.

Figure 40 shows three decoupling capacitors close to the device. Ferrite beads are recommended to isolate

the different frequency domains and the VDD_VCO domain.

•

Preferably use multiple VIAs to connect wide supply traces to the respective power planes.

12.2 Layout Examples

Figure 39. Layout Example, Top Layer

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Layout Examples (continued)

Figure 40. Layout Example, Bottom Layer

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Development Support

Contact your TI representative for more information.

13.1.2 Device Nomenclature

CDCE6214 - 62= clock generator 1= 1x PLL 4=4x outputs

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RGE 24

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4204104/H

PACKAGE OUTLINE

RGE0024P

VQFN - 0.9 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

4.1

3.9

0.1 MIN

(0.05)

A

-

A

4

0

.

0

SECTION A-A

TYPICAL

0.9

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

SYMM

(0.2) TYP

A2

A3

7

12

(0.25) TYP

EXPOSED

THERMAL PAD

6

13

SYMM

25

A

2X 2.5

2.7 0.1

20X 0.5

18

1

PIN 1 ID

A1

0.3

0.2

A4

24X

24

19

0.1

C A B

0.5

0.3

24X

(0.25) TYP

0.05

4X ( 0.25)

4224751/A 01/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RGE0024P

VQFN - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.7)

SYMM

SEE SOLDER MASK

DETAIL

24

19

A1

A4

24X (0.6)

1

18

24X (0.25)

SYMM

20X (0.5)

(3.8)

25

(

0.2) TYP

(1.1)

VIA

(1.75)

13

6

A2

(R0.05) TYP

A3

4X ( 0.25)

7

12

(1.75)

(1.1)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224751/A 01/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RGE0024P

VQFN - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.695)

19

24

A1

A4

24X (0.6)

1

18

24X (0.25)

20X (0.5)

(0.695)

(3.8)

25

SYMM

4X ( 1.19)

13

(1.75)

6

A2

(R0.05) TYP

4X ( 0.25)

A3

7

12

(1.75)

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 25

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4224751/A 01/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CDCE6214RGER
厂家：	TEXAS INSTRUMENTS
描述：	具有一个 PLL、四个差分输出的超低功耗时钟发生器 \| RGE \| 24 \| -40 to 105 时钟时钟发生器
文件：	总55页 (文件大小：5707K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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