CDCE6214TWRGETQ1 [TI]
支持第 1-5 代 PCIe 且具有 2 个输入、4 个输出和内部 EEPROM 的超低功耗时钟发生器 | RGE | 24 | -40 to 105;
| 型号： | CDCE6214TWRGETQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 支持第 1-5 代 PCIe 且具有 2 个输入、4 个输出和内部 EEPROM 的超低功耗时钟发生器 | RGE | 24 | -40 to 105 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 PC 外围集成电路 晶体 时钟发生器 |
| 文件： | 总53页 (文件大小：4387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCE6214-Q1
ZHCSK34B –JULY 2020 –REVISED OCTOBER 2021
具有一个PLL、四个差分输出、两个输入和内部EEPROM 的CDCE6214-Q1 超
低功耗时钟发生器
– 兼容I2C 的接口：频率高达400kHz
– 具有两个页面和外部选择引脚的集成
1 特性
EEPROM。可现场编程。
• 支持100Ω系统
• 电磁辐射低
• 符合面向汽车应用的AEC-Q100 标准
– 温度等级2：-40°C 至+105°C
• 提供功能安全
• 小尺寸：24 引脚VQFN (4mm × 4mm)
– 可帮助进行功能安全系统设计的文档
• 通过RMS 抖动和杂散（12kHz –20MHz，Fout
>
2 应用
100MHz）可将高性能、低功耗分数N PLL 配置如
下：
– 整数模式：
• PCIe 第1 至5 代时钟
• 高级驾驶辅助系统(ADAS) - 传感器融合
• 信息娱乐和仪表组- 汽车音响主机- eAVB
• 数据中心和企业计算、PC 与笔记本电脑
• 企业机器- 多功能打印机
• 差分输出：典型值350fs，最大值600fs
• LVCMOS 输出：典型值1.05ps，最大值
1.5ps
• 测试和测量、手持设备
– 分数模式：
3 说明
• 差分输出：典型值1.7ps，最大值2.1ps
• LVCMOS 输出：典型值2.0ps，最大值
4.0ps
CDCE6214-Q1 是一款适合汽车应用的四通道、超低功
耗、中级抖动时钟发生器，可生成五个在各种驱动器模
式之间可选的独立时钟输出。输入源可以是单端或差分
输入时钟源，也可以是晶振。CDCE6214-Q1 具有一个
分数 N PLL，可在任何输入频率下合成不相关的基础
频率。CDCE6214-Q1 可通过I2C 接口进行配置。无串
行接口时，可以在引脚模式下将 GPIO 引脚用于对产
品进行独特配置。
• 支持有SSC 的PCIe Gen1/2/3/4 和无SSC 的Gen
1/2/3/4/5
• 内部VCO 频率范围为2.335GHz 至2.625GHz
• 典型功耗：4 输出通道为65mA，单输出通道为
23mA。
• 通用时钟输入、两个用于提供冗余支持的基准输入
– 差分交流耦合或LVCMOS：10MHz 至200MHz
– 晶振：10MHz 至50MHz
器件信息(1)
封装尺寸（标称值）
器件型号
封装
VQFN (24)
• 灵活的输出时钟分配
CDCE6214-Q1
4.00mm × 4.00mm
– 4 通道分频器：多达5 个独特输出频率，范围为
24kHz 至328.125MHz
– OUT0 –OUT4 引脚具有类似LVDS、LP-
HCSL 或LVCMOS 输出
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
Voltage Domain
1.8V / 2.5V / 3.3V
FPGA
– 无毛刺输出分频器切换和输出通道同步
– 通过GPIO 和寄存器实现独立输出使能端
• 频率裕量选项
Crystal
DAC
– DCO 模式：频率以10ppb 或更小的阶跃幅度递
增/递减
Voltage Domain
1.8V / 2.5V / 3.3V
CDCE6214
• 完全集成的可配置环路带宽：100kHz 至1.6MHz
• 单电源或混合电源可进行电平转换：1.8V/2.5V/
3.3V
MCU
Ethernet
LVCMOS
Crystal Copy
PCIe
Voltage Domain
1.8V / 2.5V / 3.3V
• 可配置GPIO 和灵活配置选项
应用示例CDCE6214-Q1
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS786
CDCE6214-Q1
ZHCSK34B –JULY 2020 –REVISED OCTOBER 2021
www.ti.com.cn
Table of Contents
7.25 Typical Characteristics............................................13
8 Parameter Measurement Information..........................15
8.1 Reference Inputs.......................................................15
8.2 Outputs..................................................................... 15
8.3 Serial Interface..........................................................16
8.4 PSNR Test................................................................ 16
8.5 Clock Interfacing and Termination.............................16
9 Detailed Description......................................................18
9.1 Overview...................................................................18
9.2 Functional Block Diagram.........................................18
9.3 Feature Description...................................................18
9.4 Device Functional Modes..........................................30
9.5 Programming............................................................ 30
10 Application and Implementation................................39
10.1 Application Information........................................... 39
10.2 Typical Application.................................................. 40
11 Power Supply Recommendations..............................42
11.1 Power-Up Sequence...............................................42
11.2 Decoupling.............................................................. 42
12 Layout...........................................................................43
12.1 Layout Guidelines................................................... 43
12.2 Layout Examples.................................................... 43
13 Device and Documentation Support..........................45
13.1 Device Support....................................................... 45
13.2 接收文档更新通知................................................... 45
13.3 支持资源..................................................................45
13.4 Trademarks.............................................................45
13.5 Electrostatic Discharge Caution..............................45
13.6 术语表..................................................................... 45
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 EEPROM Characteristics............................................6
7.6 Reference Input, Single-Ended Characteristics..........6
7.7 Reference Input, Differential Characteristics.............. 6
7.8 Reference Input, Crystal Mode Characteristics.......... 6
7.9 General-Purpose Input Characteristics.......................7
7.10 Triple Level Input Characteristics..............................7
7.11 Logic Output Characteristics.....................................7
7.12 Phase Locked Loop Characteristics......................... 7
7.13 Closed-Loop Output Jitter Characteristics................ 8
7.14 Input and Output Isolation.........................................8
7.15 Buffer Mode Characteristics......................................8
7.16 PCIe Spread Spectrum Generator............................8
7.17 LVCMOS Output Characteristics.............................. 9
7.18 LP-HCSL Output Characteristics.............................. 9
7.19 LVDS Output Characteristics.................................. 10
7.20 Output Synchronization Characteristics..................10
7.21 Power-On Reset Characteristics.............................10
7.22 I2C-Compatible Serial Interface Characteristics......11
7.23 Timing Requirements, I2C-Compatible Serial
Information.................................................................... 45
Interface.......................................................................11
7.24 Power Supply Characteristics................................. 11
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2019) to Revision B (October 2021)
Page
• 向特性部分添加了功能安全要点........................................................................................................................ 1
Changes from Revision * (August 2019) to Revision A (December 2019)
Page
• 将数据表状态从“预告信息”更改为：量产数据................................................................................................ 1
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5 说明（续）
片上 EEPROM 可用于更改配置，通过引脚可预选配置。该器件可提供频率裕量选项和无干扰运行功能，以支持
系统设计验证测试 (DVT) 和以太网音频/视频桥接(eAVB)。通过将分数反馈分频器转为 DCO 模式，任何输出通道
上均可使用精细频率裕量。
内部电源调节功能可提供出色的电源纹波抑制(PSRR)，从而降低供电网络的成本和复杂性。模拟和数字核心块由
1.8V、2.5V 或3.3V ±5% 电源供电运行，输出块由1.8V、2.5V 或3.3V ±5% 电源供电运行。
CDCE6214-Q1 采用小外形封装，具有超低功耗，可根据单个基准实现高性能时钟树。工厂和用户可编程的
EEPROM 特性使得CDCE6214-Q1 成为一款低功耗、方便易用、瞬时启动的时钟器件。
6 Pin Configuration and Functions
SECREF_P
SECREF_N
VDD_REF
REFSEL
1
2
3
4
5
6
18
17
16
15
14
13
OUT2_P
OUT2_N
VDDO_12
VDDO_34
OUT3_P
OUT3_N
DAP
PRIREF_P
PRIREF_N
Not to scale
图6-1. CDCE6214-Q1 RGE Package 24-Pin VQFN Top View
表6-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
POWER
Die Attach Pad. The DAP is an electrical connection and provides a thermal dissipation path.
For proper electrical and thermal performance of the device, the DAP must be connected to
PCB ground plane.
DAP
G
—
VDD_REF
VDD_VCO
VDDO_12
VDDO_34
3
P
P
P
P
1.8 V/2.5 V/3.3 V Power Supply for Reference Input and Digital.
1.8 V/2.5 V/3.3 V Power Supply for PLL/VCO.
24
16
15
1.8 V/2.5 V/3.3 V Power Supply for OUT1 and OUT2 channels
1.8 V/2.5 V/3.3 V Power Supply for OUT0, OUT3, and OUT4 channels
INPUT BLOCK
HW_SW_CT
RL
Manual selection pin for EEPROM pages (3-state). Weak Pullup/Pulldown. RPU = 50 kΩ.
RPD = 50 kΩ.
23
I, RPUPD
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表6-1. Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NAME
NO.
PRIREF_P
5
I
I
Primary reference clock. Accepts a differential or single-ended input. Input pins need AC-
coupling capacitors and internally biased in differential mode. For LVCMOS, input should be
provided on PRIREF_P and the non-driven input pin should be pulled down to ground.
Internal biasing for differential mode is disabled in single-ended mode.
PRIREF_N
6
Manual selection pin of reference input (3-state). Weak Pullup/Pulldown. RPU = 50 kΩ. RPD
= 50 kΩ.
REFSEL
4
1
I, RPUPD
I
SECREF_P
Secondary reference clock. Accepts a differential or single-ended input or XTAL. Input pins
need AC-coupling capacitors and internally biased in differential mode. For XTAL input,
connect crystal between SECREF_P and SECREF_N pin. SECREF_P is XOUT,
SECREF_N is XIN. This device do not need any power limiting resistor on XOUT. For
LVCMOS input, input should be provided on SECREF_P, and the non-driven input pin
should be pulled down to ground. Internal biasing for differential mode is disabled in single-
ended and XTAL mode.
SECREF_N
2
I
OUTPUT BLOCK
OUT0
LVCMOS Output 0. Reference Input can be bypassed into this output. Output slew-rate
configurable on all LVCMOS outputs.
7
O
OUT1_P
OUT1_N
OUT2_P
OUT2_N
OUT3_P
OUT3_N
OUT4_P
OUT4_N
22
21
18
17
14
13
10
9
O
O
O
O
O
O
O
O
LVDS-like/LP-HCSL/LVCMOS Output Pair 1. Programmable driver with LVDS-like/LP-HCSL
or 2x LVCMOS outputs.
LVDS-like/LP-HCSL Output Pair 2. Programmable driver with LVDS-like/LP-HCSL outputs.
LVDS-like/LP-HCSL Output Pair 3. Programmable driver with LVDS-like/LP-HCSL outputs.
LVDS-like/LP-HCSL/LVCMOS Output Pair 4. Programmable driver with LVDS-like/LP-HCSL
or 2x LVCMOS outputs.
DIGITAL CONTROL / INTERFACES
STATUS output or GPIO1 input. Weak pullup resistor when configured as Input. RPU = 50
kΩ. Pullup resistor disabled in output mode.
GPIO1
GPIO4
PDN
20
11
8
I/O, RPU
I/O, RPU
I, RPU
STATUS output or GPIO4 input. Weak pullup resistor when configured as Input. RPU = 50
kΩ. Pullup resistor disabled in output mode.
Device Power-down/RESET (active low) or SYNCN. Weak pullup resistor. RPU = 50 kΩ.
Pullup resistor disabled in output mode.
I2C Serial Data (bidirectional, open-drain) or GPIO2 input. Requires an external pullup
resistor to VDD_REF in I2C mode. I2C slave address is initialized from on-chip EEPROM.
Fail-safe Input.
SDA/GPIO2
19
12
I/O
I
I2C Serial Clock or GPIO3 input. Requires an external pullup resistor to VDD_REF in I2C
mode. Fail-safe Input.
SCL/GPIO3
(1) Type:
•
•
•
•
•
•
•
•
G = Ground
P = Power
I = Input
I/O = Input/Output
O = Output
I, RPUPD = Input with Resistive Pullup and Pulldown
I, RPU = Input with Resistive Pullup
I/O, RPU = Input/Output with Resistive Pullup
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VDD_REF, VDD_VCO, VDDO_12, VDDO_34
PRIREF_P, PRIREF_N, SECREF_P, SECREF_N
Supply Voltage
Input Voltage
-0.3
3.63
V
VDD_REF +
0.3
-0.3
-0.3
-0.3
V
V
V
GPIO1, SDA/GPIO2, SCL/GPIO3, GPIO4, REFSEL, HW_SW_CTRL,
PDN
VDD_REF +
0.3
Input Voltage
OUT0, OUT1_P, OUT1_N, OUT2_P, OUT2_N, OUT3_P, OUT3_N,
OUT4_P, OUT4_N(2)
VDDO_X(2)
+
Output Voltage
0.3
125
150
TJ
Junction Temperature
Storage temperature
°C
°C
Tstg
-65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDDO_X refers to the output supply for a specific output channel, where X denotes the channel index.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002, HBM ESD Classification Level
2(1)
2000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level
C5
750
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD_VCO
Core supply voltage
Output supply voltage
1.71
1.8, 2.5, 3.3
3.465
V
VDDO_12,
VDDO_34
1.71
1.8, 2.5, 3.3
1.8, 2.5, 3.3
3.465
V
VDD_REF
TA
Reference supply voltage
1.71
-40
3.465
105
125
145
30
V
Ambient temperature
°C
°C
°C
ms
TJ
Junction temperature
-40
TLOCK
tRAMP
Continuous lock over temperature (without VCO calibration)
Maximum supply voltage ramp time(1)
0.1
(1) VDD pin should monotonically reach 95% of its final value within supply ramp time. All VDD pins were tied together for this evaluation.
For non-monotonic or slower power supply ramp, it is recommended to pull-down PDN pin until VDD pins have reached 95% of its final
value. PDN pin has a 50 kΩ pullup resistor. When PDN pin cannot be actively controlled, TI recommends to add a capacitor to GND on
PDN pin to delay the release of reset.
7.4 Thermal Information
CDCE6214-Q1
THERMAL METRIC(1)
RGE (VQFN)
24 PINS
32.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
RθJC(bot)
ψJT
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
32.5
12.2
Junction-to-case (bottom) thermal resistance
Junction-to-top characterization parameter
2.0
0.4
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CDCE6214-Q1
RGE (VQFN)
24 PINS
THERMAL METRIC(1)
UNIT
Junction-to-board characterization parameter
12.2
°C/W
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 EEPROM Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
cycles
years
nEEcyc
tEEret
EEPROM programming cycles
EEPROM data retention
each word
10
10
7.6 Reference Input, Single-Ended Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN_Ref
VIH
Reference frequency
10
200
MHz
0.8 ×
VDD_REF
Input high voltage
Input low voltage
LVCMOS Input Buffer
V
V
0.2 ×
VDD_REF
VIL
LVCMOS Input Buffer
20% - 80%
dVIN/dT
IDC
Input slew rate
1
40
V/ns
%
Input duty cycle
60
100
5
IIN_LEAKAGE
CIN_REF
Input leakage current
Input capacitance
-100
µA
pF
at 25°C
7.7 Reference Input, Differential Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN_Ref
Reference frequency
10
200
MHz
Differential input voltage swing, peak-to-
peak
VIN_DIFF
VDD_REF = 2.5 V/3.3 V
0.4
0.4
1.6
1.0
V
V
Differential input voltage swing, peak-to-
peak
VIN_DIFF
VDD_REF = 1.8 V
20% - 80%
dVIN/dT
IDC
Input slew rate
1
40
V/ns
%
Input duty cycle
60
IIN_LEAKAGE
CIN_REF
Input leakage current
Input capacitance
-100
100
µA
pF
at 25°C
5
7.8 Reference Input, Crystal Mode Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
Ω
fIN_Xtal
ZESR
ZESR
ZESR
Crystal frequency
Fundamental mode
10
50
Crystal equivalent series resistance
Crystal equivalent series resistance
Crystal equivalent series resistance
fXTAL = 10 MHz to 16 MHz
fXTAL = 16 MHz to 30 MHz
fXTAL = 30 MHz to 50 MHz
60
50
Ω
30
Ω
Using on-chip load capacitance. A
supported Crystal is within
CL
Crystal load capacitance
5
3
12.8
pF
PXTAL
Crystal tolerated drive power
On-Chip load capacitance
A supported crystal tolerates up to
Programmable in typ. 200 fF steps
200
9.1
µW
pF
CXIN_LOAD
(1) For detailed application report on configuring the XTAL Input, please refer to SNAA331: CDCI6214 and CDCE6214-Q1 design with
crystal input.
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7.9 General-Purpose Input Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.8 ×
VDD_REF
VIH
VIL
Input high voltage
V
0.2 ×
VDD_REF
Input low voltage
V
IIH
Input high level current
Input low level current
Input low level current
Input slew rate
VIH = VDD_REF, GPIO[1:4], PDN
VIL = GND, GPIO[2:3]
-5
-5
5
5
µA
µA
IIL
IIL
VIL = GND, GPIO[1], GPIO[4], PDN
20% - 80%
-100
0.5
100
µA
dVIN/dT
V/ns
TPULSE_WIDT
Pulse width for correct operation
10
30
ns
H
RPU
CIN
Pullup Resistance
Pin Capacitance
Pins PDN, GPIO[1], GPIO[4]
55
80
10
kΩ
pF
7.10 Triple Level Input Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.8 ×
VDD_REF
VIH
VIM
VIL
Input high voltage
V
0.41 ×
VDD_REF
0.5 ×
VDD_REF
0.58 ×
VDD_REF
Input mid voltage
Input low voltage
Float pin
V
V
0.2 ×
VDD_REF
IIH
IIL
Input high level current
Input low level current
VIH = VDD_REF
VIL = GND
20
50
100
-20
µA
µA
-100
-50
7.11 Logic Output Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.8 ×
VDD_REF
VOH
VOL
Output high voltage
V
0.2 ×
VDD_REF
Output low voltage
V
7.12 Phase Locked Loop Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
fPFD
fVCO
fBW
Phase Detector Frequency
Voltage Controlled Oscillator Frequency
Integer and Fractional PLL mode
1
100
2335
100
2625
1600
MHz
Configurable closed-loop PLL Bandwidth REF = 25 MHz
kHz
KVCO
KVCO
Voltage-Controlled Oscillator Gain
Voltage-Controlled Oscillator Gain
fVCO = 2.4 GHz
fVCO = 2.5 GHz
140
175
MHz/V
MHz/V
Allowable Temperature Drift for
Continuous Lock(1)
145
0.1
oC
|ΔTCL
|
dT/dt ≤20 K / min
fMAX-ERROR
Maximum frequency error with frac-N PLL
ppm
(1) The maximum allowable temperature drift for continuous lock: how far the temperature can drift in either direction from the value it was
at the time, when the On-Chip VCO was calibrated while the PLL stays in lock throughout the temperature drift. The internal VCO
calibration takes place: at device start-up, when the device is reset using the RESET pin and when REGISTER bit is changed. This
implies the device will work over the entire frequency range, but if the temperature drifts more than the 'maximum allowable
temperature drift for continuous lock', then it is necessary to re-calibrate the VCO, using the appropriate REGISTER bit, to ensure the
PLL stays in lock. Regardless of what temperature the part was initially calibrated at, the temperature can never drift outside the
ambient temperature range of -40° C to 105° C.
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7.13 Closed-Loop Output Jitter Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RMS jitter with spurs from 12 kHz to 20
MHz , Input Crystal = 25 MHz, Differential
OUTx > 100 MHz, int-PLL
tRJ_CL
RMS Phase Jitter
350
600
fs
RMS jitter with spurs from 12 kHz to 20
MHz, Input Crystal = 25 MHz, Differential
OUTx > 100 MHz, frac-PLL
tRJ_CL
RMS Phase Jitter(1)
RMS Phase Jitter
1600
475
2100
fs
fs
PCIe Gen 3 Filter applied, XIN = Crystal
25 MHz, OUTx = 100 MHz, frac-N PLL
with and without SSC, LP-HCSL or LVDS
output
tRJ_CL, PCIE
1000
(1) FIN = 25MHz, FOUT= 161.1328MHz, FPFD = 25MHz, RMS Noise = 1.83ps. FIN = 25MHz, FOUT= 161.1328MHz, FPFD = 50MHz, RMS
Noise = 1.33ps. FIN = 25MHz, FOUT= 148.5MHz, FPFD = 25MHz, RMS Noise = 1.74ps. FIN = 25MHz, FOUT= 148.5MHz, FPFD
50MHz, RMS Noise = 1.43ps. FIN = 25MHz, FOUT= 148.3516MHz, FPFD = 25MHz, RMS Noise = 1.6ps. FIN = 25MHz, FOUT
=
=
148.3516MHz, FPFD = 50MHz, RMS Noise = 1.5ps. FIN = 25MHz, FOUT= 106.5MHz, FPFD = 25MHz, RMS Noise = 0.8ps. FIN
25MHz, FOUT= 106.5MHz, FPFD = 50MHz, RMS Noise = 1.3ps.
=
7.14 Input and Output Isolation
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Crosstalk between reference inputs,
PRIREF = 27MHz LVCMOS, SECREF =
25MHz XTAL
PISOLATION
PISOLATION
PISOLATION
PISOLATION
Reference input isolation
-64
dB
Crosstalk between reference inputs,
PRIREF = 100MHz LVDS, SECREF =
25MHz LVCMOS
Reference input isolation
Clock output isolation
Clock output isolation
-72
-65
-42
dB
dB
dB
Crosstalk between clock outputs, OUT1 =
100MHz LP-HCSL, OUT2 = 156.25MHz
LVDS, PFD = 25MHz, int-PLL
Crosstalk between clock outputs, OUT1 =
156.25MHz LVDS, OUT0 = 25MHz
LVCMOS
7.15 Buffer Mode Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
int. Range from 10 kHz to 20 MHz , REF =
tRJ_ADD
Additive RMS Phase Jitter, System Level HCSL 100 MHz with 0.5 V/ns, OUTx =
100 MHz LP-HCSL
350
fs
REF = LVCMOS 25 MHz, OUTx = 25 MHz
LVCMOS
tPROP, LVCMOS Input-to-output propagation delay
1
ns
ns
tPROP,
REF = AC-LVDS 100 MHz, OUTx = 100
MHz. Measured on OUT0
Input-to-output propagation delay(1)
2.3
Differential
ZDB mode, LVCMOS input = LVCMOS
output = 25 MHz, PLL BW = 300 kHz to
900 kHz across temperature
tPROP-
Input-to-output delay variation in ZDB
mode
-400
400
ps
VARIATION
(1) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS
buffer. There is an additional skew 150 ps- 250 ps between OUT1/OUT4 and OUT2/OUT3.
7.16 PCIe Spread Spectrum Generator
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
31.5
6.8
MAX
UNIT
kHz
dB
fSSC-RATE
PAMPL-RED
PAMPL-RED
fSSC-STEP
SSC modulation rate
OUTx = 100 MHz
30
33
SSC amplitude reduction
SSC amplitude reduction
Down and Center spread SSC step size
OUTx = 100 MHz, -0.25% Down spread
OUTx = 100 MHz, -0.50% Down spread
OUTx = 100 MHz
9.9
dB
0.25
%
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VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSSC_FREQ_DE Down spread minimum/maximum
OUTx = 100 MHz. FPFD = 25 MHz, 50
MHz, 100 MHz
-0.5
0
%
deviation
VIATION
tSSC_FREQ_DE Center spread minimum/maximum
OUTx = 100 MHz. FPFD = 25 MHz, 50
MHz, 100 MHz
-0.5
0.5
%
deviation
VIATION
7.17 LVCMOS Output Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fO_LVCMOS
Output frequency
2 pF to GND, normal mode
0.024
200
MHz
IOH = 1 mA, VDDO_x is corresponding
supply voltage.
0.8 ×
VDDO_x
VOH_LVCMOS Output high voltage
VOL_LVCMOS Output low voltage
V
V
IOL = 1 mA, VDDO_x is corresponding
supply voltage.
0.2 ×
VDDO_x
IOH
Output high current
Output high current
Output high current
Output low current
Output low current
Output low current
Output rise/fall time
Vout = 0.8 × VDDO_x, VDDO_x = 1.8 V
Vout = 0.8 × VDDO_x, VDDO_x = 2.5 V
Vout = 0.8 × VDDO_x, VDDO_x = 3.3 V
Vout = 0.2 × VDDO_x, VDDO_x = 1.8 V
Vout = 0.2 × VDDO_x, VDDO_x = 2.5 V
Vout = 0.2 × VDDO_x, VDDO_x = 3.3 V
20/80%, CL= 5 pF, normal mode
-6
-8.5
-11.2
6
mA
mA
mA
mA
mA
mA
ps
IOH
IOH
IOL
IOL
8.5
IOL
11.2
500
TRISE-FALL
300
700
20/80%, CL= 5 pF, slow mode, measured
on OUT0
TRISE-FALL
TSKEW
Output rise/fall time
1000
100
ps
ps
ps
LVCMOS-to-LVCMOS outputs, same
divide value
Output-to-output skew(1)
LVCMOS-to-Differential outputs, same
divide value
TSKEW
ODC
Output-to-output skew(1)
Output duty cycle
400
Not in PLL bypass mode
Normal mode
45
45
50
55
75
85
%
Ω
Ω
RON_LVCMOS Output impedance
RON_LVCMOS Output impedance
60
65
Slow mode
(1) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS
buffer. OUT1/OUT4 is matched within TOUT-SKEW. OUT2/OUT3 is matched within TOUT-SKEW
.
7.18 LP-HCSL Output Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
0.024
660
TYP
MAX
328.125
850
UNIT
MHz
mV
mV
Ω
fO_HCSL
VOH
Output frequency
Output high voltage(3)
VOL
Output low voltage
-150
90
150
ZDIFF
Differential Output Impedance(3)
100
110
12-in, 100 Ω±10% diff. trace with 2
pF±5%/pin in FR4.
VCROSS
Absolute crossing point
250
550
140
4
mV
mV
Relative crossing point variation
Slew rate for rising and falling edge
with respect to average crossing point
ΔVCROSS
differential, at VCROSS +/-150 mV,
fO_HCSL=100 MHz (1)
dV/dt
1
V/ns
single-ended, at VCROSS +/-75 mV,
fO_HCSL=100 MHz (1)
Slew rate matching
20
%
ΔdV/dt
Measured on differential output at 100
MHz and specifies minimum voltage from
zero crossing
Vrb
Output ringback voltage
-100
100
mV
Tstable
ODC
Time elapsed until ringback
Output duty cycle
Minimum time until ringback is allowed
Not in PLL bypass mode
500
45
ps
%
55
TOUT-SKEW
Output skew(2)
Same divide value, LP-HCSL to LP-HCSL
100
ps
(1) PCIe test load slew rate
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(2) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS
buffer. OUT1/OUT4 is matched within TOUT-SKEW. OUT2/OUT3 is matched within TOUT-SKEW. There is an additional skew 150 ps- 250
ps between OUT1/OUT4 and OUT2/OUT3.
(3) Differential Output characteristic is trimmed in factory and trim settings are stored in EEPROM. Parameter not valid in Fall-back mode.
7.19 LVDS Output Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
0.024
1.025
0.85
TYP
MAX
328.125
1.375
UNIT
MHz
V
fO_PRG_AC
VCM
Output frequency
Output common mode(2)
Output common mode(2)
VDDO_X = 2.5 V, 3.3 V
1.2
VCM
VDDO_X = 1.8 V
0.95
1.05
V
VDDO_X = 1.8 V (Fout < 200 MHz), 2.5 V,
3.3 V.
VOD
Differential output voltage(2)
0.25
0.30
0.45
V
VOD
Differential output voltage(2)
Output rise/fall times
Output duty cycle
VDDO_X = 1.8 V & Fout > 200 MHz
LVDS (20% to 80%)
0.22
450
45
0.30
650
0.45
900
55
V
tRF
ps
%
ps
ODC
Not in PLL bypass mode
TOUT-SKEW
Output skew(1)
Same divide value, LVDS to LVDS output
100
(1) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS
buffer. OUT1/OUT4 is matched within TOUT-SKEW. OUT2/OUT3 is matched within TOUT-SKEW. There is an additional skew 150 ps- 250
ps between OUT1/OUT4 and OUT2/OUT3.
(2) Output Common Mode voltage and Differential output swing is dependent upon register settings DIFFBUF_IBIAS_TRIM,
LVDS_CMTRIM_DEC and LVDS_CMTRIM_INC. Parameters defined for DIFFBUF_IBIAS_TRIM=6h, LVDS_CMTRIM_DEC=0h and
LVDS_CMTRIM_INC=0h. Output Common Mode tested at DC.
7.20 Output Synchronization Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
with respect to PLL reference rising edge
at 100 MHz with R=1
tSU_SYNC
tH_SYNC
Setup time SYNC pulse
3
ns
with respect to PLL reference rising edge
at 100 MHz with R=1
Hold time SYNC pulse
3
ns
ns
With R = 1, at least 2 PFD periods + 24
feedback pre-scaler periods
tPWH_SYNC
High pulse width for SYNC
60
6
tPWL_SYNC
tEN
Low pulse width for SYNC
With R = 1, at least 1 PFD period
tri-state to first valid rising edge
last valid falling edge to tri-state
ns
Individual output enable time(1)
Individual output disable time(1)
4
4
nCK
nCK
tDIS
(1) Output clock cycles of respective output channel. Global output enable handled by digital logic, additional propagation will be added.
7.21 Power-On Reset Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VTHRESHOLD POR threshold voltage(1)
0.875
1.275
V
Start-up time after VDD reaches 95% to
the time outputs are toggling with correct
frequency (input = crystal or external
clock)
tSTARTUP
Start-up time
9
ms
ms
timing requirement for any VDD pin while
PDN=LOW
tVDD
Power supply ramp time(2)
0.1
30
(1) POR threshold voltage is the power supply voltage at which the internal reset is deasserted. It is qualified internally with PDN.
(2) VDD pin should monotonically reach 95% of its final value within supply ramp time. Parameters specified by characterization. All VDD
pins were tied together for this evaluation. For non-monotonic or slower power supply ramp, it is recommended to pull-down PDN pin
until VDD pins have reached 95% of its final value. PDN pin has a 50 kΩ pullup resistor. When PDN pin cannot be actively controlled,
TI recommends to add a capacitor to GND on PDN pin to delay the release of reset.
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7.22 I2C-Compatible Serial Interface Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.7 ×
VDD_REF
VIH
VIL
Input Voltage, Logic High
V
0.3 ×
VDD_REF
Input Voltage, Logic Low
V
IIH
Input Leakage Current
Low Level Output Voltage
Input Capacitance
VDD_REF ± 10%
-5
5
0.4
10
µA
V
VOL
CIN
COUT
at 3 mA sink current
pF
pF
Output Capacitance
max bus capacitance per pin
400
7.23 Timing Requirements, I2C-Compatible Serial Interface
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
tPW_G
fSCL
Pulse Width of Suppressed Glitches
SCL Clock Frequency
50
Standard
100
400
0.6
kHz
kHz
µs
fSCL
SCL Clock Frequency
Fast-mode
tSU_STA
Setup Time Start Condition
SCL=VIH before SDA=VIL
SCL=VIL after SCL=VIL After this time, the
first clock edge is generated.
tH_STA
Hold Time Start Condition
0.6
µs
tSU_SDA
tSU_SDA
tH_SDA
tVD_SDA
tVD_SDA
tPWH_SCL
tPWH_SCL
tPWL_SCL
tPWL_SCL
tIR
Setup Time Data
SDA valid after SCL=VIL, fSCL=100 kHz
SDA valid after SCL=VIL, fSCL=400 kHz
SDA valid before SCL=VIH
fSCL=100 kHz(3)
250
100
0(2)
ns
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Setup Time Data
Hold Time Data(1)
(3)
Valid Data or Acknowledge Time
Valid Data or Acknowledge Time
Pulse Width High, SCL
Pulse Width High, SCL
Pulse Width Low, SCL
Pulse Width Low, SCL
Input Rise Time
3.45
0.9
fSCL=400 kHz(2)
fSCL=100 kHz
4.0
0.6
4.7
1.3
fSCL=400 kHz
fSCL=100 kHz
fSCL=400 kHz
300
300
250
tIF
Input Fall Time
tOF
Output Fall Time
10 pF ≤COUT ≤400 pF
tSU_STOP
Setup Time Stop Condition
0.6
1.3
Time between a Stop and a Start
condition
tBUS
Bus-Free Time
µs
(1) tH_SDA is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
(3) The maximum tH_SDA could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of tVD_SDA
by a transition time. This maximum must only be met if the device does not stretch the LOW period (tPWL_SCL) of the SCL signal. If the
clock stretches the SCL, the data must be valid by the setup time before it releases the clock.
7.24 Power Supply Characteristics
VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDD_REF
IDD_VCO
VDD_REF supply current
25 MHz XTAL, DBL ON
8
mA
fVCO=2400 MHz, PSA = PSB = 4 and N-
divider = 48
VCO and PLL current
14
22
mA
mA
IOD=6, LP-HCSL, 100MHz on OUT3 and
OUT4, 25MHz on OUT0
IDD_OUT
Output Channel Current
IOD = 6, LP-HCSL, 100 MHz on OUT1
and OUT2
IDD_OUT
IDD_PDN
Output Channel Current
Power down current
17.5
2.8
mA
mA
using reset pin / bits
5
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VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4 x 100 MHz LVDS case using crystal
input and doubler, SSC off
IDD_TYP
IDD_TYP
LPSNR
Typical current
50
70
90
mA
4 x 100 MHz LP-HCSL case using crystal
input and doubler, SSC off
Typical current
65
-61
-57
mA
dB
dB
OUTx = 100 MHz differential, on one of
VDDx injected sine wave at fINJ = 100 kHz
Power supply noise rejection
Power supply noise rejection
OUTx = 100 MHz differential, on one of
VDDx injected sine wave at fINJ = 1 MHz
LPSNR
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7.25 Typical Characteristics
Measured at room temperature
Reference: Crystal Closed-Loop Phase 100-MHz LP-HCSL
Reference: Crystal Closed-Loop Phase 156.25-MHz LVDS
Input 25 MHz Noise from 2.4-GHz
VCO
Input 25 MHz Noise from 2.5-GHz
VCO
图7-2. 100-MHz LP-HCSL Output
图7-1. 156.25-MHz LVDS Output
Reference: Crystal Closed-Loop Phase
Input 25 MHz Noise from 2.376-
GHz VCO
148.5-MHz LVDS
Reference: Crystal Closed-Loop Phase
Input 25 MHz Noise from 2.4576-
GHz VCO
24.576-MHz
LVCMOS
图7-3. 148.5-MHz LVDS Output
图7-4. 24.576-MHz LVCMOS Output
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图7-6. All Power Supply = 3.3 V, VDD Ramp Time =
图7-5. All Power Supply = 1.8 V, VDD Ramp Time =
1 ms
1 ms
图7-8. All Power Supply = 3.3 V, VDD Ramp Time =
图7-7. All Power Supply = 1.8 V, VDD Ramp Time =
10 ms
10 ms
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8 Parameter Measurement Information
8.1 Reference Inputs
Signal
< 2 VPP
100 ꢀ
DUT
Generator
图8-1. Differential AC-Coupled Input
8.2 Outputs
Scope
LVCMOS
50 ꢀ
DUT
GND
图8-2. LVCMOS Output Test Configuration
Scope
50ꢀ
50ꢀ
DUT
LVDS
GND
图8-3. LVDS Output Test Configuration, AC-Coupled
Scope
(50 Ω)
DUT
Balun
图8-4. LP-HCSL Test Configuration, DC-Coupled
50 ꢀ
>1MΩ
CDCE6214-Q1
Scope
50 ꢀ
GND
图8-5. LVDS Common Mode Voltage, DC-Coupled
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QAx, QBx
VOD
nQAx, nQBx
80%
0 V
VOUT,DIFF,PP = 2xVOD
20%
tf
tf
图8-6. Differential Output Voltage and Rise/Fall Time
8.3 Serial Interface
ACK
STOP
STOP
START
tIR
tIF
tPWL_SCL tPWH_SCL
VIH
VIL
SCL
tH_STA
tSU_STA
tBUS
tSU_SDA
tIR
tH_SDA
tSU_STOP
tIF
VIH
VIL
SDA
图8-7. I2C Timing
8.4 PSNR Test
Sine
Wave
Modulator
Power Supply
Phase Noise/
Spectrum
Analyzer
Signal
Generator
DUT
Device Output
Balun
Reference
Input
图8-8. PSNR Test Configuration
8.5 Clock Interfacing and Termination
8.5.1 Reference Input
Rs
LVCMOS
Driver
CDCE6214-Q1
图8-9. Single-Ended LVCMOS to Reference
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Signal
Generator
100 ꢀ
< 2 VPP
DUT
图8-10. Differential Input to Reference
8.5.2 Outputs
Rs
CDCE6214-Q1
DUT
GND
图8-11. LVCMOS Output
CDCE6214-Q1
DUT
图8-12. LVDS Output - DC-Coupled. Place 100Ωclose to the DUT
VCM
CDCE6214-Q1
DUT
VCM
图8-13. LVDS Output - AC-Coupled
Rs
CDCE6214-Q1
DUT
Rs
图8-14. LP-HCSL Output
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9 Detailed Description
9.1 Overview
The CDCE6214-Q1 automotive clock generator is a Phase-Locked Loop (PLL) with integrated voltage controlled
Oscillator (VCO) and integrated loop filter with selectable input reference. Input reference supports XTAL,
Differential and single-ended LVCMOS inputs. The PLL consists of Frac-N PLL with integrated VCO range of
2335MHz - 2625MHz. The output of the VCO is connected to the clock distribution network, which includes
multiple frequency dividers and multiplexers. The output of these network is connected to four output channels
with configurable differential and single ended buffers. There are 4 power supply pins which can be
independently configured to 1.8V/2.5V/3.3V. CDCE6214-Q1 can be configured using the I2C serial interface or
built-in EEPROM at power up. This device supports various modes such as Digitally Controlled Oscillator (DCO)
through GPIO/I2C and Internal/external Zero Delay mode.
9.2 Functional Block Diagram
Outputs (1.8/2.5/3.3 V)
7
OUT0
LVCMOS
Inputs (1.8/2.5/3.3 V)
0
22
OUT1
LVDS,
LP-HCSL,
LVCMOS
Integer Div
14-b
1
21
2
5
6
PRIREF
Differential,
LVCMOS
APLL (1.8/2.5/3.3 V)
0
1
2
18
17
OUT2
LVDS,
LP-HCSL
x2
Integer Div
14-b
VCO: 2.335-2.625 GHz
R div
8-b
f
/4 - /6
1
2
SECREF
Differential,
XTAL, LVCMOS
XO
0
1
2
14
13
OUT3
LVDS,
LP-HCSL
Integer Div
14-b
N Div
MARGIN
/4 - /6
15-b int,
24-b frac
4
REFSEL
0
1
2
10
9
OUT4
LVDS,
LP-HCSL,
LVCMOS
Integer Div
14-b
Control (1.8/2.5/3.3 V)
Registers
EEPROM
Device Control
and Status
Power Conditioning
图9-1. CDCE6214-Q1 Clock Generator With 2 Inputs, 1 Fractional-N PLL, and 4 Outputs
9.3 Feature Description
The following sections describe the individual blocks of the CDCE6214-Q1 ultra low power clock generator.
9.3.1 Reference Block
A reference clock to the PLL is fed to pins 1 (SECREF_P) and 2 (SECREF_N) or to pins 5 (PRIREF_P) and 6
(PRIREF_N). There are multiple input stages to accommodate various clock references. Pins 1 and 2 can be
used to connect a XTAL across it or provide an external single-ended LVCMOS clock or a differential clock.
These modes are selectable through register programming. When differential mode is selected, appropriated
biasing is applied to the pin. In case of differential mode, external AC-coupling capacitor is needed. When XTAL
or LVCMOS mode is selected, biasing circuitry is disengaged. Pins 5 and 6 can be used to provide an external
single-ended LVCMOS clock or a differential clock.
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The reference MUX selects the reference clock for the PLL. Setting REFSEL pin = L selects SECREF input,
while setting REFSEL pin = H selects PRIREF Input. Alternatively, this can be configured through the register
settings.
表9-1. Reference Input Selection
REGISTER BIT ADDRESS
REGISTER BIT FIELD NAME
VALUE
DESCRIPTION
Input Reference Mux controlled
through Pin 4 (REFSEL)
R2[1:0]
REFSEL_SW
0h or 1h
Pin1/Pin 2 SECREF Input
selected. This is independent of
Pin 4 status.
(Default: 0h)
2h
3h
Pin 5/Pin 6 PRIREF Input
selected. This is independent of
Pin 4 status.
XO enabled. Valid for SECREF
pins.
R24[1:0]
R24[15]
IP_SECREF_BUF_SEL
(Default: 0h)
0h
1h
LVCMOS Buffer enabled. Valid
for SECREF pins.
Differential Buffer enabled. Valid
for SECREF pins.
2h or 3h
0h
LVCMOS Buffer enabled. Valid
for PRIREF pins.
IP_PRIREF_BUF_SEL
(Default: 0h)
Differential Buffer enabled. Valid
for PRIREF pins.
1h
A reference divider or a clock-doubler can be engaged to further multiply (2x) or divide the reference clock to the
PLL. IP_RDIV[7:0] can be used to set the value of the divider. Setting this to 00h would enable the doubler.
The output clock from the reference block can be bypassed to the OUT0 and other output channels. The
bypassed clock is selectable between the Input clock or PFD clock. More details available in 表9-9.
The SECREF_P and SECREF_N pins provide a crystal oscillator stage to drive a fundamental mode crystal in
the range of 10 MHz to 50 MHz. The crystal input stage integrates a tunable load capacitor array up to 9 pF and
programmable through R24[12:8]. The drive capability of the oscillator is programmable through R24[5:2].
The LVCMOS input buffer threshold voltage follows VDD_REF. This device can be used as a level shifter
because the outputs have separate supplies.
9.3.1.1 Zero Delay Mode, Internal and External Path
The CDCE6214-Q1 can operate in Zero Delay Mode with internal as well as external feedback. In Zero Delay
Mode, PRIREF clock is used as the reference clock to the PFD. SECREF input clock can be used to feed an
external source as feedback clock to the PFD. External feedback path is recommended for zero delay operation.
Moreover there is an additional internal feedback path which is sourced from output channel 2. It is expected
that the Input-output propagation delay would be higher in Internal zero-delay mode than external zero delay
mode.
表9-2. Zero Delay Operation 1 2 3
R24[1:0] -
IP_SECREF_B IP_PRIREF_BU
R24[15] -
R0[10] -
R2[1:0] -
REFSEL_SW
R0[8] -
ZDM_EN
OPERATION
REFSEL
ZDM_CLOCKS DESCRIPTION
EL
UF_SEL
F_SEL
Normal
Normal
Operation,
XTAL Input
L
0h or 1h or 2h
0h
X
0h
0h
Operation,
XTAL Input
1
In zero delay mode, all dividers should be programmed such that PLL can lock. On power-up in zero-delay mode, PLL would lock
automatically
For internal Zero delay mode, channel 2 is required. Channel 2 should not be powered down
"X" allows any possible bit-field value. It has no impact on the functionality
2
3
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表9-2. Zero Delay Operation 1 2 3 (continued)
R24[1:0] -
IP_SECREF_B IP_PRIREF_BU
R24[15] -
R0[10] -
R2[1:0] -
REFSEL_SW
R0[8] -
ZDM_EN
OPERATION
REFSEL
ZDM_CLOCKS DESCRIPTION
EL
UF_SEL
F_SEL
Normal
Operation,
Differential
Input
SECREF/
Differential
Input
L
0h or 1h or 2h
2h or 3h
X
0h
0h
0h
0h
Normal
Operation,
Differential
Input
PRIREF/
Differential
Input
H
0h or 1h or 3h
X
1h
Normal
Operation,
LVCMOS Input
SECREF/
LVCMOS Input
L
0h or 1h or 2h
0h or 1h or 3h
1h
X
X
0h
0h
0h
0h
Normal
Operation,
LVCMOS Input
PRIREF/
LVCMOS Input
H
0h
External Zero
Delay Mode,
Differential
Input
Input Clock on
PRIREF,
Feedback clock
on SECREF
H
H
H
H
0h or 1h or 3h
0h or 1h or 3h
0h or 1h or 3h
0h or 1h or 3h
2h or 3h
1h
0h
1h
0h
1h
1h
1h
1h
1h
1h
0h
0h
Input Clock on
PRIREF,
Feedback clock
on SECREF
External Zero
Delay Mode,
LVCMOS Input
1h
X
Internal Zero
Delay Mode,
Differential
Input
Input clock on
PRIREF
Internal Zero
Delay Mode,
Differential
Input
Input clock in
PRIREF
X
图9-2. Input/Output Alignment in External Zero Delay Mode for LVCMOS Output
1
In zero delay mode, all dividers should be programmed such that PLL can lock. On power-up in zero-delay mode, PLL would lock
automatically
For internal Zero delay mode, channel 2 is required. Channel 2 should not be powered down
"X" allows any possible bit-field value. It has no impact on the functionality
2
3
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9.3.2 Phase-Locked Loop (PLL)
The CDCE6214-Q1 has a fully-integrated Phase-Locked Loop (PLL) circuit. The error between a reference
phase and an internal feedback phase is compared at the phase-frequency-detector. The comparison result is
fed to a charge pump that is connected to an integrated loop filter. The control voltage resulting from the loop
filter tunes an internal Voltage-Controlled Oscillator (VCO). The frequency of the VCO is fed through a feedback
divider (N-counter) back to the PFD.
• Integer and Fractional-N PLL mode of operation.
• First-, Second-, or Third-Order MASH operation in Fractional mode.
• 24-bit Numerator and Denominator can be used to generate fractional frequencies with 0 ppb frequency
accuracy.
• PFD operates between 1 MHz and 100 MHz.
• Live Lock Detector (R7[0] or PLL_LOCK in GPIO) provides PLL Lock status (in fractional mode and SSC
enabled, lock detect window need to be widened. R50[10:8] = 7h). Additionally, sticky bit lock detect (R7[1])
detects if there was any temporary loss of lock.
• Integrated selectable loop filter components.
• For a 25-MHz PFD frequency, PFD bandwidth between 100 kHz and 1.6 MHz can be achieved to optimize
PLL to input reference.
• Voltage-controlled oscillator (VCO) ranges from 2335 MHz to 2615 MHz.
• Supports 0.25% and 0.5% center and down spread Spread Spectrum Clocking (SSC) generation. Further,
VCO also supports up to 0.5% SSC references at 100 MHz for PCIe clocking.
表9-3. Common Clock Generator Loop Filter Settings
PHASE
MARGIN IN °
DAMPING
FACTOR
fVCO IN MHz fPFD IN MHz
BW IN MHz
ICP IN mA
CPcap IN pF
CZcap IN pF
RRes IN kΩ
2400
2400
2400
2457.6
2500
2500
2400
25
50
0.469
0.938
1.60
1.04
0.49
0.93
400
70
70
70
70
70
70
65
0.5
2
0.60
0.60
0.80
0.60
0.60
0.60
0.40
16.1
8.2
2.5
2.5
2.5
2.0
2.5
2.5
1.5
580
276
303
331
497
386
636
100
61.44
25
0.5
1.15
0.4
1.0
0.1
8.2
9.2
13.5
11.7
11.7
50
50
表9-4. Common PLL Divider Settings 4
INPUT
FREQUENCY
IN MHz
OUTPUT
FREQUENCY
IN MHz
N-COUNTER
DIVIDER VALUE
OUTPUT
DIVIDER
fPFD IN MHz
fVCO
NUMERATOR DENOMINATOR
PSA
25
25
25
25
25
25
50
25
50
25
25
25
100
100
2400
2400
2500
2400
2457.6
2376
48
96
50
96
98
95
NA
NA
NA
NA
4
4
4
4
4
4
6
6
156.25
25
NA
NA
4
NA
NA
24
25
4
24.576
148.5
5071614
664983
16682942
16624579
9.3.2.1 PLL Configuration and Divider Settings
fPFD= Fin/Ffactor
Ffactor is determined by R25[7:0] - ip_ref_div. Ffactor = 0.5 when ip_ref_div=0, Ffactor = ip_ref_div, otherwise.
fVCO = fPFD × (N + Num/Den).
N is set by R30[14:0] - PLL_NDIV. Num is the numerator of the fraction, set by {R32[7:0],R31[15:0]}. Den is the
denominator of the fraction, set by R34[7:0],R33[15:0]. When {R34[7:0],R33[15:0]} = 0, Den=224.
4
Fractional Mode settings are based on DCO mode step size of 0.1ppm
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The sigma delta modulator supports different order of MASH to shape the quantization noise. For Integer mode,
R27[1:0] is set as 0h. For fractional mode, it can be set to 1h, 2h or 3h for first, second and third order,
respectively.
In integer mode, PLL is configured in single-ended PFD configuration by setting R51[6]=1h. In Fractional mode,
PLL should be configured in Differential PFD configuration by setting R51[6]=0h. Further, R51[10] is set as 1h in
fractional mode and 0h in Integer mode.
9.3.2.2 Spread Spectrum Clocking
The energy of the harmonics from the rectangular clock signal can be spread over a certain frequency range.
This frequency deviation leads to lowered average amplitude of the harmonics. This can help to mitigate
electromagnetic interference (EMI) challenges in a system when the receiver supports this mode of operation.
The modulation shape is triangular.
The SSC clock is generated through the fractional-N PLL. When SSC is enabled, SSC clock is available on all
clock sourced from the PLL. Reference clock or PFD clock is available on the OUT1–OUT4 pins.
Down spread and center spread are supported. The following modes are supported.
• PFD frequencies: Either 25 MHz or 50 MHz.
• Down spread: –0.25% and ±0.5%
• Center spread: ±0.25% and ±0.5%
Pre-configured settings are available to select any of these combinations.
Using these pre-configured settings, fmod of 31.5 kHz is synthesized for 100-MHz output clock.
Center-Spread
Frequency
fupper
fSSC_MOD
fnom
fSPREAD
flower
Time
Down-Spread
Frequency
fupper = fnom
fSSC_MOD
fSPREAD
flower
Time
图9-3. Spread Spectrum Clock
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表9-5. Spread Spectrum Settings 5 6
R41[15] - SSC_EN
R42[5] - SSC_TYPE
R42[3:1] - SSC_SEL
DESCRIPTION
0h
X
X
No SSC modulation at output
Down spread SSC modulation.
SSC spread is determined by
ssc_sel
1h
0h
1h
X
X
Center spread SSC modulation.
SSC spread is determined by
ssc_sel
1h
1h
1h
1h
X
25-MHz PFD, +/- 0.25% for
Center spread, -0.25% for Down
spread.
0h
1h
2h
25-MHz PFD, +/- 0.50% for
Center spread, -0.50% for Down
spread.
X
50-MHz PFD, +/- 0.25% for
Center spread, -0.25% for Down
spread.
X
50-MHz PFD, +/- 0.50% for
Center spread, -0.50% for Down
spread.
1h
1h
X
X
3h
4h-7h
Do not use
图9-4. 100 MHz With - 0.25% Down Spread With 图9-5. 100 MHz With +/- 0.25% Center Spread With
and Without Trace and Without Trace
图9-6. 100 MHz With - 0.5% Down Spread With and 图9-7. 100 MHz With +/- 0.5% Center Spread With
Without Trace
and Without Trace
5
6
X signifies that this bitfield can take any value
For any other SSC spread and modulation rate, please contact TI representative.
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RESULT
表9-6. PCI Express Compliance Measurement
MEASURED PNA
METHOD
MEASURED
SCOPE METHOD
NO.
CLASS
DATA RATE
ARCHITECTURE
SPEC LIMIT
1
2
3
4
Gen4
Gen4
Gen5
Gen5
16 Gb/s
16 Gb/s
32 Gb/s
32 Gb/s
CC
SRIS
CC
195 fs
260 fs
490 fs
111 fs
157 fs
500 fs
500 fs
150 fs
*
PASS
PASS
PASS
*
-
87 fs
-
SRIS
9.3.2.3 Digitally-Controlled Oscillator/ Frequency Increment and Decrement - Serial Interface Mode and
GPIO Mode
In this mode, the output clock frequency can be incremented or decremented by a fixed frequency step. The
frequency step size is determined by the register R43[15:0]. This value is added or subtracted to the numerator
of the sigma-delta modulator. Various bit fields as shown in BROKEN_LINK can be used to exercise this
functionality. Every rising edge of FREQ_INC signal increases the output frequency, while every rising edge of
FREQ_DEC signal decreases the output frequency. There are two ways to trigger the increment or decrement:
1. Appropriate configuration of the GPIOs and sending FREQ_INC/FREQ_DEC signal through an external
microcontroller or ASIC.
2. Using register bit fields controlled through serial interface.
表9-7. Register Settings for Frequency Increment/Decrement Functionality
REGISTER BIT ADDRESS
REGISTER BIT FIELD NAME
DESCRIPTION
R3[3]
FREQ_INC_DEC_EN
Enables/Disables DCO mode
Selects DCO trigger through GPIOs or Serial
Interface.
R3[4]
FREQ_INC_DEC_REG_MODE
Generates FREQ_INC/FREQ_DEC signal
through serial Interface
R3[6:5]
FREQ_DEC_REG, FREQ_INC_REG
FREQ_INC_DEC_DELTA
R43[15:0]
Frequency Increment/Decrement step size
表9-8. Computing Divider Settings in DCO Mode
PARAMETERS
VALUE (EXAMPLE)
DESCRIPTION
Input PFD Frequency (FPFD
)
25 MHz
Set according to FPFD.
FVCO is set within the operating VCO range of
2335 MHz - 2625 MHz. FVCO is selected such
that PSA/PSB/Output Divider is Integer.
Expected VCO Frequency (FVCO
)
2457.6 MHz
24.576 MHz
PSA = 4, IOD = 25. FVCO = PSA × IOD ×
Expected Output Frequency (FOUT
)
FOUT
.
Every rising edge of FREQ_INC/FREQ_DEC
would change the output by this step size.
Expected step size (in ppm) (Fstep
)
0.1
98
76
N-divider Value (N)
INT(FVCO/FPFD
)
Minimum Numerator value to meet 0ppb
accuracy (Num)
These values are computed to meet
accuracy requirement at output. Should be
less than 224
.
Minimum Denominator to meet 0ppb
accuracy (Den)
250
Minimum Denominator value to meet ppm
101725.26
500000
1/(Fstep × 1e6) / (FVCO/FPFD)
step size (FDEN,min
)
Final Denominator value (FDEN,final
)
FDEN,final should be greater than FDEN,min and
less than 224. FDEN,final and FNUM,final should
be integer multiple of Den and Num
Final Numerator value (FNUM,final
)
152000
5
respectively. FDEN,final/Den = FNUM,final/Num
This value should be less than 216-1.
FDEN,final should be closest integer multiple of
Increment/ Decrement step size
FDEN,min
.
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9.3.3 Clock Distribution
The VCO output connects to two individually configurable pre-scalar dividers sourcing the on-chip clock
distribution –PSA and PSB. PSA and PSB can be configured as division value of /4, /5 or /6 independently.
The clock distribution consists of four output channels. Each output channel contains an integer divider (IOD)
with glitchless switching and synchronization capabilities.
IOD can be sourced from either the PSA, the PSB, or the Reference Clock. IOD can be bypassed to provide a
Reference clock at the output.
There are five output channels –OUT0, OUT1, OUT2, OUT3, and OUT4.
The OUT0 is a slew-rate controllable LVCMOS output. Either the reference clock or PFD clock can be routed to
this output through the clock distribution network.
The OUT1 and OUT4 are identical output channels. The output buffers in this channel are compatible with
various signaling standards –LVCMOS, LP-HCSL, and LVDS-like.
The OUT2 and OUT3 are identical output channels. The output buffers in this channel are compatible with
various signaling standards –LP-HCSL and LVDS-like.
• The LP-HCSL output buffer can be directly connected to the receiver without any termination resistor to GND.
The output impedance of LP-HCSL is trimmed to 50 Ω± 10%. A series resistor can be used to adapt to the
trace impedance.
• The LVDS-like requires a differential termination connected between the positive and negative polarity output
pins. The termination can be connected directly or through an AC-coupling capacitor. For a 50-Ωsystem, a
100-Ωdifferential termination is appropriate.
• LVCMOS outputs are designed for capacitive loads only. The polarity of the positive and negative output pins
can be configured individually.
The differential buffers support wide range of output frequencies up to 328.125 MHz. LVCMOS supports up to
200 MHz.
表9-9. Configuring Input Reference/PFD/PLL Clock to Output 7
REGISTER BIT ADDRESS
REGISTER BIT FIELD NAME
DESCRIPTION
Enables Reference Clock/PFD Clock to
OUT0.
R25[10]
IP_BYP_OUT0_EN
Selects between PFD Clock or Input
Reference Clock
R25[9]
REF_CH_MUX
IP_REF_TO_OUT4_EN,
IP_REF_TO_OUT3_EN,
IP_REF_TO_OUT2_EN,
IP_REF_TO_OUT1_EN
R25[14:11]
Selects reference clock to OUT1-OUT4
R56[15:14]
R62[15:14]
R67[15:14]
R72[15:14]
CH1_MUX
CH2_MUX
CH3_MUX
CH4_MUX
Clock selection MUX control for OUT1
Clock selection MUX control for OUT2
Clock selection MUX control for OUT3
Clock selection MUX control for OUT4
表9-10. Configuring Clock Distribution Network
REGISTER BIT ADDRESS
R47[6:5]
REGISTER BIT FIELD NAME
DESCRIPTION
PLL_PSB
PLL_PSA
CH1_DIV
CH2_DIV
CH3_DIV
Programmable Pre-scalar divider PSB
Programmable Pre-scalar divider PSA
OUT1 Integer Divider value
R47[4:3]
R56[13:0]
R62[13:0]
OUT2 Integer Divider value
R67[13:0]
OUT3 Integer Divider value
7
It is recommended to disable any clock when not in use to reduce crosstalk
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表9-10. Configuring Clock Distribution Network (continued)
REGISTER BIT ADDRESS
REGISTER BIT FIELD NAME
DESCRIPTION
R72[13:0]
CH4_DIV
OUT4 Integer Divider value
表9-11. Configuring LVCMOS Output Buffer 8 9
REGISTER BIT FIELD NAME
REGISTER BIT ADDRESS
DESCRIPTION
R78[12]
CH0_EN
Enables OUT0 LVCMOS Buffer
Controls output slew rate of OUT0 LVCMOS
Buffer
R79[3:0]
CH0_CMOS_SLEW_RATE_CTRL
R59[14], R75[14]
R59[13], R75[13]
CH1_CMOSN_EN, CH4_CMOSP_EN
CH1_CMOSP_EN, CH4_CMOSN_EN
Enables OUT1N/OUT4P LVCMOS Buffer
Enables OUT1P/OUT4N LVCMOS Buffer
Sets output polarity of OUT1N/OUT4P
LVCMOS Buffer
R59[12], R75[12]
R59[11], R75[11]
R60[3:0], R76[3:0]
CH1_CMOSN_POL, CH4_CMOSP_POL
CH1_CMOSP_POL, CH4_CMOSN_POL
Sets output polarity of OUT1P/OUT4N
LVCMOS Buffer
CH1_CMOS_SLEW_RATE_CTRL,
CH4_CMOS_SLEW_RATE_CTRL
Controls output slew rate of OUT1/OUT4
LVCMOS Buffer
表9-12. Configuring LP-HCSL Output Buffer 10 11 12
REGISTER BIT ADDRESS
REGISTER BIT FIELD NAME
DESCRIPTION
CH1_HCSL_EN, CH2_HCSL_EN,
CH3_HCSL_EN, CH4_HCSL_EN
Enables LP-HCSL buffer on OUT1/OUT2/
OUT3/OUT4
R57[14] , R63[13], R68[13], R73[13]
表9-13. Configuring LVDS-Like Output Buffer 13 14 15
REGISTER BIT ADDRESS
REGISTER BIT FIELD NAME
DESCRIPTION
CH1_LVDS_EN, CH2_LVDS_EN,
CH3_LVDS_EN, CH4_LVDS_EN
Enables LVDS-like buffer on OUT1/OUT2/
OUT3/OUT4
R59[15], R65[11], R70[11], R75[15]
CH1_DIFFBUF_IBIAS_TRIM,
CH2_DIFFBUF_IBIAS_TRIM,
CH3_DIFFBUF_IBIAS_TRIM,
CH4_DIFFBUF_IBIAS_TRIM
Sets the output swing and output common
mode of OUT1/OUT2/OUT3/OUT4
R60[15:12], R66[3:0], R71[3:0], R76[9:6]
CH1_LVDS_CMTRIM_INC,
CH2_LVDS_CMTRIM_INC,
CH3_LVDS_CMTRIM_INC,
CH4_LVDS_CMTRIM_INC
Increases the output common mode of
OUT1/OUT2/OUT3/OUT4. 2.5 V/3.3 V mode
only.
R60[11:10], R66[5:4], R71[5:4], R76[5:4]
CH1_LVDS_CMTRIM_DEC,
CH2_LVDS_CMTRIM_DEC,
CH3_LVDS_CMTRIM_DEC,
CH4_LVDS_CMTRIM_DEC
Decreases the output common mode of
OUT1/OUT2/OUT3/OUT4. 2.5 V/3.3 V mode
only.
R60[5:4], R65[14:13], R71[10:9], R77[1:0]
9.3.3.1 Glitchless Operation
The bit fields ch{x}_glitchless_en can be used to enable glitchless output divider update. This feature ensures
that the high pulse of a clock period is not cut off by the output divider update process. It also ensures that setup
8
Multiple output buffers should not be enabled at the same time
Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8V,
9
safety_1p8v_mode should be set.
Multiple output buffers should not be enabled at the same time
External termination not needed. Voltage mode driver.
Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8V,
10
11
12
safety_1p8v_mode should be set.
Multiple output buffers should not be enabled at the same time.
100 Ωdifferential termination needed in DC-coupled mode. 50 Ωsingle ended or 100 Ωdifferential termination needed in AC-
13
14
coupled mode
15
Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8V,
safety_1p8v_mode should be set.
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and hold time of a receiver is not violated. The low pulse in the transition from earlier period to the new period is
extended accordingly.
Glitch-Less Divider Disabled:
Glitch-Less Divider Enabled:
tper1 > tper2
tper1 < tper2
图9-8. Glitchless Divider Update
9.3.3.2 Divider Synchronization
The output dividers can be reset in a deterministic way. This can be achieved using the sync bit or PDN pin. The
level of the pin is qualified internally using the reference frequency at the PFD input. A low level on the SYNCN
pin or sync bit will mute the outputs. A high level will synchronously release all output dividers to operation, so
that all outputs share a common rising edge. The first rising edge can be individually delayed in steps of the
respective pre-scalar period, up to 32 cycles using ch{x}_sync_delay. This allows the user to compensate
external delays like routing mismatch, cables, or inherent delays introduced by logic gates in an FPGA design.
Each channel can be included or excluded from the SYNC process. Divider synchronization can be enabled
individually by ch{x}_sync_en.
For a deterministic behavior over power-cycles seen from input to output the reference divider must be set to 1.
It should not divide the reference clock nor should the reference doubler be used.
VCO
Clock Distribution Pre-Scaler Dividers
PS[BA]=4
PS[BA]=5
PS[BA]=6
Output Channel Dividers
All clocks muted.
PS[BA]=4
IOD=4
PS[BA]=5
IOD=4
PS[BA]=6
IOD=4
Internal SYNC
(ä PFD qualified)
1
2
3
Internal synchronization start
All signals muted
Synchronized dividers released
图9-9. Output Divider Synchronization
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9.3.3.3 Global and Individual Output Enable
The output enable functionality allows the user to enable or disable all or a specific output buffer. The bypass
copy on OUT0 is excluded from the global output enable signal. When an output is disabled, it drives a
configurable mute-state. When the serial interface is deactivated one can use all individual output enable signals
at the same time. The individual output enable signal controls the respective output channel integer divider to
gate the clock, therefore each integer divider must be active.
The individual output enable signal enables and disables the respective output in a deterministic way. Therefore
the high and low level of the signal is qualified by counting four cycles of the respective output clock.
1. The OE falling edge disables the output. The output is enabled for 4 cycles after asserting the Output Enable
of a channel. This will enable any further operation in the system after OE is asserted.
2. The OE rising edge enables the output. Outputs starts toggling after 4 internal clock cycles.
MUTE_SEL= Logic Low
OE
Y1P
1
2
3
4
1
2
3
4
Y1N
Y2P
Y2N
1
2
3
4
1
2
3
4
1
2
3
4
5
6
MUTE_SEL= Logic High
OE
Y1P
1
2
3
4
1
2
3
4
Y1N
Y2P
Y2N
1
2
3
4
1
2
3
4
1
2
3
4
5
6
图9-10. Individual Output Enable and Disable
表9-14. Glitch-less Operation, Divider Synchronization and Global/Individual OE Settings
REGISTER BIT ADDRESS
REGISTER BIT FIELD NAME
DESCRIPTION
R0[14]
PDN_INPUT_SEL
Configures PDN pin as PDN or SYNCN
Generates SYNC signal through serial
interface
R0[5]
SYNC
CH1_GLITCHLESS_EN,
CH2_GLITCHLESS_EN,
CH3_GLITCHLESS_EN,
CH4_GLITCHLESS_EN
Enables Glitch-less switching for OUT1/
OUT2/OUT3/OUT4
R57[9], R63[9], R68[9], R73[9]
CH1_SYNC_EN, CH2_SYNC_EN,
CH3_SYNC_EN, CH4_SYNC_EN
R57[3], R63[3], R68[3], R73[3]
R57[1], R63[1], R68[1], R73[1]
R57[0], R63[0], R68[0], R73[0]
Enables SYNC for OUT1/OUT2/OUT3/OUT4
CH1_MUTESEL, CH2_MUTESEL,
CH3_MUTESEL, CH4_MUTESEL
Sets Output level when mute on OUT1/
OUT2/OUT3/OUT4
CH1_MUTE, CH2_MUTE, CH3_MUTE,
CH4_MUTE
Mutes output on OUT1/OUT2/OUT3/OUT4
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9.3.4 Power Supplies and Power Management
The CDCE6214-Q1 provides multiple power supply pins. Each of the power supplies supports 1.8 V, 2.5 V, or
3.3 V individually. Internal low-dropout regulators (LDO) source the internal blocks and allow each pin to be
supplied with its individual supply voltage. The VDDREF pin supplies the control pins and the serial interface,
therefore any pullup resistors shall be connected to the same domain as VDDREF.
The device is very flexible with respect to internal power management. Each block offers a power-down bit and
can be disabled to save power when the block is not required. The available bits are illustrated in 表 9-15. The
bypass output Y0 is connected to the pdn_ch4 bit. Each output channel has a bit which should be adapted to the
applied supply voltage, ch[4:1]_1p8vdet.
表9-15. Power Management
VDDREF
VDDVCO
VDDO_12
R0[1] - POWERDOWN
R4[4] - CH1_PD
VDDO_34
R0[1] - POWERDOWN
R4[6] - CH3_PD
R0[1] - POWERDOWN
R0[1] - POWERDOWN
R5[8] - PLL_VCOBUFF_LDO_PD
R5[7] - PLL_VCO_LDO_PD
R5[6] - PLL_VCO_BUFF_PD
R5[5] - PLL_CP_LDO_PD
R5[4] - PLL_LOCKDET_PD
R5[3] - PLL_PSB_PD
R4[5] - CH2_PD
R4[7] - CH4_PD
R5[2] - PLL_PSA_PD
R5[1] - PLL_PFD_PD
R53[6] - PLL_NCTR_EN
R53[3] - PLL_CP_EN
9.3.5 Control Pins
The ultra-low power clock generator is controlled by multiple LVCMOS input pins.
HW_SW_CTRL pin acts as EEPROM page select. The CDCE6214-Q1 clock generator contains two pages of
configuration settings. The level of this pin is sampled after device power up. A low level selects page zero. A
high level selects page one. The HW_SW_CTRL pin is a tri-level input pin. This third voltage level is
automatically applied by an internal voltage divider. The mid-level is used to select an internal default where the
serial interface is enabled.
PDN/SYNCN (pin 8) , SCL (pin 12), and SDA (pin 19) have a secondary functionality and can act as general-
purpose inputs and outputs (GPIO). This means that either the serial interface or the GPIO functionality can be
active.
PDN/SYNCN resets the internal circuitry and is used in the initial power-up sequence. The pin can be
reconfigured to act as synchronization input. The differential outputs are kept in mute while SYNCN is low. When
SYNCN is high, outputs are active.
表9-16. Control and GPIO Pins
PIN NO.
23
NAME
HW_SW_CTRL
GPIO1
TYPE
2-LEVEL INPUT
3-LEVEL INPUT
OUTPUT
TERMINATION
PUPD
Input
-
Yes
-
-
20
Input/Output
Yes
Yes
PU (when Input)
Open-Drain I/O in
I2C mode, CMOS
(Input)
19
GPIO2
Input/Output
Yes
-
Yes
12
11
8
GPIO3
GPIO4
PDN
Input
Input/Output
Input
Yes
Yes
Yes
-
-
-
-
-
-
Yes
PU (when Input)
PU (when Input)
PUPD
-
-
4
REFSEL
Input
Yes
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表9-17. GPIO Input/Output Signal List
ABBREVIATION
TYPE
DESCRIPTION
Frequency Increment; Increments the MASH
numerator
FREQ_INC
Input
Frequency Decrement; Decrements the
MASH numerator
FREQ_DEC
OE (global)
Input
Input
Enables or disables all differential outputs
Y[4:1] (bypass not affected)
SSC_EN
OE1
Input
Input
Input
Input
Input
Enables or disables SSC.
Enables or disables OUT1
Enables or disables OUT2
Enables or disables OUT3
Enables or disables OUT4
OE2
OE3
OE4
PLL Lock Status. 0 = PLL out of lock; 1 =
indicates PLL in lock
PLL_LOCK
Output
9.4 Device Functional Modes
9.4.1 Operation Modes
The operating modes listed in 表 9-18 can be set, and the GPIOs configured. An operating mode change only
becomes effective when it is loaded from the EEPROM after a power cycle.
表9-18. Modes of Operations
DESCRIPTION
I2C + GPIO
OE
MODE
Fall-back
Pin Mode
REFSEL
M
HW_SW_CTRL
GPIO1
GPIO2
SDA
GPIO3
SCL
GPIO4
I/O
M
I/O
L/H
L/H
OE1
OE2
OE3
OE4
Serial Interface
Mode
I2C + GPIO
L/H
L/H
I/O
SDA
SCL
I/O
9.4.1.1 Fall-Back Mode
As the programming interface can be intentionally deactivated using the EEPROM, an accidental disabling of the
I2C blocks further access to the device. The serial interface can be forced using the fall-back mode. To enter this
mode, the user leaves pin 4 and pin 23 floating while the supply voltage is applied to VDDREF. In this mode,
EEPROM Read at power up is bypassed and device boots in default mode. In this mode, pin 11 is pre-
configured as an input and pin 20 is configured as an output. After powering up in fall-back mode, the device can
be re-programmed through serial interface and be re-configured for normal operation. EEPROM can also be re-
programmed. The PLL would not be auto-calibrated, however, and the I2C interface would be active. This mode
would allow the user to fully configure the device before re-locking the PLL.
9.4.1.2 Pin Mode
In pin mode, the pins 12 and 19 are input pins which act as individual output enable pins. Together with pins 11
and 20, this allows for one output enable pin per output channel.
9.4.1.3 Serial Interface Mode
In serial interface mode, pins 12 and 19 are configured as an I2C interface.
9.5 Programming
9.5.1 I2C Serial Interface
The CDCE6214-Q1 ultra-low power clock generator provides an I2C-compatible serial interface for register and
EEPROM access. The device is compatible to standard-mode I2C at 100 kHz and the fast-mode I2C at 400-kHz
clock frequency.
1. In fall-back mode, I2C slave address = 67h.
2. In other modes, I2C slave address = 68h (Default).
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3. The LSB bit of the device can be programmed in the EEPROM. For example, if I2C_A0 is programmed H in
Page 0 of EEPROM, setting HW_SW_CTRL=0 would set I2C address as 69h.
4. Two devices with EEPROM + 1 device in fall-back mode can be used on the same I2C bus with addresses
67h, 68h and 69h.
表9-19. I2C-Compatible Serial Interface, Slave Address Byte 16 17
7
6
5
4
3
2
1
0
Slave Address [6:0]
R/W# Bit
表9-20. I2C-Compatible Serial Interface, Programmable Slave Address 18 19
A6
A5
A4
A3
A2
A1
A0
HW_SW_SEL DESCRIPTION
1
1
1
0
0
1
1
1
MID
Fall-back Mode
EEPROM Page
0
1
1
0
0
1
1
0
0
0
0
I2C_A0
I2C_A0
LOW
EEPROM Page
1
1
HIGH
The serial interface uses the following protocol as shown in 图 9-11. The slave address is followed by a word-
wide register offset and a word-wide register value.
16
The slave address consists of two sections. The hardwired MSBs A[6:1] and the software-selectable LSBs A[0].
The R/W# bit indicates a read (1) or a write (0) transfer.
In EEPROM Page 0, Serial Interface is not available. Device configured in Pin Mode
In EEPROM Page 1, I2C_A0 is programmed as 0, Expected Slave Address is 68h
17
18
19
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Write Transfer
7
1
1
S
Slave Address
Wr
A
8
8
1
1
Register Address High
A
Register Address Low
A
8
8
1
1
Date Byte High
A
Date Byte Low
A
P
Read Transfer
7
1
1
S
Slave Address
Wr
A
8
8
1
1
Register Address High
A
Register Address Low
A
7
1
1
Sr
Slave Address
Rd
A
8
8
1
1
Date Byte High
A
Date Byte Low
N
P
Legend
S
Sr
Start condition sent by master device
Write bit = 0 sent by master device
Acknowledge sent by master device
Stop condition sent by master device
Not-acknowledge sent by master device
|
|
|
Repeated start condition sent by master device
Read bit = 1 sent by master device
Wr Rd
A
P
N
A
Acknowledge sent by slave device
N
|
Not-acknowledge sent by slave device
Data
Data
Data sent by master | Data sent by slave
图9-11. I2C-Compatible Serial Interface, Supported Protocol
9.5.2 EEPROM
9.5.2.1 EEPROM - Cyclic Redundancy Check
The device contains a cyclic redundancy check (CRC) function for reads from the EEPROM to the device
registers. At start-up, the EEPROM will be read internally and a CRC value calculated. One of the EEPROM
words contains an earlier stored CRC value. The stored and the actual CRC value are compared and the result
transferred to register. The CRC calculation can be triggered again by writing a 1 to the update_crc bit. A
mismatch between stored and calculated CRC value is informational only and non-blocking to the device
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operation. Just reading back the CRC status bit and the live CRC value can speed up in-system EEPROM
programming and avoid reading back each word of the EEPROM for known configurations.
The polynomial used is CCITT-CRC16: x16 + x12 + x5 + 1.
9.5.2.2 Recommended Programming Procedure
TI recommends programming the registers of the device in the following way:
1. Read-back factory default EEPROM page configuration. Each device will have different EEPROM base page
configuration.
2. Modify register bits.
3. Ensure that ee_lock is set to 5h (unlock) when overwriting the EEPROM.
4. Program register addresses in descending order from 0x53 to 0x00 including all register addresses with
reserved values.
9.5.2.3 EEPROM Access
Note
The EEPROM word write access time is typically 8 ms.
There are two methods to write into the internal EEPROM
1. Register Commit method.
2. EEPROM Direct Access Method
Use the following steps to bring the device into a good known configuration.
1. Power down all the supplies.
2. Apply PDN = LOW.
3. REFSEL and HW_SW_CTRL pins can be High, Low or High-Z. For factory programmed device, I2C
interface is not available when HW_SW_CTRL is LOW.
4. Apply power supplies to all VDD pins. When device operation is not required, apply power supply to
VDDREF.
5. Apply PDN = HIGH.
6. Use the I2C interface to configure the device.
9.5.2.3.1 Register Commit Flow
In the Register Commit flow, all bits from the device registers are copied into the EEPROM. The recommended
flow is:
1. Pre-configure the device as desired, except the serial interface using mode.
2. Write 1 to RECAL to calibrate the VCO in this operation mode.
3. Select the EEPROM page, to copy the register settings into, using REGCOMMIT_PAGE.
4. Unlock the EEPROM for write access with EE_LOCK = x5.
5. Start the register commit operation by writing 1 to REGCOMMIT.
6. Force a CRC update by writing a 1 to UPDATE_CRC.
7. Read back the calculated CRC in NVMLCRC.
8. Store the read CRC value in the EEPROM by writing 0x3F to NVM_WR_ADDR and then the CRC value to
NVM_WR_DATA.
9.5.2.3.2 Direct Access Flow
In the EEPROM direct access flow, the EEPROM words are directly accessed using the address and the data
bit-fields. The recommended flow is:
1. Prepare an EEPROM image consisting of 64 words of 16 bits each.
2. Unlock the EEPROM for write access with EE_LOCK = 0x5.
3. Write the initial address offset to the address bit-field. Write a 0x00 to NVM_WR_ADDR.
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4. Loop through the EEPROM image from address 0 to 63 by writing each word from the image to
NVM_WR_DATA. The EEPROM word address is automatically incremented by every write access to
NVM_WR_DATA.
Write Transfer
I2C register
offset
15
15
6
5
0
0
Reserved
NVM_WR_ADDR
0x0E
NVM_WR_DATA
0x0D
Read Transfer
I2C register
offset
15
15
6
5
0
0
Reserved
NVM_RD_ADDR
0x0B
0x0C
NVM_RD_DATA
Copyright
©
2017, Texas Instruments Incorporated
图9-12. EEPROM Direct Access Using I2C
9.5.2.4 Register Bits to EEPROM Mapping
Register bits settings are mapped into EEPROM. EEPROM is divided into three segments:
• EEPROM Base Page: Selectable by connecting HW_SW_CTRL pin either to Logic 0 to Logic 1.
• EEPROM Page 0: Selectable by connecting HW_SW_CTRL pin to Logic 0.
• EEPROM Page 1: Selectable by connecting HW_SW_CTRL pin to Logic 1.
表9-21. EEPROM Mapping 20 21 22 23
15
0
14
1
13
1
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
1
0
1
0
R5[8] R5[7] R5[6] R5[5] R5[4] R5[1] R4[3] R4[2] R4[1] R4[0] R3[9] R0[3]
0
1
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
R15[5]
1
0
0
0
0
0
1
0
0
0
0
R47[1 R47[1 R47[1
4
R48[4] R48[3] R48[2] R48[1] R48[0]
R47[9] R47[8] R47[7]
0
0
0
0
0
2]
1]
0]
20
21
22
23
Address Locations 0-15: EEPROM Base Page
Address Locations 16-39: EEPROM Page 0
Address Locations 40-63: EEPROM Page 1
Bit locations marked in Red may vary from device to device
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15
表9-21. EEPROM Mapping 20 21 22 23 (continued)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R48[1 R48[1 R48[1 R48[1 R48[1
5
6
0
0
R49[4] R49[3] R49[2] R49[1] R49[0]
R48[9] R48[8] R48[7] R48[6] R48[5]
4]
3]
2]
1]
0]
R50[1
0
0
R50[9] R50[8]
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0]
R53[2] R53[1] R53[0]
7
8
R55[6] R53[6]
1
0
1
1
0
1
0
0
0
0
1
0
0
1
0
0
0
R58[4] R58[3] R58[2] R58[1] R58[0]
R55[9] R55[8] R55[7]
R60[1 R60[1 R60[1 R60[1
9
R60[3] R60[2] R60[1] R60[0] R59[9] R59[8] R59[7] R59[6] R59[5] R59[4]
5]
4]
3]
2]
10
11
12
13
14
15
16
17
18
R65[8] R65[7] R65[6] R65[5] R65[4]
1
0
0
0
0
0
0
R64[9] R64[8] R64[7] R64[6] R64[5]
0
0
0
0
0
0
R69[9] R69[8] R69[7] R69[6] R69[5]
1
R66[3] R66[2] R66[1] R66[0] R65[9]
R74[5]
1
R71[3] R71[2] R71[1] R71[0] R70[9] R70[8] R70[7] R70[6] R70[5] R70[4]
1
0
R76[0] R75[9] R75[8] R75[7] R75[6] R75[5] R75[4]
1
0
0
0
0
R74[9] R74[8] R74[7] R74[6]
0
0
0
0
0
0
0
0
0
0
R79[3] R79[2] R79[1] R79[0] R76[9] R76[8] R76[7] R76[6] R76[3] R76[2] R76[1]
0
R81[3]
1
0
0
0
0
0
0
0
0
R80[3]
0
R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] R0[15] R0[14] R0[13] R0[12]
R0[10]
R0[8] R0[0]
R2[6] R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] R1[15] R1[14] R1[13] R1[12] R1[11] R1[10] R1[9] R1[8] R1[7]
R5[3] R5[2] R4[7] R4[6] R4[5] R4[4] R3[4] R3[3] R2[13] R2[12] R2[11] R2[10] R2[9] R2[8] R2[7]
R24[1 R24[1 R24[1 R24[1
0
19
20
21
R24[9] R24[8]
0
0
R24[5] R24[4] R24[3] R24[2] R24[1] R24[0]
0
0
5]
2]
1]
0]
R25[1 R25[1 R25[1 R25[1 R25[1
R27[0]
0
R25[9] R25[7] R25[6] R25[5] R25[4] R25[3] R25[2] R25[1] R25[0]
4]
3]
2]
1]
0]
R30[1 R30[1 R30[1 R30[1 R30[1
R30[9] R30[8] R30[7] R30[6] R30[5] R30[4] R30[3] R30[2] R30[1] R30[0] R27[1]
4]
3]
2]
1]
0]
R31[1 R31[1 R31[1 R31[1 R31[1 R31[1
22
23
24
R31[9] R31[8] R31[7] R31[6] R31[5] R31[4] R31[3] R31[2] R31[1] R31[0]
5]
4]
3]
2]
1]
0]
R33[7] R33[6] R33[5] R33[4] R33[3] R33[2] R33[1] R33[0] R32[7] R32[6] R32[5] R32[4] R32[3] R32[2] R32[1] R32[0]
R33[1 R33[1 R33[1 R33[1 R33[1 R33[1
R34[7] R34[6] R34[5] R34[4] R34[3] R34[2] R34[1] R34[0]
R33[9] R33[8]
5]
4]
3]
2]
1]
0]
R43[1
0]
R41[1
5]
25
26
27
28
29
30
31
32
33
R43[9] R43[8] R43[7] R43[6] R43[5] R43[4] R43[3] R43[2] R43[1] R43[0] R42[5] R42[3] R42[2] R42[1]
R51[1
0]
R43[1 R43[1 R43[1 R43[1 R43[1
0
0
1
R51[6]
0
0
R47[6] R47[5] R47[4] R47[3]
5]
4]
1
3]
0
2]
0
1]
0
R56[1
0]
R56[9] R56[8] R56[7] R56[6] R56[5] R56[4] R56[3] R56[2] R56[1] R56[0] R53[3]
R57[1 R57[1
4]
R56[1 R56[1 R56[1 R56[1 R56[1
R57[9] R57[8] R57[7] R57[6] R57[5] R57[4] R57[3] R57[1] R57[0]
R60[1 R60[1
2]
5]
4]
4]
0]
3]
0]
3]
3]
R62[9] R62[8] R62[7]
2]
1]
R59[1 R59[1 R59[1 R59[1 R59[1
R62[6] R62[5] R62[4] R62[3] R62[2] R62[1] R62[0]
R63[7] R63[6] R63[5] R63[4] R63[3] R63[1] R63[0]
R60[5] R60[4]
1]
0]
5]
1]
1]
2]
1]
R62[1 R62[1 R62[1 R62[1 R62[1 R62[1
5]
4]
3]
2]
3]
2]
R71[9] R71[5] R71[4]
R65[1 R65[1 R65[1 R63[1 R63[1
4]
R67[6] R67[5] R67[4] R67[3] R67[2] R67[1] R67[0] R66[5] R66[4]
R63[9] R63[8]
2]
R67[1 R67[1 R67[1 R67[1 R67[1 R67[1
5]
R68[7] R68[6] R68[5] R68[4] R68[3] R68[1] R68[0]
R72[6] R72[5] R72[4] R72[3] R72[2] R72[1] R72[0]
R67[9] R67[8] R67[7]
4]
3]
1]
R71[1
0]
R70[1 R68[1 R68[1
1]
R68[9] R68[8]
3]
2]
20
21
22
23
Address Locations 0-15: EEPROM Base Page
Address Locations 16-39: EEPROM Page 0
Address Locations 40-63: EEPROM Page 1
Bit locations marked in Red may vary from device to device
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表9-21. EEPROM Mapping 20 21 22 23 (continued)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R72[1 R72[1 R72[1 R72[1 R72[1 R72[1
34
35
36
R73[7] R73[6] R73[5] R73[4] R73[3] R73[1] R73[0]
R72[9] R72[8] R72[7]
5]
4]
3]
2]
1]
0]
R75[1 R75[1 R75[1 R75[1 R75[1 R73[1 R73[1
0
0
0
0
0
0
R77[1] R77[0] R76[5] R76[4]
R73[9] R73[8]
5]
0
4]
0
3]
2]
1]
0
3]
0
2]
0
R78[1
2]
0
0
0
0
R79[9]
0
0
37
38
39
40
41
42
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] R0[15] R0[14] R0[13] R0[12]
R0[10]
R0[8] R0[0]
R2[6] R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] R1[15] R1[14] R1[13] R1[12] R1[11] R1[10] R1[9] R1[8] R1[7]
R5[3] R5[2] R4[7] R4[6] R4[5] R4[4] R3[4] R3[3] R2[13] R2[12] R2[11] R2[10] R2[9] R2[8] R2[7]
R24[1 R24[1 R24[1 R24[1
0
43
44
45
R24[9] R24[8]
0
0
R24[5] R24[4] R24[3] R24[2] R24[1] R24[0]
0
0
5]
2]
1]
0]
R25[1 R25[1 R25[1 R25[1 R25[1
4]
R27[0]
0
R25[9] R25[7] R25[6] R25[5] R25[4] R25[3] R25[2] R25[1] R25[0]
3]
2]
1]
0]
R30[1 R30[1 R30[1 R30[1 R30[1
4]
R30[9] R30[8] R30[7] R30[6] R30[5] R30[4] R30[3] R30[2] R30[1] R30[0] R27[1]
3]
2]
1]
0]
R31[1 R31[1 R31[1 R31[1 R31[1 R31[1
46
47
48
R31[9] R31[8] R31[7] R31[6] R31[5] R31[4] R31[3] R31[2] R31[1] R31[0]
5]
4]
3]
2]
1]
0]
R33[7] R33[6] R33[5] R33[4] R33[3] R33[2] R33[1] R33[0] R32[7] R32[6] R32[5] R32[4] R32[3] R32[2] R32[1] R32[0]
R33[1 R33[1 R33[1 R33[1 R33[1 R33[1
R34[7] R34[6] R34[5] R34[4] R34[3] R34[2] R34[1] R34[0]
R33[9] R33[8]
5]
4]
3]
2]
1]
0]
R43[1
0]
R41[1
5]
49
50
51
52
53
54
55
56
57
58
59
R43[9] R43[8] R43[7] R43[6] R43[5] R43[4] R43[3] R43[2] R43[1] R43[0] R42[5] R42[3] R42[2] R42[1]
R51[1
0]
R43[1 R43[1 R43[1 R43[1 R43[1
0
0
1
R51[6]
0
0
R47[6] R47[5] R47[4] R47[3]
5]
4]
1
3]
0
2]
0
1]
0
R56[1
0]
R56[9] R56[8] R56[7] R56[6] R56[5] R56[4] R56[3] R56[2] R56[1] R56[0] R53[3]
R57[1 R57[1
4]
R56[1 R56[1 R56[1 R56[1 R56[1
R57[9] R57[8] R57[7] R57[6] R57[5] R57[4] R57[3] R57[1] R57[0]
R60[1 R60[1
2]
5]
4]
4]
0]
3]
0]
3]
3]
R62[9] R62[8] R62[7]
2]
1]
R59[1 R59[1 R59[1 R59[1 R59[1
R62[6] R62[5] R62[4] R62[3] R62[2] R62[1] R62[0]
R63[7] R63[6] R63[5] R63[4] R63[3] R63[1] R63[0]
R60[5] R60[4]
1]
0]
5]
1]
1]
2]
1]
R62[1 R62[1 R62[1 R62[1 R62[1 R62[1
5]
4]
3]
2]
3]
2]
R71[9] R71[5] R71[4]
R65[1 R65[1 R65[1 R63[1 R63[1
4]
R67[6] R67[5] R67[4] R67[3] R67[2] R67[1] R67[0] R66[5] R66[4]
R63[9] R63[8]
2]
R67[1 R67[1 R67[1 R67[1 R67[1 R67[1
5]
R68[7] R68[6] R68[5] R68[4] R68[3] R68[1] R68[0]
R72[6] R72[5] R72[4] R72[3] R72[2] R72[1] R72[0]
R73[7] R73[6] R73[5] R73[4] R73[3] R73[1] R73[0]
R67[9] R67[8] R67[7]
4]
3]
1]
R71[1
0]
R70[1 R68[1 R68[1
1]
R68[9] R68[8]
3]
2]
R72[1 R72[1 R72[1 R72[1 R72[1 R72[1
R72[9] R72[8] R72[7]
5]
4]
3]
2]
1]
0]
R75[1 R75[1 R75[1 R75[1 R75[1 R73[1 R73[1
0
0
0
R77[1] R77[0] R76[5] R76[4]
R73[9] R73[8]
5]
0
4]
0
3]
R79[9]
0
2]
1]
0
3]
0
2]
0
R78[1
2]
60
61
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
20
21
22
23
Address Locations 0-15: EEPROM Base Page
Address Locations 16-39: EEPROM Page 0
Address Locations 40-63: EEPROM Page 1
Bit locations marked in Red may vary from device to device
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15
表9-21. EEPROM Mapping 20 21 22 23 (continued)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
62
63
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[ SCRC[
15] 14] 13] 12] 11] 10] 9] 8] 7] 6] 5] 4] 3] 2] 1] 0]
表9-22. Register Defaults in Fall-Back Mode and EEPROM Mode
REGISTER
ADDRESSES
FALL-BACK
HW_SW_CTRL = HW_SW_CTRL =
REGISTER
ADDRESSES
FALL-BACK
MODE
HW_SW_CTRL = HW_SW_CTRL =
MODE
x0000
x0000
x0000
x0000
x0004
x0000
x0008
x1000
x0000
x0008
x0008
xA181
x2000
x0006
x0000
x0008
xA181
x2000
x0006
x0000
x0008
xA181
x2000
x0006
x0000
x0008
x0008
x502C
x4000
x0006
x001E
x3400
x0069
x5000
x40C0
x01C0
x0013
x1A14
x0A00
0
1
0
1
R85
R84
R83
R82
R81
R80
R79
R78
R77
R76
R75
R74
R73
R72
R71
R70
R69
R68
R67
R66
R65
R64
R63
R62
R61
R60
R59
R58
R57
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
x0000
x0000
xFF00
x01C0
x0004
x0008
x0008
x0000
x0002
x0188
x0008
xA181
x2000
x0006
x0406
x0008
xA181
x2000
x0006
x0006
x4008
xA181
x2000
x0006
x0000
x0008
x0008
x502C
x4000
x0006
x001E
x3400
x0069
x5000
x40C0
x01C0
x0013
x1A05
x0280
x0000
x0000
xFF00
x01C0
x0004
x0008
x0008
x0000
x0002
x0188
x8008
xA181
x0000
x0006
x0406
x0808
xA181
x0000
x0006
x0006
x4808
xA181
x0000
x0006
x0000
x6028
x8008
x502C
x0000
x0006
x001E
x3400
x0069
x5000
x40C0
x01C0
x0013
x1A05
x0280
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
x0002
x0000
x0000
x0000
x0000
x0000
x0000
x0000
x0000
x0000
x0000
x0000
x0030
x0000
x0000
x0005
x0000
x0400
x0718
x0000
x06A2
x0000
x0000
x0000
x0000
x26C4
x921F
xA037
x0000
x0000
x0000
x0000
x0000
x0000
x0000
x0000
x0000
x0008
x0000
x0002
x0000
x0000
x0000
x0000
x0000
x0000
x0028
x0000
x0000
x0000
x0000
x0030
x0000
x0000
x0004
x0000
x0400
x091C
x2406
x06A2
x0590
x0000
x0000
x0000
x26C4
x921F
xA037
x0000
x0000
x0000
x0000
xA777
x7BFA
x0001
x0C2D
x0E6C
x0008
x0000
x0002
x0000
x0000
x0000
x0000
x0000
x0000
x0028
x0000
x0000
x0000
x0000
x0030
x0000
x0000
x0004
x0000
x0400
x091C
x2406
x06A2
x0513
x0000
x0000
x0000
x26C4
x921F
xA037
x0000
x0000
x7002
x003F
xA777
xA777
x0001
x0C0D
x0E6C
x0008
x0000
R8
R7
R6
R5
R4
20
Address Locations 0-15: EEPROM Base Page
Address Locations 16-39: EEPROM Page 0
Address Locations 40-63: EEPROM Page 1
21
22
23
Bit locations marked in Red may vary from device to device
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表9-22. Register Defaults in Fall-Back Mode and EEPROM Mode (continued)
REGISTER
ADDRESSES
FALL-BACK
MODE
HW_SW_CTRL = HW_SW_CTRL =
REGISTER
ADDRESSES
FALL-BACK
MODE
HW_SW_CTRL = HW_SW_CTRL =
0
1
0
1
R46
R45
R44
R43
x0000
x4F80
x0318
x0051
x0000
x4F80
x0318
x0051
x0000
x4F80
x0318
x0051
R3
R2
R1
R0
x0000
x0000
x2310
x0000
x0200
x0000
x7654
x0001
x0200
x0000
x7652
x2000
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10 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
A typical application using the I2C interface and a 25-MHz crystal input is shown in 图 10-1. The two ends of 25-
MHz XTAL are connected to pin 1 and 2. The REFSEL pin is pulled down to select a secondary input. The
HW_SW_CTRL can be pulled either low or high if EEPROM is used, or kept floating if EEPROM is unused. 1.8
V, 2.5 V, or 3.3 V can be supplied to the VDD_REF and VDD_VCO pins, as well as VDDO_12 and VDDO_34
pins with filtering. Data and clock lines of I2C must be pulled to VDD_REF using pullup resistors. The PDN can
be connected to the MCU if a hardware reset is required, otherwise it can be left floating. The GPIO1 and 4 pins
can be connected to the MCU if needed, otherwise they can be left floating. Unused outputs can be left floating.
1.8V
/ 2.5V
/ 3.3V
1.8V
/ 2.5V
/ 3.3V
1.8V
/ 2.5V
/ 3.3V
1.8V
/ 2.5V
/ 3.3V
VDD_REF
VDD_VCO
VDDO_12
VDDO_34
SECREF_P
OUT0
OUT1_P
OUT1_N
OUT2_P
OUT2_N
OUT3_P
OUT3_N
OUT4_P
OUT4_N
100 nF
25 MHz
SECREF_N
PDN
100 nF
100 nF
100 nF
MCU_GPIO
U1
CDCE6214
100 nF
100 nF
REFSEL
HW_SW_CTRL
100 nF
VDD_REF
DAP
100 nF
GND
GPIO4
SCL/GPIO3
SDA/GPIO2
GPIO1
MCU_GPIO
MCU_I2C_SCL
MCU_I2C_SDA
MCU_GPIO
图10-1. Typical Application Schematic With I2C Interface
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10.2 Typical Application
图10-2 图10-2 shows typical block diagram for eAVB system using CDCE6214-Q1.
25MHz
XTAL
PFD
Output
Divider
2.4576GHz
VCO
Audio CODEC
N Div
98.304
Output
Divider
CDCE6214-Q1
Processor
PTP
TS
PHY
CNT1
CNT1
I2C
MAC
CMP
(freq inc/dec by
< 1ppm steps)
图10-2. eAVB System Block Diagram Using CDCE6214-Q1
10.2.1 Design Requirements
For designs with the CDCE6214-Q1, the designer must select:
• a primary or secondary input
• an input type
• an input frequency
• a device communication mode (I2C and/or EEPROM)
• the required device operation modes to configure the connections of GPIO pins
• a supply voltage (1.8 V, 2.5 V, or 3.3 V)
• a digital reference (1.8 V, 2.5 V, or 3.3 V)
• an output reference (1.8 V, 2.5 V, or 3.3 V)
• an output format
10.2.2 Detailed Design Procedure
The CDCE6214-Q1 is designed for ease-of-use. To power up the device:
1. Either tie the power supply pin (VDD_REF, VDD_VCO, VDDO_12 and VDDO_34) together or independently
connect them to the 1.8-V, 2.5-V, or 3.3-V power supply.
2. Solder the GND Pin (DAP) to the PCB Plane.
3. Ensure that the REFSEL, HW_SW_CTRL, and PDN configuration pins are appropriately connected:
a. Internally connect the PDN pin to VDD_REF through a pullup resistor. When floating, the PDN pin would
automatically release device from PDN.
b. If PDN pin is low, the device will not respond to I2C commands.
c. REFSEL and HW_SW_CTRL are tri-level pins. If left floating, the device will start in fall-back mode.
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The device is factory-configured to provide:
• 100-MHz LVDS with 25-MHz XTAL when HW_SW_CTRL=L. The 25-MHz output on OUT0 is enabled.
• 100-MHz LP-HCSL with 25-MHz XTAL and HW_SW_CTRL = H. The 25-MHz output on OUT0 is enabled.
10.2.3 Application Curves
Reference: Crystal Closed-Loop Phase 100-MHz LP-HCSL
Reference: Crystal Closed-Loop Phase
Input 25 MHz Noise from 2.4576-
GHz VCO
24.576-MHz
LVCMOS
Input 25 MHz Noise from 2.4-GHz
VCO
图10-3. 100-MHz LP-HCSL Output for PCIe
图10-4. 24.576MHz LVCMOS Output for Audio
Application
Clocking
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11 Power Supply Recommendations
The CDCE6214-Q1 provides multiple power supply pins. Each power supply supports 1.8 V, 2.5 V, or 3.3 V.
Internal low-dropout regulators (LDO) source the internal blocks and allow each pin to be supplied with its
individual supply voltage. The VDD_REF pin supplies the control pins and the serial interface. Therefore, any
pullup resistors shall be connected to the same domain as VDD_REF. VDD_VCO powers all PLL blocks.
VDDO_12 powers outputs OUT1 and OUT2. VDDO_34 powers OUT0, OUT3, and OUT4.
VDD_REF and VDDO_34 can be used for level translation operation on OUT0.
11.1 Power-Up Sequence
There are no restrictions from the device for applying power to the supply pins. From an application perspective,
TI recommends to either apply all the VDDs at the same time or apply the VDDREF first. The digital core is
connected to VDDREF and thus the settings of the EEPROM are applied automatically.
11.2 Decoupling
TI recommends isolating all power supplies using a ferrite bead and provide decoupling for each of the supplies.
TI also recommends optimizing the decoupling for the respective layout, and consider the power supply
impedance to optimize for the individual frequency plan.
An example for a decoupling per supply pin: 1x 4.7 µF, 1x 470 nF, and 1x 100 nF.
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12 Layout
12.1 Layout Guidelines
For this example, follow these guidelines:
• Isolate inputs and outputs using a GND shield. BROKEN_LINK routes all inputs and outputs as differential
pairs.
• Isolate outputs to adjacent outputs when generating multiple frequencies.
• Isolate the crystal area, connect the GND pads of the crystal package and flood the adjacent area. 图12-2
shows a foot print which supports multiple crystal sizes.
• Try to avoid impedance jumps in the fan-in and fan-out areas when possible.
• Use five VIAs to connect the thermal pad to a solid GND plane. Full-through VIAs are preferred.
• Place decoupling capacitors with small capacitance values very close to the supply pins. Try to place them
very close on the same layer or directly on the backside layer. Larger values can be placed more far away. 图
12-2 shows three decoupling capacitors close to the device. Ferrite beads are recommended to isolate the
different frequency domains and the VDD_VCO domain.
• Preferably use multiple VIAs to connect wide supply traces to the respective power planes.
12.2 Layout Examples
图12-1. Layout Example, Top Layer
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图12-2. Layout Example, Bottom Layer
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
Contact your TI representative for more information.
13.1.2 Device Nomenclature
CDCE6214-Q1 - 62= clock generator 1= 1x PLL 4=4x outputs E = EEPROM, integer and fractional output
dividers
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CDCE6214TWRGERQ1
CDCE6214TWRGETQ1
ACTIVE
VQFN
VQFN
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
6214Q1
A2Z
ACTIVE
RGE
SN
6214Q1
A2Z
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2021
OTHER QUALIFIED VERSIONS OF CDCE6214-Q1 :
Catalog : CDCE6214
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCE6214TWRGERQ1
CDCE6214TWRGETQ1
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCE6214TWRGERQ1
CDCE6214TWRGETQ1
VQFN
VQFN
RGE
RGE
24
24
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
重要声明和免责声明
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