CDCV857BIDGGRG4 [TI]
CDCV857B, CDCV857BI 2.5-V Phase-Lock Loop Clock Driver 48-TSSOP -40 to 85;
| 型号： | CDCV857BIDGGRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CDCV857B, CDCV857BI 2.5-V Phase-Lock Loop Clock Driver 48-TSSOP -40 to 85 驱动 CD 光电二极管 逻辑集成电路 |
| 文件： | 总17页 (文件大小：842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
D
Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
D
Enters Low-Power Mode When No CLK
Input Signal Is Applied or PWRDWN Is Low
D
D
Operates From Dual 2.5-V Supplies
D
D
D
D
D
D
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 200 MHz
Low Jitter (cycle-cycle): 50 ps
Low Static Phase Offset: 50 ps
Low Jitter (Period): 35 ps
Available in a 48-Pin TSSOP Package or
56-Ball MicroStar Junior™ BGA Package
Consumes < 100-μA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
D
D
Distributes One Differential Clock Input to
10 Differential Outputs
D
Meets/Exceeds the Latest DDR JEDEC
Spec JESD82−1
Description
The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback
clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback
clocks (FBIN, FBIN), and the analog power input (AV ). When PWRDWN is high, theoutputs switch in phase
DD
and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)
and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input
frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this
detection circuit turns the PLL on and enables the outputs.
When AV is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857B is also able
DD
to track spread spectrum clocking for reduced EMI.
Since the CDCV857B is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV857B is characterized for both commercial and
industrial temperature ranges.
AVAILABLE OPTIONS
T
TSSOP (DGG)
CDCV857BDGG
CDCV857BIDGG
MicroStar Junior™ BGA (GQL)
A
0°C to 85°C
CDCV857BGQL
—
−40°C to 85°C
FUNCTION TABLE
(Select Functions)
INPUTS
PWRDWN
OUTPUTS
PLL
AV
CLK
L
CLK
Y[0:9]
Y[0:9]
FBOUT
FBOUT
DD
GND
H
H
L
H
L
L
H
Z
Z
L
H
L
L
H
Z
Z
L
H
L
Bypassed/Off
GND
H
Bypassed/Off
X
L
H
L
Z
Z
H
L
Z
Z
H
L
Off
Off
On
On
Off
X
L
H
2.5 V (nom)
2.5 V (nom)
2.5 V (nom)
H
H
X
L
H
L
H
H
Z
H
Z
<20 MHz <20 MHz
Z
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments Incorporated.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
™
MicroStar Junior (GQL) Package
(TOP VIEW)
DGG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
GND
Y0
Y0
VDDQ
Y1
GND
Y5
Y5
VDDQ
Y6
Y6
1
48
47
46
45
44
43
A
2
3
4
B
C
Y6
Y6
Y1
Y1
5
Y1
6
GND
GND
Y2
7
42 GND
41 GND
40 Y7
NC
NC
NC
GND
GND
GND
GND
8
9
D
E
F
NC
NC
NC
Y7
Y7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Y2
Y7
Y2
Y2
VDDQ
VDDQ
CLK
CLK
VDDQ
AVDD
AGND
GND
Y3
Y3
VDDQ
Y4
Y4
GND
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
VDDQ
Y9
Y9
GND
PWRDN
V
V
DDQ
DDQ
V
DDQ
NC
NC
NC
FBIN
FBIN
CLK
CLK
G
H
J
NC
NC
V
DDQ
V
DDQ
FBOUT
AV
DD
FBOUT
GND
AGND
GND
Y8
Y8
Y3
Y3
K
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
functional block diagram
3
Y0
2
Y0
5
Y1
37
PWRDWN
6
Power Down
and Test
Logic
Y1
16
AV
DD
10
Y2
9
Y2
20
Y3
19
Y3
22
Y4
23
Y4
46
Y5
47
Y5
13
14
CLK
CLK
44
Y6
43
Y6
PLL
FBIN 36
39
Y7
35
FBIN
40
Y7
29
Y8
30
Y8
27
Y9
26
Y9
32
FBOUT
33
FBOUT
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
Terminal Functions
TERMINAL
DGG
DESCRIPTION
NAME
AGND
AV
GQL
H1
17
Ground for 2.5-V analog supply
2.5-V Analog supply
16
G2
DD
CLK, CLK
FBIN, FBIN
FBOUT, FBOUT
GND
13, 14
35, 36
32, 33
F1, F2
F5, F6
H6, G5
I
I
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
O
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
A3, A4,
C1, C2,
C5, C6,
H2, H5,
K3, K4
PWRDWN
37
E6
I
Output enable for Y and Y
2.5-V Supply
V
DDQ
4, 11, 12,
15, 21, 28,
34, 38, 45
B3, B4,
E1, E2,
E5, G1,
G6, J3, J4
Y[0:9]
Y[0:9]
3, 5, 10,
20, 22, 27,
29, 39, 44,
46
A1, B2,
D1, J2,
K1, A6,
B5, D6,
J5, K6
O
O
Buffered output copies of input clock, CLK
Buffered output copies of input clock, CLK
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
A2, B1,
D2, J1,
K2, A5,
B6, D5,
J6, K5
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, V
, AV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
DDQ
DD
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
DDQ
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
DDQ
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
I
DDQ
Output clamp current, I (V < 0 or V > V )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O
O
DDQ
Continuous output current, I (V = 0 to V
O
O
DDQ
Continuous current to GND or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
DDQ
Package thermal impedance, θ (see Note 3): GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137.6°C/W
JA
Storage temperature range T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
recommended operating conditions (see Note 4)
MIN
2.3
TYP
MAX UNIT
V
2.7
2.7
V
V
DDQ
Supply voltage
AV
V
DDQ
− 0.12
DD
CLK, CLK, FBIN, FBIN
PWRDWN
V /2 – 0.18
DDQ
0.7
Low-level input voltage, V
V
IL
−0.3
CLK, CLK, FBIN, FBIN
PWRDWN
V
DDQ
/2 + 0.18
High-level input voltage, V
V
V
IH
1.7
V
DDQ
V
DDQ
V
DDQ
V
DDQ
+ 0.3
+ 0.3
+ 0.6
+ 0.6
DC input signal voltage (see Note 5)
Differential input signal voltage, V (see Note 6)
–0.3
0.36
0.7
dc
ac
CLK, FBIN
CLK, FBIN
V
ID
Input differential pair cross voltage, V (see Note 7)
V
DDQ
/2 – 0.2
V
DDQ
/2 + 0.2
−12
12
V
IX
High-level output current, I
mA
mA
V/ns
OH
OL
Low-level output current, I
Input slew rate, SR
1
0
4
Commercial
Industrial
85
Operating free-air temperature, T
°C
A
−40
85
NOTES: 4. The unused inputs must be held high or low to prevent them from floating.
5. The dc input signal voltage specifies the allowable dc execution of the differential input.
6. The differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input
level and VCP is the complementary input level.
7. The differential cross-point voltage is expected to track variations of V and is the voltage at which the differential signals must
CC
be crossing.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input voltage
TEST CONDITIONS
= 2.3 V, I = –18 mA
MIN
TYP
MAX UNIT
V
V
All inputs
V
V
V
V
V
–1.2
V
IK
DDQ
DDQ
DDQ
DDQ
DDQ
I
= min to max, I = –1 mA
V
– 0.1
1.7
OH
DDQ
High-level output voltage
Low-level output voltage
V
OH
= 2.3 V, I = –12 mA
OH
= min to max, I = 1 mA
0.1
0.6
OL
V
OL
V
V
= 2.3 V, I = 12 mA
OL
}
Differential outputs are terminated
with 120 Ω /CL = 14 pF (See
Figure 3)
V
V
Output voltage swing
1.1
V
– 0.4
OD
DDQ
w
Output differential cross-voltage
V
/2 – 0.15
V
/2
V
/2 + 0.15
OX
DDQ
DDQ
DDQ
I
I
Input current
V
V
= 2.7 V, V = 0 V to 2.7 V
10
10
μA
μA
I
DDQ
DDQ
I
High-impedance state output current
Power-down current on
= 2.7 V, V = V
or GND
OZ
O
DDQ
CLK and CLK = 0 MHz; PWRDWN
= Low; Σ of I and AI
I
20
100
μA
DDPD
V
DDQ
+ AV
DD
DD DD
f
f
= 170 MHz
= 200 MHz
7
9
10
12
O
AI
Supply current on AV
Input capacitance
mA
pF
DD
DD
O
C
V
= 2.5 V, V = V
or GND
2
2.5
3.5
I
DDQ
I
DDQ
†
‡
All typical values are at a respective nominal V
The differential output signal voltage specifies the differential voltage ⎮VTR − VCP⎮, where VTR is the true output level and VCP is the
.
DDQ
complementary output level.
The differential cross-point voltage is expected to track variations of V
The frequency range is 100 MHz to 200 MHz.
§
and is the voltage at which the differential signals must be crossing.
DDQ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
110
f
O
f
O
= 170 MHz
= 200 MHz
100
Without load
105
200
120
Differential outputs
terminated with
120 Ω/CL = 0 pF
f
O
f
O
f
O
f
O
= 170 MHz
= 200 MHz
= 170 MHz
= 200 MHz
240
I
Dynamic current on V
mA
DD
DDQ
210
260
280
250
Differential outputs
terminated with
120 Ω/CL = 14 pF
300
320
Part-to-part input capacitance
variation
ΔC
V
= 2.5 V, V = V
or GND
or GND
1
pF
DDQ
I
DDQ
DDQ
Input capacitance difference between
CLK and CLKB, FBIN, and FBINB
C
C
V
= 2.5 V, V = V
0.25
3.5
pF
pF
Δ)
I(
DDQ
DDQ
I
Output capacitance
V
= 2.5 V, V = V or GND
DDQ
2.5
3
O
O
†
All typical values are at a respective nominal V
.
DDQ
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
Operating clock frequency
Application clock frequency
Input clock duty cycle
f
60
200
MHz
CLK
40%
60%
10
{
Stabilization time (PLL mode)
μs
}
Stabilization time (Bypass mode)
30
ns
†
‡
The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK and V must be applied. Until phase lock is obtained, the specifications
DD
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply
for input modulation under SSC application.
A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).
switching characteristics
PARAMETER
TEST CONDITIONS
Test mode/CLK to any output
Test mode/CLK to any output
66 MHz
MIN
TYP
3.5
MAX
UNIT
ns
w
w
t
t
Low to high level propagation delay time
High-to low level propagation delay time
PLH
3.5
ns
PHL
−60
−35
−75
−50
−100
−75
1
60
35
ps
W
t
Jitter (period), See Figure 7
jit(per)
100/133/167/200 MHz
66 MHz
ps
75
W
t
Jitter (cycle-to-cycle), See Figure 4
ps
jit(cc)
100/133/167/200 MHz
66 MHz
50
100
75
W
t
t
Half-period jitter, See Figure 8
ps
jit(hper)
100/133/167/200 MHz
Load: 120 Ω/14 pF
66 MHz
Output clock slew rate, See Figure 9
2
V/ns
slr(o)
–100
–50
100
50
t
Static phase offset, See Figure 5
ps
(Ø)
100/133/167/200 MHz
Load: 120 Ω/14 pF
Load: 120 Ω/14 pF
tsk
Output skew, See Figure 6
70
100
900
ps
ps
(o)
f
t , t
r
Output rise and fall times (20% − 80%)
600
§
¶
Refers to the transition of the noninverting output.
This parameter is assured by design but can not be 100% production tested.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
PARAMETER MEASUREMENT INFORMATION
V
DD
V
Yx
R = 60 Ω
R = 60 Ω
V
DD
/2
V
Yx
CDCV857B
GND
Figure 1. IBIS Model Output Load
V
DD
/2
SCOPE
CDCV857B
−V /2
DD
C = 14 pF
R = 10 Ω
Z = 50 Ω
Z = 60 Ω
Z = 60 Ω
R = 50 Ω
V
(TT)
Z = 50 Ω
R = 10 Ω
R = 50 Ω
C = 14 pF
V
(TT)
−V /2
DD
V
(TT)
= GND
−V /2
DD
Figure 2. Output Load Test Circuit
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
V
DD
PROBE
CDCV857B
C = 14 pF
GND
Z = 60 Ω
Z = 60 Ω
C = 1 pF
C = 1 pF
R = 1 MΩ
R = 120 Ω
V
(TT)
C = 14 pF
R = 1 MΩ
V
(TT)
GND
V
(TT)
= GND
GND
Figure 3. Output Load Test Circuit for Crossing Point
Yx, FBOUT
Yx, FBOUT
t
t
c(n+1)
c(n)
t
= t
− t
jit(cc)
c(n) c(n+1)
Figure 4. Cycle-to-Cycle Jitter
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
PARAMETER MEASUREMENT INFORMATION
CLK
CLK
FBIN
FBIN
t
t
(
) n
(
) n+1
n = N
1
∑
t
(
) n
t
=
)
(
N
(N > 1000 Samples)
Figure 5. Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
t
sk(o)
Figure 6. Output Skew
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
t
c(n)
Yx, FBOUT
Yx, FBOUT
1
f
o
1
t
= t
cn
−
jit(per)
f
= Average input frequency measured at CLK/CLK
O
f
o
Figure 7. Period Jitter
Yx, FBOUT
Yx, FBOUT
t
t
(hper_n+1)
(hper_n)
1
f
o
n = any half cycle
1
t
= t
(hper_n) −
jit(hper)
f
= Average input frequency measured at CLK/CLK
O
2xf
o
Figure 8. Half-Period Jitter
V
OH
, V
IH
80%
80%
20%
20%
20%
Clock Inputs
and Outputs
V , V
OL IL
t
t
f
r
V
* V
V
* V
80%
t
20%
80%
+
t
+
t
slr(IńO)
slf(IńO)
t
r(IńO)
f(IńO)
Figure 9. Input and Output Slew Rates
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
CDCV857BDGG
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
DGG
48
48
48
48
56
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNPB
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2A-220C-4 WKS
CDCV857B
CDCV857B
CDCV857B
CDCV857B
CDCV857B
CDCV857BDGGG4
CDCV857BDGGR
CDCV857BDGGRG4
CDCV857BGQLR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGG
DGG
DGG
GQL
40
Green (RoHS
& no Sb/Br)
0 to 70
2000
2000
1000
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
BGA
TBD
0 to 70
MICROSTAR
JUNIOR
CDCV857BIDGG
CDCV857BIDGGG4
CDCV857BIDGGR
CDCV857BIDGGRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
DGG
48
48
48
48
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
CDCV857B-I
CDCV857B-I
CDCV857B-I
CDCV857B-I
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCV857BIDGGR
TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
CDCV857BIDGGR
2000
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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相关型号：
CDCV857BIGG
857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, TSSOP-48
TI
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