CSD17312Q5_11 [TI]
30V N-Channel NexFET⢠Power MOSFET; 30V N通道NexFETâ ?? ¢功率MOSFET
| 型号： | CSD17312Q5_11 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 30V N-Channel NexFET⢠Power MOSFET |
| 文件： | 总11页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD17312Q5
www.ti.com
SLPS256A –MARCH 2010–REVISED OCTOBER 2010
30V N-Channel NexFET™ Power MOSFET
Check for Samples: CSD17312Q5
PRODUCT SUMMARY
1
FEATURES
VDS
Qg
Drain to Source Voltage
Gate Charge Total (4.5V)
Gate Charge Gate to Drain
30
28
6
V
2
•
•
•
•
•
•
•
•
Optimized for 5V Gate Drive
Ultra Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
nC
nC
mΩ
mΩ
mΩ
V
Qgd
VGS = 3V
1.8
1.4
1.2
RDS(on) Drain to Source On Resistance
VGS = 4.5V
VGS = 8V
1.1
Pb Free Terminal Plating
RoHS Compliant
VGS(th)
Threshold Voltage
Halogen Free
ORDERING INFORMATION
SON 5-mm × 6-mm Plastic Package
Device
CSD17312Q5
Package
Media
Qty
Ship
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Tape and
Reel
2500
APPLICATIONS
•
Notebook Point-of-Load
•
Point-of-Load Synchronous Buck in
Networking, Telecom and Computing Systems
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
V
VDS
VGS
Drain to Source Voltage
30
DESCRIPTION
Gate to Source Voltage
+10 / –8
100
V
Continuous Drain Current, TC = 25°C
Continuous Drain Current(1)
Pulsed Drain Current, TA = 25°C(2)
Power Dissipation(1)
A
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications
and optimized for 5V gate drive applications.
ID
38
A
IDM
PD
TJ,
200
A
3.2
W
Top View
Operating Junction and Storage
–55 to 150
845
°C
TSTG Temperature Range
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
Avalanche Energy, Single Pulse
ID = 130A, L = 0.1mH, RG = 25Ω
EAS
mJ
(1) Typical RqJA
= 39°C/W when mounted on a
1-inch2
(6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch
(1.52-mm) thick FR4 PCB.
(2) Pulse duration ≤300ms, duty cycle ≤2% TextAddedForSpacing
D
Text_added_for_spacing_Text_added_for_spacing
D
P0094-01
RDS(on) vs VGS
GATE CHARGE
4
3.5
3
8
ID = 35A
ID = 35A
VDS = 15V
7
6
5
4
3
2
1
0
TC = 125°C
2.5
2
1.5
1
TC = 25°C
0.5
0
0
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
VGS - Gate-to-Source Voltage - V
Qg - Gate Charge - nC
G006
G003
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CSD17312Q5
SLPS256A –MARCH 2010–REVISED OCTOBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Static Characteristics
BVDSS
IDSS
Drain to Source Voltage
VGS = 0V, ID = 250mA
30
V
mA
nA
V
Drain to Source Leakage Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
VGS = 0V, VDS = 24V
VDS = 0V, VGS = +10/–8V
VDS = VGS, ID = 250mA
VGS = 3V, ID = 35A
1
100
1.5
2.4
1.7
1.5
IGSS
VGS(th)
0.9
1.1
1.8
1.4
1.2
200
mΩ
mΩ
mΩ
S
RDS(on)
Drain to Source On Resistance
Transconductance
VGS = 4.5V, ID = 35A
VGS = 8V, ID = 35A
gfs
VDS = 15V, ID = 35A
Dynamic Characteristics
Ciss
Coss
Crss
RG
Input Capacitance
4030 5240
2220 2890
pF
pF
pF
Ω
VGS = 0V, VDS = 15V,
f = 1MHz
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
93
1.1
28
6
120
2.2
36
Qg
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 15V,
IDS = 35A
8.4
4.4
57
9.5
27
35
23
VDS = 14.8V, VGS = 0V
Turn On Delay Time
Rise Time
VDS = 15V, VGS = 4.5V,
IDS = 35A, RG = 2Ω
td(off)
tf
Turn Off Delay Time
Fall Time
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
ISD = 35A, VGS = 0V
0.8
88
43
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDD = 14.8V, IF = 35A,
di/dt = 300A/ms
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Thermal Resistance Junction to Case(1)
Thermal Resistance Junction to Ambient(1)(2)
qJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
MIN TYP
MAX UNIT
°C/W
49 °C/W
RqJC
RqJA
1
(1)
R
2
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CSD17312Q5
CSD17312Q5
www.ti.com
SLPS256A –MARCH 2010–REVISED OCTOBER 2010
GATE
Source
GATE
Source
Max RqJA = 49°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
Max RqJA = 119°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
Text Added For Spacing
Text Added For Spacing
Text Added For Spacing
Text Added For Spacing
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
10
1
0.5
0.3
Duty Cycle = t1/t2
0.1
0.1
0.01
0.05
P
0.02
0.01
t1
t2
Typical RqJA = 95°C/W (min Cu)
TJ = P ´ ZqJA ´ RqJA
Single Pulse
0.001
0.001
0.01
0.1
1
10
100
1k
tp - Pulse Duration - s
G012
Figure 1. Transient Thermal Impedance
Copyright © 2010, Texas Instruments Incorporated
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3
Product Folder Link(s): CSD17312Q5
CSD17312Q5
SLPS256A –MARCH 2010–REVISED OCTOBER 2010
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VDS = 5V
VGS = 2.5V
VGS = 3V
TC = 125°C
VGS = 3.5V
TC = 25°C
TC = -55°C
VGS = 4.5V
VGS = 8V
0
0.1
0.2
0.3
0.4
0.5
0
0.5
1
1.5
2
2.5
3
VDS - Drain-to-Source Voltage - V
VGS - Gate-to-Source Voltage - V
G001
G002
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
8
7
6
5
4
3
2
1
12
10
8
ID = 35A
VDS = 15V
f = 1MHz
VGS = 0V
Coss = Cds + Cgd
6
Ciss = Cgd + Cgsgs
4
Crss = CGgd
2
0
0
0
10
20
30
40
50
0
5
10
15
20
25
30
Qg - Gate Charge - nC
VDS - Drain-to-Source Voltage - V
G003
G004
Figure 4. Gate Charge
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
4
3.5
3
1.6
1.4
1.2
1
ID = 35A
ID = 250µA
TC = 125°C
2.5
2
0.8
0.6
0.4
0.2
0
1.5
1
TC = 25°C
0.5
0
-75
-25
25
75
125
175
0
1
2
3
4
5
6
7
8
9
10
TC - Case Temperature - °C
VGS - Gate-to-Source Voltage - V
G005
G006
Figure 6. Threshold Voltage vs. Temperature
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
4
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CSD17312Q5
CSD17312Q5
www.ti.com
SLPS256A –MARCH 2010–REVISED OCTOBER 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
10
1.8
1.6
1.4
1.2
1
ID = 35A
VGS = 8V
1
TC = 125°C
0.1
0.8
0.6
0.4
0.2
TC = 25°C
0.01
0.001
0.0001
-75
-25
25
75
125
175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature - °C
VSD - Source-to-Drain Voltage - V
G007
G008
Figure 8. Normalized On-State Resistance vs. Temperature
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1k
1k
100
10
100
1ms
TC = 25°C
10
10ms
10101m10s
1
Area Limited
by RDS(on)
1s
TC = 125°C
0.1
Single Pulse
Typical RθJA = 95°C/W (min Cu)
DC
0.01
1
0.01
0.1
1
10
100
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage - V
t(AV) - Time in Avalanche - ms
G009
G010
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
120
100
80
60
40
20
0
-50
-25
0
25
50
75
100 125 150 175
TC - Case Temperature - °C
G011
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s): CSD17312Q5
CSD17312Q5
SLPS256A –MARCH 2010–REVISED OCTOBER 2010
www.ti.com
MECHANICAL DATA
Q5 Package Dimensions
K
L
L
E1
c1
E2
q
Top View
Side View
Bottom View
q
E1
Front View
M0140-01
MILLIMETERS
MAX
INCHES
DIM
MIN
MIN
MAX
0.039
0.018
0.010
0.010
0.201
0.178
0.201
0.240
0.162
A
b
0.950
0.360
0.150
0.150
4.900
4.320
4.900
5.900
3.920
1.050
0.037
0.014
0.006
0.006
0.193
0.170
0.193
0.232
0.154
0.460
c
0.250
c1
D1
D2
E
0.250
5.100
4.520
5.100
E1
E2
e
6.100
4.12
1.27 TYP
0.050
K
0.760
0.510
0.00
0.030
0.020
L
0.710
0.028
q
6
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CSD17312Q5
CSD17312Q5
www.ti.com
SLPS256A –MARCH 2010–REVISED OCTOBER 2010
Recommended PCB Pattern
F1
MILLIMETERS
MIN
INCHES
F7
F6
DIM
MAX
6.305
4.560
4.560
0.700
0.670
0.680
0.800
0.700
0.670
5.000
4.560
MIN
MAX
0.248
0.180
0.180
0.028
0.026
0.027
0.031
0.028
0.026
0.197
0.180
F1
F2
6.205
4.460
4.460
0.650
0.620
0.630
0.700
0.650
0.620
4.900
4.460
0.244
0.176
0.176
0.026
0.024
0.025
0.028
0.026
0.024
0.193
0.176
F3
F4
F5
F6
F7
F8
F9
F10
F10
F11
M0139-01
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Text added for spacing
Text added for spacing
Q5 Tape and Reel Information
K0
4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
A0
8.00 0.10
R 0.30 MAX
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 6.50 0.10
B0 = 5.30 0.10
K0 = 1.40 0.10
M0138-01
Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
Copyright © 2010, Texas Instruments Incorporated
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SLPS256A –MARCH 2010–REVISED OCTOBER 2010
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REVISION HISTORY
Changes from Original (March 2010) to Revision A
Page
•
Deleted the Package Marking Information section ............................................................................................................... 7
8
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PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD17312Q5
SON
DQH
8
2500
330.0
12.8
6.5
5.3
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DQH
SPQ
Length (mm) Width (mm) Height (mm)
335.0 335.0 32.0
CSD17312Q5
8
2500
Pack Materials-Page 2
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相关型号：
CSD17381F4T
30V, N ch NexFET MOSFET™, single LGA 1.0 x 0.6mm, 117mOhm 3-PICOSTAR -55 to 150
TI
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