CSD17318Q2 [TI]
采用 2mm x 2mm SON 封装的单路、16.9mΩ、30V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD17318Q2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2mm x 2mm SON 封装的单路、16.9mΩ、30V、N 沟道 NexFET™ 功率 MOSFET |
| 文件： | 总15页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD17318Q2
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
CSD17318Q2 30V N 通道 NexFET™ 功率 MOSFET
1 特性
产品概要
1
•
•
•
•
•
•
•
•
针对 5V 栅极驱动器进行优化
TA = 25°C
典型值
30
单位
V
低电容和电荷
VDS
Qg
漏源电压
低 RDS(ON)
栅极电荷总量 (4.5V)
栅极电荷（栅极到漏极）
6.0
nC
nC
低热阻
Qgd
1.3
VGS = 2.5V
20
无铅
RDS(on) 漏源导通电阻
VGS(th) 阈值电压
VGS = 4.5V
VGS = 8V
13.9
12.6
mΩ
符合 RoHS 环保标准
无卤素
0.9
V
小外形尺寸无引线 (SON) 2mm x 2mm 塑料封装
器件信息(1)
2 应用
器件型号
数量
包装介质
封装
运输
•
•
•
•
存储、平板电脑和手持设备
CSD17318Q2
3000
250
SON
2.00mm × 2.00mm
塑料封装
卷带封
装
7 英寸卷带
优化负载开关 应用
直流/直流转换器
CSD17318Q2T
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
电池和负载管理 应用
绝对最大额定值
3 说明
TA = 25°C
值
30
单位
V
这款采用 2mm × 2mm SON 封装的 30V、12.6mΩ
NexFET™功率 MOSFET 的设计被用来降低功率转换
中的损耗， 并优化 5V 栅极驱动器。 2mm x 2mm
SON 针对封装尺寸提供了出色的散热性能。
VDS
VGS
漏源电压
栅源电压
±10
21.5
V
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），TC = 25°C 时
测得
ID
25
A
持续漏极电流(1)
10
68
2.5
16
顶视图
IDM
PD
脉冲漏极电流，TA = 25°C 时测得(2)
功率耗散(1)
A
D
D
G
1
2
3
6
5
4
D
D
S
W
D
功率耗散，TC = 25°C
TJ， 工作结温，
TSTG 储存温度
-55 至 150
°C
雪崩能量，单脉冲，
ID = 12.4A，L = 0.1mH，RG = 25Ω
EAS
7.7
mJ
S
(1) RθJA = 55°C/W，这是在 0.06 英寸厚 FR4 PCB 上的 1 平方英
寸、2oz 铜焊盘上测得的典型值。
P0108-01
(2) 最大 RθJC = 7°C/W，脉冲持续时间 ≤ 100μs，占空比 ≤ 1%。
导通电阻与栅极至源极电压
栅极电荷
40
35
30
25
20
15
10
5
8
TC = 25°C, I D = 8 A
TC = 125°C, I D = 8 A
ID = 8 A
VDS = 15 V
7
6
5
4
3
2
1
0
0
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
12
VGS - Gate-To-Source Voltage (V)
Qg - Gate Charge (nC)
D007
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS667
CSD17318Q2
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
www.ti.com.cn
目录
1
2
3
4
5
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Characteristics ............................................ 3
5.3 Typical MOSFET Characteristics.............................. 4
6
7
器件和文档支持........................................................ 7
6.1 接收文档更新通知 ..................................................... 7
6.2 社区资源.................................................................... 7
6.3 商标........................................................................... 7
6.4 静电放电警告............................................................. 7
6.5 Glossary.................................................................... 7
机械数据................................................................... 8
7.1 Q2 封装尺寸.............................................................. 8
7.2 Q2 卷带信息............................................................ 10
4 修订历史记录
Changes from Original (February 2017) to Revision A
Page
•
更新后的 机械数据 图纸.......................................................................................................................................................... 8
2
版权 © 2017, Texas Instruments Incorporated
CSD17318Q2
www.ti.com.cn
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
30
V
Drain-to-source leakage
Gate-to-source leakage
VGS = 0 V, VDS = 24 V
VDS = 0 V, VGS = 10 V
VDS = VGS, ID = 250 μA
VGS = 2.5 V, ID = 8 A
VGS = 4.5 V, ID = 8 A
VGS = 8 V, ID = 8 A
1
100
1.2
30
μA
nA
V
IGSS
VGS(th)
Gate-to-source threshold voltage
0.6
0.9
20
RDS(on)
Drain-to-source on-resistance
13.9 16.9
12.6 15.1
42
mΩ
gfs
Transconductance
VDS = 3 V, ID = 8 A
S
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
676 879
pF
pF
pF
Ω
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
71
39
1.0
6.0
1.3
1.5
0.7
2.7
5
92
51
2.0
Qg
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 15 V,
ID = 8 A
VDS = 15 V, VGS = 0 V
Turnon delay time
Rise time
16
13
4
VDS = 15 V, VGS = 4.5 V,
ID = 8 A, RG = 2 Ω
td(off)
tf
Turnoff delay time
Fall time
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
ISD = 8 A, VGS = 0 V
0.8
2.9
12
1.0
V
nC
ns
VDD= 15 V, IF = 8 A,
di/dt = 300 A/μs
5.2 Thermal Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
MIN
TYP MAX UNIT
7.9 °C/W
RθJC
RθJA
Thermal resistance junction-to-case(1)
Thermal resistance junction-to-ambient(1)(2)
65 °C/W
(1)
R
θJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-inch (3.81-cm × 3.81-
cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
Copyright © 2017, Texas Instruments Incorporated
3
CSD17318Q2
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
www.ti.com.cn
Max RθJA = 250°C/W
Max RθJA = 65°C/W
when mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
when mounted on 1 in2
(6.45 cm2) of 2-oz
(0.071-mm) thick Cu.
G1 D1 S1
G1 S1 D1
M0179-01
M0180-01
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise noted)
Figure 1. Transient Thermal Impedance
80
70
60
50
40
30
20
25
TC = 125°C
TC = 25°C
TC = -55°C
20
15
10
5
VGS = 2.5 V
10
0
VGS = 4.5 V
VGS = 8 V
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
D002
D003
VDS = 5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
4
Copyright © 2017, Texas Instruments Incorporated
CSD17318Q2
www.ti.com.cn
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise noted)
1000
100
10
8
7
6
5
4
3
2
1
0
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0
5
10
15
20
25
30
0
2
4
6
8
10
12
VDS - Drain-to-Source Voltage (V)
Qg - Gate Charge (nC)
D005
D004
ID = 8 A
VDS = 15 V
Figure 5. Capacitance
Figure 4. Gate Charge
40
35
30
25
20
15
10
5
1.3
TC = 25°C, I D = 8 A
TC = 125°C, I D = 8 A
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0
-75 -50 -25
0
25
50
75 100 125 150 175
0
1
2
3
4
5
6
7
8
9
10
TC - Case Temperature (èC)
VGS - Gate-To-Source Voltage (V)
D006
D007
ID = 250 µA
ID = 8 A
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
100
1.8
1.6
1.4
1.2
1
TC = 25èC
TC = 125èC
VGS = 2.5 V
VGS = 4.5 V
VGS = 8 V
10
1
0.1
0.01
0.8
0.6
0.4
0.001
0.0001
-75 -50 -25
0
25
50
75 100 125 150 175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (°C)
VSD - Source-to-Drain Voltage (V)
D008
D009
ID = 8 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
Copyright © 2017, Texas Instruments Incorporated
5
CSD17318Q2
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
www.ti.com.cn
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise noted)
1000
100
10
1
TC = 25è C
TC = 125è C
100
10
1
DC
10 ms
1 ms
100 µs
0.1
0.1
1
10
100
0.01
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (ms)
D010
D011
Single pulse, max RθJC = 7.9°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
16
14
12
10
8
6
4
2
0
-50
-25
0
25
50
75
100 125 150 175
TC - Case Temperature (èC)
D012
Figure 12. Maximum Drain Current vs Temperature
6
版权 © 2017, Texas Instruments Incorporated
CSD17318Q2
www.ti.com.cn
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
6 器件和文档支持
6.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
6.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
6.3 商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2017, Texas Instruments Incorporated
7
CSD17318Q2
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
www.ti.com.cn
7 机械数据
7.1 Q2 封装尺寸
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8 MAX
C
SEATING PLANE
0.05
0.00
0.75±0.1
PKG
(0.2)
(0.2) TYP
(0.47)
0.3±0.05
3
4
7
4X
(0.5)
0.65
PKG
2X
1.3
8
0.95±0.1
6
1
(0.2)
0.35
0.25
6X
PIN 1 ID
(45 X0.3)
1±0.1
0.1
C A
C
B
0.3
0.2
0.05
6X
4222322/A 08/2015
1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和容限值遵循 ASME Y14.5M。
2. 本图纸如有变更，恕不通知。
3. 封装散热盘必须在印刷电路板上焊接，包装散热和机械性能。
8
版权 © 2017, Texas Instruments Incorporated
CSD17318Q2
www.ti.com.cn
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
Q2 封装尺寸 (接下页)
7.1.1 建议 PCB 布局
(1)
PKG
6X (0.45)
1
6
8
6X (0.3)
PKG
(0.95)
(0.325)
4X (0.65)
(0.65)
4
7
3
(0.3)
(R0.05) TYP
(0.095)
(0.75)
(1.95)
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
1. 此封装设计用于焊接到电路板的散热焊盘上。更多信息，请参见《QFN/SON
号：SLUA271）。
PCB
连接》（文献编
版权 © 2017, Texas Instruments Incorporated
9
CSD17318Q2
ZHCSGE6A –FEBRUARY 2017–REVISED JULY 2017
www.ti.com.cn
Q2 封装尺寸 (接下页)
7.1.2 推荐的模版布局
(0.9)
PKG
METAL
ALL AROUND, TYP
6X (0.45)
1
6X (0.3)
6
8
(0.86)
(0.325)
PKG
4X (0.65)
(0.65)
7
(0.29)
3
4
(R0.05) TYP
(0.095)
(0.7)
(1.95)
1. 具有漏斗形壁和圆角的激光切割窗孔将提供更佳的焊锡膏脱离。IPC-7525 可能提供其他替代性设计建议。
7.2 Q2 卷带信息
4.00 0.10
2.00 0.0ꢀ
Ø 1.ꢀ0 0.10
10° Max
4.00 0.10
Ø 1.00 0.2ꢀ
1.00 0.0ꢀ
0.2ꢀ4 0.02
10° Max
2.30 0.0ꢀ
M0168-01
Notes: 1. 测自链齿孔中心线到孔眼中心线。
2. 10 个链齿孔的累积容差为 ±0.20。
3. 提供了其他材料。
4. 卷带的 SR 典型值最大为 109 OHM/SQ。
5. 所有尺寸单位均为 mm，除非另有说明。
10
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD17318Q2
CSD17318Q2T
ACTIVE
ACTIVE
WSON
WSON
DQK
DQK
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
1718
1718
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD17318Q2
CSD17318Q2T
WSON
WSON
DQK
DQK
6
6
3000
250
180.0
180.0
9.5
9.5
2.3
2.3
2.3
2.3
1.0
1.0
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD17318Q2
CSD17318Q2T
WSON
WSON
DQK
DQK
6
6
3000
250
189.0
189.0
185.0
185.0
36.0
36.0
Pack Materials-Page 2
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