CSD18541F5 [TI]
采用 1.5mm x 0.8mm LGA 封装、具有栅极 ESD 保护的单路、65mΩ、60V、N 沟道 NexFET™ 功率 MOSFET;型号: | CSD18541F5 |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 1.5mm x 0.8mm LGA 封装、具有栅极 ESD 保护的单路、65mΩ、60V、N 沟道 NexFET™ 功率 MOSFET 栅 栅极 |
文件: | 总14页 (文件大小:1947K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CSD18541F5
ZHCSF08B –MAY 2016 –REVISED FEBRUARY 2022
CSD18541F5 60V N 沟道FemtoFET™ MOSFET
产品概要
1 特性
TA = 25°C
VDS
典型值
单位
60
V
漏源电压
• 低导通电阻
• 超低Qg 和Qgd
• 超小尺寸
Qg
11
nC
nC
栅极电荷总量(10V)
Qgd
1.6
栅极电荷(栅极到漏极)
漏源导通电阻
VGS = 4.5V
VGS = 10V
1.75
57
54
– 1.53mm × 0.77mm
• 薄型封装
RDS(on)
VGS(th)
mΩ
V
阈值电压
– 厚度为0.36mm
• 集成型ESD 保护二极管
• 无铅且无卤素
• 符合RoHS
器件信息
介质
器件
数量
封装
配送
CSD18541F5
3000
Femto
1.53mm × 0.77mm
卷带
包装
7 英寸卷带
2 应用
CSD18541F5T
250
无引线SMD
• 针对工业负载开关应用进行了优化
• 针对通用开关应用进行了优化
1. 如需了解所有可用封装,请参阅数据表末尾的可订
购产品附录。
3 说明
绝对最大额定值
该 54mΩ、60V N 沟道 FemtoFET™ MOSFET 技术经
过设计和优化,能够最大限度地减小在空间受限的工业
负载开关应用中占用的空间。这项技术能够在替代标准
小信号MOSFET 的同时大幅减小封装尺寸。
TA = 25°C
值
60
单位
V
VDS
VGS
ID
漏源电压
±20
2.2
V
栅源电压
A
持续漏极电流
脉冲漏极电流(1)(2)
功率耗散
IDM
PD
21
A
500
mW
0.36 mm
TJ、
Tstg
工作结温,
贮存温度
–55 至
150
°C
雪崩能量,单脉冲
ID = 12.8A,L = 0.1mH,RG = 25Ω
EAS
8.2
mJ
0.77 mm
1.53 mm
G
S
典型器件尺寸
D
顶视图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLPS571
CSD18541F5
ZHCSF08B –MAY 2016 –REVISED FEBRUARY 2022
www.ti.com.cn
Table of Contents
6 Device and Documentation Support..............................7
6.1 Receiving Notification of Documentation Updates......7
6.2 Community Resources................................................7
6.3 Trademarks.................................................................7
7 Mechanical, Packaging, and Orderable Information....8
7.1 Mechanical Dimensions..............................................8
7.2 Recommended Minimum PCB Layout........................9
7.3 Recommended Stencil Pattern................................... 9
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................3
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2016) to Revision B (February 2022)
Page
• 将超薄型封装要点中的厚度从0.35mm 更改为0.36mm..................................................................................... 1
• 将超薄型封装图片中的厚度从0.35mm 更新为0.36mm..................................................................................... 1
• Changed ultra-low profile image height from 0.35 mm to 0.36 mm....................................................................8
• Added FemtoFET Surface Mount Guide note.................................................................................................... 9
Changes from Revision * (May 2016) to Revision A (August 2017)
Page
• Added the 节6.1 section to 节6 ........................................................................................................................7
• Added 表7-1 to the 节7.1 section......................................................................................................................8
• Updated the 节7.2 .............................................................................................................................................9
• Updated the 节7.3 .............................................................................................................................................9
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
60
V
µA
µA
V
VGS = 0 V, IDS = 250 μA
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 48 V
VDS = 0 V, VGS = 20 V
VDS = VGS, IDS = 250 μA
VGS = 4.5 V, IDS = 1 A
VGS = 10 V, IDS = 1 A
VDS = 6 V, IDS = 1 A
1
10
2.2
75
65
IGSS
VGS(th)
1.4
1.75
57
RDS(on)
gfs
Drain-to-source on-resistance
Transconductance
mΩ
54
7.7
S
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
598
47
777
61
pF
pF
pF
VGS = 0 V, VDS = 30 V,
ƒ= 1 MHz
8.1
10.5
1600
14
1200
11
Ω
Qg
nC
nC
nC
nC
nC
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
1.6
VDS = 30 V, IDS = 1 A
VDS = 30 V, VGS = 0 V
1.5
0.8
3.2
Turnon delay time
Rise time
572
540
1076
496
ns
VDS = 30 V, VGS = 4.5 V,
IDS = 1 A, RG = 0 Ω
td(off)
tf
Turnoff delay time
Fall time
ns
ns
DIODE CHARACTERISTICS
VSD Diode forward voltage
ISD = 1 A, VGS = 0 V
0.8
1
V
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance(1)
Junction-to-ambient thermal resistance(2)
MIN
TYP
85
MAX
UNIT
RθJA
°C/W
245
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
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图5-1. Transient Thermal Impedance
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
VGS = 4.5 V
VGS = 6.0 V
VGS = 10 V
TC = 125°C
TC = 25°C
TC = -55°C
0
0.1
0.2
VDS - Drain-to-Source Voltage (V)
0.3
0.4
0.5
0.6
0
0.5
1
1.5
VGS - Gate-to-Source Voltage (V)
2
2.5
3
3.5
4
D002
D003
VDS = 5 V
图5-2. Saturation Characteristics
图5-3. Transfer Characteristics
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10
9
8
7
6
5
4
3
2
1
1000
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
0
0
0
6
12
18
24
30
36
42
VDS - Drain-to-Source Voltage (V)
48
54
60
2
4
6
8
Qg - Gate Charge (nC)
10
12
D005
D004
图5-5. Capacitance
ID = 1 A VDS = 30 V
图5-4. Gate Charge
2.2
2.05
1.9
120
110
100
90
TC = 25°C, ID = 1 A
TC = 125°C, ID = 1 A
1.75
1.6
80
1.45
1.3
70
60
1.15
1
50
40
-75 -50 -25
0
25
50
TC - Case Temperature (°C)
75 100 125 150 175
0
2
4
6
8
10
12
14
VGS - Gate-to-Source Voltage (V)
16
18
20
D006
D007
ID = 250 µA
图5-7. On-State Resistance vs Gate-to-Source
Voltage
图5-6. Threshold Voltage vs Temperature
100
1.8
TC = 25èC
TC = 125èC
VGS = 4.5 V
VGS = 10 V
1.6
10
1
0.1
1.4
1.2
1
0.01
0.001
0.0001
0.8
0.6
0
0.2
0.4
0.6
VSD - Source-To-Drain Voltage (V)
0.8
1
-75 -50 -25
0
25
50
75 100 125 150 175
D009
TC - Case Temperature (èC)
D008
图5-9. Typical Diode Forward Voltage
ID = 1 A
图5-8. Normalized On-State Resistance vs
Temperature
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100
10
1
100
10
1
TC = 25è C
TC = 125è C
0.1
100 ms
10 ms
1 ms
100 µs
10 µs
0.01
0.1
1
10
VDS - Drain-To-Source Voltage (V)
100
0.001
0.01
TAV - Time in Avalanche (ms)
0.1
D010
D011
Single pulse, typ RθJA = 245°C/W
图5-11. Single Pulse Unclamped Inductive
Switching
图5-10. Maximum Safe Operating Area (SOA)
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
TA - Ambient Temperature (°C)
75
100 125 150 175
D012
图5-12. Maximum Drain Current vs Temperature
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6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
6.3 Trademarks
FemtoFET™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
0.77
0.69
B
A
PIN 1 INDEX AREA
1.53
1.45
C
0.36 MAX
SEATING PLANE
3
0.5
(R0.05) TYP
1
1
0.16
0.14
3X
0.015
TOP B
A
0.40
0.38
3X
4222132/A 06/2015
A. All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).
B. This drawing is subject to change without notice.
C. This package is a PB-free solder land design.
表7-1. Pin Configuration
POSITION
DESIGNATION
Pin 1
Gate
Pin 2
Source
Pin 3
Drain
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7.2 Recommended Minimum PCB Layout
3X (0.39)
(0.05) MIN
ALL AROUND
1
(R0.05) TYP
SYMM
3X (0.15)
SOLDER MASK
OPENING
TYP
(0.5)
3
METAL UNDER
SOLDER MASK
TYP
SYMM
A. All dimensions are in millimeters.
B. For more information, see FemtoFET Surface Mount Guide (SLRA003D).
7.3 Recommended Stencil Pattern
3X (0.39)
1
3X (0.2)
(R0.05) TYP
2X (0.15)
SYMM
(0.15)
(0.525)
3
SOLDER MASK EDGE
TYP
SYMM
A. All dimensions are in millimeters.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD18541F5
ACTIVE
ACTIVE
PICOSTAR
PICOSTAR
YJK
YJK
3
3
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
1T
1T
CSD18541F5T
NIAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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11-Jan-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD18541F5
PICOST
AR
YJK
YJK
3
3
3000
250
180.0
8.4
0.92
1.68
0.42
4.0
8.0
Q1
CSD18541F5T
PICOST
AR
180.0
8.4
0.92
1.68
0.42
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD18541F5
PICOSTAR
PICOSTAR
YJK
YJK
3
3
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
CSD18541F5T
Pack Materials-Page 2
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CSD18541F5T
采用 1.5mm x 0.8mm LGA 封装、具有栅极 ESD 保护的单路、65mΩ、60V、N 沟道 NexFET™ 功率 MOSFET | YJK | 3 | -55 to 150
TI
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