CSD23202W10T [TI]
采用 1mm x 1mm WLP 封装、具有栅极 ESD 保护的单路、53mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YZB | 4 | -55 to 150;
| 型号： | CSD23202W10T |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 1mm x 1mm WLP 封装、具有栅极 ESD 保护的单路、53mΩ、-12V、P 沟道 NexFET™ 功率 MOSFET | YZB | 4 | -55 to 150 栅 开关 晶体管 栅极 |
| 文件： | 总13页 (文件大小：805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD23202W10
ZHCSCW2 –AUGUST 2014
CSD23202W10 12V P 通道 NexFET™ 功率金属氧化物半导体场效应晶体
管 (MOSFET)
1 特性
产品概要
1
•
•
•
•
•
•
•
超低 Qg 和 Qgd
TA = 25°C
VDS
典型值
-12
单位
V
小尺寸封装 1mm x 1mm
薄型，0.62mm 高度
无铅
漏源电压
Qg
栅极电荷总量 (-4.5V)
栅漏栅极电荷
2.9
nC
nC
mΩ
mΩ
mΩ
mΩ
V
Qgd
0.28
VGS = –1.5V
82
67
54
44
栅极静电放电 (ESD) 保护 - 3kV
符合 RoHS 环保标准
无卤素
VGS = –1.8V
VGS = -2.5V
VGS = -4.5V
RDS(on) 漏源导通电阻
VGS(th)
阀值电压
–0.60
2 应用范围
订购信息(1)
•
•
•
电池管理
负载开关
电池保护
器件
数量
3000 7 英寸卷带
250 7 英寸卷带
介质
封装
出货
卷带封装
CSD23202W10
CSD23202W10T
1 x 1mm 晶圆级封
装
3 说明
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
这款 12V，44mΩ 器件设计用于在超薄且具有出色散
热特性的 1mm × 1mm 小外形
封装内提供最低的导通电阻和栅极电荷。
最大绝对额定值
TA = 25°C
值
-12
-6
单位
V
VDS
VGS
ID
漏源电压
栅源电压
V
。
持续漏极电流(1)
脉冲漏极电流(2)
持续栅极钳位电流
脉冲栅极钳位电流
功率耗散(1)
–2.2
–25
-0.5
-7
A
顶视图
IDM
A
A
IG
A
D
D
PD
1
W
TJ，
Tstg
运行结温和
储存温度范围
-55 至 150
°C
(1) 器件在 105ºC 温度下运行
G
S
(2) RθJA 典型值 = 195°C/W，脉宽 ≤ 100μs，占空比 ≤ 1%
P0097-01
。
。
.
.
RDS(on) 与 VGS 间的关系
栅极电荷
150
135
120
105
90
4.5
4
TC = 25°C,I D = − 0.5 A
TC = 125°C,I D = −0.5 A
3.5
3
2.5
2
75
60
1.5
1
45
30
ID = −0.5A
VDS = −6V
0.5
0
15
0
0
1
2
3
4
5
6
0
0.5
1
1.5
2
2.5
3
Qg - Gate Charge (nC)
−VGS - Gate-to- Source Voltage (V)
G001
G001
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLPS506
CSD23202W10
ZHCSCW2 –AUGUST 2014
www.ti.com.cn
目录
1
2
3
4
5
特性.......................................................................... 1
6
7
器件和文档支持........................................................ 7
6.1 商标........................................................................... 7
6.2 静电放电警告............................................................. 7
6.3 术语表 ....................................................................... 7
机械封装和可订购信息............................................. 8
7.1 CSD23202W10 封装尺寸.......................................... 8
7.2 焊盘布局建议............................................................. 9
7.3 卷带封装信息............................................................. 9
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information.................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
4 修订历史记录
日期
修订版本
注释
2014 年 8 月
*
最初发布。
2
版权 © 2014, Texas Instruments Incorporated
CSD23202W10
www.ti.com.cn
ZHCSCW2 –AUGUST 2014
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
BVGSS
IDSS
Drain-to-Source Voltage
VGS = 0 V, ID = –250 μA
–12
–6
V
Gate-to-Source Voltage;
VDS = 0 V, IG = –250 μA
VGS = 0 V, VDS = –9.6 V
VDS = 0 V, VGS = –6 V
–7.2
–1
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
μA
nA
V
IGSS
–100
–0.9
123
92
VGS(th)
VDS = VGS, ID = –250 μA
VGS = –1.5 V, ID = –0.5 A
VGS = –1.8 V, ID = –0.5 A
VGS = –2.5 V, ID = –0.5 A
VGS = –4.5 V, ID = –0.5 A
VDS = –1.2 V, ID = –0.5 A
–0.4
–0.6
82
mΩ
mΩ
mΩ
mΩ
S
67
RDS(on)
Drain-to-Source On-Resistance
Transconductance
54
66
44
53
gƒs
5.6
DYNAMIC CHARACTERISTICS
CISS
COSS
CRSS
Qg
Input Capacitance
394
238
29
512
310
37
pF
pF
pF
nC
nC
nC
nC
nC
ns
Output Capacitance
Reverse Transfer Capacitance
Gate Charge Total (–4.5 V)
Gate Charge Gate-to-Drain
Gate Charge Gate-to-Source
Gate Charge at Vth
Output Charge
VGS = 0 V, VDS = –6.0 V, ƒ = 1 MHz
2.9
0.28
0.55
0.29
2.0
9
3.8
Qgd
Qgs
VDS = –6 V, ID = –0.5 A
VDS = –6 V, VGS = 0 V
Qg(th)
QOSS
td(on)
tr
Turn On Delay Time
Rise Time
4
ns
VDS = –6 V, VGS = –4.5 V,
ID = –0.5 A RG = 0 Ω
td(off)
tƒ
Turn Off Delay Time
Fall Time
58
ns
21
ns
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode Forward Voltage
Reverse Recovery Charge
Reverse Recovery Time
IS = –0.5 A, VGS = 0 V
–0.66
3.7
–1
V
nC
ns
VDS= –6 V, IF = –0.5 A, di/dt = 100 A/μs
12
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
Junction-to-Ambient Thermal Resistance(1)
Junction-to-Ambient Thermal Resistance(2)
MIN
TYP
195
65
MAX UNIT
RθJA
°C/W
(1) Device mounted on FR4 material with minimum Cu mounting area.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
Copyright © 2014, Texas Instruments Incorporated
3
CSD23202W10
ZHCSCW2 –AUGUST 2014
www.ti.com.cn
P-Chan 1.0x1.0 CSP TTA MAX Rev1
P-Chan 1.0x1.0 CSP TTA MIN Rev1
Typical RθJA
195°C/W when
mounted on minimum
pad area of 2 oz. Cu.
=
Typical RθJA = 65°C/W
when mounted on
1 inch2 of 2 oz. Cu.
M0149-01
M0150-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
Copyright © 2014, Texas Instruments Incorporated
CSD23202W10
www.ti.com.cn
ZHCSCW2 –AUGUST 2014
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
10
10
8
9
8
7
6
5
4
6
4
3
VGS = −4.5 V
VGS = −2.5 V
VGS = −1.8 V
VGS = −1.5 V
TC = 125°C
TC = 25°C
TC = −55°C
2
1
0
2
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
−VDS - Drain-to-Source Voltage (V)
−VGS - Gate-to-Source Voltage (V)
G001
G001
VDS = –5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
4.5
4
500
450
400
350
300
250
200
150
100
50
3.5
3
2.5
2
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1.5
1
0.5
0
0
0
0.5
1
1.5
2
2.5
3
2
4
6
8
10
12
Qg - Gate Charge (nC)
−VDS - Drain-to-Source Voltage (V)
G001
G001
ID = –0.5 A
VDS = –6 V
Figure 4. Gate Charge
Figure 5. Capacitance
1.1
1
150
135
120
105
90
TC = 25°C,I D = − 0.5 A
TC = 125°C,I D = −0.5 A
0.9
0.8
0.7
0.6
0.5
0.4
75
60
45
30
15
0
−75 −50 −25
0
25
50
75 100 125 150 175
1
2
3
4
5
6
TC - Case Temperature (ºC)
−VGS - Gate-to- Source Voltage (V)
G001
G001
ID = –250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Drain-to-Source Resistance vs
Gate-to-Source Voltage
Copyright © 2014, Texas Instruments Incorporated
5
CSD23202W10
ZHCSCW2 –AUGUST 2014
www.ti.com.cn
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
1.4
10
1
VGS = −1.5 V
TC = 25°C
TC = 125°C
VGS = −1.8 V
VGS = −2.5 V
VGS = −4.5 V
1.3
1.2
1.1
1
0.1
0.01
0.001
0.0001
0.9
0.8
0.7
−75 −50 −25
0
25
50
75 100 125 150 175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
−VSD − Source-to-Drain Voltage (V)
G001
G001
ID = –0.5 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
100
2.5
2.0
1.5
1.0
0.5
0.0
10
1
100us
1ms
10ms
100ms
0.1
0.1
1
10
100
−50 −25
0
25
50
75 100 125 150 175 200
TC - Case Temperature (ºC)
−VDS - Drain-to-Source Voltage (V)
G001
G001
Single Pulse, Max RθJA = 195°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Maximum Drain Current vs Temperature
6
版权 © 2014, Texas Instruments Incorporated
CSD23202W10
www.ti.com.cn
ZHCSCW2 –AUGUST 2014
6 器件和文档支持
6.1 商标
NexFET is a trademark of Texas Instruments.
6.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
6.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
版权 © 2014, Texas Instruments Incorporated
7
CSD23202W10
ZHCSCW2 –AUGUST 2014
www.ti.com.cn
7 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
7.1 CSD23202W10 封装尺寸
Pin 1
Mark
Solder Ball
Ø 0.31 0.0ꢀ5
1
2
2
1
A
B
A
B
+0.00
–0.10
1.00
0.62 Max
0.50
Bottom View
Top View
Side View
Seating Plate
Front View
NOTE: 全部尺寸单位为 mm（除非另外注明）。
M0151-01
引脚配置表
位置
B1
名称
源极
栅极
漏极
A1
A2，B2
8
版权 © 2014, Texas Instruments Incorporated
CSD23202W10
www.ti.com.cn
ZHCSCW2 –AUGUST 2014
7.2 焊盘布局建议
Ø 0.25
1
2
A
B
0.50
M0152-01
NOTE: 全部尺寸单位为 mm（除非另外注明）。
7.3 卷带封装信息
4.00 0.10
2.00 0.0ꢀ
Ø 1.ꢀ0 0.10
ꢀ° Max
4.00 0.10
Ø 0.ꢀ0 0.0ꢀ
0.78 0.0ꢀ
0.2ꢀ4 0.02
ꢀ° Max
1.18 0.0ꢀ
M01ꢀ3-01
NOTE: 全部尺寸单位为 mm（除非另外注明）。
版权 © 2014, Texas Instruments Incorporated
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD23202W10
CSD23202W10T
ACTIVE
ACTIVE
DSBGA
DSBGA
YZB
YZB
4
4
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
202
202
SNAGCU
-55 to 150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
D: Max = 0.994 mm, Min =0.934 mm
E: Max = 0.99 mm, Min = 0.93 mm
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