CSD87331Q3D [TI]
Synchronous Buck NexFET⢠Power Block; 同步降压NexFETâ ?? ¢电源模块
| 型号： | CSD87331Q3D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Synchronous Buck NexFET⢠Power Block |
| 文件： | 总21页 (文件大小：872K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD87331Q3D
www.ti.com
SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
Synchronous Buck NexFET™ Power Block
1
FEATURES
DESCRIPTION
The CSD87331Q3D NexFET™ power block is an
optimized design for synchronous buck applications
offering high current, high efficiency, and high
frequency capability in a small 3.3-mm × 3.3-mm
outline. Optimized for 5V gate drive applications, this
product offers a flexible solution capable of offering a
high density power supply when paired with any 5V
gate drive from an external controller/driver.
2
•
•
•
•
•
•
Half-Bridge Power Block
Up to 27V VIN
Up to 15A Operation
91% system Efficiency at 10A
High Frequency Operation (Up To 1.5MHz)
High Density – SON 3.3-mm × 3.3-mm
Footprint
TEXT ADDED FOR SPACING
Top View
•
•
•
•
•
•
Optimized for 5V Gate Drive
Low Switching Losses
Ultra Low Inductance Package
RoHS Compliant
VIN
VIN
TG
VSW
VSW
VSW
1
2
3
4
8
7
6
5
PGND
(Pin 9)
Halogen Free
Pb-Free Terminal Plating
TGR
BG
P0116-01
APPLICATIONS
•
Synchronous Buck Converters
TEXT ADDED FOR SPACING
ORDERING INFORMATION
–
–
High Frequency Applications
Device
Package
Media
Qty
Ship
High Current, Low Duty Cycle Applications
SON
3.3-mm × 3.3-mm
Plastic Package
13-Inch
Reel
Tape and
Reel
•
•
•
Multiphase Synchronous Buck Converters
POL DC-DC Converters
CSD87331Q3D
2500
IMVP, VRM, and VRD Applications
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TYPICAL POWER BLOCK EFFICIENCY
and POWER LOSS
TYPICAL CIRCUIT
96
88
80
72
64
56
48
6
5
4
3
2
1
0
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1.0µH
fSW = 500kHz
TA = 25ºC
0
5
10
Output Current (A)
15
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
CSD87331Q3D
SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
TA = 25°C (unless otherwise noted)(1)
VALUE
UNIT
PARAMETER
CONDITIONS
MIN
MAX
30
30
32
10
10
45
6
VIN to PGND
V
V
V
V
V
A
W
VSW to PGND
VSW to PGND (10ns)
TG to TGR
Voltage Range
-8
-8
BG to PGND
Pulsed Current Rating, IDM
Power Dissipation, PD
Sync FET, ID = 42A, L = 0.1mH
Control FET, ID = 24A, L = 0.1mH
88
29
150
Avalanche Energy EAS
mJ
Operating Junction and Storage Temperature Range, TJ, TSTG
–55
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
TA = 25° (unless otherwise noted)
PARAMETER
Gate Drive Voltage, VGS
CONDITIONS
MIN
MAX
8
UNIT
V
4.5
Input Supply Voltage, VIN
Switching Frequency, fSW
Operating Current
27
V
CBST = 0.1µF (min)
1500
15
kHz
A
Operating Temperature, TJ
125
°C
POWER BLOCK PERFORMANCE(1)
TA = 25° (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
W
VIN = 12V, VGS = 5V, VOUT = 1.3V,
IOUT = 10A, fSW = 500kHz,
LOUT = 1µH, TJ = 25ºC
(1)
Power Loss, PLOSS
1.3
10
VIN Quiescent Current, IQVIN
TG to TGR = 0V BG to PGND = 0V
µA
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5V driver IC.
THERMAL INFORMATION
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction to ambient thermal resistance (Min Cu)(1)
Junction to ambient thermal resistance (Max Cu)(1)(2)
Junction to case thermal resistance (Top of package)(1)
Junction to case thermal resistance (PGND Pin)(1)
MIN
TYP
MAX UNIT
149
RθJA
80
°C/W
36
RθJC
(1)
3.1
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch
(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2) Cu.
2
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CSD87331Q3D
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SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise stated)
Q1 Control FET
Q2 Sync FET
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX UNIT
Static Characteristics
BVDSS
IDSS
Drain to Source Voltage
VGS = 0V, IDS = 250µA
30
30
V
Drain to Source Leakage
Current
VGS = 0V, VDS = 20V
1
100
2.1
1
100
1.2
µA
Gate to Source Leakage
Current
IGSS
VDS = 0V, VGS = +10 / –8V
VDS = VGS, IDS = 250µA
nA
V
Gate to Source Threshold
Voltage
VGS(th)
1
0.8
VIN = 12V, VGS = 5V,
VOUT = 1.3V, IOUT = 10A,
fSW = 500kHz,
ZDS(on)
Effective AC On-Impedance
Transconductance
18
26
5.5
48
mΩ
LOUT = 1µH
gfs
VDS = 15V, IDS = 8A
S
Dynamic Characteristics
CISS
Input Capacitance
Output Capacitance
432
158
518
190
926
378
1110
454
pF
pF
COSS
VGS = 0V, VDS = 15V,
f = 1MHz
Reverse Transfer
Capacitance
CRSS
7
9
24
30
pF
RG
Qg
Series Gate Resistance
Gate Charge Total (4.5V)
Gate Charge - Gate to Drain
5.2
2.7
0.4
6.5
3.2
0.7
6.4
1.1
1.5
7.7
Ω
nC
nC
Qgd
VDS = 15V,
IDS = 8A
Gate Charge - Gate to
Source
Qgs
0.9
1.5
nC
Qg(th)
QOSS
td(on)
tr
Gate Charge at Vth
Output Charge
Turn On Delay Time
Rise Time
0.5
3.6
3.4
4.5
7.4
1.3
0.8
7.7
nC
nC
ns
ns
ns
ns
VDS = 14V, VGS = 0V
3.8
4.7
VDS = 15V, VGS = 4.5V,
IDS = 8A, RG = 2Ω
td(off)
tf
Turn Off Delay Time
Fall Time
11.2
2.4
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
IDS = 8A, VGS = 0V
0.85
4
1
0.85
5.9
13
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDS = 14V, IF = 8A,
di/dt = 300A/µs
10
HD
LD
HD
LD
Max RθJA = 80°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
Max RθJA = 149°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
LG HS
LG HS
LS
LS
HG
HG
M0205-01
M0206-01
Copyright © 2011–2012, Texas Instruments Incorporated
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SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
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TYPICAL POWER BLOCK DEVICE CHARACTERISTICS
Test Conditions: VIN = 12V, VDD = 5V, fSW = 500kHz, VOUT = 1.3V, LOUT = 1µH, IOUT = 15A, TJ = 125°C, unless stated
otherwise.
4
3.5
3
1.4
1.3
1.2
1.1
1
2.5
2
0.9
0.8
0.7
0.6
0.5
0.4
1.5
1
0.5
0
1
3
5
7
9
11
13
15
−50
−25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (ºC)
Figure 1. Power Loss vs Output Current
Figure 2. Power Loss vs Temperature
20
15
10
5
20
15
10
5
400LFM
200LFM
100LFM
Nat Conv
400LFM
200LFM
100LFM
Nat Conv
0
0
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
Ambient Temperature (ºC)
Ambient Temperature (ºC)
Figure 3. Safe Operating Area – PCB Vertical Mount(1)
Figure 4. Safe Operating Area – PCB Horizontal Mount(1)
20
15
10
5
0
0
20
40
60
80
100
120
140
Board Temperature (ºC)
Figure 5. Typical Safe Operating Area(1)
(1) The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section
for detailed explanation.
4
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CSD87331Q3D
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SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued)
Test Conditions: VIN = 12V, VDD = 5V, fSW = 500kHz, VOUT = 1.3V, LOUT = 1µH, IOUT = 15A, TJ = 125°C, unless stated
otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.6
1.5
1.4
1.3
1.2
1.1
1
17.2
14.3
11.4
8.6
1.6
1.5
1.4
1.3
1.2
1.1
1
17.1
14.3
11.4
8.6
5.7
5.7
2.9
2.9
0.0
0.0
0.9
0.8
0.7
0.6
−2.9
−5.7
−8.6
−11.4
0.9
0.8
0.7
0.6
−2.9
−5.7
−8.6
−11.4
200 350 500 650 800 950 1100 1250 1400 1550
Switching Frequency (kHz)
3
5
7
9
11
13
15
17
19
21
23
Input Voltage (V)
Figure 6. Normalized Power Loss vs Switching Frequency
Figure 7. Normalized Power Loss vs Input Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
22.5
19.7
16.9
14.1
11.2
8.4
1.6
1.5
1.4
1.3
1.2
1.1
1
16.9
14.1
11.2
8.4
5.6
2.8
5.6
0
2.8
0.9
0.8
0.7
0.6
−2.8
−5.6
−8.4
−11.2
0
0.9
0.8
−2.8
−5.6
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Inductance (µH)
1
1.1
Output Voltage (V)
Figure 8. Normalized Power Loss vs. Output Voltage
Figure 9. Normalized Power Loss vs. Output Inductance
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TYPICAL POWER BLOCK MOSFET CHARACTERISTICS
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
50
40
30
20
10
0
50
40
30
20
10
0
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
0
1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
VDS - Drain-to-Source Voltage - V
VDS - Drain-to-Source Voltage - V
Figure 10. Control MOSFET Saturation
TEXT ADDED FOR SPACING
Figure 11. Sync MOSFET Saturation
TEXT ADDED FOR SPACING
100
10
100
10
VDS = 3V
VDS = 3V
1
1
0.1
0.1
0.01
0.001
0.01
0.001
TC = 125°C
TC = 25°C
TC = −55°C
TC = 125°C
TC = 25°C
TC = −55°C
1.5
2
2.5
3
3.5
4
0.5
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage - V
VGS - Gate-to-Source Voltage - V
Figure 12. Control MOSFET Transfer
TEXT ADDED FOR SPACING
Figure 13. Sync MOSFET Transfer
TEXT ADDED FOR SPACING
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
ID = 8A
VDD = 15V
ID = 8A
VDD = 15V
1
2
3
4
5
2
4
6
8
10
Qg - Gate Charge - nC (nC)
Qg - Gate Charge - nC (nC)
Figure 14. Control MOSFET Gate Charge
Figure 15. Sync MOSFET Gate Charge
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CSD87331Q3D
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SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1
0.1
10
1
0.01
0.1
0.001
0.0001
0.01
0.001
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
f = 1MHz
VGS = 0V
f = 1MHz
VGS = 0V
0
5
10
15
20
25
30
0
5
10
15
20
25
30
VDS - Drain-to-Source Voltage - V
VDS - Drain-to-Source Voltage - V
Figure 16. Control MOSFET Capacitance
TEXT ADDED FOR SPACING
Figure 17. Sync MOSFET Capacitance
TEXT ADDED FOR SPACING
2
1.8
1.6
1.4
1.2
1
1.6
1.4
1.2
1
ID = 250µA
ID = 250µA
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
−75
−25
25
75
125
175
−75
−25
25
75
125
175
TC - Case Temperature - ºC
TC - Case Temperature - ºC
Figure 18. Control MOSFET VGS(th)
TEXT ADDED FOR SPACING
Figure 19. Sync MOSFET VGS(th)
TEXT ADDED FOR SPACING
60
15
ID = 8A
ID = 8A
50
40
30
20
10
0
12
9
6
3
TC = 25°C
TC = 125ºC
TC = 25°C
TC = 125ºC
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
VGS - Gate-to- Source Voltage - V
VGS - Gate-to- Source Voltage - V
Figure 20. Control MOSFET RDS(on) vs VGS
Figure 21. Sync MOSFET RDS(on) vs VGS
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TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1
ID = 8A
VGS = 8V
ID = 8A
VGS = 8V
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
−75
−25
25
75
125
175
−75
−25
25
75
125
175
TC - Case Temperature - ºC
TC - Case Temperature - ºC
Figure 22. Control MOSFET Normalized RDS(on)
TEXT ADDED FOR SPACING
Figure 23. Sync MOSFET Normalized RDS(on)
TEXT ADDED FOR SPACING
100
10
100
10
1
1
0.1
0.1
0.01
0.001
0.0001
0.01
0.001
0.0001
TC = 25°C
TC = 125°C
TC = 25°C
TC = 125°C
0.2
0.4
0.6
0.8
1
1.2
0
0.2
0.4
0.6
0.8
1
VSD − Source-to-Drain Voltage - V
VSD − Source-to-Drain Voltage - V
Figure 24. Control MOSFET Body Diode
TEXT ADDED FOR SPACING
Figure 25. Sync MOSFET Body Diode
TEXT ADDED FOR SPACING
100
10
1
100
10
1
TC = 25°C
TC = 125°C
TC = 25°C
TC = 125°C
0.01
0.1
1
10
0.01
0.1
1
10
t
- Time in Avalanche - ms
t
(AV)
- Time in Avalanche - ms
(AV)
Figure 26. Control MOSFET Unclamped Inductive
Switching
Figure 27. Sync MOSFET Unclamped Inductive Switching
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APPLICATION INFORMATION
Equivalent System Performance
Many of today’s high performance computing systems require low power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an
emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this
Application (see Figure 28). As such, optimization of the power semiconductors in these applications, needs to
go beyond simply reducing RDS(ON)
.
Figure 28.
The CSD87331Q3D is part of TI’s Power Block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the Control FET and Sync FET connections (see Figure 29). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in TI’s Application Note SLPA009.
Figure 29.
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The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figure 30 and Figure 31 compare the efficiency and power loss performance of the
CSD87331Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD87331Q3D clearly highlights the importance of considering the Effective AC On-Impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block
technology.
96
94
92
90
88
86
84
82
80
4
3.5
3
PowerBlock HS/LS RDS(ON) = 18mΩ/6.7mΩ
Discrete HS/LS RDS(ON) = 18mΩ/6.7mΩ
Discrete HS/LS RDS(ON) = 18mΩ/5.5mΩ
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1µH
fSW = 500kHz
TA = 25ºC
2.5
2
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 1µH
fSW = 500kHz
TA = 25ºC
1.5
1
PowerBlock HS/LS RDS(ON) = 18mΩ/6.7mΩ
Discrete HS/LS RDS(ON) = 18mΩ/6.7mΩ
Discrete HS/LS RDS(ON) = 18mΩ/5.5mΩ
0.5
0
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Output Current (A)
Output Current (A)
Figure 30.
Figure 31.
The chart below compares the traditional DC measured RDS(ON) of CSD87331Q3D versus its ZDS(ON). This
comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As
such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs
in a standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD87331Q3D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Comparison of RDS(ON) vs. ZDS(ON)
HS
LS
Parameter
Typ
18
Max
-
Typ
5.5
6.7
Max
Effective AC On-Impedance ZDS(ON) (VGS = 5V)
DC Measured RDS(ON) (VGS = 4.5V)
-
18
22
8
10
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SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
The CSD87331Q3D NexFET™ power block is an optimized design for synchronous buck applications using 5V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87331Q3D as a function of load current. This curve
is measured by configuring and running the CSD87331Q3D as it would be in the final application (see
Figure 32).The measured power loss is the CSD87331Q3D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power Loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
Safe Operating Curves (SOA)
The SOA curves in the CSD87331Q3D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) ×
3.5” (L) × 0.062” (T) and 6 copper layers of 1 oz. copper thickness.
Normalized Curves
The normalized curves in the CSD87331Q3D data sheet provides guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Figure 32. Typical Application
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Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
Design Example
Operating Conditions:
•
•
•
•
•
Output Current = 10A
Input Voltage = 10V
Output Voltage = 1V
Switching Frequency = 1000kHz
Inductor = 0.4µH
Calculating Power Loss
•
•
•
•
•
•
Power Loss at 10A = 1.8W (Figure 1)
Normalized Power Loss for input voltage ≈ 1.0 (Figure 7)
Normalized Power Loss for output voltage ≈ 0.95 (Figure 8)
Normalized Power Loss for switching frequency ≈ 1.15 (Figure 6)
Normalized Power Loss for output inductor ≈ 1.04 (Figure 9)
Final calculated Power Loss = 1.8W × 1.0 × 0.95 × 1.15 × 1.04 ≈ 2.05W
Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 0.1ºC (Figure 7)
SOA adjustment for output voltage ≈ -1.3ºC (Figure 8)
SOA adjustment for switching frequency ≈ 4.2ºC (Figure 6)
SOA adjustment for output inductor ≈ 1ºC (Figure 9)
Final calculated SOA adjustment = 0.1 + (–1.3) + 4.2 + 1 ≈ 4.8ºC
In the design example above, the estimated power loss of the CSD87331Q3D would increase to 2.05W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 4.8ºC. Figure 33
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 4.8ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
20
15
1
10
2
5
3
0
0
20
40
60
80
100
120
140
Board Temperature (°C)
Figure 33. Power Block SOA
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CSD87331Q3D
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SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and
Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
Electrical Performance
The Power Block has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
•
The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34).
The example in Figure 34 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8
should follow in order.
•
•
The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to
the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and
should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap
capacitor for the Driver IC will also connect to this pin.
The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
(1)
actually reduce the switching noise level.
In the event the switch node waveform exhibits ringing that
reaches undesirable levels, the use of a Boost Resistor or RC snubber can be an effective way to easily
reduce the peak ring level. The recommended Boost Resistor value will range between 1.0 Ohms to 4.7
Ohms depending on the output characteristics of Driver IC used in conjunction with the Power Block. The RC
snubber values can range from 0.5 Ohms to 2.2 Ohms for the R and 330pF to 2200pF for the C. Please refer
to TI App Note SLUP100 for more details on how to properly tune the RC snubber values. The RC snubber
should be placed as close as possible to the Vsw node and PGND see Figure 34(1)
(1) (1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University
of Missouri – Rolla
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CSD87331Q3D
SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
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Thermal Performance
The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
•
•
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
•
Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 34. Recommended PCB Layout (Top Down)
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CSD87331Q3D
www.ti.com
SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
MECHANICAL DATA
Q3D Package Dimensions
A
E2
d1
L
E1
L
c1
q
b
9
E
D1
D2
d
e
d3
Top View
Side View
d2
K
Pinout
Bottom View
Position
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Designation
VIN
VIN
TG
c
TGR
BG
VSW
VSW
VSW
PGND
Exposed tie clips may vary
q
M0192-01
MILLIMETERS
INCHES
DIM
MIN
MAX
MIN
MAX
0.059
0.016
0.010
0.010
0.041
0.010
0.010
0.014
0.134
0.108
0.134
0.134
0.073
A
b
1.40
1.5
0.055
0.011
0.006
0.006
0.037
0.006
0.006
0.010
0.126
0.104
0.126
0.126
0.069
0.280
0.150
0.150
0.940
0.160
0.150
0.250
3.200
2.650
3.200
3.200
1.750
0.400
0.250
0.250
1.040
0.260
0.250
0.350
3.400
2.750
3.400
3.400
1.850
c
c1
d
d1
d2
d3
D1
D2
E
E1
E2
e
0.650 TYP
0.300 TYP
0.026 TYP
L
0.400
0.00
0.500
0.016
0.020
θ
–
–
–
K
0.012 TYP
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CSD87331Q3D
SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
www.ti.com
Land Pattern Recommendation
1.900 (0.075)
0.200
(0.008)
0.210
(0.008)
0.350 (0.014)
0.440
(0.017)
0.650
(0.026)
2.800
(0.110)
2.390
(0.094)
1.090
(0.043)
0.210
(0.008)
0.300 (0.012)
0.650 (0.026)
0.650 (0.026)
3.600 (0.142)
M0193-01
NOTE: Dimensions are in mm (inches).
Stencil Recommendation
0.160 (0.005)
0.550 (0.022)
0.200 (0.008)
0.300 (0.012)
0.300
(0.012)
0.340
(0.013)
2.290
(0.090)
0.333
(0.013)
0.990
(0.039)
0.100
(0.004)
0.350 (0.014)
0.300 (0.012)
0.850 (0.033)
3.500 (0.138)
M0207-01
NOTE: Dimensions are in mm (inches).
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
16
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CSD87331Q3D
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SLPS283A –SEPTEMBER 2011–REVISED JANUARY 2012
Q3D Tape and Reel Information
4.00 0.ꢀ0 ꢁ(SS ꢂNoS ꢀ1
8.00 0.ꢀ0
2.00 0.0ꢃ
+0.ꢀ0
–0.00
Ø ꢀ.ꢃ0
3.60
M0ꢀ44-0ꢀ
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
Spacer
REVISION HISTORY
Changes from Original (September 2011) to Revision A
Page
•
Added Feature Bullet: Up to 15A Operation ......................................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CSD87331Q3D
ACTIVE
SON
DQZ
8
2500
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD87331Q3D
SON
DQZ
8
2500
330.0
12.8
3.6
3.6
1.75
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DQZ
SPQ
Length (mm) Width (mm) Height (mm)
335.0 335.0 32.0
CSD87331Q3D
8
2500
Pack Materials-Page 2
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