CSD88584Q5DCT [TI]
采用 5mm x 6mm SON 封装的 50A、40V、N 沟道同步降压 NexFET™ 功率 MOSFET Dual-Cool™ 电源块 | DMM | 22 | -55 to 150;
| 型号： | CSD88584Q5DCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 5mm x 6mm SON 封装的 50A、40V、N 沟道同步降压 NexFET™ 功率 MOSFET Dual-Cool™ 电源块 | DMM | 22 | -55 to 150 电动机控制 光电二极管 |
| 文件： | 总25页 (文件大小：1397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
CSD88584Q5DC 40V 半桥 NexFET™ 电源块
1 特性
3 说明
•
•
•
半桥电源块
CSD88584Q5DC 40V 电源块是一款针对手持设备、
无绳园艺工具和电动工具等高电流电机控制应用的优化
设计。该器件利用 TI 获得专利的堆叠裸片技术来更大
限度地减小寄生电感，同时采用节省空间的散热增强型
DualCool™ 5mm × 6mm 封装，可提供完整半桥。利用
外露的金属顶部，该电源块器件允许简单散热应用通过
封装顶部散发 PCB 热量，从而在许多电机控制应用所
要求的较高电流下，实现出色的热性能。
高密度 5mm × 6mm SON 封装
低 RDS(ON)，可更大限度地降低传导损耗
– 电流为 35A 时，PLoss 为 2.4W
DualCool™ 散热增强型封装
超低电感封装
•
•
•
•
•
符合 RoHS
无卤素
无铅端子镀层
底视图
顶视图
2 应用
•
•
•
GL
NC
GH
SH
用于无刷直流电机控制的三相桥
多达 8s 电池的电动工具
其他半桥和全桥拓扑
VIN
PGND
VSW
VIN
GH
SH
VSW
器件信息
介质
器件
数量
封装
配送
GL
CSD88584Q5DC 2500 13 英寸卷带
SON
5.00mm × 6.00mm
塑料封装
卷带包
装
PGND
CSD88584Q5DCT 250
7 英寸卷带
Copyright © 2017, Texas Instruments Incorporated
电源块原理图
6
VIN
VIN = 24 V
VGS = 10 V
5
4
3
2
1
0
D.C. = 50%
L = 480 mH
fSW = 20 kHz
TA = 25èC
VM
CSD88584
CSD88584
CSD88584
GH_A
GL_A
Motor
GH_B
GL_B
DRV832X
Gate Driver
GH_C
GL_C
0
5
10
15
20
25
30
RMS Phase Current (A)
35
40
45
50
D000
功率损耗与输出电流
Copyright © 2018, Texas Instruments Incorporated
典型电路
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Absolute Maximum Ratings(1) ....................................3
5.2 Recommended Operating Conditions.........................3
5.3 Power Block Performance.......................................... 3
5.4 Thermal Information....................................................3
5.5 Electrical Characteristics.............................................4
5.6 Typical Power Block Device Characteristics...............6
5.7 Typical Power Block MOSFET Characteristics...........8
6 Application and Implementation..................................10
6.1 Application Information............................................. 10
6.2 Brushless DC Motor With Trapezoidal Control..........11
6.3 Power Loss Curves...................................................13
6.4 Safe Operating Area (SOA) Curve............................14
6.5 Normalized Power Loss Curves................................14
6.6 Design Example – Regulate Current to Maintain
Safe Operation............................................................ 14
6.7 Design Example – Regulate Board and Case
Temperature to Maintain Safe Operation.................... 15
7 Layout.............................................................................17
7.1 Layout Guidelines..................................................... 17
7.2 Layout Example........................................................ 19
8 Device and Documentation Support............................20
8.1 接收文档更新通知..................................................... 20
8.2 支持资源....................................................................20
8.3 Trademarks...............................................................20
8.4 静电放电警告............................................................ 20
8.5 术语表....................................................................... 20
9 Mechanical, Packaging, and Orderable Information..21
4 Revision History
Changes from Revision C (January 2018) to Revision D (December 2018)
Page
•
Updated current sense resistor description in applications section .................................................................17
Changes from Revision * (May 2017) to Revision A (May 2017)
Page
•
更新了典型电路 图中的栅极驱动器器件型号......................................................................................................1
Changes from Revision A (May 2017) to Revision B (September 2017)
Page
•
Updated 图 5-3 to extend to 50 A....................................................................................................................... 6
Changes from Revision B (September 2017) to Revision C (January 2018)
Page
•
•
在功率损耗与输出电流 图 3-1 图中将 VDD = 10V 改为 VGS = 10V.....................................................................1
Changed VDD to VGS in sections Recommended Operating Conditions, Block Performance, & Typical Power
Block Device Characteristics ............................................................................................................................. 3
Changed IDSS test condition from 20 V to 32 V in the Electrical Characteristics table....................................... 4
•
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
2
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
5 Specifications
5.1 Absolute Maximum Ratings(1)
TJ = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
–0.8
–0.3
–20
–20
MAX
40
UNIT
VIN to PGND
VSW to PGND
40
Voltage
V
GH to SH
20
GL to PGND
20
(2)
Pulsed current rating, IDM
400
12
A
Power dissipation, PD
W
High-side FET, ID = 103 A, L = 0.1 mH
Low-side FET, ID = 103 A, L = 0.1 mH
525
525
150
150
Avalanche energy, EAS
mJ
Operating junction temperature, TJ
Storage temperature, Tstg
–55
–55
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Single FET conduction, max RθJC = 1.1°C/W, pulse duration ≤ 100 μs, single pulse.
5.2 Recommended Operating Conditions
TJ = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX
16
UNIT
V
VGS
VIN
ƒSW
IOUT
TJ
Gate drive voltage
4.5
Input supply voltage(1)
Switching frequency
36
V
CBST = 0.1 µF (min)
5
50
kHz
A
RMS motor winding current
Operating temperature
50
125
°C
(1) Up to 32-V input use one capacitor per phase, MLCC 10 nF, 100 V, X7S, 0402, PN: C1005X7S2A103K050BB from VIN to GND return.
Between 32-V to 36-V input operation, add RC switch-node snubber as described in the 节 7.1.1 section of this data sheet.
5.3 Power Block Performance
TJ = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
VIN = 24 V, VGS = 10 V,
MIN
TYP
MAX UNIT
IOUT = 35 A, ƒSW = 20 kHz,
TJ = 25°C, duty cycle = 50%,
L = 480 µH
PLOSS
Power loss(1)
2.4
W
VIN = 24 V, VGS = 10 V,
IOUT = 35 A, ƒSW = 20 kHz,
TJ = 125°C, duty cycle = 50%,
L = 480 µH
PLOSS
Power loss
3.5
W
(1) Measurement made with eight 10-µF, 50-V, ±10% X5R (TDK C3225X5R1H106K250AB or equivalent) ceramic capacitors placed
across VIN to PGND pins and using UCC27210DDAR 100-V, 4-A driver IC.
5.4 Thermal Information
TJ = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-ambient thermal resistance (min Cu)(2)
Junction-to-ambient thermal resistance (max Cu)(2) (1)
MIN
TYP MAX UNIT
125
°C/W
50
RθJA
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
TJ = 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP MAX UNIT
Junction-to-case thermal resistance (top of package)(2)
Junction-to-case thermal resistance (VIN pin)(2)
2.1
°C/W
1.1
RθJC
(1) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
(2) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
5.5 Electrical Characteristics
TJ = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 µA
VGS = 0 V, VDS = 32 V
VDS = 0 V, VGS = 20 V
VDS = VGS, IDS = 250 µA
VGS = 4.5 V, IDS = 30 A
VGS = 10 V, IDS = 30 A
VDS = 4 V, IDS = 30 A
40
V
µA
nA
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
1
100
2.3
IGSS
VGS(th)
1.2
1.7
1.0
1.5
RDS(on)
gfs
Drain-to-source on resistance
Transconductance
mΩ
S
0.68
149
0.95
DYNAMIC CHARACTERISTICS
CISS
COSS
CRSS
RG
Input capacitance
9540
957
474
1.0
68
12400
1240
616
2.0
pF
pF
pF
Ω
VGS = 0 V, VDS = 20 V,
ƒ = 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
Qg
88
nC
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qg
137
26
178
VDS = 20 V,
IDS = 30 A
Qgd
Qgs
Qg(th)
QOSS
td(on)
tr
24
16
VDS = 20 V, VGS = 0 V
42
Turnon delay time
11
Rise time
24
VDS = 20 V, VGS = 10 V,
IDS = 30 A, RG = 0 Ω
td(off)
tf
Turnoff delay time
53
Fall time
17
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
IDS = 30 A, VGS = 0 V
0.75
34
1.0
V
Reverse recovery charge
Reverse recovery time
nC
ns
VDS = 20 V, IF = 30 A,
di/dt = 300 A/µs
24
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
4
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
Max RθJA = 50°C/W when mounted on 1 in2 (6.45 cm2) of
2-oz (0.071-mm) thick Cu.
Max RθJA = 125°C/W when mounted on minimum pad area
of 2-oz (0.071-mm) thick Cu.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
5.6 Typical Power Block Device Characteristics
The typical power block system characteristic curves (图 5-1 through 图 5-6) are based on measurements made
on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 2-oz copper
thickness. See 节 6 section for detailed explanation. TJ = 125°C, unless stated otherwise.
10
9
8
7
6
5
4
3
2
1
0
1.2
1.1
1
Typical
Max
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
Output Current (A)
35
40
45
50
Junction Temperature (èC)
D002
D001
VIN = 24 V
VGS = 10 V
IOUT = 50 A
D.C. = 50%
L = 480 µH
VIN = 24 V
VGS = 10 V
L = 480 µH
D.C. = 50%
ƒSW = 20 kHz
ƒSW = 20 kHz
图 5-2. Power Loss vs Temperature
图 5-1. Power Loss vs Output Current
Top Case Temperature (èC)
108 112 116 120
100
55
104
124
128
TX
50
45
40
35
30
25
20
15
10
5
0
100
104
108
112
116
120
124
128
Board Temperature (èC)
D005
VIN = 24 V
VGS = 10 V
L = 480 µH
D.C. = 50%
ƒSW = 20 kHz
图 5-3. Typical Safe Operating Area
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
6
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
1.4
2.8
2.1
1.4
0.7
0.0
-0.7
-1.4
1.12
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.8
0.7
0.6
0.4
0.3
0.1
0.0
-0.1
-0.3
-0.4
1.3
1.2
1.1
1
0.9
0.8
5
10
15
20
Switching Frequency (kHz)
25
30
35
40
45
50
12
16
20 24
Input Voltage (V)
28
32
D006
D007
VIN = 24 V
IOUT = 50 A
VGS = 10 V
D. C. = 50%
L = 480 µH
IOUT = 50 A
VGS = 10 V
D. C. = 50%
L = 480 µH
ƒSW = 20 kHz
图 5-4. Normalized Power Loss vs Switching
图 5-5. Normalized Power Loss vs Input Voltage
Frequency
1.12
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.8
0.7
0.6
0.4
0.3
0.1
0.0
-0.1
10
20
30
40
50 60
Duty Cycle (%)
70
80
90
100
D009
VIN = 24 V
ƒSW = 20 kHz
VGS = 10 V
L = 480 µH
IOUT = 50 A
图 5-6. Normalized Power Loss vs Duty Cycle
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
5.7 Typical Power Block MOSFET Characteristics
TJ = 25°C, unless stated otherwise.
450
400
350
300
250
200
150
100
50
200
180
160
140
120
100
80
60
40
VGS = 4.5 V
VGS = 8 V
VGS = 10 V
20
0
0
1E-5
0
0.05
0.1
0.15
0.2
0.25
0.3
VDS - Drain-to-Source Voltage (V)
0.35
0.4
0.0001
0.001
0.01
0.1
1
Duration (s)
D010
D014
D018
Max RθJA = 125°C/W
图 5-8. MOSFET Saturation Characteristics
图 5-7. Single Pulse Current vs Pulse Duration
100
10
9
8
7
6
5
4
3
2
1
0
TC = 125° C
TC = 25° C
TC = -55° C
10
1
0.1
0.01
0.001
0
0.5
1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)
3
3.5
0
15
30
45
60
Qg - Gate Charge (nC)
75
90 105 120 135 150
D012
VDS = 5 V
ID = 30 A
VDS = 20 V
图 5-9. MOSFET Transfer Characteristics
图 5-10. MOSFET Gate Charge
100000
2.3
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
10000
1000
100
0
10
20
30
VDS - Drain-to-Source Voltage (V)
40
-75 -50 -25
0
25
50
TC - Case Temperature (° C)
75 100 125 150 175
D016
图 5-11. MOSFET Capacitance
ID = 250 µA
图 5-12. Threshold Voltage vs Temperature
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
8
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
5
4.5
4
2
1.8
1.6
1.4
1.2
1
TC = 25° C
TC = 125° C
VGS = 4.5 V
VGS = 10 V
3.5
3
2.5
2
1.5
1
0.8
0.6
0.4
0.5
0
0
-75 -50 -25
0
25
50
TC - Case Temperature (° C)
75 100 125 150 175
2
4
6
8
10
12
14
VGS - Gate-to-Source Voltage (V)
16
18
20
D022
D020
ID = 30 A
VDS = 20 V
ID = 30 A
图 5-14. MOSFET Normalized RDS(on) vs
图 5-13. MOSFET RDS(on) vs VGS
Temperature
100
10
1000
TC = 25° C
TC = 125° C
TC = 25è C
TC = 125è C
1
100
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
VSD - Source-to-Drain Voltage (V)
0.8
1
0.01
0.1
TAV - Time in Avalanche (ms)
1
D024
D026
图 5-15. MOSFET Body Diode Forward Voltage
图 5-16. MOSFET Single Pulse Unclamped
Inductive Switching
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
6 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
6.1 Application Information
Historically, battery powered tools have favored brushed DC configurations to spin their primary motors, but
more recently, the advantages offered by brushless DC operation (BLDC) operation have brought about the
advent of popular designs that favor the latter. Those advantages include, but are not limited to higher efficiency
and therefore longer battery life, superior reliability, greater peak torque capability, and smooth operation over
a wider range of speeds. However, BLDC designs put increased demand for higher power density and current
handling capabilities on the power stage responsible for driving the motor.
The CSD88584Q5DC is part of TI’s power block product family and is a highly optimized product designed
explicitly for the purpose driving higher current DC motors in power and gardening tools. It incorporates TI’s
latest generation silicon which has been optimized for low resistance to minimize conduction losses and offer
excellent thermal performance. The power block utilizes TI’s stacked die technology to offer one complete half
bridge vertically integrated into a single 5-mm × 6-mm package with a DualCool exposed metal case. This
feature allows the designer to apply a heatsink to the top of the package and pull heat away from the PCB, thus
maximizing the power density while reducing the power stage footprint by up to 50%.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
10
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
6.2 Brushless DC Motor With Trapezoidal Control
The trapezoidal commutation control is simple and has fewer switching losses compared to sinusoidal control.
Vin
Vin
Vin
PB1
Vin
PB2
PB3
PWM1
PWM2
PWM3
PWM4
GH1
DRV8323RX
SH1
GL1
GH2
SH2
GL2
GH3
SH3
Q3
Q2
Q1
GH2
SH2
GH3
SH3
GH1
SH1
Three Phase
Gate Driver
Vsw1
Vsw3
Vsw2
SPEED SET
U
PWM5
PWM6
VCS
Hall
Sensors
TORQUE SET
GL3
Q5
N
S
GL2
GL1
A
B
C
Q4
Q6
GL3
PGND
PGND
PGND
V
W
SPA
SPB
SPC
SPA
SPB
SPC
A
Rcs1
Rcs2
Rcs3
B
C
0
0
0
0
Hall
Inputs
Copyright © 2017, Texas Instruments Incorporated
图 6-1. Functional Block Diagram
The block diagram shown in 图 6-1 offers a simple instruction of what is required to drive a BLDC motor: one
microcontroller, one three-phase driver IC, 3 power blocks (historically 6 power MOSFETs) and 3 Hall effect
sensors. The microcontroller responsible for block commutation must always know the rotor orientation or its
position relative to the stator coils. This is easy achieved with a brushed DC motor due to the fixed geometry and
position of the rotor windings, shaft and commutator.
A three-phase BLDC motor requires three Hall effect sensors or a rotary encoder to detect the rotor
position in relation to stator armature windings. Combining these three Hall effect sensors output signals, the
microcontroller can determine the proper commutation sequence. The three Hall sensors named A, B, and C
are mounted on the stator core at 120° intervals and the stator phase windings are implemented in a star
configuration. For every 60° of motor rotation, one Hall sensor changes its state. Based on the Hall sensor
outputs code, at the end of each block commutation interval the ampere conductors are commutated to the next
position. There are 6 steps needed to complete a full electrical cycle. The number of block commutation cycles
to complete a full mechanical rotation is determined by the number of rotor pole pairs.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
H a l l
c o d e
1 0 1
1 0 0
0 0 1
0 1 1
1 1 0
0 1 0
i _ U
0
i _ V
0
i _ W
0
图 6-2. Winding Current Waveforms on a BLDC Motor
图 6-2 above shows the three phase motor winding currents i_U, i_V, and i_W when running at 100% duty cycle.
Trapezoidal commutation control offers the following advantages:
•
•
•
Only two windings in series carry the phase winding current at any time while the third winding is open.
Only one current sensor is necessary for all 3 windings U, V, and W.
The position of the current sensor allows the use of low-cost shunt resistors.
However, trapezoidal commutation control has the disadvantage of commutation torque ripple. The current
sense on a three-phase inverter can be configured to use a single-shunt or three different sense resistors. For
cost sensitive applications targeting sensorless control, the three Hall effect sensors can be replaced with BEMF
voltage feedback dividers.
To obtain faster motor rotations and higher revolutions per minute (RPM), shorter periods and higher VIN voltage
are necessary. Contrarily, to reduce the rotational speed of the motor, it is necessary to lower the RMS voltage
applied across stator windings. This can easily be easily achieved by modulating the duty cycle, while maintain
a constant switching frequency. Frequency for the three-phase inverter chosen is usually low between 10 kHz to
50 kHz to reduce winding losses and to avoid audible noise.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
12
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
6.3 Power Loss Curves
CSD88584Q5DC was designed to operate up to 7-cell Li-Ion battery voltage applications ranging from 18 V to
32 V, typical 24 V. For 8s, input voltages between 32 V to 36 V, RC snubbers are required for each switch-node
U, V, and W. To reduce ringing, refer to the 节 7.1.1 section. In an effort to simplify the design process, Texas
Instruments has provided measured power loss performance curves over a variety of typical conditions.
图 5-1 plots the CSD88584Q5DC power loss as a function of load current. The measured power loss includes
both input conversion loss and gate drive loss.
方程式 1 is used to generate the power loss curve:
Power loss (W) = (VIN × IIN_SHUNT) + (VDD × IDD_SHUNT) – (VSW_AVG × IOUT
)
(1)
The power loss measurements were made on the circuit shown in 图 6-3, power block devices for legs U
and V, PB1 and PB2 were disabled by shorting the CSD88584Q5DC high-side and low-side FETs gate-to-
source terminals. Current shunt Iin_shunt provides Input current and Idd_SHUNT provides driver supply current
measurements. The winding current is measured from the DC load. An averaging circuit provides switch node W
equivalent RMS voltage.
Iin_SHUNT
Vin
Vin
PB1
Vin
PB2
PB3
Idd_SHUNT
Cin2
Cin1
Vdd
Vdd
GH2
SH2
0
0
GH3
SH3
GH1
SH1
0
0
W
HI
Vsw3
Vsw1
U
V
Vsw2
Vin
GATE
DRIVER
Lout
DCR
U1A
1
2
GL2
LI
GL1
GL3
Iout
LOAD
PGND
PGND
PGND
0
0
0
0
0
0
0
0
0
AVERAGE
SWITCH NODE
AVERAGING
CIRCUIT
PWM
Vsw_AVG
Copyright © 2017, Texas Instruments Incorporated
图 6-3. Power Loss Test Circuit
The RMS current on the CSD88584Q5DC device depends on the motor winding current. For trapezoidal control,
the MOSFET RMS current is calculated using 方程式 2.
IRMS = IOUT × √2
(2)
Taking into consideration system tolerances with the current measurement scheme, the inverter design needs to
withstand a 20% overload current.
表 6-1. RMS and Overload Current Calculations
Winding RMS Current (A)
CSD88584Q5DC IRMS (A)
Overload 120% × IRMS (A)
30
40
50
42
56
70
51
68
85
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
6.4 Safe Operating Area (SOA) Curve
The SOA curve in 图 5-3 provide guidance on the temperature boundaries within an operating system
by incorporating the thermal resistance and system power loss. This curve outlines the board and case
temperatures required for a given load current. The area under the curve dictates the safe operating area.
This curve is based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in
(H) and 6 copper layers of 2-oz copper thickness.
6.5 Normalized Power Loss Curves
The normalized curves in the CSD88584Q5DC data sheet provide guidance on the power loss and SOA
adjustments based on application specific needs. These curves show how the power loss and SOA temperature
boundaries will adjust for different operation conditions. The primary Y-axis is the normalized change in power
loss while the secondary Y-axis is the change in system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the typical power loss. The change in SOA temperature is
subtracted from the SOA curve.
6.6 Design Example – Regulate Current to Maintain Safe Operation
If the case and board temperature of the power block are known, the SOA can be used to determine the
maximum allowed current that will maintain operation within the safe operating area of the device. The following
procedure outlines how to determine the RMS current limit while maintaining operation within the confines of the
SOA, assuming the temperatures of the top of the package and PCB directly underneath the part are known.
1. Start at the maximum current of the device on the Y-axis and draw a line from this point at the known top
case temperature to the known PCB temperature.
2. Observe where this point intersects the TX line.
3. At this intersection with the TX line, draw vertical line until you hit the SOA current limit. This intercept is the
maximum allowed current at the corresponding power block PCB and case temperatures.
In the example below, we show how to achieve this for the temperatures TC = 124°C and TB = 120°C. First we
draw from 50 A on the Y-axis at 124°C to 120°C on the X-axis. Then, we draw a line up from where this line
crosses the TX line to see that this line intercepts the SOA at 39 A. Thus we can assume if we are measuring a
PCB temperature of 124°C, and a top case temperature of 120°C, the power block can handle 39-A RMS, at the
normalized conditions. At conditions that differ from those in 图 5-1, the user may be required to make an SOA
temperature adjustment on the TX line, as shown in the next section.
图 6-4. Regulating Current to Maintain Safe Operation
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
14
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
6.7 Design Example – Regulate Board and Case Temperature to Maintain Safe Operation
In the previous example we showed how given the PCB and case temperature, the current of the power block
could be limited to ensure operation within the SOA. Conversely, if the current and other application conditions
are known, one can determine from the SOA what board or case temperature the user will need to limit their
design to. The user can estimate product loss and SOA boundaries by arithmetic means (see 节 6.7.1 section).
Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the
following procedure outlines the steps the user should take to predict product performance for any set of system
conditions.
6.7.1 Operating Conditions
•
•
•
•
Winding output current (IOUT) = 40 A
Input voltage (VIN) = 32 V
Switching frequency (FSW) = 40 kHz
Duty cycle (D.C.) = 95%
6.7.2 Calculating Power Loss
•
•
•
•
•
Power loss at 40 A ≈ 4.7 W (图 5-1)
Normalized power loss for switching frequency ≈ 1.24 (图 5-4)
Normalized power loss for input voltage ≈ 1.09 (图 5-5)
Normalized power loss for duty cycle ≈ 1.06 (图 5-6)
Final calculated power loss = 4.7 W × 1.24 × 1.09 × 1.06 ≈ 6.7 W
6.7.3 Calculating SOA Adjustments
•
•
•
•
SOA adjustment for switching frequency ≈ 1.7°C (图 5-4)
SOA adjustment for input voltage ≈ 0.6°C (图 5-5)
SOA adjustment for duty cycle ≈ 0.4°C (图 5-6)
Final calculated SOA adjustment = 1.7 + 0.6 + 0.4 ≈ 2.7°C
In the 节 6.6 section above, the estimated power loss of the CSD88584Q5DC would increase to 6.7 W. In
addition, the maximum allowable board temperature would have to increase by 2.7°C. In 图 6-5, the SOA graph
was adjusted accordingly.
1. Start by drawing a horizontal line from the application current (40 A) to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the TX line.
3. Adjust the intersection point by subtracting the temperature adjustment value.
In this design example, the SOA board/ambient temperature adjustment yields a decrease of allowed junction
temperature of 2.7°C from 121.0°C to 118.3°C. Now it is known that the intersection of the case and PCB
temperatures on the TX line must stay below this point. For instance, if the power block case is observed
operating at 124°C, the PCB temperature must in turn be kept under 115°C to maintain this crossover point.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
图 6-5. Regulate Temperature to Maintain Safe Operation
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
16
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
7 Layout
The two key system-level parameters that can be optimized with proper PCB design are electrical and thermal
performance. A proper PCB layout will yield maximum performance in both areas. Below are some tips for how
to address each.
7.1 Layout Guidelines
7.1.1 Electrical Performance
The CSD88584Q5DC power block has the ability to switch at voltage rates greater than 1 kV/µs. Special care
must be then taken with the PCB layout design and placement of the input capacitors; high-current, high dI/dT
switching path; current shunt resistors; and GND return planes. As with any high-power inverter operated in
hard switching mode, there will be voltage ringing present on the switch nodes U, V, and W. Switch-node
ringing appears mainly at the HS FET turnon commutation with positive winding current direction. The U, V,
and W phase connections to the BLDC motor can be usually excluded from the ringing behavior since they
are subjected to high-peak currents but low dI/dT slew-rates. However, a compact PCB design with short and
low-parasitic loop inductances is critical to achieve low ringing and compliance with EMI specifications.
For safe and reliable operation of the three-phase inverter, motor phase currents have to be accurately
monitored and reported to the system microcontroller. One current sensor needs to be connected on each
motor phase winding U, V, and W. This sensing method is best for current sensing as it provides good accuracy
over a wide range of duty cycles, motor torque, and winding currents. Using current sensors is recommended
because it is less intrusive to the VIN and GND connections.
V i n
V i n
V i n
PB1
PB3
PB2
C 4
C 5
C 6
G H 1
S H 1
G H 2
S H 2
G H 3
S H 3
0
0
0
U
W
V
V s w
V s w
V s w
V in
C s1
C s3
C s2
G L 3
G L 1
G L 2
P G N D
P G N D
P G N D
R cs
G N D
0
R s1
R s2
R s3
0
0
0
0
Copyright © 2017, Texas Instruments Incorporated
图 7-1. Recommended Ringing Reduction Components
However, for cost sensitive applications, current sensors are generally replaced with current sense resistors.
•
For designs using the 60-V three-phase smart gate driver DRV8320SRHBR, current sense resistor RCS can
be placed between common source terminals for all 3 power block devices CSD88584Q5DC to PGND and
measured using an external current sense amplifier as depicted in 图 7-1 above.
•
For designs using the 60-V three-phase gate driver DRV8323RSRGZT, three current sense resistors RCS1
,
RCS2 and RCS3 can be used between each CSD88584Q5DC source terminal to GND and measured by the
included DRV8323 current sense amplifiers. The three-phase driver IC should be placed as close as possible
to the power block gate GL and GH terminals.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
Breaking the high-current flow path from the source terminals of the power block to GND by introducing the RCS
current shunt resistors introduces parasitic PCB inductance. In the event the switch node waveforms exhibits
peak ringing that reaches undesirable levels, the ringing can be reduced by using the following ringing reduction
components:
•
The use of a high-side gate resistor in series with the GH pin is one effective way to reduce peak ringing.
The recommended HS FET gate resistor value will range between 4.7 Ω to 10 Ω depending on the driver IC
output characteristics used in conjunction with the power block device. The low-side FET gate pin GL should
connect directly to the driver IC output to avoid any parasitic cdV/dT turnon effect.
Low inductance MLCC caps C4, C5, and C6 can be used across each power block device from VIN
to the source terminal PGND. MLCC 10 nF, 100 V, ±10%, X7S, 0402, PN: C1005X7S2A103K050BB are
recommended.
•
•
Ringing can be reduced via the implementation of RC snubbers from each switch node U, V, and W to GND.
Recommended snubber component values are as follows:
– Snubber resistors Rs1, Rs2, Rs3: 2.21 Ω, 1%, 0.125 W, 0805, PN: CRCW08052R21FKEA
– Snubber caps Cs1, Cs2, and Cs3: MLCC 4.7 nF, 100 V, X7S, 0402, PN: C1005X7S2A472M050BB
With a switching frequency of 20 kHz on the three-phase inverter, the power dissipation on the RC snubber
resistor is 80 mW per channel. As a result, 0805 package size for resistors Rs1, Rs2, and Rs3 is adequate.
7.1.2 Thermal Considerations
The CSD88584Q5DC power block device has the ability to utilize the PCB copper planes as the primary thermal
path. As such, the use of thermal vias included in the footprint is an effective way to pull away heat from
the device and into the system board. Concerns regarding solder voids and manufacturability issues can be
addressed through the use of three basic tactics to minimize the amount of solder attach that will wick down the
via barrel:
•
•
Intentionally space out the vias from one another to avoid a cluster of holes in a given area.
Use the smallest drill size allowed by the design. The example in 图 7-2 uses vias with a 10-mil drill hole and
a 16-mil solder pad.
•
Tent the opposite side of the via with solder-mask. Ultimately the number and drill size of the thermal vias
should align with the end user’s PCB design rules and manufacturing capabilities.
To take advantage of the DualCool thermally enhanced package, an external heatsink can be applied on top of
the power block devices. For low EMI, the heatsink is usually connected to GND through the mounting screws
to the PCB. Gap pad insulators with good thermal conductivity should be used between the top of the package
and the heatsink. The Bergquist Sil-Pad 980 is recommended which provides excellent thermal impedance of
1.07°C/W at 50 psi.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
18
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
7.2 Layout Example
图 7-2. Top Layer
图 7-3. Bottom Layer
The placement of the input capacitors C4, C5, and C6 relative to VIN and PGND pins of CSD88584Q5DC device
should have the highest priority during the component placement routine. It is critical to minimize the VIN to GND
parasitic loop inductance. A shunt resistor R21 is used between all three U4, U5, and U6 power block source
terminals to the input supply GND return pin.
Input RMS current filtering is achieved via two bulk caps C17 and C18. Based on the RMS current ratings, the
recommended part number for input bulk is CAP AL, 330 µF, 63 V, ±20%, PN: EMVA630ADA331MKG5S.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
8 Device and Documentation Support
8.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
8.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
8.3 Trademarks
NexFET™ and DualCool™ are trademarks of TI.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
8.4 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
8.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLPS598
20
Submit Document Feedback
Product Folder Links: CSD88584Q5DC
CSD88584Q5DC
ZHCSG78D – MAY 2017 – REVISED DECEMBER 2018
www.ti.com.cn
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
表 9-1. Pin Configuration Table
POSITION
PIN NAME
DESCRIPTION
High Side Gate
High Side Gate Return
Switch Node
1
2
GH
SH
3-11
12-20
21
VSW
PGND
NC
Power Ground
No Connect
22
GL
Low Side Gate
No Connect
23-26
27
NC
VIN
Input Voltage
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: CSD88584Q5DC
English Data Sheet: SLPS598
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com/legal/termsofsale.html) 或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器 (TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD88584Q5DC
CSD88584Q5DCT
ACTIVE
VSON-CLIP
VSON-CLIP
DMM
22
22
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
88584
88584
Samples
Samples
ACTIVE
DMM
RoHS-Exempt
& Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2023
Addendum-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
CSD88599Q5DCT
采用 5mm x 6mm SON 封装的 40A、60V、N 沟道同步降压 NexFET™ 功率 MOSFET Dual-Cool™ 电源块 | DMM | 22 | -55 to 150
TI
©2020 ICPDF网 联系我们和版权申明