CSD95372AQ5M [TI]
Synchronous Buck NexFET⢠Power Stage; 同步降压NexFETâ ?? ¢功率级
| 型号： | CSD95372AQ5M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Synchronous Buck NexFET⢠Power Stage |
| 文件： | 总24页 (文件大小：1138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD95372AQ5M
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SLPS416 –JUNE 2013
Synchronous Buck NexFET™ Power Stage
1
FEATURES
APPLICATIONS
23
•
60A Continuous Operating Current Capability
•
Multiphase Synchronous Buck Converter
•
92.4% System Efficiency at 30A
Ultra Low Power Loss of 3.3W at 30A
High Frequency Operation (up to 2 MHz)
High Density - SON 5x6-mm Footprint
Ultra Low Inductance Package
System Optimized PCB Footprint
3.3V and 5V PWM Signal Compatible
Diode Emulation Mode with FCCM
Analog Temperature Output
–
–
High Frequency Applications
High Current, Low Duty Cycle Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Point-of-Load DC-DC Converters
Memory and Graphic Cards
Desktop and Server VR11.x and VR12.x for
VCore Synchronous Buck Converters
ORDERING INFORMATION
Device
Package
Media
Qty
Ship
SON 5 × 6-mm
Plastic Package
13-Inch
Reel
Tape and
Reel
CSD95372AQ5M
2500
Input Voltages up to 16V
Three-State PWM Input
Integrated Bootstrap Switch
Optimized Dead Time for Shoot Through
Protection
•
•
RoHS Compliant – Lead Free Terminal Plating
Halogen Free
DESCRIPTION
The CSD95372AQ5M NexFET™ Power Stage is a highly optimized design for use in a high power, high density
Synchronous Buck converters. This product integrates the driver IC and NexFET technology to complete the
power stage switching function. The driver IC has a built-in selectable diode emulation function that enables
DCM operation to improve light load efficiency. This combination produces high current, high efficiency, and high
speed switching capability in a small 5x6mm outline package. It also integrates the temperature sensing
functionality to simplify system design and improve accuracy. In addition, the PCB footprint has been optimized
to help reduce design time and simplify the completion of the overall system design.
VIN
100
90
80
70
60
50
40
30
20
16
14
12
10
8
CSD95372A
VOUT
VCC
VDD = 5V
VIN = 12V
VOUT = 1.2V
LOUT = .22µH
fSW = 500kHz
TA = 25ºC
VCC
PWM1
+Is1
6
4
-Is2
VOUT
VOUT
SS
+NTC
-NTC
+Is2
2
RT
0
-Is2
0
10
20
30
40
50
60
PWM2
PGND
Output Current (A)
G001
Multi-Phase
Controller
CSD95372A
Figure 1. Application Diagram
Figure 2. Efficiency and Power Loss
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD95372AQ5M
SLPS416 –JUNE 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)
TA = 25°C (unless otherwise noted)
VALUE
UNIT
MIN
-0.3
-0.3
-7
MAX
25
VIN to PGND
V
V
VSW to PGND
25
VSW to PGND (<10ns)
VDD to PGND
27
V
–0.3
–0.3
–0.3
7
V
(2)
ENABLE, PWM, FCCM, TAO to PGND
BOOT to BOOT_R(2)
VDD + 0.3
VDD + 0.3
2000
500
V
V
Human Body Model (HBM)
V
ESD Rating
Charged Device Model (CDM)
V
Power Dissipation, PD
12
W
°C
°C
Operating Temperature Range, TJ
Storage Temperature Range, TSTG
-55
150
–55
150
(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.
(2) Should not exceed 7V
RECOMMENDED OPERATING CONDITIONS
TA = 25° (unless otherwise noted)
Parameter
Gate Drive Voltage, VDD
Conditions
MIN
MAX
5.5
16
UNIT
V
4.5
Input Supply Voltage, VIN
Output Voltage, VOUT
V
5.5
60
V
Continuous Output Current, IOUT
VIN = 12V, VDD = 5V, VOUT = 1.8V,
fSW = 500kHz, LOUT = 0.29µH(1)
A
(2)
Peak Output Current, IOUT-PK
90
A
Switching Frequency, fSW
On Time Duty Cycle
CBST = 0.1µF (min)
fSW = 1MHz
2000
85
kHz
%
Minimum PWM On Time
Operating Temperature
20
ns
°C
–40
125
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) System conditions as defined in Note 1. Peak Output Current is applied for tp = 50µs
THERMAL INFORMATION
TA = 25°C (unless otherwise noted)
PARAMETER
Thermal Resistance, Junction-to-Case (Top of package)(1)
Thermal Resistance, Junction-to-Board(2)
MIN
TYP
MAX UNIT
RθJC
RθJB
15 °C/W
2
°C/W
(1)
(2)
R
θJC is determined with the device mounted on a 1-inch² (6.45 -cm²), 2-oz (.071-mm thick) Cu pad on a 1.5-inch x 1.5-inch, 0.06-inch
(1.52-mm) thick FR4 board.
RθJB value based on hottest board temperature within 1mm of the package.
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ELECTRICAL CHARACTERISTICS
TA = 25°C, VDD = POR to 5.5V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
PLOSS
VIN = 12V, VDD = 5V, VOUT = 1.2V, IOUT = 30A,
fSW = 500kHz, LOUT = 0.22µH , TJ = 25°C
Power Loss(1)
Power Loss(2)
3.3
3.9
W
W
VIN = 12V, VDD = 5V, VOUT = 1.2V, IOUT = 30A,
fSW = 500kHz, LOUT = 0.22µH , TJ = 125°C
VIN
VIN Quiescent Current, IQ
VDD
ENABLE = 0, VDD = 5V
ENABLE = 0, PWM = 0
10
µA
Standby Supply Current, IDD
250
µA
ENABLE = 5V, PWM = 50% Duty cycle,
fSW = 500kHz
Operating Supply Current, IDD
23
mA
POWER-ON RESET AND UNDER VOLTAGE LOCKOUT
Power-On Reset, VDD Rising
UVLO, VDD Falling
3.9
V
V
3.4
Hysteresis
Startup Delay(3)
100
250
mV
µs
ENABLE = 5V
6
ENABLE
Logic Level High, VIH
Logic Level Low, VIL
Weak Low Down Impedance
Rising Propagation Delay, tPDH
Falling Propagation Delay, tPDL
FCCM
2.0
V
V
0.8
0.8
Scmitt Trigger Input
See Figure 15
100
3
kΩ
µs
ns
30
Logic Level High, VIH
Logic Level Low, VIL
Weak Pull-Down Current
THERMAL SHUTDOWN(2)
Start Threshold
2.0
V
V
Scmitt Trigger Input
See Figure 17 and Figure 18
5
µA
150
165
25
°C
°C
Temperature Hysteresis
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design
(3) POR to VSW Rising
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ELECTRICAL CHARACTERISTICS (continued)
TA = 25°C, VDD = POR to 5.5V (unless otherwise noted)
PARAMETER
PWM
CONDITIONS
MIN
TYP
MAX
UNIT
IPWMH
PWM = 5V
PWM = 0
500
-500
2.5
µA
µA
V
IPWML
PWM Logic Level High, VPWMH
PWM Logic Level Low, VPWML
PWM Three-State Open Voltage
PWM to VSW Propagation Delay, tPDLH and
2.3
0.7
2.7
1.1
0.9
V
1.5
V
CPWM = 10pF
50
ns
(4)
tPDHL
(4)
Three-State Shutdown Hold-off Time, t3HT
30
80
ns
ns
ns
ns
(4)
Three-State Shutdown Propagation Delay, t3SD
160
80
(4)
Three-State Recovery Propagation Delay, t3RD
50
(4)
Diode Emulation Minimum On Time, tDEM
150
BOOTSTRAP SWITCH
Forward Voltage, VFBOOT
Measured from VDD to VBOOT, IF = 10mA
VBOOT - VDD = 20V
200
360
1
mV
µA
(5)
Reverse Leakage, IRBOOT
0.15
ZERO CROSSING COMPARATOR
Diode Emulation Mode Enabled
VOUT = 1.8V, L = 150nH
LS FET Turn-off Current
0
0.8
A
THERMAL ANALOG OUTPUT TAO
Output Voltage at 25°C
0.56
0.60
8
0.64
V
Output Voltage Temperature Coefficient
mV/°C
(4) Specified by design
(5) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
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TYPICAL CHARACTERISTICS
TJ = 125°C, unless stated otherwise.
20
18
16
14
12
10
8
1.1
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
LOUT = 0.22µH
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
LOUT = 0.22µH
1
0.9
0.8
0.7
0.6
6
4
Typ
Max
2
0
4
12
20
28
36
44
52
60
−50
−25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (ºC)
G001
G001
Figure 3. Power Loss vs Output Current
Figure 4. Power Loss vs Temperature
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
400LFM
200LFM
100LFM
Min
Typ
Nat Conv
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
LOUT = 0.22µH
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
LOUT = 0.22µH
0
10
20
30
40
50
60
70
80
90
0
20
40
60
80
100
120
140
Ambient Temperature (ºC)
Board Temperature (ºC)
G001
G001
Figure 5. Safe Operating Area – PCB Horizontal Mount (1)
Figure 6. Typical Safe Operating Area (1)
1.5
19.1
15.3
11.5
7.6
1.12
1.1
4.6
3.9
3.1
2.3
1.5
0.8
0.0
−0.8
VIN = 12V
VDD = 5V
VOUT = 1.2V
LOUT = 0.22µH
IOUT = 60A
VDD = 5V
VOUT = 1.2V
LOUT = 0.22µH
fSW = 500kHz
IOUT = 60A
1.4
1.3
1.2
1.1
1
1.08
1.06
1.04
1.02
1
3.8
0.0
0.9
200
−3.8
2200
0.98
600
1000
1400
1800
3
5
7
9
11
13
15
17
Input Voltage (V)
Switching Frequency (kHz)
G001
G001
Figure 7. Normalized Power Loss vs Frequency
Figure 8. Normalized Power Loss vs Input Voltage
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TYPICAL CHARACTERISTICS (continued)
TJ = 125°C, unless stated otherwise.
2
38.4
30.7
23
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1
3.1
2.7
2.3
VIN = 12V
VDD = 5V
fSW = 500kHz
LOUT = 0.22µH
IOUT = 60A
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
IOUT = 60A
1.8
1.6
1.4
1.2
1
1.9
1.5
1.2
0.8
0.4
0
15.3
7.7
0
0.8
−7.7
0.99
−0.4
240
0
1
2
3
4
5
6
100
120
140
160
180
200
220
Output Voltage (V)
Output Inductance (nH)
G001
G001
Figure 9. Normalized Power Loss vs Output Voltage
Figure 10. Normalized Power Loss vs Output Inductance
100
VIN = 12V
VDD = 5V
90
VOUT = 1.2V
LOUT = 0.22µH
IOUT = 60A
80
70
60
50
40
30
20
10
0
200
600
1000
1400
1800
2200
Switching Frequency (kHz)
G000
Figure 11. Driver Current vs Frequency
1. The Typical CSD95372AQ5M System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness. See the Application
Information section for detailed explanation.
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PIN CONFIGURATION
NC
NC
1
2
3
4
5
12 PWM
11 TAO
ENABLE
NC
10 FCCM
9
8
BOOT
13
VDD
BOOT_R
PGND
VSW
6
7
VIN
Figure 12. Top View
PIN DESCRIPTION
PIN
NAME
DESCRIPTION
NO.
1, 2, 4 NC
No Connect, must leave floating
3
ENABLE
Enables device operation. If ENABLE = logic HIGH, turns on device. If ENABLE = logic LOW, the device is turned off
and both MOSFET gates are actively pulled low. An internal 100kΩ pull down resistor will pull the ENABLE pin LOW if
left floating.
5
6
7
8
9
VDD
Supply Voltage to Gate Driver and internal circuitry
VSW
Phase node connecting the HS MOSFET Source and LS MOSFET Drain - pin connection to the output inductor
Input Voltage Pin. Connect input capacitors close to this pin.
VIN
BOOT_R
BOOT
Return path for HS gate driver, connected to VSW internally
Bootstrap capacitor connection. Connect a minimum of 0.1µF 16V X7R, ceramic capacitor from BOOT to BOOT_R
pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootsrap diode is integrated.
10
11
FCCM
This pin enables the Diode Emulation function. When this pin is held LOW, Diode Emulation Mode is enabled for Sync
FET. When FCCM is HIGH, the device operated in Forced Continuous Conduction Mode. An internal 5µA currect
source will pull the FCCM pin to VDD if left floating.
TAO/
FAULT
Temperature amplifier output. Reports a voltage proportional to the die temperature. An ORing diode is integrated in
the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the IC's. Only
the highest temperature will be reported. TAO will be pulled up to 3V if Thermal Shutdown occurs. TAO should be
bypassed to PGND with a 1nF 16V X6R ceramic capacitor.
12
13
PWM
PGND
Pulse Width modulated 3-state input from external controller. Logic LOW sets Control FET gate low and Sync FET
gate high. Logic HIGH sets Control FET gate high and Sync FET gate low. Open or High Z sets both MOSFET gates
low if greater than the 3-State Shutdown Hold-off Time (t3HT
)
Power Ground
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ENABLE (3) FCCM (10)
VDD (5)
NC (1)
NC (2)
NC (4)
BOOT (9)
BOOT_R (8)
VIN (7)
−
+
POR
HG
SW
PWMH
PWML
PWMT
Gate Driver Logic
+
−
−
+
+
−
VSW (6)
Tri-State Logic
PWM (12)
3V LDO
+
−
ZX
LG
Fault Detection
GND
PGND (13)
−
+
+
−
Temperature Sense
Thermal Shutdown
TAO (11)
Figure 13. Functional Block Diagram
FUNCTIONAL DESCRIPTION
POWERING CSD95372AQ5M AND GATE DRIVERS
An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive
power for the MOSFETS. The gate driver IC is capable of supplying in excess of 4A peak current into the
MOSFET gates to achieve fast switching. A 1µF 10V X5R or higher ceramic capacitor is recommended to
bypass VDD pin to PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The
bootstrap supply to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor
between BOOT and BOOT_R pins. An optional RBOOT resistor can be used to slow down the turn on speed of
the Control FET and reduce voltage spikes on the VSW node. A typical 1Ω to 4.7Ω value is a compromise
between switching loss and VSW spike amplitude.
Undervoltage Lockout Protection (UVLO)
The VDD supply is monitored for UVLO conditions and both Control FET and Sync FET gates are held low until
adequate supply is available. An internal comparator evaluates the VDD voltage level and if VDD is greater than
the Power On Reset threshold (VPOR), the gate driver becomes active. If VDD is less than the UVLO threshold,
the gate driver is disabled and the internal MOSFET gates are actively driven low. At the rising edge of the VDD
voltage, both Control FET and Sync FET gates will be actively held low during VDD transitions between 1.0V to
VPOR. This region is referred to as the Gate Drive Latch Zone, seen in Figure 14. In addition, at the falling edge
of the VDD voltage, both Control FET and Sync FET gates are actively held low during the UVLO to 1.0V
transition.
The Power Stage CSD97372AQ5M device must be powered up and Enabled before the PWM signal is applied.
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VDD
VPOR
UVLO
1.0V
Gate Drive
Latch Zone
1.0V
T0487-01
Figure 14. UVLO Operation
ENABLE
The ENABLE pin is TTL compatible. The logic level thresholds are sustained under all VDD operating conditions
between VPOR to VDD. In addition, if this pin is left floating, a weak internal pull down resistor of 100kΩ will pull the
ENABLE pin below the logic level low threshold. The operational functions of this pin should follow the timing
diagram outlined in Figure 15. A logic level low will actively hold both Control FET and Sync FET gates low and
VDD pin should typically draw less than 5µA.
90%
tPDL
ENABLE
tPDH
10%
90%
VSW
10%
T0488-01
Figure 15. CSD97372AQ5M ENABLE Timing Diagram (VDD = PWM = 5V)
POWER UP SEQUENCING
If the ENABLE signal is used, it is necessary to ensure proper co-ordination with the ENABLE and soft-start
features of the external PWM controller in the system. If the CSD97372AQ5M was disabled through ENABLE
without sequencing with the PWM IC controller, the buck converter output will have no voltage or fall below
regulation set point voltage. As a result, the PWM controller IC delivers Max duty cycle on the PWM line. If the
Power Stage is re-enabled by driving the ENABLE pin high, there will be an extremely large input inrush current
when the output voltage builds back up again. The input inrush current might have undesirable consequences
such as inductor saturation, driving the input power supply into current limit or even catastrophic failure of the
CSD97372AQ5M device. Disabling the PWM controller is recommended when the CSD97372AQ5M is disabled.
The PWM controller should always be re-enabled by going through soft-start routine to control and minimize the
input inrush current and reduce current and voltage stress on all buck converter components. It is recommended
that the external PWM controller be disabled when CSD97372AQ5M is disabled or nonoperational because of
UVLO.
When ENABLE signal is toggled, there is an internal 3µs hold-off time before the driver will respond to PWM
events to ensure the analog sensing circuitry is properly powered and stable. This hold-off time should be
considered when designing the power-up sequencing of the controller IC and the Power Stage
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PWM
The input PWM pin incorporates a 3-State function. The Control FET and Sync FET gates are forced low if the
PWM pin is left floating for more than the 3-State Hold off time (t3HT). The 3-state mode can be entered by
actively driving the PWM input to the VT3 voltage or the PWM input can be made high impedance and internal
current sources will driver PWM to VT3. The PWM input can source up to IPWMH and sink down to IPWML current to
drive PWM to the VT3 coltage, but will consume no current when sitting at the VT3 voltage. Operation in and out
of 3-State mode should follow the timing diagram outlined in Figure 16. Both VPWML and VPWMH threshold levels
are set to accommodate both 3.3V and 5V logic controllers. During normal operation, the PWM signal should be
driven to logic levels Low and High with a maximum of 500Ω sink/source impedance respectively.
PWM 3-State Window
VPWMH
PWM
VPWML
t3RD
t3HT + t3SD
VOUT
VOUT
VSW
tPDLH
tPDHL
t3HT + t3SD
t3RD
T0489-01
Figure 16. PWM Timing Diagram
FCCM
The input FCCM pin enables the Power Stage device to operate in either continuou current conduction mode or
diode emulation mode. When FCCM is driven above its high threshold, the Power Stage will operate in
continuous conduction mode regardless of the polarity of the output inductor current. When FCCM is driven
below its low threshold, the Power Stage's internal zero-cross detection circuit is enabled. When the zero-cross
detection circuit is active, diode emulation mode will be enterered on the third consecutive PWM pulse in which a
zero-crossing event is detected. If FCCM is driven high after diode emulation mode has been enabled,
continuous conduction mode will begin after the next PWM event. See Figure 17 and Figure 18 for FCCM timing
TAO/FAULT (Thermal Analog Output/Protection Flag
During normal operation the output TAO pin is a highly accurate analog temperature measurement of the lead-
frame temperature of the Power Stage. Because the source junction of the Sync FET sits directly on the lead-
frame of the Power Stage, this output can be used as an accurate measurement of the junction temperature of
the Sync FET. The TAO pin should be bypassed to PGND using a 1nF X7R ceramic capacitor to ensure accurate
temperature measurement.
This Power Stage device has built-in over-temperature protection (described below) which is flagged by pulling
TAO to 3V. The TAO pin also includes a built in ORing function. When connecting TAO pins of more than one
device together, the TAO bus automatically reads the highest TAO voltage among all devices. This greatly
simplifies the temperature sense and fault reporting design for multi-phase applications, where a single line
TAO/FAULT bus can be used to tie the TAO pins of all phases together and the system can monitor the
temperature of the hottest component.
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Over Temperature
An overtemperature fault occurs when the dies temperature reaches Thermal Shutdown Temperature (see the
Electrical Characteristics). An over-temperature event is the only fault condition to which the Power Stage will
automatically react. When the over-temperature event is detected, the Power Stage will automatically turn off
both HS and LS MOSFETs and pull TAO to 3.3V. If the temperature falls below the over-temperature threshold
hysteresis band, the driver will again respond to PWM commands and the TAO pin will return to normal
operation. A weak pull down is used to pull TAO back from a fault event so there is a significant delay before the
TAO output will report the correct temperature.
Gate Drivers
This Power Stage has an internal high-performance gate driver IC that is trimmed to achieve minimum dead-time
for lowest possible switching loss and switch-node ringing reduction. To eliminate the possibility of shoot-through
at light load conditions, the dead-time is adjusted to a longer period when the inductor current is negative prior to
a PWM HIGH input.
PWM
Vin
VSW
Vout
FCCM (OFF#)
LO GATE
During Diode Emulation Mode (DEM) the Lo Gate signal is latched off by the
zero-cross comparator and reset by rising edge of PWM. If FCCM is pulled high
after Lo Gate has been latched off, normal CCM operation does not begin until
after the next PWM pulse.
Figure 17. FCCM Rising Timing Diagram
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PWM
Vin
VSW
Vout
FCCM (OFF#)
LO GATE
IL
Diode Emulation
Enabled
Zero-Cross<2>
Zero-Cross<1>
Zero-cross detection is enabled by FCCM low. Diode-Emulation Mode is entered on the third
consecutive PWM pulse in which a zero-crossing event is detected. If at any time no zero-cross
event is detected when FCCM is low, the zero-cross counter is reset and diode-emulation mode is
not enabled. If FCCM remains low, diode-emulation mode will be re-enabled on the third
consecutive PWM pulse in which a zero-cross event is detected.
Figure 18. FCCM Falling Timing Diagram
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APPLICATION INFORMATION
The Power Stage CSD95372AQ5M is a highly optimized design for synchronous buck applications using
NexFET devices with a 5V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield
the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards
a more systems centric environment. The high-performance gate driver IC integrated in the package helps
minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level
performance curves such as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict
the product performance in the actual application.
Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss
generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has
provided measured power loss performance curves. Figure 3 plots the power loss of the CSD95372AQ5M as a
function of load current. This curve is measured by configuring and running the CSD95372AQ5M as it would be
in the final application (see ). The measured power loss is the CSD95372AQ5M device power loss which
consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.
Power Loss = (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT
)
(1)
The power loss curve in Figure 3 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.
Safe Operating Curves (SOA)
The SOA curves in the CSD95372AQ5M datasheet give engineers guidance on the temperature boundaries
within an operating system by incorporating the thermal resistance and system power loss. Figure 5 and Figure 6
outline the temperature and airflow conditions required for a given load current. The area under the curve
dictates the safe operating area. All the curves are based on measurements made on a PCB design with
dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness.
Normalized Curves
The normalized curves in the CSD95372AQ5M data sheet give engineers guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).
Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the
following procedure will outline the steps engineers should take to predict product performance for any set of
system conditions.
Design Example
Operating Conditions: Output Current (lOUT) = 40A, Input Voltage (VIN ) = 7V, Output Voltage (VOUT) = 1.5V,
Switching Frequency (fSW) = 800kHz, Output Inductor (LOUT) = 0.2µH
Calculating Power Loss
•
•
•
•
•
•
Typical Power Loss at 40A = 6.5W (Figure 3)
Normalized Power Loss for switching frequency ≈ 1.08 (Figure 7)
Normalized Power Loss for input voltage ≈ 1.06 (Figure 8)
Normalized Power Loss for output voltage ≈ 1.06(Figure 9)
Normalized Power Loss for output inductor ≈ 1.01 (Figure 10)
Final calculated Power Loss = 6.5W × 1.08 × 1.06 × 1.06 × 1.01 ≈ 8.0W
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Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for switching frequency ≈ 3.2°C (Figure 7)
SOA adjustment for input voltage ≈ 2.4°C (Figure 8)
SOA adjustment for output voltage ≈ -0.8°C (Figure 9)
SOA adjustment for output inductor ≈ 0.5°C (Figure 10)
Final calculated SOA adjustment = 3.2 + 2.4 + 2.4 + 0.5 ≈ 8.5°C
Figure 19. Power Stage CSD95372AQ5M SOA
In the design example above, the estimated power loss of the CSD95372AQ5M would increase to 8.0W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 8.5°C. Figure 19
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 8.5°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
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RECOMMENDED SCHEMATIC OVERVIEW
There are several critical components that must be used in conjunction with this Power Stage device. Figure 20
shows a portion of a schematic with the critical components needed for proper operation.
•
•
•
•
•
•
C1: Bootstrap Capacitor
R1: Bootstrap Resistor
C4: Bypass Capacitor for TAO
C3: Bypass Capacitor for VDD
C5: Bypass Capacitor for VIN to Help with Ringing Reduction
C6: Bypass Capacitor for VIN
5V
R1
0
C1
0.1µF
C3
1µF
12V
TP4 TP3 TP2 TP1
5
3
U1
VDD
EN
C5
3300pF
C6
10µF
C7
10µF
C8
10µF
C9
10µF
C10
10µF
C11
10µF
PGND
EN
FCCM
PWM
10
12
11
7
6
FCCM
PWM
TAO/FAULT
VIN
PGND
TAO
VOUT
1
2
VSW
1
L1
2
C4
1000pF
C16
DNP
C12
100µF
C13
100µF
C14
100µF
C15
100µF
1
2
4
NC
NC
NC
R2
DNP
PGND
PGND
PGND
Figure 20. Recommended Schematic
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RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below
is a brief description on how to address each parameter.
Electrical Performance
The CSD95372AQ5M has the ability to switch at voltage rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.
•
The placement of the input capacitors relative to VIN and PGND pins of CSD95372AQ5M device should have
the highest priority during the component placement routine. It is critical to minimize these node lengths. As
such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see
Figure 21). The example in Figure 21 uses 1 x 3.3nF 0402 50V and 6 x 10µF 1206 25V ceramic capacitors
(TDK Part # C3216X7R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the
board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to
the Power Stage C5, C8 and C6, C19 should follow in order.
•
•
The bootstrap cap CBOOT 0.1µF 0603 16V ceramic capacitor should be closely connected between BOOT and
BOOT_R pins
The switching node of the output inductor should be placed relatively close to the Power Stage
CSD95372AQ5M VSW pins. Minimizing the VSW node length between these two components will reduce the
(1)
PCB conduction losses and actually reduce the switching noise level.
Thermal Performance
The CSD95372AQ5M has the ability to use the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
•
•
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in Figure 21 uses vias with a 10 mil drill hole
and a 26 mil capture pad.
•
Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 21. Recommended PCB Layout (Top Down View)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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Sensing Performance
The integrated temperature sensing technology built in the driver of the CSD95372AQ5M produces an analog
signal that is proportional to the temperature of the lead-fram of the device, which is almost identical to the
junction temperature of the Sync FET. To calculate the junction temperature based on the TAO voltage, use
Equation 2 below. TAO should be bypassed to PGND with a 1nF X7R ceramic capacitor for optimal performance.
The TAO pin has limited sinking current capability in order to enable several power stages that are wire OR-ed
together to report only the highest temperature (or fault condition if present). In order to ensure accurate
temperature reporting, the TAO nets should be routed on a quiet inner layer between ground planes where
possible. In addition, the TAO bypass capacitor should have a PGND pour on the layer directly beneath to ensure
proper decoupling. The TAO net should always be shielded from VSW and VIN whenever possible.
TJ[C°] = (TAO[mV] - 400[mV]) / 8[mV/°C]
(2)
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Application Schematic
5V
12V
12V
12V
12V
TPS53640
VDD
ENABLE
PGND
VIN
LOAD
VSP
PWM1
PGND
VSN
SKIP#-RAMP
CSD95372A
PWM
FCCM
TAO/FAULT
VSW
OCP-I
CSP1
CSN1
COMP
VREF
F-IMAX
5V
5V
PWM2
VDD
ENABLE
PGND
VIN
B-TMAX
O-USR
PGND
CSD95372A
PWM
FCCM
TAO/FAULT
VSW
CSP2
CSN2
ADDR
SLEW-MODE
TSEN
PWM3
5V
5V
VDD
ENABLE
PGND
VIN
PGND
CSP3
CSN3
CSD95372A
PWM
FCCM
TAO/FAULT
VSW
ISUM
IMON
PWM4
SCLK
ALERT#
SDIO
To/From
CPU
5V
5V
{
VR_RDY
VR_HOT#
PMB_CLK
PMB_ALERT#
PMB_DIO
ENABLE
CSP4
CSN4
VDD
ENABLE
PGND
VIN
12V
PGND
I2C or
PMBUS
V12
V5
V3R3
CSD95372A
{
PWM
FCCM
VSW
ENABLE
TAO/FAULT
VR_FAULT#
VR_FAULT#
18
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SLPS416 –JUNE 2013
MECHANICAL DATA
Exposed tie clip may vary
A
c2
E2
d2
E1
c1
L1
d1
K
b3
b2
b1
E
D2
b
e
a1
L
0.300 x 45°
d
MILLIMETERS
Nom
INCHES
Nom
DIM
Min
Max
1.500
0.050
0.320
Min
Max
0.059
0.002
0.013
A
a1
b
1.400
0.000
0.200
1.450
0.055
0.000
0.008
0.057
0.000
0.000
0.250
0.010
b1
b2
b3
c1
D2
d
2.750 TYP
0.250
0.108 TYP
0.010
0.200
0.320
0.008
0.013
0.250 TYP
0.200
0.010 TYP
0.008
0.150
5.300
0.200
0.350
1.900
5.900
4.900
3.200
0.250
5.500
0.300
0.450
2.100
6.100
5.100
3.400
0.006
0.209
0.008
0.014
0.075
0.232
0.193
0.126
0.010
0.217
0.012
0.018
0.083
0.240
0.201
0.134
5.400
0.213
0.250
0.010
d1
d2
E
0.400
0.016
2.000
0.079
6.000
0.236
E1
E2
e
5.000
0.197
3.300
0.130
0.500 TYP
0.350 TYP
0.500
0.020 TYP
0.014 TYP
0.020
K
L
0.400
0.210
0.00
0.600
0.410
—
0.016
0.008
0.00
0.024
0.016
—
L1
θ
0.310
0.012
—
—
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Recommended PCB Land Pattern
0.331(0.013)
0.370 (0.015)
1.000 (0.039)
0.410 (0.016)
0.550 (0.022)
0.300 (0.012)
2.800
(0.110)
6.300
(0.248)
5.300
(0.209)
5.639
(0.222)
0.500
(0.020)
0.300
(0.012)
R0.127 (R0.005)
3.400
(0.134)
5.900
(0.232)
Recommended Stencil Opening
0.350(0.014)
2.750
(0.108)
0.250
(0.010)
1. Dimensions are in mm (inches).
2. Stencil Thickness 100 µm
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
CSD95372AQ5M
ACTIVE
SON
DQP
12
2500 Pb-Free (RoHS CU NIPDAU
Exempt)
Level-2-260C-1 YEAR
-50 to 150
95372AM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD95372AQ5M
SON
DQP
12
2500
330.0
12.4
5.3
6.3
1.8
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DQP 12
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
CSD95372AQ5M
2500
Pack Materials-Page 2
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