CSD88599Q5DC [TI]
采用 5mm x 6mm SON 封装的 40A、60V、N 沟道同步降压 NexFET™ 功率 MOSFET Dual-Cool™ 电源块;
| 型号： | CSD88599Q5DC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 5mm x 6mm SON 封装的 40A、60V、N 沟道同步降压 NexFET™ 功率 MOSFET Dual-Cool™ 电源块 驱动 光电二极管 接口集成电路 |
| 文件： | 总25页 (文件大小：1003K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD88599Q5DC
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
CSD88599Q5DC 60V 半桥 NexFET™电源块
1 特性
3 说明
1
•
•
•
半桥电源块
CSD88599Q5DC 60V 电源块是用于高电流电机控制
应用的经优化设计，这些 应用包括手持无线园艺和电
动工具等。该器件利用 TI 的堆叠裸片技术，以最大限
度地减小寄生电感，同时在节省空间的热增强型
DualCool™5mm × 6mm 封装中提供完整的半桥。利
用外露的金属顶部，该电源块器件允许简单散热应用将
热量从封装顶部吸收并将其从 PCB 带走，从而在许多
电机控制应用所要求的较高电流下，实现出色的热 性
能。
高密度 5mm × 6mm SON 封装
低 RDS(ON)，可实现最小的传导损耗
–
电流为 30A 时，PLoss 为 3.0W
•
•
•
•
•
DualCool™热增强型封装
超低电感封装
符合 RoHS 标准
无卤素
无铅引脚镀层
底视图
俯视图
2 应用
GL
NC
GH
SH
•
•
•
用于无刷直流电机控制的三相桥
多达 12s 电池的电动工具
其他半桥和全桥拓扑
VIN
PGND
VSW
电源块原理图
VIN
GH
SH
器件信息
包装介质
器件
数量
封装
发货
VSW
CSD88599Q5DC 2500 13 英寸卷带
SON
5.00mm × 6.00mm
塑料封装
卷带封
装
CSD88599Q5DCT 250
7 英寸卷带
GL
PGND
Copyright © 2017, Texas Instruments Incorporated
典型电路
功率损耗与输出电流
VIN
6
VIN = 36 V
VDD = 10 V
D.C. = 50%
L = 480 mH
fSW = 20 kHz
TA = 25èC
5
4
3
2
1
0
VM
CSD88599
GH_A
Motor
GL_A
CSD88599
GH_B
DRV832X
Gate Driver
GL_B
CSD88599
GH_C
GL_C
0
5
10
15
20
25
RMS Phase Current (A)
30
35
40
D000
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS597
CSD88599Q5DC
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
www.ti.com.cn
目录
6.5 Normalized Power Loss Curves.............................. 13
1
2
3
4
5
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Absolute Maximum Ratings ...................................... 3
5.2 Recommended Operating Conditions....................... 3
5.3 Power Block Performance ........................................ 3
5.4 Thermal Information.................................................. 4
5.5 Electrical Characteristics........................................... 4
5.6 Typical Power Block Device Characteristics............. 6
5.7 Typical Power Block MOSFET Characteristics......... 7
Application and Implementation .......................... 9
6.1 Application Information.............................................. 9
6.2 Brushless DC Motor With Trapezoidal Control ....... 10
6.3 Power Loss Curves................................................. 12
6.4 Safe Operating Area (SOA) Curve.......................... 13
6.6 Design Example – Regulate Current to Maintain Safe
Operation ................................................................. 13
6.7 Design Example – Regulate Board and Case
Temperature to Maintain Safe Operation ................ 14
7
8
Layout ................................................................... 16
7.1 Layout Guidelines ................................................... 16
7.2 Layout Example ...................................................... 18
器件和文档支持...................................................... 19
8.1 接收文档更新通知 ................................................... 19
8.2 社区资源.................................................................. 19
8.3 商标......................................................................... 19
8.4 静电放电警告........................................................... 19
8.5 Glossary.................................................................. 19
机械、封装和可订购信息 ....................................... 20
9.1 Q5DC 封装尺寸....................................................... 20
9.2 焊盘图案建议........................................................... 21
9.3 模版建议.................................................................. 22
6
9
4 修订历史记录
Changes from Revision B (January 2018) to Revision C
Page
•
•
Corrected Figure 20 to show 40-A maximum....................................................................................................................... 13
Corrected Figure 21 to show 40-A maximum....................................................................................................................... 14
Changes from Revision A (May 2017) to Revision B
Page
•
更新了机械制图..................................................................................................................................................................... 20
Changes from Original (April 2017) to Revision A
Page
•
•
•
更新了典型电路制图 ............................................................................................................................................................... 1
Changed the copper thickness to 2-oz in Typical Power Block Device Characteristics conditions ....................................... 6
Changed the copper thickness to 2-oz in Safe Operating Area (SOA) Curve paragraph.................................................... 13
2
Copyright © 2017–2018, Texas Instruments Incorporated
CSD88599Q5DC
www.ti.com.cn
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
5 Specifications
5.1 Absolute Maximum Ratings(1)
TJ = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
–0.8
–0.3
–20
–20
MAX
60
UNIT
VIN to PGND
VSW to PGND
60
Voltage
V
GH to SH
20
GL to PGND
20
(2)
Pulsed current rating, IDM
400
12
A
Power dissipation, PD
W
High-side FET, ID = 95 A, L = 0.1 mH
Low-side FET, ID = 95 A, L = 0.1 mH
448
448
150
150
Avalanche energy, EAS
mJ
Operating junction temperature, TJ
Storage temperature, Tstg
–55
–55
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Single FET conduction, max RθJC = 1.1°C/W, pulse duration ≤ 100 μs, single pulse.
5.2 Recommended Operating Conditions
TJ = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX
16
UNIT
V
VDD
VIN
ƒSW
IOUT
TJ
Gate drive voltage
4.5
Input supply voltage(1)
Switching frequency
54
V
CBST = 0.1 µF (min)
5
50
kHz
A
RMS motor winding current
Operating temperature
40
125
°C
(1) Up to 42-V input use one capacitor per phase, MLCC 10 nF, 100 V, X7S, 0402, PN: C1005X7S2A103K050BB from VIN to GND return.
Between 42-V to 54-V input operation, add RC switch-node snubber as described in the Electrical Performance section of this data
sheet.
5.3 Power Block Performance
TJ = 25°C (unless otherwise noted)
PARAMETER
Power loss(1)
CONDITIONS
VIN = 36 V, VDD = 10 V,
IOUT = 30 A, ƒSW = 20 kHz,
TJ = 25°C, duty cycle = 50%,
L = 480 µH
MIN
TYP
MAX UNIT
PLOSS
3.0
W
VIN = 36 V, VDD = 10 V,
IOUT = 30 A, ƒSW = 20 kHz,
TJ = 125°C, duty cycle = 50%,
L = 480 µH
PLOSS
Power loss
3.4
W
(1) Measurement made with eight 10-µF 50-V ±10% X5R (TDK C3225X5R1H106K250AB or equivalent) ceramic capacitors placed across
VIN to PGND pins and using UCC27210DDAR 100-V, 4-A driver IC.
Copyright © 2017–2018, Texas Instruments Incorporated
3
CSD88599Q5DC
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
www.ti.com.cn
MAX UNIT
5.4 Thermal Information
TJ = 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP
Junction-to-ambient thermal resistance (min Cu)(1)
Junction-to-ambient thermal resistance (max Cu)(1)(2)
Junction-to-case thermal resistance (top of package)(1)
Junction-to-case thermal resistance (VIN pin)(1)
125
°C/W
50
RθJA
2.1
RθJC
(1)
°C/W
1.1
R
θJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
5.5 Electrical Characteristics
TJ = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 µA
VGS = 0 V, VDS = 48 V
VDS = 0 V, VGS = 20 V
VDS = VGS, IDS = 250 µA
VGS = 4.5 V, IDS = 30 A
VGS = 10 V, IDS = 30 A
VDS = 6 V, IDS = 30 A
60
V
µA
nA
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
1
100
2.5
3.3
2.1
IGSS
VGS(th)
1.4
2.0
2.5
1.7
130
RDS(on)
gfs
Drain-to-source on-resistance
Transconductance
mΩ
S
DYNAMIC CHARACTERISTICS
CISS
COSS
CRSS
RG
Input capacitance
3720
670
12
4840
870
16
pF
pF
pF
Ω
VGS = 0V, VDS = 30 V,
ƒ = 1 MHz
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
0.9
21
1.8
27
Qg
nC
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qg
43
56
VDS = 30 V,
IDS = 30 A
Qgd
Qgs
Qg(th)
QOSS
td(on)
tr
7.0
10.1
6.3
100
9
VDS = 30 V, VGS = 0 V
Turnon delay time
Rise time
20
VDS = 30 V, VGS = 10 V,
IDS = 30 A, RG = 0 Ω
td(off)
tf
Turnoff delay time
Fall time
23
3
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
IDS = 30 A, VGS = 0 V
0.8
172
36
1.0
V
Reverse recovery charge
Reverse recovery time
nC
ns
VDS = 30 V, IF = 30 A,
di/dt = 300 A/µs
4
Copyright © 2017–2018, Texas Instruments Incorporated
CSD88599Q5DC
www.ti.com.cn
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
Max RθJA = 125°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
Max RθJA = 50°C/W
when mounted on 1 in2
(6.45 cm2) of 2-oz
(0.071-mm) thick Cu.
Copyright © 2017–2018, Texas Instruments Incorporated
5
CSD88599Q5DC
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
www.ti.com.cn
5.6 Typical Power Block Device Characteristics
The typical power block system characteristic curves (Figure 1 through Figure 6) are based on measurements made on a
PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 2-oz copper thickness. See
Application and Implementation section for detailed explanation. TJ = 125°C, unless stated otherwise.
8
7
6
5
4
3
2
1
0
1.2
1.1
1
Typical
Max
0.9
0.8
0.7
0.6
0.5
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (èC)
D001
D002
VIN = 36 V
ƒSW = 20 kHz
VDD = 10 V
D.C. = 50%
VIN = 36 V
VDD = 10 V
D.C. = 50%
IOUT = 40 A
L = 480 µH
ƒSW = 20 kHz
L = 480 µH
Figure 1. Power Loss vs Output Current
Figure 2. Power Loss vs Temperature
Top Case Temperature (èC)
1.4
1.3
1.2
1.1
1
2.7
2.1
1.4
0.7
0.0
-0.7
-1.4
100
45
104
108
112
116
120
124
128
TX
40
35
30
25
20
15
10
5
0.9
0.8
0
100
104
108
112
116
120
124
128
5
10
15
20
25
30
35
40
45
50
Board Temperature (èC)
Switching Frequency (kHz)
D005
D006
VIN = 36 V
VDD = 10 V
D.C. = 50%
VIN = 36 V
L = 480 µH
VDD = 10 V
IOUT = 40 A
ƒSW = 20 kHz
L = 480 µH
D.C. = 50%
Figure 3. Typical Safe Operating Area
Figure 4. Normalized Power Loss vs Switching Frequency
1.075
1.05
1.025
1
0.5
1.2
1.15
1.1
1.4
1.0
0.7
0.3
0.0
-0.3
0.3
0.2
0.0
0.975
0.95
0.925
0.9
-0.2
-0.3
-0.5
-0.7
1.05
1
0.95
15
20
25
30
35
40
45
50
10
20
30
40
50
60
70
80
90
100
Input Voltage (V)
VDD = 10 V
L = 480 µH
Duty Cycle (%)
D007
D009
D.C. = 50%
ƒSW = 20 kHz
IOUT = 40 A
VIN = 36 V
ƒSW = 20 kHz
VDD = 10 V
L = 480 µH
Figure 5. Normalized Power Loss vs Input Voltage
Figure 6. Normalized Power Loss vs Duty Cycle
6
Copyright © 2017–2018, Texas Instruments Incorporated
CSD88599Q5DC
www.ti.com.cn
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
5.7 Typical Power Block MOSFET Characteristics
TJ = 25°C, unless stated otherwise.
450
400
350
300
250
200
150
100
50
200
180
160
140
120
100
80
60
40
VGS = 4.5 V
VGS = 8 V
VGS = 10 V
20
0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VDS - Drain-to-Source Voltage (V)
1
1E-5
0.0001
0.001
Duration (s)
Max RθJA = 125°C/W
0.01
0.1
1
D010
Figure 8. MOSFET Saturation Characteristics
Figure 7. Single Pulse Current vs Pulse Duration
10
9
8
7
6
5
4
3
2
1
0
100
10
TC = 125°C
TC = 25°C
TC = -55°C
1
0.1
0.01
0.001
0
5
10
15
20
25
30
35
40
45
50
0
0.5
1
1.5
2
2.5
3
3.5
Qg - Gate Charge (nC)
VGS - Gate-to-Source Voltage (V)
D012
D014
VDS = 5 V
ID = 30 A
VDS = 30 V
Figure 9. MOSFET Transfer Characteristics
Figure 10. MOSFET Gate Charge
10000
1000
100
10
2.55
2.35
2.15
1.95
1.75
1.55
1.35
1.15
0.95
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
0
10
20
30
40
50
60
-75 -50 -25
0
25
50
75 100 125 150 175
VDS - Drain-to-Source Voltage (V)
TC - Case Temperature (°C)
D016
D018
ID = 250 µA
Figure 11. MOSFET Capacitance
Figure 12. Threshold Voltage vs Temperature
Copyright © 2017–2018, Texas Instruments Incorporated
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CSD88599Q5DC
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
www.ti.com.cn
Typical Power Block MOSFET Characteristics (continued)
TJ = 25°C, unless stated otherwise.
10
9
8
7
6
5
4
3
2
1
0
2
1.8
1.6
1.4
1.2
1
TC = 25°C
TC = 125°C
VGS = 4.5 V
VGS = 10 V
0.8
0.6
0.4
0
2
4
6
8
10
12
14
16
18
20
-75 -50 -25
0
25
50
75 100 125 150 175
VGS - Gate-to-Source Voltage (V)
TC - Case Temperature (°C)
D022
D020
ID = 30 A
VDS = 30 V
ID = 30 A
Figure 14. MOSFET Normalized RDS(on) vs Temperature
Figure 13. MOSFET RDS(on) vs VGS
100
10
1000
TC = 25°C
TC = 125°C
TC = 25è C
TC = 125è C
1
100
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
0.01
0.1
1
VSD - Source-to-Drain Voltage (V)
TAV - Time in Avalanche (ms)
D024
D026
Figure 15. MOSFET Body Diode Forward Voltage
Figure 16. MOSFET Single Pulse Unclamped Inductive
Switching
8
Copyright © 2017–2018, Texas Instruments Incorporated
CSD88599Q5DC
www.ti.com.cn
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
6 Application and Implementation
NOTE
Information in the following Application section is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI customers are
responsible for determining suitability of components selection for their designs.
Customers should validate and test their design implementation to confirm system
functionality.
6.1 Application Information
Historically, battery powered tools have favored brushed DC configurations to spin their primary motors, but more
recently, the advantages offered by brushless DC operation (BLDC) operation have brought about the advent of
popular designs that favor the latter. Those advantages include, but are not limited to higher efficiency and
therefore longer battery life, superior reliability, greater peak torque capability, and smooth operation over a wider
range of speeds. However, BLDC designs put increased demand for higher power density and current handling
capabilities on the power stage responsible for driving the motor.
The CSD88599Q5DC is part of TI’s power block product family and is a highly optimized product designed
explicitly for the purpose driving higher current DC motors in power and gardening tools. It incorporates TI’s
latest generation silicon which has been optimized for low resistance to minimize conduction losses and offer
excellent thermal performance. The power block utilizes TI’s stacked die technology to offer one complete half
bridge vertically integrated into a single 5-mm × 6-mm package with a DualCool exposed metal case. This
feature allows the designer to apply a heatsink to the top of the package and pull heat away from the PCB, thus
maximizing the power density while reducing the power stage footprint by up to 50%.
Copyright © 2017–2018, Texas Instruments Incorporated
9
CSD88599Q5DC
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
www.ti.com.cn
6.2 Brushless DC Motor With Trapezoidal Control
The trapezoidal commutation control is simple and has fewer switching losses compared to sinusoidal control.
Vin
Vin
Vin
PB1
Vin
PB2
PB3
PWM1
PWM2
PWM3
PWM4
GH1
DRV8323RX
SH1
GL1
GH2
SH2
GL2
GH3
SH3
Q3
Q2
Q1
GH2
SH2
GH3
SH3
GH1
SH1
Three Phase
Gate Driver
Vsw1
Vsw3
Vsw2
SPEED SET
U
PWM5
PWM6
VCS
Hall
Sensors
TORQUE SET
GL3
Q5
N
S
GL2
GL1
A
B
C
Q4
Q6
GL3
PGND
PGND
PGND
V
W
SPA
SPB
SPC
SPA
SPB
SPC
A
Rcs1
Rcs2
Rcs3
B
C
0
0
0
0
Hall
Inputs
Copyright © 2017, Texas Instruments Incorporated
Figure 17. Functional Block Diagram
The block diagram shown in Figure 17 offers a simple instruction of what is required to drive a BLDC motor: one
microcontroller, one three-phase driver IC, three power blocks (historically six power MOSFETs) and three Hall
effect sensors. The microcontroller responsible for block commutation must always know the rotor orientation or
its position relative to the stator coils. This is easy achieved with a brushed DC motor due to the fixed geometry
and position of the rotor windings, shaft and commutator.
A three-phase BLDC motor requires three Hall effect sensors or a rotary encoder to detect the rotor position in
relation to stator armature windings. With input from these three Hall effect sensors output signals, the
microcontroller can determine the proper commutation sequence. The three Hall sensors named A, B, and C are
mounted on the stator core at 120° intervals and the stator phase windings are implemented in a star
configuration. For every 60° of motor rotation, one Hall sensor changes its state. Based on the Hall sensors'
output code, at the end of each block commutation interval the ampere conductors are commutated to the next
position. There are 6 steps required to complete a full electrical cycle. The number of block commutation cycles
to complete a full mechanical rotation is determined by the number of rotor pole pairs.
10
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www.ti.com.cn
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
Brushless DC Motor With Trapezoidal Control (continued)
H
c
a
o
l
d
l
e
1
0 1
1
0
0
0 0 1
0
1 1
1
1
0
0 1 0
i _ U
0
i _ V
0
i _ W
0
Figure 18. Winding Current Waveforms on a BLDC Motor
Figure 18 above shows the three phase motor winding currents i_U, i_V, and i_W when running at 100% duty
cycle.
Trapezoidal commutation control offers the following advantages:
•
•
•
Only two windings in series carry the phase winding current at any time while the third winding is open.
Only one current sensor is necessary for all three windings U, V, and W.
The position of the current sensor allows the use of low-cost shunt resistors.
However, trapezoidal commutation control has the disadvantage of commutation torque ripple. The current sense
on a three-phase inverter can be configured to use a single-shunt or three different sense resistors. For cost
sensitive applications targeting sensorless control, the three Hall effect sensors can be replaced with BEMF
voltage feedback dividers.
To obtain faster motor rotations and higher revolutions per minute (RPM), shorter periods and higher VIN voltage
are necessary. Contrarily, to reduce the rotational speed of the motor, it is necessary to lower the RMS voltage
applied across stator windings. This can easily be easily achieved by modulating the duty cycle, while maintain a
constant switching frequency. Frequency for the three-phase inverter chosen is usually low between 10 kHz to
50 kHz to reduce winding losses and to avoid audible noise.
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6.3 Power Loss Curves
CSD88599Q5DC was designed to operate up to 10-cell Li-Ion battery voltage applications ranging from 30 V to
42 V, typical 36 V. For 11 and 12s, input voltages between 42 V to 54 V, RC snubbers are required for each
switch-node U, V, and W. To reduce ringing, refer to the Electrical Performance section. In an effort to simplify
the design process, Texas Instruments has provided measured power loss performance curves over a variety of
typical conditions.
Figure 1 plots the CSD88599Q5DC power loss as a function of load current. The measured power loss includes
both input conversion loss and gate drive loss.
Equation 1 is used to generate the power loss curve:
Power loss (W) = (VIN × IIN_SHUNT) + (VDD × IDD_SHUNT) – (VSW_AVG × IOUT
)
(1)
The power loss measurements were made on the circuit shown in Figure 19. Power block devices for legs U and
V, PB1 and PB2 were disabled by shorting the CSD88599Q5DC high-side and low-side FETs' gate-to-source
terminals. Current shunt Iin_SHUNT provides input current and Idd_SHUNT provides driver supply current
measurements. The winding current is measured from the DC load. An averaging circuit provides switch node W
equivalent RMS voltage.
Iin_SHUNT
Vin
Vin
PB1
Vin
PB2
PB3
Idd_SHUNT
Cin2
Cin1
Vdd
Vdd
GH2
SH2
0
0
GH3
SH3
GH1
SH1
0
0
W
HI
Vsw3
Vsw1
U
V
Vsw2
Vin
GATE
DRIVER
Lout
DCR
U1A
1
2
GL2
LI
GL1
GL3
Iout
LOAD
PGND
PGND
PGND
0
0
0
0
0
0
0
0
0
AVERAGE
SWITCH NODE
AVERAGING
CIRCUIT
PWM
Vsw_AVG
Copyright © 2017, Texas Instruments Incorporated
Figure 19. Power Loss Test Circuit
The RMS current on the CSD88599Q5DC device depends on the motor winding current. For trapezoidal control,
the MOSFET RMS current is calculated using Equation 2.
IRMS = IOUT × √2
(2)
Taking into consideration system tolerances with the current measurement scheme, the inverter design needs to
withstand a 20% overload current.
Table 1. RMS and Overload Current Calculations
Winding RMS Current (A)
CSD88599Q5DC IRMS (A)
Overload 20% × IRMS (A)
20
30
40
28
42
56
34
51
68
12
Copyright © 2017–2018, Texas Instruments Incorporated
CSD88599Q5DC
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ZHCSG79C –APRIL 2017–REVISED APRIL 2018
6.4 Safe Operating Area (SOA) Curve
The SOA curve in Figure 3 provides guidance on the temperature boundaries within an operating system by
incorporating the thermal resistance and system power loss. This curve outlines the board and case
temperatures required for a given load current. The area under the curve dictates the safe operating area. This
curve is based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H)
and 6 copper layers of 2-oz copper thickness.
6.5 Normalized Power Loss Curves
The normalized curves in the CSD88599Q5DC data sheet provide guidance on the power loss and SOA
adjustments based on application specific needs. These curves show how the power loss and SOA temperature
boundaries will adjust for different operation conditions. The primary Y-axis is the normalized change in power
loss while the secondary Y-axis is the change in system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the typical power loss. The change in SOA temperature is
subtracted from the SOA curve.
6.6 Design Example – Regulate Current to Maintain Safe Operation
If the case and board temperature of the power block are known, the SOA can be used to determine the
maximum allowed current that will maintain operation within the safe operating area of the device. The following
procedure outlines how to determine the RMS current limit while maintaining operation within the confines of the
SOA, assuming the temperatures of the top of the package and PCB directly underneath the part are known.
1. Start at the maximum current of the device on the Y-axis and draw a line from this point at the known top
case temperature to the known PCB temperature.
2. Observe where this point intersects the TX line.
3. At this intersection with the TX line, draw vertical line until you hit the SOA current limit. This intercept is the
maximum allowed current at the corresponding power block PCB and case temperatures.
In the example below, we show how to achieve this for the temperatures TC = 124°C and TB = 120°C. First we
draw from 40 A on the Y-axis at 124°C to 120°C on the X-axis. Then, we draw a line up from where this line
crosses the TX line to see that this line intercepts the SOA at 34 A. Thus we can assume if we are measuring a
PCB temperature of 124°C, and a top case temperature of 120°C, the power block can handle 34-A RMS, at the
normalized conditions. At conditions that differ from those in Figure 1, the user may be required to make an SOA
temperature adjustment on the TX line, as shown in the next section.
Figure 20. Regulating Current to Maintain Safe Operation
Copyright © 2017–2018, Texas Instruments Incorporated
13
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www.ti.com.cn
6.7 Design Example – Regulate Board and Case Temperature to Maintain Safe Operation
In the previous example we showed how given the PCB and case temperature, the current of the power block
could be limited to ensure operation within the SOA. Conversely, if the current and other application conditions
are known, one can determine from the SOA what board or case temperature the user will need to limit their
design to. The user can estimate product loss and SOA boundaries by arithmetic means (see Operating
Conditions section). Though the power loss and SOA curves in this data sheet are taken for a specific set of test
conditions, the following procedure outlines the steps the user should take to predict product performance for any
set of system conditions.
6.7.1 Operating Conditions
•
•
•
•
Winding output current (IOUT) = 30 A
Input voltage (VIN) = 42 V
Switching frequency (FSW) = 40 kHz
Duty cycle (D.C.) = 95%
6.7.2 Calculating Power Loss
•
•
•
•
•
Power loss at 30 A ≈ 3.4 W (Figure 1)
Normalized power loss for switching frequency ≈ 1.19 (Figure 4)
Normalized power loss for input voltage ≈ 1.03 (Figure 5)
Normalized power loss for duty cycle ≈ 1.12 (Figure 6)
Final calculated power loss = 3.4 W × 1.19 × 1.03 × 1.12 ≈ 4.7 W
6.7.3 Calculating SOA Adjustments
•
•
•
•
SOA adjustment for switching frequency ≈ 1.3°C (Figure 4)
SOA adjustment for input voltage ≈ 0.1°C (Figure 5)
SOA adjustment for duty cycle ≈ 0.7°C (Figure 6)
Final calculated SOA adjustment = 1.3 + 0.1 + 0.7 ≈ 2.1°C
In the Design Example – Regulate Current to Maintain Safe Operation section above, the estimated power loss
of the CSD88599Q5DC would increase to 4.7 W. In addition, the maximum allowable board temperature would
have to increase by 2.1°C. In Figure 21, the SOA graph was adjusted accordingly.
1. Start by drawing a horizontal line from the application current (30 A) to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the TX line.
3. Adjust the intersection point by subtracting the temperature adjustment value.
In this design example, the SOA board/ambient temperature adjustment yields a decrease of allowed junction
temperature of 2.1°C from 122.2°C to 120.1°C. Now it is known that the intersection of the case and PCB
temperatures on the TX line must stay below this point. For instance, if the power block case is observed
operating at 124°C, the PCB temperature must in turn be kept under 118°C to maintain this crossover point.
14
Copyright © 2017–2018, Texas Instruments Incorporated
CSD88599Q5DC
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ZHCSG79C –APRIL 2017–REVISED APRIL 2018
Design Example – Regulate Board and Case Temperature to Maintain Safe
Operation (continued)
Figure 21. Regulate Temperature to Maintain Safe Operation
Copyright © 2017–2018, Texas Instruments Incorporated
15
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www.ti.com.cn
7 Layout
The two key system-level parameters that can be optimized with proper PCB design are electrical and thermal
performance. A proper PCB layout will yield maximum performance in both areas. Below are some tips for how
to address each.
7.1 Layout Guidelines
7.1.1 Electrical Performance
The CSD88599Q5DC power block has the ability to switch at voltage rates greater than 1 kV/µs. Special care
must be then taken with the PCB layout design and placement of the input capacitors; high-current, high dI/dT
switching path; current shunt resistors; and GND return planes. As with any high-power inverter operated in hard
switching mode, there will be voltage ringing present on the switch nodes U, V, and W. Switch-node ringing
appears mainly at the HS FET turnon commutation with positive winding current direction. The U, V, and W
phase connections to the BLDC motor can be usually excluded from the ringing behavior since they are
subjected to high-peak currents but low dI/dT slew-rates. However, a compact PCB design with short and low-
parasitic loop inductances is critical to achieve low ringing and compliance with EMI specifications.
For safe and reliable operation of the three-phase inverter, motor phase currents have to be accurately
monitored and reported to the system microcontroller. One current sensor needs to be connected on each motor
phase winding U, V, and W. This sensing method is best for current sensing as it provides good accuracy over a
wide range of duty cycles, motor torque, and winding currents. Using current sensors is recommended because it
is less intrusive to the VIN and GND connections.
V i n
V i n
V i n
PB1
PB3
PB2
C 4
C 5
C 6
G H 1
S H 1
G H 2
S H 2
G H 3
S H 3
0
0
0
U
W
V
V s w
V s w
V s w
V in
C s1
C s3
C s2
G L 3
G L 1
G L 2
P G N D
P G N D
P G N D
R cs
G N D
0
R s1
R s2
R s3
0
0
0
0
Copyright © 2017, Texas Instruments Incorporated
Figure 22. Recommended Ringing Reduction Components
However, for cost sensitive applications, current sensors are generally replaced with current sense resistors.
•
•
For designs using the 60-V three-phase smart gate driver DRV8320SRHBR, only one current sense resistor
RCS can be placed between common source terminals for all three power block devices CSD88599Q5DC to
PGND as depicted in Figure 22 above.
For designs using the 60-V three-phase gate driver DRV8323RSRGZT, three current sense resistors RCS1
,
RCS2, and RCS3 can be used between each CSD88599Q5DC source terminals to GND. The three-phase
driver IC should be placed as close as possible to the power block gate GL and GH terminals.
16
Copyright © 2017–2018, Texas Instruments Incorporated
CSD88599Q5DC
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ZHCSG79C –APRIL 2017–REVISED APRIL 2018
Layout Guidelines (continued)
Breaking the high-current flow path from the source terminals of the power block to GND by introducing the RCS
current shunt resistors introduces parasitic PCB inductance. In the event the switch node waveforms exhibits
peak ringing that reaches undesirable levels, the ringing can be reduced by using the following ringing reduction
components:
•
The use of a high-side gate resistor in series with the GH pin is one effective way to reduce peak ringing. The
recommended HS FET gate resistor value will range between 4.7 Ω to 10 Ω depending on the driver IC
output characteristics used in conjunction with the power block device. The low-side FET gate pin GL should
connect directly to the driver IC output to avoid any parasitic cdV/dT turnon effect.
•
•
Low-inductance MLCC caps C4, C5, and C6 can be used across each power block device from VIN to the
source terminal PGND. MLCC 10 nF, 100 V, ±10%, X7S, 0402, PN: C1005X7S2A103K050BB are
recommended.
Ringing can be reduced via the implementation of RC snubbers from each switch node U, V, and W to GND.
Recommended snubber component values are as follows:
–
–
Snubber resistors Rs1, Rs2, Rs3: 2.21 Ω, 1%, 0.125 W, 0805, PN: CRCW08052R21FKEA
Snubber caps Cs1, Cs2, and Cs3: MLCC 4.7 nF, 100 V, X7S, 0402, PN: C1005X7S2A472M050BB
With a switching frequency of 20 kHz on the three-phase inverter, the power dissipation on the RC snubber
resistor is 80 mW per channel. As a result, 0805 package size for resistors Rs1, Rs2, and Rs3 is sufficient.
7.1.2 Thermal Considerations
The CSD88599Q5DC power block device has the ability to utilize the PCB copper planes as the primary thermal
path. As such, the use of thermal vias included in the footprint is an effective way to pull away heat from the
device and into the system board. Concerns regarding solder voids and manufacturability issues can be
addressed through the use of three basic tactics to minimize the amount of solder attach that will wick down the
via barrel.
•
•
Intentionally space out the vias from one another to avoid a cluster of holes in a given area.
Use the smallest drill size allowed by the design. The example in Figure 23 uses vias with a 10-mil drill hole
and a 16-mil solder pad.
•
Tent the opposite side of the via with solder-mask. Ultimately the number and drill size of the thermal vias
should align with the end user’s PCB design rules and manufacturing capabilities.
To take advantage of the DualCool thermally enhanced package, an external heatsink can be applied on top of
the power block devices. For low EMI, the heatsink is usually connected to GND through the mounting screws to
the PCB. Gap pad insulators with good thermal conductivity should be used between the top of the package and
the heatsink. The Bergquist Sil-Pad 980 is recommended which provides excellent thermal impedance of
1.07°C/W @ 50 psi.
Copyright © 2017–2018, Texas Instruments Incorporated
17
CSD88599Q5DC
ZHCSG79C –APRIL 2017–REVISED APRIL 2018
www.ti.com.cn
7.2 Layout Example
Figure 23. Top Layer
Figure 24. Bottom Layer
The placement of the input capacitors C4, C5, and C6 relative to VIN and PGND pins of CSD88599Q5DC device
should have the highest priority during the component placement routine. It is critical to minimize the VIN to GND
parasitic loop inductance. A shunt resistor R21 is used between all three U4, U5, and U6 power block source
terminals to the input supply GND return pin.
Input RMS current filtering is achieved via two bulk caps C17 and C18. Based on the RMS current ratings, the
recommended part number for input bulk is CAP AL, 330 µF, 63 V, ±20%, PN: EMVA630ADA331MKG5S.
18
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CSD88599Q5DC
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ZHCSG79C –APRIL 2017–REVISED APRIL 2018
8 器件和文档支持
8.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
8.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
8.3 商标
NexFET, DualCool, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
9.1 Q5DC 封装尺寸
A
5.1
4.9
B
PIN 1 INDEX AREA
6.1
5.9
3.329 0.1
EXPOSED
HEAT SLUG
(CONNECTED TO PGND)
(0.701)
2X (0.35)
2.284 0.1
(1.486)
C
1.05 MAX
SEATING PLANE
0.08 C
0.05
0.00
3.3 0.1
4X (1.9)
2X (2)
4X (0.25)
2X (0.3)
0.48
0.38
4X
(0.2) TYP
24
11
25
12
4X (0.175)
EXPOSED
THERMAL
PAD
2X
PKG
27
5
5.4 0.1
1
22
20X 0.5
0.3
0.2
23
22X
26
SYMM
PIN 1 ID
(OPTIONAL)
0.1
C A
C
B
0.55
0.45
0.05
22X
4222731/A 02/2016
•
•
•
所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
本图如有变更，恕不另行通知。
必须在印刷电路板上焊接封装散热焊盘，以获得良好的散热和机械性能。
20
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CSD88599Q5DC
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ZHCSG79C –APRIL 2017–REVISED APRIL 2018
表 2. 引脚配置表
位置
1
引脚名称
GH
说明
高侧栅极
高侧栅极回路
开关节点
电源接地
无连接
2
SH
3-11
12-20
21
VSW
PGND
NC
22
GL
低侧栅极
无连接
23-26
27
NC
输入电压
输入电压间
9.2 焊盘图案建议
(3.3)
4X (2.115)
22X (0.7)
SYMM
23
26
1
22
22X (0.25)
4X
(3.013)
20X (0.5)
SYMM
27
(5.4)
6X
(1.32)
2X
(1.13)
(
0.2) VIA
TYP
11
12
(R0.05) TYP
24
25
6X (1.4)
(0.3) TYP
4X (0.375)
4X (0.43)
(4.7)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
•
•
•
所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
此封装设计用于焊接到电路板的散热焊盘上。有关更多信息，请参阅《QFN/SON PCB 连接》(SLUA271)。
根据应用决定是否选用过孔，详情请参见器件数据表。如果实现了部分或全部过孔，则会显示建议的过孔位
置。
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www.ti.com.cn
9.3 模版建议
SYMM
22X (0.7)
4X (2.115)
8X (1.41)
METAL
TYP
26
23
27
1
22
22X (0.25)
8X
(1.12)
4X
(3.013)
20X (0.5)
SYMM
(0.66)
TYP
(R0.05) TYP
(1.32)
TYP
12
11
(0.81) TYP
24
25
4X (0.375)
(0.3) TYP
4X (0.43)
(4.7)
•
•
所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
具有漏斗形壁和圆角的激光切割孔可提供更佳的锡膏脱离。IPC-7525 可能提供替代设计建议。
如需了解针对 PCB 设计的建议电路布局，请参阅《通过 PCB 布局技巧来减少振铃》(SLPA005)。
22
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD88599Q5DC
CSD88599Q5DCT
ACTIVE
VSON-CLIP
VSON-CLIP
DMM
22
22
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
88599
88599
ACTIVE
DMM
RoHS-Exempt
& Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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Addendum-Page 2
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TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
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