CSD95472Q5MCT [TI]
20V 60A SON 5 x 6mm DualCool 同步降压 NexFET™ 功率级 | DMC | 12 | -55 to 150;
| 型号： | CSD95472Q5MCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20V 60A SON 5 x 6mm DualCool 同步降压 NexFET™ 功率级 | DMC | 12 | -55 to 150 |
| 文件： | 总11页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD95472Q5MC
ZHCSEM4 –FEBRUARY 2016
CSD95472Q5MC 同步降压 NexFET™智能功率级
1 特性
2 应用
1
•
•
•
•
•
•
•
•
60A 持续运行电流能力
•
多相位同步降压转换器
1.2V/30A 下系统效率达 94.4%
30A 电流下功率损耗低至 2.3W
高频工作（高达 1.25MHz）
支持强制连续传导模式 (FCCM) 的二极管仿真模式
温度补偿双向电流感测
–
–
高频 应用
高电流、低占空比 应用
•
•
负载点 (POL) 直流 - 直流转换器
内存和图形卡
3 说明
模拟温度输出（0°C 时 600mV）
故障监控
CSD95472Q5MC NexFET™智能功率级的设计针对高
功率、高密度同步降压转换器中的使用进行了高度优
化。这个产品集成了驱动器集成电路 (IC) 和功率金属
氧化物半导体场效应晶体管 (MOSFET) 来完善功率级
开关功能。这个组合在小型 5mm x 6mm 外形尺寸封
装中产生出高电流、高效和高速切换功能。它还集成了
准确电流感测和温度感测功能，以简化系统设计并提高
准确度。此外，已对 PCB 封装进行了优化以帮助减少
设计时间并简化总体系统设计的完成。
–
高端短路、过流和过热保护
•
•
•
•
•
•
•
•
•
•
3.3V 和 5V 脉宽调制 (PWM) 信号兼容
三态 PWM 输入
集成型自举二极管
优化了击穿保护死区时间
高密度小外形尺寸无引线 (SON) 5mm x 6mm 封装
超低电感封装
系统优化的 PCB 封装
DualCool™封装
器件信息(1)
符合 RoHS 标准 - 无铅引脚镀层
无卤素
器件
包装介质
13 英寸卷带
7 英寸卷带
数量
2500
250
封装
运输
CSD95472Q5MC
CSD95472Q5MCT
SON 5 × 6mm
DualCool 封装
卷带封
装
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
间隔
应用图表
典型功率级效率与功率损耗
VIN
100
90
80
70
60
50
40
30
14
12
10
8
CSD95472
VOUT
VCC
VDD = 5 V
VIN = 12 V
VOUT = 1.2 V
LOUT = 0.225 mH
fSW = 500 kHz
TA = 25èC
VCC
6
PWM1
+Is1
4
-Is2
VOUT
VOUT
SS
2
TSEN
+Is2
-Is2
0
60
RT
0
10
20
30
40
50
Output Current (A)
D000
PWM2
PGND
Multiphase
Controller
CSD95472
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS599
CSD95472Q5MC
ZHCSEM4 –FEBRUARY 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
7
8
Application Schematic .......................................... 5
器件和文档支持........................................................ 6
8.1 社区资源.................................................................... 6
8.2 商标........................................................................... 6
8.3 静电放电警告............................................................. 6
8.4 Glossary.................................................................... 6
机械、封装和可订购信息 ......................................... 7
9.1 机械制图.................................................................... 7
9.2 建议印刷电路板 (PCB) 焊盘图案............................... 8
9.3 建议模板开口............................................................. 8
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
9
4 修订历史记录
日期
修订版本
注释
2 月 2016
*
最初发布。
2
Copyright © 2016, Texas Instruments Incorporated
CSD95472Q5MC
www.ti.com.cn
ZHCSEM4 –FEBRUARY 2016
5 Pin Configuration and Functions
Top View
IOUT
REFIN
ENABLE
PGND
1
2
3
4
5
12 PWM
11 TAO/FAULT
10 FCCM
9
8
BOOT
13
VDD
BOOT_R
PGND
VSW
6
7
VIN
Pin Functions
PIN
NUMBER
DESCRIPTION
NAME
IOUT
REFIN
1
2
Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.
External reference voltage input for current sensing amplifier.
Enables device operation. If ENABLE = logic HIGH, turns on device. If ENABLE = logic LOW, the device is turned
3
ENABLE off and both MOSFET gates are actively pulled low. An internal 100 kΩ pulldown resistor will pull the ENABLE pin
LOW if left floating.
4
5
6
7
8
PGND
VDD
VSW
VIN
Power ground, connected directly to pin 13.
Supply voltage to gate driver and internal circuitry.
Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor.
Input voltage pin. Connect input capacitors close to this pin.
BOOT_R Return path for HS gate driver, connected to VSW internally.
Bootstrap capacitor connection. Connect a minimum of 0.1 µF 16 V X7R ceramic capacitor from BOOT to BOOT_R
pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.
9
BOOT
This pin enables the diode emulation function. When this pin is held LOW, diode emulation mode is enabled for
10
FCCM
sync FET. When FCCM is HIGH, the device is operated in forced continuous conduction mode. An internal 5 µA
current source will pull the FCCM pin to 3.3 V if left floating.
Temperature Analog Output. Reports a voltage proportional to the die temperature. An ORing diode is integrated in
the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only
the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown occurs. TAO should be
bypassed to PGND with a 1 nF 16 V X7R ceramic capacitor.
TAO/
FAULT
11
Pulse width modulated tri-state input from external controller. Logic LOW sets control FET gate low and sync FET
gate high. Logic HIGH sets control FET gate high and sync FET gate low. Open or High Z sets both MOSFET
gates low if greater than the tri-state shutdown hold-off time (t3HT).
12
13
PWM
PGND
Power ground.
Copyright © 2016, Texas Instruments Incorporated
3
CSD95472Q5MC
ZHCSEM4 –FEBRUARY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
UNIT
V
VIN to PGND
20
VIN to VSW
20
V
VIN to VSW (10 ns)
VSW to PGND
23
V
–0.3
–7
20
V
VSW to PGND (10 ns)
VDD to PGND
23
V
–0.3
–0.3
–0.3
7
VDD + 0.3 V
VDD + 0.3 V
12
V
(2)
ENABLE, PWM, FCCM, TAO, IOUT, REFIN to PGND
V
BOOT to BOOT_R(2)
Power dissipation
Operating junction
Storage temperature
V
PD
TJ
W
–55
–55
150
°C
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Should not exceed 7 V.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM)
6.3 Recommended Operating Conditions
TA = 25° (unless otherwise noted)
MIN
MAX
5.5
UNIT
VDD
VIN
Gate drive voltage
Input supply voltage(1)
4.5
V
V
16
VOUT
Output voltage
5.5
V
IOUT
Continuous output current
VIN = 12 V, VDD = 5 V, VOUT = 1.2 V,
ƒSW = 500 kHz, LOUT = 0.225 µH(2)
60
A
IOUT-PK Peak output current(3)
90
A
ƒSW
Switching frequency
On time duty cycle
CBST = 0.1 µF (min)
ƒSW = 1 MHz
1250
85%
kHz
Minimum PWM on time
Operating temperature
40
ns
°C
–40
125
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
(2) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(3) System conditions as defined in Note 1. Peak Output Current is applied for tp = 50 µs.
6.4 Thermal Information
TA = 25°C (unless otherwise noted)
THERMAL METRIC
MIN
TYP
MAX UNIT
(1)
RθJC(top) Junction-to-case (top of package) thermal resistance
5
°C/W
1.5
RθJB
Junction-to-board thermal resistance(2)
(1)
(2)
R
θJC(top) is determined with the device mounted on a 1 inch² (6.45 cm²), 2-oz (0.071 mm thick) Cu pad on a 1.5 inches x 1.5 inches,
0.06-inch (1.52-mm) thick FR4 board.
θJB value based on hottest board temperature within 1 mm of the package.
R
4
Copyright © 2016, Texas Instruments Incorporated
CSD95472Q5MC
www.ti.com.cn
ZHCSEM4 –FEBRUARY 2016
7 Application Schematic
12V
BOOT
BOOT_R
VIN
TPS53661
VCORE_OUT
Load
TAO/FAULT
PWM1
PWM
VSP
VSW
SKIP#-RAMP
FCCM
VDD
CSD95472
PGND
5V
VSN
ENABLE
PGND IOUT REFIN
OCP-I
COMP
CSP1
TSEN
12V
VREF
BOOT
BOOT_R
VIN
F-IMAX
TAO/FAULT
PWM
PWM2
VSW
FCCM
VDD
CSD95472
PGND
5V
B-TMAX
ENABLE
PGND IOUT REFIN
CSP2
O-USR
12V
BOOT
BOOT_R
VIN
TAO/FAULT
ADDR
PWM
PWM3
VSW
FCCM
VDD
CSD95472
PGND
5V
ENABLE
PGND IOUT REFIN
SLEW-MODE
CSP3
12V
ISUM
IMON
IMON
BOOT
BOOT_R
VIN
TAO/FAULT
PWM
PWM4
VSW
FCCM
VDD
CSD95472
PGND
5V
ENABLE
PGND IOUT REFIN
SCLK
ALERT#
SDIO
To/From
CPU
CSP4
VR_RDY
12V
VR_HOT#
PMB_CLK
PMB_ALERT#
PMB_DIO
ENABLE
BOOT
BOOT_R
VIN
I2C or
PMBus
(Optional)
TAO/FAULT
PWM
PWM5
VSW
FCCM
VDD
CSD95472
PGND
5V
ENABLE
ENABLE
PGND IOUT REFIN
VR_FAULT#
VR_FAULT#
CSP5
12V
12V
5V
V12
V5
BOOT
BOOT_R
VIN
TAO/FAULT
PWM
PWM6
VSW
FCCM
VDD
CSD95472
PGND
5V
ENABLE
3.3V
IOUT REFIN
V3R3
PGND
CSP6
GND
版权 © 2016, Texas Instruments Incorporated
5
CSD95472Q5MC
ZHCSEM4 –FEBRUARY 2016
www.ti.com.cn
8 器件和文档支持
8.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.2 商标
NexFET, DualCool, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
8.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
6
版权 © 2016, Texas Instruments Incorporated
CSD95472Q5MC
www.ti.com.cn
ZHCSEM4 –FEBRUARY 2016
9 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
9.1 机械制图
Exposed tie clip may vary
A
c2
E2
d2
E1
c1
L1
d1
K
b3
b2
b1
E
D2
b
e
a1
L
0.300 x 45°
d
毫米
标称值
英寸
DIM
最小值
0.950
0.000
0.200
最大值
1.050
0.050
0.320
最小值
0.037
0.000
0.008
标称值
0.039
0.000
0.010
最大值
A
a1
b
1.000
0.000
0.041
0.002
0.013
0.250
b1
b2
b3
c1
c2
D2
d
2.750 典型值
0.250
0.108 典型值
0.010
0.200
0.320
0.008
0.013
0.250 典型值
0.200
0.010 典型值
0.008
0.150
0.200
5.300
0.200
0.350
1.900
5.900
4.900
3.200
0.250
0.300
5.500
0.300
0.450
2.100
6.100
5.100
3.400
0.006
0.008
0.209
0.008
0.014
0.075
0.232
0.193
0.126
0.010
0.012
0.217
0.012
0.018
0.083
0.240
0.201
0.134
0.250
0.010
5.400
0.213
0.250
0.010
d1
d2
E
0.400
0.016
2.000
0.079
6.000
0.236
E1
E2
e
5.000
0.197
3.300
0.130
0.500 典型值
0.350 典型值
0.500
0.020 典型值
0.014 典型值
0.020
K
L
0.400
0.210
0.00
0.600
0.410
—
0.016
0.008
0.00
0.024
0.016
—
L1
θ
0.310
0.012
—
—
版权 © 2016, Texas Instruments Incorporated
7
CSD95472Q5MC
ZHCSEM4 –FEBRUARY 2016
www.ti.com.cn
9.2 建议印刷电路板 (PCB) 焊盘图案
0.331(0.013)
0.370 (0.015)
1.000 (0.039)
0.410 (0.016)
0.550 (0.022)
0.300 (0.012)
2.800
(0.110)
6.300
(0.248)
5.300
(0.209)
5.639
(0.222)
0.500
(0.020)
0.300
(0.012)
R0.127 (R0.005)
3.400
(0.134)
5.900
(0.232)
1. 尺寸单位为 mm（英寸）。
9.3 建议模板开口
0.350(0.014)
2.750
(0.108)
0.250
(0.010)
1. 尺寸单位为 mm（英寸）。
2. 模板厚度为 100µm。
8
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD95472Q5MC
CSD95472Q5MCT
ACTIVE
VSON-CLIP
VSON-CLIP
DMC
12
12
RoHS-Exempt
& Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 150
-55 to 150
95472MC
95472MC
ACTIVE
DMC
RoHS-Exempt
& Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2021
Addendum-Page 2
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