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CSD95482RWJ [TI]

采用业界通用封装的 40A 同步降压 NexFET™ 智能功率级;
CSD95482RWJ
型号： CSD95482RWJ
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

采用业界通用封装的 40A 同步降压 NexFET™ 智能功率级
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CSD95482RWJ  
SLPS688 –JUNE 2017  
CSD95482RWJ Synchronous Buck NexFET™ Smart Power Stage  
1 Features  
2 Applications  
1
•
•
•
•
•
40-A Continuous Operating Current Capability  
Over 93.5% System Efficiency at 20 A  
High-Frequency Operation (up to 1.25 MHz)  
Diode Emulation Function  
•
Multiphase Synchronous Buck Converters  
–
–
High-Frequency Applications  
High-Current, Low-Duty Cycle Applications  
•
•
•
POL DC-DC Converters  
Temperature Compensated Bi-Directional Current  
Sense  
Memory and Graphic Cards  
Desktop and Server VR12.x / VR13.x V-Core  
Synchronous Buck Converters  
•
•
•
•
•
•
Analog Temperature Output  
Fault Monitoring  
3 Description  
3.3-V and 5-V PWM Signal Compatible  
Tri-State PWM Input  
The CSD95482RWJ NexFET™ power stage is a  
highly optimized design for use in a high-power, high-  
density synchronous buck converter. This product  
integrates the driver IC and power MOSFETs to  
complete the power stage switching function. This  
combination produces high-current, high-efficiency,  
and high-speed switching capability in a small 5-mm  
× 6-mm outline package. It also integrates the  
accurate current sensing and temperature sensing  
functionality to simplify system design and improve  
accuracy. In addition, the PCB footprint has been  
optimized to help reduce design time and simplify the  
completion of the overall system design.  
Integrated Bootstrap Switch  
Optimized Dead Time for Shoot-Through  
Protection  
•
•
•
•
•
•
High-Density QFN 5-mm × 6-mm Footprint  
Ultra-Low Inductance Package  
System Optimized PCB Footprint  
Thermally Enhanced Topside Cooling  
RoHS Compliant – Lead-Free Terminal Plating  
Halogen Free  
Device Information(1)  
DEVICE  
MEDIA  
QTY  
PACKAGE  
SHIP  
Application Diagram  
CSD95482RWJ  
13-Inch Reel  
2500  
QFN  
Tape  
and  
Reel  
5.00-mm × 6.00-mm  
Package  
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CSD95482RWJT 7-Inch Reel  
250  
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(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
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Typical Power Stage Efficiency and Power Loss  
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100  
90  
80  
70  
60  
50  
40  
30  
7
6
5
4
3
2
1
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VDD = 5 V  
VIN = 12 V  
VOUT = 1.2 V  
LOUT = 220 nH  
fSW = 500 kHz  
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10  
15  
20  
25  
30  
35  
40  
Output Current (A)  
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Copyright © 2017, Texas Instruments Incorporated  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
CSD95482RWJ  
SLPS688 –JUNE 2017  
www.ti.com  
Table of Contents  
1
2
3
4
5
6
Features.................................................................. 1  
8
Device and Documentation Support.................... 6  
8.1 Receiving Notification of Documentation Updates.... 6  
8.2 Community Resources.............................................. 6  
8.3 Trademarks............................................................... 6  
8.4 Electrostatic Discharge Caution................................ 6  
8.5 Glossary.................................................................... 6  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
6.1 Absolute Maximum Ratings ...................................... 4  
6.2 ESD Ratings.............................................................. 4  
6.3 Recommended Operating Conditions....................... 4  
Application Schematic .......................................... 5  
9
Mechanical, Packaging, and Orderable  
Information ............................................................. 7  
9.1 Mechanical Drawing.................................................. 7  
9.2 Recommended PCB Land Pattern............................ 8  
9.3 Recommended Stencil Opening ............................... 9  
7
4 Revision History  
DATE  
REVISION  
NOTES  
June 2017  
*
Initial release.  
2
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CSD95482RWJ  
www.ti.com  
SLPS688 –JUNE 2017  
5 Pin Configuration and Functions  
Top View  
39 38 37 36 35 34 33 32 31 30  
VOS  
AGND  
VDD  
1
2
3
4
5
6
VIN  
29  
28 VIN  
27 VIN  
26 VIN  
25 VIN  
VIN  
40  
PVDD  
PGND  
NC  
41  
PGND  
24  
23 PGND  
22 PGND  
21 PGND  
PGND  
PGND  
PGND  
7
8
9
PGND  
PGND  
20  
10 11 12 13 14 15 16 17 18 19  
Pin Functions  
PIN  
DESCRIPTION  
NAME  
VOS  
NO.  
1
Output voltage sensing pin for the internal current sensing circuitry.  
This pin is internally connected to PGND.  
AGND  
VDD  
2
3
Supply voltage for internal circuitry. This pin should be bypassed directly to pin 2.  
Supply voltage for gate drivers. This pin should be bypassed to PGND.  
Power ground.  
PVDD  
PGND  
NC  
4
5
6
Not connected. This pin needs to be left floating in application.  
Power ground.  
PGND  
VSW  
PGND  
VIN  
7-9  
10-19  
20-24  
25-30  
31  
Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor.  
Power ground.  
Input voltage pin. Connect input capacitors close to this pin.  
Not connected. This pin needs to be left floating in application.  
Return path for HS gate driver. It is connected to VSW internally.  
NC  
BOOTR  
32  
Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic capacitor from BOOT to  
BOOTR pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is  
integrated.  
BOOT  
PWM  
33  
34  
Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high  
sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for  
greater than the tri-state shutdown hold-off time (T3HT).  
This dual function pin either enables the diode emulation function or can be used as a simple enable for the  
device. When this pin is driven into the tri-state window and held there for more than the tri-state hold-off time,  
Diode Emulation Mode is enabled for sync FET. When the pin is high, device operates in Forced Continuous  
Conduction Mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left  
floating.  
EN/FCCM  
35  
Temperature amplifier output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated  
in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs.  
Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown LSOC or HSS  
detection circuit is tripped.  
TAO/FLT  
36  
LSET  
IOUT  
REFIN  
PGND  
NC  
37  
38  
39  
40  
41  
A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry.  
Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.  
External reference voltage input for current sensing amplifier.  
Power ground.  
Not connected. This pin needs to be left floating in application.  
Copyright © 2017, Texas Instruments Incorporated  
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CSD95482RWJ  
SLPS688 –JUNE 2017  
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6 Specifications  
6.1 Absolute Maximum Ratings  
TA = 25°C (unless otherwise stated)(1)  
MIN  
–0.3  
–0.3  
MAX  
UNIT  
V
VIN to PGND  
20  
VIN to VSW  
20  
V
VIN to VSW (10 ns)  
VSW to PGND  
23  
V
–0.3  
–7  
20  
V
VSW to PGND (10 ns)  
VDD to PGND  
23  
V
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–55  
–55  
7
V
PVDD to PGND  
7
VDD + 0.3  
7
V
EN/FCCM, TAO/FLT, LSET to PGND  
IOUT, VOS, PWM to PGND  
REFIN  
V
V
3.6  
V
BOOT to BOOTR(2)  
VDD + 0.3  
30  
V
BOOT to PGND  
V
TJ  
Operating junction temperature  
Storage temperature  
150  
°C  
°C  
Tstg  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied in the Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) Should not exceed 7 V.  
6.2 ESD Ratings  
VALUE  
±2000  
±500  
UNIT  
Human-body model (HBM)  
V(ESD)  
Electrostatic discharge  
V
Charged-device model (CDM)  
6.3 Recommended Operating Conditions  
TA = 25°C (unless otherwise stated)  
MIN  
4.5  
4.5  
4.5  
MAX  
5.5  
UNIT  
VDD  
Driver supply voltage  
Gate drive voltage  
Input supply voltage(1)  
Output voltage  
V
V
PVDD  
VIN  
5.5  
16  
V
VOUT  
5.5  
V
PWM to PGND  
VDD  
40  
V
IOUT  
Continuous output current  
IOUT-PK Peak output current(3)  
A
VIN = 12 V, VDD = 5 V, PVDD = 5 V, VOUT = 1.2 V,  
ƒSW = 500 kHz(2)  
60  
A
ƒSW  
Switching frequency  
CBST = 0.1 µF (min), VOUT = 2.5 V (max)  
ƒSW = 1 MHz  
1250  
85%  
kHz  
On-time duty cycle  
Minimum PWM on-time  
Operating junction temperature  
20  
ns  
°C  
–40  
125  
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For  
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.  
(2) Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins.  
(3) System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs.  
4
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SLPS688 –JUNE 2017  
7 Application Schematic  
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Copyright © 2017, Texas Instruments Incorporated  
Figure 1. Application Schematic  
Copyright © 2017, Texas Instruments Incorporated  
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Product Folder Links: CSD95482RWJ  
CSD95482RWJ  
SLPS688 –JUNE 2017  
www.ti.com  
8 Device and Documentation Support  
8.1 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
8.2 Community Resources  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
8.3 Trademarks  
NexFET, E2E are trademarks of Texas Instruments.  
All other trademarks are the property of their respective owners.  
8.4 Electrostatic Discharge Caution  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
8.5 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
6
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CSD95482RWJ  
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SLPS688 –JUNE 2017  
9 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
9.1 Mechanical Drawing  
5.1  
4.9  
A
B
PIN 1 INDEX AREA  
6.1  
5.9  
C
1.05 MAX  
SEATING PLANE  
0.08  
(0.203) TYP  
0.05  
0.00  
0.3  
0.2  
9X 0.45  
10X  
0.13 TYP  
10  
19  
0.3  
0.2  
13X  
2.6 0.1  
2.2 0.1  
9
20  
2.05  
1.95  
7
6
10X 0.45  
0.8 0.1  
0.4 0.1  
0.1 0.1  
R0.05  
TYP  
24  
25  
41  
0.000  
PKG  
0.3 0.1  
0.45  
0.35  
16X  
40  
2.25 0.1  
2.275  
2.175  
29  
1
PIN 1 ID  
39  
30  
(45 X0.3)  
0.3  
0.2  
14X 0.45  
16X  
0.1  
C A B  
0.05  
4221590/C 01/2017  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning  
and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical  
performance.  
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SLPS688 –JUNE 2017  
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9.2 Recommended PCB Land Pattern  
METAL UNDER  
SOLDER MASK  
TYP  
16X (0.6)  
39  
30  
(2.9)  
16X (0.25)  
1
(2.25)  
(2.175)  
(2.05)  
(2.25)  
29  
SOLDER MASK  
OPENING, TYP  
40  
(1.275)  
14X (0.45)  
(0.5)  
(0.3)  
25  
24  
(0.3)  
(0.025)  
6
(0.1)  
0.000 PKG  
(0.3)  
41  
(0.4)  
(R0.05) TYP  
5X (1.15)  
(0.8)  
7
(1.05)  
19X (0.45)  
(
0.2) VIA  
TYP  
9
5X (2)  
(2.05)  
20  
(2.2)  
(0.05) MIN  
TYP  
(2.6)  
(2.75) TYP  
(3.2) TYP  
19  
10  
PKG  
20X (0.25)  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning  
and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This package is designed to be soldered to thermal pads on the board. For more information, see QFN/SON  
PCB Attachment (SLUA271).  
8
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SLPS688 –JUNE 2017  
9.3 Recommended Stencil Opening  
29X (0.6)  
39  
30  
29X (0.25)  
1
EXPOSED  
METAL  
4X (2.245)  
29  
24X (0.45)  
4X (1.375)  
4X (1.175)  
40  
EXPOSED  
METAL  
SOLDER MASK  
OPENING  
TYP  
25  
24  
(0.375)  
4X (0.305)  
(0.025)  
6
(0.1)  
(0.4)  
0.000 PKG  
3X (0.13)  
(0.25)  
41  
(0.84)  
(1.05)  
7
9
3X (1.05)  
3X (1.25)  
(R0.05) TYP  
20  
EXPOSED  
METAL  
4X (2.17)  
(2.6)  
(2.75) TYP  
METAL UNDER  
SOLDER MASK  
TYP  
10  
(3.2) TYP  
19  
10X (0.25)  
9X (0.45)  
SOLDER PAST EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning  
and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525  
may have alternate design recommendations.  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
2500  
250  
(1)  
(2)  
(3)  
(4/5)  
(6)  
CSD95482RWJ  
CSD95482RWJT  
ACTIVE  
VQFN-CLIP  
VQFN-CLIP  
RWJ  
41  
41  
RoHS-Exempt  
& Green  
SN  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-55 to 150  
-55 to 150  
95482RWJ  
95482RWJ  
ACTIVE  
RWJ  
RoHS-Exempt  
& Green  
SN  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2021  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CSD95482RWJ  
CSD95482RWJT  
VQFN-  
CLIP  
RWJ  
RWJ  
41  
41  
2500  
250  
330.0  
12.4  
5.3  
6.3  
1.2  
8.0  
12.0  
Q1  
VQFN-  
CLIP  
180.0  
12.4  
5.3  
6.3  
1.2  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Jan-2021  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CSD95482RWJ  
CSD95482RWJT  
VQFN-CLIP  
VQFN-CLIP  
RWJ  
RWJ  
41  
41  
2500  
250  
367.0  
213.0  
367.0  
191.0  
38.0  
35.0  
Pack Materials-Page 2  
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
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Copyright © 2021, Texas Instruments Incorporated  

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