CSD95485RWJ [TI]
采用业界通用封装的 75A NexFET™ 同步降压智能功率级;
| 型号： | CSD95485RWJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用业界通用封装的 75A NexFET™ 同步降压智能功率级 |
| 文件： | 总13页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CSD95485RWJ
ZHCSKY7 –MARCH 2020
CSD95485RWJ 同步降压 NexFET™智能功率级
1 特性
2 应用
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
具有 75A 持续工作电流能力
•
多相同步降压转换器
30A 电流下系统效率超过 95%
工作频率高（高达 1.25MHz）
二极管仿真功能
–
–
高频率 应用
高电流、低占空比 应用
•
•
•
POL 直流/直流转换器
温度补偿双向电流感应
模拟温度输出
存储器和显卡
台式机和服务器 VR12.x/VR13.x V-core 同步降压
转换器
故障监控
兼容 3.3V 和 5V PWM 信号
三态 PWM 输入
3 说明
CSD95485RWJ NexFET™功率级是经过高度优化的
设计，用于高功率、高功率密度场合的同步降压转换
器。这款产品集成了驱动器 IC 和功率 MOSFET 来完
善功率级开关功能。该组合采用 5mm × 6mm 小型封
装，可实现高电流、高效率以及高速切换功能。它还集
成了准确电流检测和温度感测功能，以简化系统设计并
提高准确度。此外，PCB 封装已经过优化，可帮助减
少设计时间并简化总体系统设计。
集成自举开关
用于击穿保护的经优化死区时间
高密度 5mm × 6mm QFN 封装
超低电感封装
系统已优化的 PCB 空间占用
耐热增强型顶部散热
符合 RoHS 标准 – 无铅端子镀层
无卤素
器件信息(1)
数量
器件
介质
封装
配送
CSD95485RWJ
13 英寸卷带
2500
QFN
5.00mm × 6.00mm
封装
卷带
封装
CSD95485RWJT
7 英寸卷带
250
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
应用图表
典型功率级效率与功率损耗
TPS53688
PWM1
100
90
80
70
60
50
40
30
17.5
15
CSD95485RWJ
Power Stage
ACSP1
12.5
10
VDD = PVDD = 5 V
IN = 12 V
VOUT = 1.8 V
V
PWM2
ACSP2
PMBus
CSD95485RWJ
Power Stage
LOUT = 150 nH
SW = 600 kHz
7.5
5
f
TA = 25 èC
2.5
0
BPWM1
BCSP1
CSD95484RWX
Power Stage
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
Output Current (A)
D000
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS721
CSD95485RWJ
ZHCSKY7 –MARCH 2020
www.ti.com.cn
目录
6.4 Thermal Information.................................................. 5
Application Schematic .......................................... 6
器件和文档支持........................................................ 7
8.1 商标........................................................................... 7
8.2 静电放电警告............................................................. 7
8.3 Glossary.................................................................... 7
机械、封装和可订购信息 ......................................... 8
9.1 机械制图.................................................................... 8
9.2 推荐 PCB 焊盘图案 ................................................... 9
9.3 建议模版开孔........................................................... 10
1
2
3
4
5
6
特性.......................................................................... 1
7
8
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
9
4 修订历史记录
日期
修订版本
说明
2020 年 3 月
*
初始发行版。
2
Copyright © 2020, Texas Instruments Incorporated
CSD95485RWJ
www.ti.com.cn
ZHCSKY7 –MARCH 2020
5 Pin Configuration and Functions
RWJ Package
41-Pin QFN
Top View
39 38 37 36 35 34 33 32 31 30
VOS
AGND
VDD
1
2
3
4
5
6
VIN
29
28 VIN
27 VIN
26 VIN
25 VIN
VIN
40
PVDD
PGND
NC
41
PGND
24
23 PGND
22 PGND
21 PGND
PGND
PGND
PGND
7
8
9
PGND
PGND
20
10 11 12 13 14 15 16 17 18 19
Pin Functions
PIN
DESCRIPTION
NAME
VOS
NUMBER
1
2
Output voltage sensing pin for the internal current sensing circuitry.
This pin is internally connected to PGND.
AGND
VDD
3
Supply voltage for internal circuitry. This pin should be bypassed directly to pin 2.
Supply voltage for gate drivers. This pin should be bypassed to PGND.
Power ground.
PVDD
PGND
NC
4
5
6
Not connected. This pin needs to be left floating in application.
Power ground.
PGND
VSW
PGND
VIN
7-9
10-19
20-24
25-30
31
Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor.
Power ground.
Input voltage pin. Connect input capacitors close to this pin.
Not connected. This pin needs to be left floating in application.
Return path for HS gate driver. It is connected to VSW internally.
NC
BOOTR
32
Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic capacitor from BOOT to
BOOTR pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is
integrated.
BOOT
PWM
33
34
Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high
sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for
greater than the tri-state shutdown holdoff time (T3HT).
This dual function pin either enables the diode emulation function or can be used as a simple enable for the
device. When this pin is driven into the tri-state window and held there for more than the tri-state holdoff time,
diode emulation mode is enabled for sync FET. When the pin is high, device operates in forced continuous
conduction mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left
floating.
EN/FCCM
35
Temperature amplifier output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated
in the IC. When used in a multi-phase application, a single wire can be used to connect the TAO pins of all the
ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown LSOC or
HSS detection circuit is tripped.
TAO/FLT
36
LSET
IOUT
REFIN
PGND
NC
37
38
39
40
41
A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry.
Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.
External reference voltage input for current sensing amplifier.
Power ground.
Not connected. This pin needs to be left floating in application.
Copyright © 2020, Texas Instruments Incorporated
3
CSD95485RWJ
ZHCSKY7 –MARCH 2020
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
20
UNIT
V
VIN to PGND
VIN to VSW
20
V
VIN to VSW (10 ns)
VSW to PGND
ILOAD > 0 A(2)
ILOAD < 0 A(2)
23
V
–0.3
20
V
VSW to PGND (10 ns)
VSW to PGND (10 ns)
VDD to PGND
23
V
–7
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–55
7
V
(3)
EN/FCCM, TAO/FLT, LSET to PGND
VDD + 0.3
V
V
IOUT, VOS, PWM to PGND
REFIN to PGND
7
3.6
V
BOOT to PGND
BOOT to BOOT_R(3)
30
V
VDD + 0.3
150
V
TJ
Operating junction temperature
Storage temperature
°C
°C
Tstg
–55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) ILOAD is defined as the current flowing out of the VSW pins.
(3) Should not exceed 7 V.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM)
6.3 Recommended Operating Conditions
TA = 25°C (unless otherwise stated)
MIN
4.5
4.5
4.5
MAX
5.5
UNIT
VDD
Driver supply voltage
Gate drive voltage
Input supply voltage(1)
Output voltage
V
V
PVDD
VIN
5.5
16
V
VOUT
5.5
V
PWM to PGND
VDD + 0.3
75
V
IOUT
Continuous output current
IOUT-PK Peak output current(3)
A
VIN = 12 V, VDD = 5 V, PVDD = 5 V, VOUT = 1.2 V,
ƒSW = 500 kHz(2)
105
A
ƒSW
Switching frequency
CBST = 0.1 µF (min), VOUT = 2.5 V (max)
ƒSW = 1 MHz
1250
85%
kHz
On-time duty cycle
Minimum PWM on-time
Operating junction temperature
20
ns
°C
–40
125
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
(2) Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins.
(3) System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs.
4
Copyright © 2020, Texas Instruments Incorporated
CSD95485RWJ
www.ti.com.cn
ZHCSKY7 –MARCH 2020
6.4 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP
7.4
2.2
0.9
MAX UNIT
°C/W
θJC
θJB
ΨJT
Thermal resistance, junction-to-case (top of package)
Thermal resistance, junction-to-board(1)
°C/W
Junction-to-top characterization parameter
°C/W
(1) θJB is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in, 0.06-in (1.52-mm)
thick FR4 board based on hottest board temperature within 1 mm of the package.
Copyright © 2020, Texas Instruments Incorporated
5
CSD95485RWJ
ZHCSKY7 –MARCH 2020
www.ti.com.cn
7 Application Schematic
P12V
TPS53688
AVSP
BOOT BOOT_R
CSD95485RWJ
VIN
VOS
PWM
AVSN
PWM1
ASKIP#
EN/FCCM
VDD
P5V
VSW
TAO
LOAD
PVDD
LSET
PGND IOUT REFIN
ACSP1
TSEN
P12V
BOOT BOOT_R
CSD95485RWJ
VIN
VOS
PWM
APWM6
EN/FCCM
VDD
P5V
VREF
ADDR
VSW
TAO
PVDD
LSET
PGND IOUT REFIN
3.3V
V3P3
ACSP6
VREF
P12V
VIN_CSNIN
CSPIN
BVSN
BVSP
VCCIO
BEN_VCCIO
P12V
SCLK
SDIO
BOOT BOOT_R
CSD95484RWX
VIN
SALERT#
PIN_ALT#
VR_HOT#
SMB_CLK
SMB_ALERT#
SMB_DIO
AVR_RDY
BVR_RDY
AVR_EN
VOS
PWM
BPWM1
BSKIP#
EN/FCCM
VDD
P5V
VSW
TAO
LOAD
PVDD
LSET
PGND IOUT REFIN
VR_FAULT#
RESET#
BCSP1
AGND
Figure 1. Application Schematic
Note: The schematic in Figure 1 is a conceptual drawing only. Actual designs may require additional components
not shown.
6
版权 © 2020, Texas Instruments Incorporated
CSD95485RWJ
www.ti.com.cn
ZHCSKY7 –MARCH 2020
8 器件和文档支持
8.1 商标
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
8.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
8.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2020, Texas Instruments Incorporated
7
CSD95485RWJ
ZHCSKY7 –MARCH 2020
www.ti.com.cn
9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
9.1 机械制图
5.1
4.9
A
B
PIN 1 INDEX AREA
6.1
5.9
C
1.05 MAX
SEATING PLANE
0.08
(0.203) TYP
0.05
0.00
0.3
0.2
9X 0.45
10X
0.13 TYP
10
19
0.3
0.2
13X
2.6 0.1
2.2 0.1
9
20
2.05
1.95
7
6
10X 0.45
0.8 0.1
0.4 0.1
0.1 0.1
R0.05
TYP
24
25
41
0.000
PKG
0.3 0.1
0.45
0.35
16X
40
2.25 0.1
2.275
2.175
29
1
PIN 1 ID
39
30
(45 X0.3)
0.3
0.2
14X 0.45
16X
0.1
C A B
0.05
4221590/C 01/2017
1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
2. 本图如有变更，恕不另行通知。
3. 封装散热焊盘必须焊接在印刷电路板上，才能实现最佳的散热和机械性能。
8
版权 © 2020, Texas Instruments Incorporated
CSD95485RWJ
www.ti.com.cn
ZHCSKY7 –MARCH 2020
9.2 推荐 PCB 焊盘图案
METAL UNDER
SOLDER MASK
TYP
16X (0.6)
39
30
(2.9)
16X (0.25)
(2.25)
1
(2.25)
(2.175)
(2.05)
29
SOLDER MASK
OPENING, TYP
40
(1.275)
14X (0.45)
(0.5)
(0.3)
25
24
(0.3)
(0.025)
0.000 PKG
(0.3)
6
(0.1)
(0.4)
41
(R0.05) TYP
5X (1.15)
(0.8)
7
(1.05)
19X (0.45)
(
0.2) VIA
TYP
9
5X (2)
(2.05)
20
(2.2)
(0.05) MIN
TYP
(2.6)
(2.75) TYP
(3.2) TYP
19
10
PKG
20X (0.25)
1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
2. 本图如有变更，恕不另行通知。
3. 此封装设计用于焊接到电路板的散热焊盘上。有关更多信息，请参阅《QFN/SON PCB 连接》(SLUA271)。
版权 © 2020, Texas Instruments Incorporated
9
CSD95485RWJ
ZHCSKY7 –MARCH 2020
www.ti.com.cn
9.3 建议模版开孔
29X (0.6)
39
30
29X (0.25)
24X (0.45)
EXPOSED
METAL
1
4X (2.245)
29
4X (1.375)
4X (1.175)
40
EXPOSED
METAL
SOLDER MASK
OPENING
TYP
25
24
(0.375)
4X (0.305)
(0.025)
0.000 PKG
3X (0.13)
(0.25)
6
7
(0.1)
(0.4)
41
(0.84)
(1.05)
3X (1.05)
3X (1.25)
(R0.05) TYP
9
20
EXPOSED
METAL
4X (2.17)
(2.6)
(2.75) TYP
METAL UNDER
SOLDER MASK
TYP
10
(3.2) TYP
19
10X (0.25)
9X (0.45)
SOLDER PAST EXAMPLE
BASED ON 0.125 mm THICK STENCIL
1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
2. 本图如有变更，恕不另行通知。
3. 具有漏斗形壁和圆角的激光切割孔可提供更佳的锡膏脱离。IPC-7525 可能提供替代设计建议。
10
版权 © 2020, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
19-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD95485RWJ
CSD95485RWJT
ACTIVE
VQFN-CLIP
VQFN-CLIP
RWJ
41
41
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 150
-55 to 150
95485RWJ
95485RWJ
Samples
Samples
ACTIVE
RWJ
RoHS-Exempt
& Green
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Aug-2022
Addendum-Page 2
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