DLP3010 [TI]

DLP® 0.3 720p DMD;


型号：	DLP3010
厂家：	TEXAS INSTRUMENTS
描述：	DLP® 0.3 720p DMD
文件：	总41页 (文件大小：1870K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLP3010

ZHCSHW7B –FEBRUARY 2018 –REVISED MAY 2022

DLP3010 0.3 720p DMD

1 特性

3 说明

• 0.3 英寸(7.93mm) 对角线微镜阵列

DLP3010 数字微镜器件 (DMD) 是一款数控微光机电系

统(MOEMS) 空间照明调制器(SLM)。当与适当的光学

系统配合使用时，DLP3010 DMD 可显示非常清晰的高

质量图像或视频。DLP3010 是 DLP3010 DMD、

DLPC3433 或 DLPC3438 显示控制器和 DLPA200x/

DLPA3000 PMIC/LED 驱动器所组成的芯片组的一部

分。DLP3010 紧凑的物理尺寸连同控制器和

PMIC/LED 驱动器共同组成了完整的系统解决方案，从

而实现了小外形尺寸、低功耗以及高分辨率高清显示

屏。

– 1280 × 720 铝制微米级微镜阵列，正交布局

– 5.4µm 微镜间距

– ±17° 微镜倾斜度（相对于平面）

– 侧面照明，实现最优的效率和光学引擎尺寸

– 偏振无关型铝微镜表面

• 8 位SubLVDS 输入数据总线

• 专用DLPC3433 或DLPC3438 显示控制器和

DLPA200x/DLPA3000 PMIC/LED 驱动器，确保可

靠运行

器件信息

2 应用

封装⁽¹⁾

封装尺寸（标称值）

18.20mm × 7.00mm

器件型号

DLP3010

• 电池供电的移动式附件高清(HD) 投影仪

• 电池供电的智能HD 投影仪

• 数字标牌

• 交互式表面投影

• 低延迟游戏显示屏

• 交互式显示

FQK (57)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

DLP® DLP3010 0.3 720p 芯片组

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: DLPS099

DLP3010

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ZHCSHW7B –FEBRUARY 2018 –REVISED MAY 2022

Table of Contents

7.5 Optical Interface and System Image Quality

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings ....................................... 6

6.2 Storage Conditions..................................................... 7

6.3 ESD Ratings............................................................... 7

6.4 Recommended Operating Conditions.........................7

6.5 Thermal Information..................................................10

6.6 Electrical Characteristics...........................................10

6.7 Timing Requirements................................................ 11

6.8 Switching Characteristics..........................................16

6.9 System Mounting Interface Loads............................ 16

6.10 Micromirror Array Physical Characteristics.............17

6.11 Micromirror Array Optical Characteristics............... 18

6.12 Window Characteristics.......................................... 19

6.13 Chipset Component Usage Specification............... 20

7 Detailed Description......................................................21

7.1 Overview...................................................................21

7.2 Functional Block Diagram.........................................21

7.3 Feature Description...................................................22

7.4 Device Functional Modes..........................................22

Considerations............................................................ 22

7.6 Micromirror Array Temperature Calculation.............. 23

7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24

8 Application and Implementation..................................28

8.1 Application Information............................................. 28

8.2 Typical Application.................................................... 28

9 Power Supply Recommendations................................31

9.1 Power Supply Power-Up Procedure......................... 31

9.2 Power Supply Power-Down Procedure.....................31

9.3 Power Supply Sequencing Requirements................ 32

10 Layout...........................................................................34

10.1 Layout Guidelines................................................... 34

10.2 Layout Example...................................................... 34

11 Device and Documentation Support..........................35

11.1 Device Support........................................................35

11.2 Related Links.......................................................... 35

11.3 接收文档更新通知................................................... 35

11.4 支持资源..................................................................36

11.5 Trademarks............................................................. 36

11.6 Electrostatic Discharge Caution..............................36

11.7 术语表..................................................................... 36

12 Mechanical, Packaging, and Orderable

Information.................................................................... 36

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (October 2021) to Revision B (May 2022)

Page

• Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6

• Updated Micromirror Array Optical Characteristics ......................................................................................... 18

• Added Third-Party Products Disclaimer ...........................................................................................................35

Changes from Revision * (February 2018) to Revision A (October 2021)

Page

• 更新了整个文档中的表、图和交叉参考的编号格式.............................................................................................1

• Updated |T_DELTA| MAX from 30°C to 15°C..........................................................................................................7

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5 Pin Configuration and Functions

图5-1. FQK Package. 57-Pin LGA. BOTTOM VIEW.

表5-1. Pin Functions –Connector Pins

PIN⁽¹⁾

NAME

PACKAGE NET

LENGTH⁽²⁾(mm)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NO.

DATA INPUTS

D_N(0)

SubLVDS

Double

Data, Negative

10.54

13.14

14.24

14.35

5.89

D_P(0)

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Data, Negative

Data, Positive

Clock, Negative

Clock, Positive

D_N(1)

D10

D11

C11

B11

D12

D13

D_P(1)

D_N(2)

D_P(2)

D_N(3)

D_P(3)

D_N(4)

D_P(4)

5.89

D_N(5)

5.45

D_P(5)

5.45

D_N(6)

8.59

D_P(6)

8.59

D_N(7)

7.69

D_P(7)

7.69

DCLK_N

DCLK_P

CONTROL INPUTS

LS_WDATA

LS_CLK

8.10

C12

C13

LPSDR⁽¹⁾

LPSDR

Single

Write data for low-speed interface.

Clock for low-speed interface.

7.16

7.89

Asynchronous reset DMD signal. A low

signal places the DMD in reset. A high

signal releases the DMD from reset

and places it in active mode.

DMD_DEN_ARSTZ C14

LPSDR

LS_RDATA

POWER

VBIAS⁽³⁾

C15

Single

Read data for low-speed interface.

Power

Supply voltage for positive bias level at

micromirrors.

C18

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表5-1. Pin Functions –Connector Pins (continued)

PIN⁽¹⁾

NAME

PACKAGE NET

LENGTH⁽²⁾(mm)

TYPE

SIGNAL

DATA RATE

DESCRIPTION

NO.

VOFFSET⁽³⁾

Power

Supply voltage for HVCMOS core

logic. Supply voltage for stepped high

level at micromirror address

electrodes.

Supply voltage for offset level at

micromirrors.

VOFFSET⁽³⁾

D17

Power

VRESET

VDD

VDD⁽³⁾

VDD

VDDI

VSS

B18

Power

Ground

Supply voltage for negative reset level

at micromirrors.

B10

B19

Supply voltage for LVCMOS core logic.

Supply voltage for LPSDR inputs.

Supply voltage for normal high level at

micromirror address electrodes.

C10

C19

D18

D19

Supply voltage for SubLVDS receivers.

VSS

B12

B13

B14

B15

B16

B17

VSS

Common return.

Ground for all power.

VSS

C16

C17

D14

D15

D16

VSS

(1) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.

(2) Net trace lengths inside the package:

Relative dielectric constant for the FQK ceramic package is 9.8.

Propagation speed = 11.8 / sqrt (9.8) = 3.769 in/ns.

Propagation delay = 0.265 ns/in = 265 ps/in = 10.43 ps/mm.

(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

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表5-2. Pin Functions –Test Pads

NUMBER

SYSTEM BOARD

A13

Do not connect

A14

A15

A16

A17

A18

E13

E14

E15

E16

E17

E18

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6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾

MIN

–0.5

MAX

2.3

UNIT

Supply voltage for LVCMOS core logic⁽²⁾

Supply voltage for LPSDR low-speed interface

VDD

VDDI

Supply voltage for SubLVDS receivers⁽²⁾

Supply voltage for HVCMOS and micromirror

electrode^{(2) (3)}

VOFFSET

Supply voltage for micromirror electrode⁽²⁾

Supply voltage delta (absolute value)⁽⁴⁾

Supply voltage delta (absolute value)⁽⁵⁾

Supply voltage delta (absolute value)⁽⁶⁾

0.5

0.3

Supply voltage

VBIAS

–0.5

–15

VRESET

|VDDI–VDD|

|VBIAS–VOFFSET|

|VBIAS–VRESET|

Input voltage for other inputs LPSDR⁽²⁾

VDD + 0.5

–0.5

Input voltage

Input pins

Input voltage for other inputs SubLVDS^{(2) (7)}

VDDI + 0.5

|VID|

IID

SubLVDS input differential voltage (absolute value)⁽⁷⁾

810

SubLVDS input differential current

Clock frequency for low-speed interface LS_CLK

Clock frequency for high-speed interface DCLK

Temperature –operational⁽⁸⁾

130

560

ƒ_clock

Clock

frequency

MHz

–20

–40

T_ARRAYand T_WINDOW

Temperature –non-operational⁽⁸⁾

Dew point temperature –operating and non-operating

(non-condensing)

Environmental

°C

T_DP

|T_DELTA

Absolute temperature delta between any point on the

window edge and the ceramic test point TP1⁽⁹⁾

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:

VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.

(3) VOFFSET supply transients must fall within specified voltages.

(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current

draw.

(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current

draw.

(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) The highest temperature of the active array (as calculated by the 节7.6) or of any point along the window edge as defined in 图7-1.

The locations of thermal test points TP2 and TP3 in 图7-1 are intended to measure the highest window edge temperature. If a

particular application causes another point on the window edge to be at a higher temperature, that point should be used.

(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图

7-1. The window test points TP2 and TP3 shown in 图7-1 are intended to result in the worst case delta. If a particular application

causes another point on the window edge to result in a larger delta temperature, that point should be used.

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6.2 Storage Conditions

applicable for the DMD as a component or non-operational in a system

MIN

MAX

UNIT

°C

T_DMD

DMD storage temperature

–40

T_DP-AVG

T_DP-ELR

CT_ELR

Average dew point temperature, (non-condensing)⁽¹⁾

Elevated dew point temperature range, (non-condensing)⁽²⁾

Cumulative time in elevated dew point temperature range

°C

Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

6.3 ESD Ratings

VALUE

UNIT

V_(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)^{(1) (2) (3)}

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE RANGE⁽⁴⁾

Supply voltage for LVCMOS core logic

V_DD

1.65

1.8

1.95

Supply voltage for LPSDR low-speed interface

Supply voltage for SubLVDS receivers

Supply voltage for HVCMOS and micromirror electrode⁽⁵⁾

Supply voltage for mirror electrode

V_DDI

1.65

9.5

1.8

1.95

10.5

18.5

–13.5

0.3

V_OFFSET

V_BIAS

17.5

V_RESET

Supply voltage for micromirror electrode

Supply voltage delta (absolute value)⁽⁶⁾

Supply voltage delta (absolute value)⁽⁷⁾

Supply voltage delta (absolute value)⁽⁸⁾

–14.5

–14

|V_DDI–V_DD

10.5

|V_BIAS–V_OFFSET

|V_BIAS–V_RESET

CLOCK FREQUENCY

Clock frequency for low-speed interface LS_CLK⁽⁹⁾

108

300

120

540

MHz

ƒ_clock

Clock frequency for high-speed interface DCLK⁽¹⁰⁾

Duty cycle distortion DCLK

44%

56%

SUBLVDS INTERFACE⁽¹⁰⁾

SubLVDS input differential voltage (absolute value), see 图6-8

and 图6-9

|V_ID|

150

250

900

350

V_CM

700

575

1100

1225

110

Common mode voltage, see 图6-8 图6-8 and 图6-9

SubLVDS voltage, see 图6-8 and 图6-9

Line differential impedance (PWB/trace)

Internal differential termination resistance, see 图6-10

100-Ωdifferential PCB trace

V_SUBLVDS

Z_LINE

Z_IN

100

120

6.35

152.4

ENVIRONMENTAL

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UNIT

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)^{(1) (2) (3)}

MIN

NOM

MAX

Array temperature –long-term operational^{(11) (13) (14) (15)}

40 to 70

Array temperature –short-term operational, 25 hr maximum⁽¹³⁾

–20

–10

(16)

T_ARRAY

°C

Array temperature –short-term operational, 500 hr maximum⁽¹³⁾

(16)

Array temperature –short-term operational, 500 hr maximum⁽¹³⁾

(16)

Absolute temperature delta between any point on the window

|T_DELTA

edge and the ceramic test point TP1⁽¹⁷⁾

Window temperature –operational^{(11) (18)}

Average dew point temperature (non-condensing)⁽²⁰⁾

Elevated dew point temperature range (non-condensing)⁽¹⁹⁾

Cumulative time in elevated dew point temperature range

Illumination wavelengths < 420 nm⁽¹¹⁾

T_WINDOW

T_DP-AVG

T_DP-ELR

CT_ELR

ILL_UV

°C

Months

mW/cm²

0.68

ILL_VIS

ILL_IR

Illumination wavelengths between 420 nm and 700 nm

Illumination wavelengths > 700 nm

Thermally limited

mW/cm²

deg

ILL_θ

Illumination marginal ray angle⁽¹²⁾

(1) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.

(2) 节6.4 are applicable after the DMD is installed in the final product.

(3) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by

the 节6.4. No level of performance is implied when operating the device above or below the 节6.4 limits.

(4) All voltage values are with respect to the ground pins (VSS).

(5) VOFFSET supply transients must fall within specified maximum voltages.

(6) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than specified limit.

(7) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified limit.

(8) To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified limit.

(9) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(10) Refer to the SubLVDS timing requirements in 节6.7.

(11) Simultaneous exposure of the DMD to the maximum 节6.4 for temperature and UV illumination will reduce device lifetime.

(12) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors

(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily

been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not

been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)

will contribute to thermal limitations described in this document, and may negatively affect lifetime.

(13) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in 图7-1 and the package thermal resistance using 节7.6.

(14) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. Refer to 节7.7 for a definition of micromirror landed duty cycle.

(15) Long-term is defined as the usable life of the device

(16) Short-term is the total cumulative time over the useful life of the device.

(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in 图7-1.

The window test points TP2 and TP3 shown in 图7-1 are intended to result in the worst case delta temperature. If a particular

application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(18) Window temperature is the highest temperature on the window edge shown in 图7-1. The locations of thermal test points TP2 and

TP3 in 图7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the

window edge to be at a higher temperature, that point should be used.

(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CT_ELR

(20) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

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0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50

90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45

100/0 95/5

D001

Micromirror Landed Duty Cycle

图6-1. Maximum Recommended Array Temperature –Derating Curve

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6.5 Thermal Information

DLP3010

FQK (LGA)

57 PINS

5.4

THERMAL METRIC⁽¹⁾

UNIT

Thermal resistance

Active area to test point 1 (TP1)⁽¹⁾

°C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the

DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by

the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy

falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the

device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS⁽³⁾

MIN

TYP

MAX UNIT

CURRENT

VDD = 1.95 V

60.5

I_DD

Supply current: VDD^{(4) (6)}

Supply current: VDDI^{(4) (6)}

Supply current: VOFFSET^{(5) (7)}

Supply current: VBIAS^{(5) (7)}

Supply current: VRESET⁽⁷⁾

VDD = 1.8 V

11.3

1.5

VDDI = 1.95 V

16.5

I_DDI

VDD = 1.8 V

VOFFSET = 10.5 V

VOFFSET = 10 V

VBIAS = 18.5 V

VBIAS = 18 V

2.2

I_OFFSET

0.6

I_BIAS

0.3

2.4

VRESET = –14.5 V

VRESET = –14 V

I_RESET

1.7

POWER⁽²⁾

P_DD

VDD = 1.95 V

118

Supply power dissipation: VDD^{(4) (6)}

Supply power dissipation: VDDI^{(4) (6)}

Supply power dissipation: VOFFSET^{(5) (7)}

Supply power dissipation: VBIAS^{(5) (7)}

VDD = 1.8 V

97.2

VDDI = 1.95 V

VDD = 1.8 V

P_DDI

VOFFSET = 10.5 V

VOFFSET = 10 V

VBIAS = 18.5 V

VBIAS = 18 V

P_OFFSET

P_BIAS

VRESET = –14.5 V

VRESET = –14 V

P_RESET

Supply power dissipation: VRESET⁽⁷⁾

Supply power dissipation: Total

P_TOTAL

LPSDR INPUT⁽⁸⁾

162.2

219

V_IH(DC)

V_IL(DC)

V_IH(AC)

V_IL(AC)

∆V_T

DC input high voltage⁽¹⁰⁾

0.7 × VDD

–0.3

VDD + 0.3

0.3 × VDD

VDD + 0.3

0.2 × VDD

0.4 × VDD

DC input low voltage⁽¹⁰⁾

AC input high voltage⁽¹⁰⁾

AC input low voltage⁽¹⁰⁾

Hysteresis ( V_T+–V_T–

Low–level input current

0.8 × VDD

–0.3

0.1 × VDD

)

See 图6-10

I_IL

VDD = 1.95 V; V_I= 0 V

VDD = 1.95 V; V_I= 1.95 V

–100

I_IH

100

High–level input current

LPSDR OUTPUT⁽⁹⁾

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6.6 Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

DC output high voltage

DC output low voltage

TEST CONDITIONS⁽³⁾

MIN

TYP

MAX UNIT

V_OH

V_OL

0.8 × VDD

I_OH= –2 mA

I_OL= 2 mA

0.2 × VDD

CAPACITANCE

Input capacitance LPSDR

ƒ= 1 MHz

C_IN

Input capacitance SubLVDS

Output capacitance

C_OUT

ƒ= 1 MHz; (720 × 160)

micromirrors

C_RESET

Reset group capacitance

200

220

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(2) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

(3) All voltage values are with respect to the ground pins (VSS).

(4) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than specified limit.

(5) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified limit.

(6) Supply power dissipation based on non–compressed commands and data.

(7) Supply power dissipation based on 3 global resets in 200 µs.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) LPSDR specification is for pin LS_RDATA.

(10) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC

Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

6.7 Timing Requirements

Device electrical characteristics are over 节6.4 unless otherwise noted.

MIN

NOM

MAX UNIT

LPSDR

t_r

Rise slew rate⁽¹⁾

Fall slew rate⁽¹⁾

V/ns

(30% to 80%) × VDD, see 图6-3

(70% to 20%) × VDD, see 图6-3

(20% to 80%) × VDD, see 图6-3

(80% to 20%) × VDD, see 图6-3

See 图6-2

t_ƒ

t_r

Rise slew rate⁽²⁾

Fall slew rate⁽²⁾

0.25

7.7

3.1

1.5

t_ƒ

t_c

Cycle time LS_CLK,

Pulse duration LS_CLK high

Pulse duration LS_CLK low

Setup time

8.3

t_W(H)

t_W(L)

t_su

50% to 50% reference points, see 图6-2

LS_WDATA valid before LS_CLK ↑, see 图6-2

LS_WDATA valid after LS_CLK ↑, see 图6-2

Setup time + hold time, see 图6-2

t _h

Hold time

t_WINDOW

Window time^{(1) (4)}

For each 0.25-V/ns reduction in slew rate below

1 V/ns, see 图6-5

t_DERATING

Window time derating^{(1) (4)}

0.35

SubLVDS

t_r

Rise slew rate

0.7

V/ns

20% to 80% reference points, see 图6-4

80% to 20% reference points, see 图6-4

See 图6-6

t_ƒ

Fall slew rate

t_c

Cycle time DCLK,

Pulse duration DCLK high

Pulse duration DCLK low

1.79

0.79

1.85

t_W(H)

t_W(L)

50% to 50% reference points, see 图6-6

D(0:3) valid before

DCLK ↑or DCLK ↓, see 图6-6

t_su

Setup time

D(0:3) valid after

DCLK ↑or DCLK ↓, see 图6-6

t _h

Hold time

t_WINDOW

Window time

0.3

Setup time + hold time, see 图6-6 and 图6-7

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6.7 Timing Requirements (continued)

Device electrical characteristics are over 节6.4 unless otherwise noted.

MIN

NOM

t_LVDS-

Power-up receiver⁽³⁾

2000

ENABLE+REFGEN

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in 图6-3.

(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in 图6-3.

(3) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

(4) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 ns to 3.7 ns.

w(L)

w(H)

LS_CLK

50%

LS_WDATA

50%

window

Low-speed interface is LPSDR and adheres to the 节6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low

Power Double Data Rate (LPDDR) JESD209B.

图6-2. LPSDR Switching Parameters

LS_CLK, LS_WDATA

DMD_DEN_ARSTZ

1.0 * VDD

0.8 * VDD

V_IH(AC)

V_IH(DC)

0.8 * VDD

0.7 * VDD

V_IL(DC)

V_IL(AC)

0.3 * VDD

0.2 * VDD

0.0 * VDD

t_r

t_f

t_r

t_f

图6-3. LPSDR Input Rise and Fall Slew Rate

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V_{DCLK_P}, V_{DCLK_N}

V_{D_P(0:7)}, V_{D_N(0:7)}

1.0 * V

0.8 * V

0.2 * V

0.0 * V

t_r

t_f

图6-4. SubLVDS Input Rise and Fall Slew Rate

V_{IH MIN}

LS_CLK Midpoint

V_{IL MAX}

t_SU

t_H

V_{IH MIN}

LS_WDATA Midpoint

V_{IL MAX}

t_WINDOW

V_{IH MIN}

Midpoint

LS_CLK

V_{IL MAX}

t_DERATING

t_H

t_SU

V_{IH MIN}

Midpoint

V_{IL MAX}

LS_WDATA

t_WINDOW

图6-5. Window Time Derating Concept

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w(H)

w(L)

DCLK_P

DCLK_N

50%

D_P(0:7)

D_N(0:7)

50%

window

图6-6. SubLVDS Switching Parameters

High Speed Training Scan Window

DCLK_P

DCLK_N

¼ t

D_P(0:7)

D_N(0:7)

Note: Refer to 节7.3.3 for details.

图6-7. High-Speed Training Scan Window

(V + V ) / 2

IP IN

DCLK_P , D_P(0:7)

DCLK_N , D_N(0:7)

SubLVDS

Receiver

图6-8. SubLVDS Voltage Parameters

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1.225V

= V

+ | 1/2 * V

ID max

SubLVDS max

CM max

= V

– | 1/2 * V

SubLVDS min

CM min

ID max

0.575V

图6-9. SubLVDS Waveform Parameters

DCLK_P , D_P(0:7)

ESD

Internal

Termination

SubLVDS

Receiver

DCLK_N , D_N(0:7)

ESD

图6-10. SubLVDS Equivalent Input Circuit

Not to Scale

T+

Δ V

T-

LS_CLK

LS_WDATA

图6-11. LPSDR Input Hysteresis

LS_CLK

LS_WDATA

Stop Start

t_PD

LS_RDATA

Acknowledge

图6-12. LPSDR Read Out

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Data Sheet Timing Reference Point

Device Pin

Tester Channel

Output Under Test

See 节7.3.4 for more information.

图6-13. Test Load Circuit for Output Propagation Measurement

6.8 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾.

PARAMETER

TEST CONDITIONS

C_L= 5 pF

MIN

TYP

MAX

UNIT

11.1

11.3

Output propagation, clock to Q, rising edge of

LS_CLK input to LS_RDATA output, see 图

6-12

t_PD

C_L= 10 pF

C_L= 85 pF

Slew rate, LS_RDATA

0.5

V/ns

Output duty cycle distortion, LS_RDATA

40%

60%

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

6.9 System Mounting Interface Loads

PARAMETER

MIN

NOM

MAX

125

UNIT

Electrical interface area, see 图6-14

Clamping and thermal interface area, see 图6-14

Maximum system mounting

interface load to be applied to the:

Electrical Interface Area

125 N Maximum

Clamping and Thermal Interface Area # 1

33.5 N Maximum

Clamping and Thermal Interface Area # 2

33.5 N Maximum

图6-14. System Interface Loads

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6.10 Micromirror Array Physical Characteristics

PARAMETER

VALUE

1280

720

UNIT

micromirrors

µm

Number of active columns

Number of active rows

See 图6-15

Micromirror (pixel) pitch

5.4

See 图6-16

Micromirror active array width

Micromirror active array height

Micromirror active border

6.912

3.888

Micromirror pitch × number of active columns; see 图6-15

Micromirror pitch × number of active rows; see 图6-15

Pond of micromirror (POM)⁽¹⁾

micromirrors/side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

Not To Scale

Width

Mirror 719

Mirror 718

Mirror 717

Mirror 716

Illumination

DMD Active Mirror Array

1280 Mirrors * 720 Mirrors

Mirror 3

Mirror 2

Mirror 1

Mirror 0

图6-15. Micromirror Array Physical Characteristics

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图6-16. Mirror (Pixel) Pitch

6.11 Micromirror Array Optical Characteristics

PARAMETER

Micromirror tilt angle

TEST CONDITIONS

MIN

NOM

MAX

UNIT

degree

DMD landed state⁽¹⁾

Micromirror tilt angle tolerance^{(2) (3) (4) (5)}

1.4

–1.4

Landed ON state

180

270

Micromirror tilt direction ^{(6) (7)}

degree

µs

Landed OFF state

Typical performance

Micromirror crossover time⁽⁸⁾

Micromirror switching time⁽⁹⁾

Bright pixel(s) in active area

Gray 10 Screen ⁽¹²⁾

(11)

Bright pixel(s) in the POM ⁽¹³⁾Gray 10 Screen ⁽¹²⁾

Image

Dark pixel(s) in the active

White Screen

micromirrors

performance⁽¹⁰⁾

area ⁽¹⁴⁾

Adjacent pixel(s) ⁽¹⁵⁾

Any Screen

Unstable pixel(s) in active

area ⁽¹⁶⁾

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result

in colorimetry variations, system efficiency variations, or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of

the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state

direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See 图6-17.

(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is

aligned with the +X Cartesian axis.

(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.

(9) The minimum time between successive transitions of a micromirror.

(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:

Test set degamma shall be linear

Test set brightness and contrast shall be set to nominal

The diagonal size of the projected image shall be a minimum of 20 inches

The projections screen shall be 1X gain

The projected image shall be inspected from a 38 inch minimum viewing distance

The image shall be in focus during all image quality tests

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(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels

(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:

Red = 10/255

Green = 10/255

Blue = 10/255

(13) POM definition: Rectangular border of off-state mirrors surrounding the active area

(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels

(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster

(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable

pixel appears to be flickering asynchronously with the image

(1279, 719)

Incident

Illumination

Light Path

Tilted Axis of

Pixel Rotation

On-State

Landed Edge

Off-State

Landed Edge

(0,0)

Off-State

Light Path

图6-17. Landed Pixel Orientation and Tilt

6.12 Window Characteristics

PARAMETER⁽³⁾

MIN

NOM

Corning Eagle XG

1.5119

MAX UNIT

Window material designation

Window refractive index

Window aperture⁽¹⁾

at wavelength 546.1 nm

See ⁽¹⁾

See ⁽²⁾

Illumination overfill⁽²⁾

Minimum within the wavelength range

420 nm to 680 nm. Applies to all angles

0° to 30° AOI.

Window transmittance, single-pass

through both surfaces and glass

97%

Average over the wavelength range 420

nm to 680 nm. Applies to all angles 30°

to 45° AOI.

Window transmittance, single-pass

through both surfaces and glass

(1) See the package mechanical characteristics for details regarding the size and location of the window aperture.

(2) The active area of the DLP3010 device is surrounded by an aperture on the inside of the DMD window surface that masks structures

of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating

the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The

illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux

level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light

on the outside of the active array may cause system performance degradation.

(3) See Optical Interface and System Image Quality Considerations for more information.

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6.13 Chipset Component Usage Specification

备注

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system

operating conditions exceeding limits described previously.

The DLP3010 is a component of one or more DLP^®chipsets. Reliable function and operation of the DLP3010

requires that it be used in conjunction with the other components of the applicable DLP chipset, including those

components that contain or implement TI DMD control technology. TI DMD control technology is the TI

technology and devices for operating or controlling a DLP DMD.

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7 Detailed Description

7.1 Overview

The DLP3010 is a 0.3-in diagonal spatial light modulator of aluminum micromirrors. Pixel array size is 1280

columns by 720 rows in a square grid pixel arrangement. The electrical interface is sub low voltage differential

signaling (SubLVDS) data.

DLP3010 is part of the chipset comprising of the DLP3010 DMD, DLPC3433 or DLPC3438 display controller and

DLPA200x/DLPA3000 PMIC/LED driver. To ensure reliable operation, DLP3010 DMD must always be used with

DLPC3433 or DLPC3438 display controller and DLPA200x/DLPA3000 PMIC/LED driver.

7.2 Functional Block Diagram

A. Details omitted for clarity.

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7.3 Feature Description

7.3.1 Power Interface

The power management IC, DLPA200x/DLPA3000, contains 3 regulated DC supplies for the DMD reset circuitry:

VBIAS, VRESET and VOFFSET, as well as the two regulated DC supplies for the DLPC3433 or DLPC3438

controller.

7.3.2 Low-Speed Interface

The low-speed interface handles instructions that configure the DMD and control reset operation. LS_CLK is the

low-speed clock, and LS_WDATA is the low-speed data input.

7.3.3 High-Speed Interface

The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high-speed

DDR transfer and compression techniques to save power and time. The high-speed interface is composed of

differential SubLVDS receivers for inputs, with a dedicated clock.

7.3.4 Timing

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. 图 6-13 shows an equivalent test load circuit for the output

under test. Timing reference loads are not intended as a precise representation of any particular system

environment or depiction of the actual load presented by a production test. System designers should use IBIS or

other simulation tools to correlate the timing reference load to a system environment. The load capacitance

value stated is only for characterization and measurement of AC timing signals. This load capacitance value

does not indicate the maximum load the device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC3433 or DLPC3438 controller. See the DLPC3430 or

DLPC3435 controller data sheet or contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.5.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device micromirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any

other light path, including undesirable flat-state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture

exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger

than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts

in the display border and/or active area could occur.

7.5.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display’s border and/or active area, which may require additional system apertures to control,

especially if the numerical aperture of the system exceeds the pixel tilt angle.

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7.5.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating

conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system

should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately

10% of the average flux level in the active area. Depending on the particular system’s optical architecture,

overfill light may have to be further reduced below the suggested 10% level in order to be acceptable.

7.6 Micromirror Array Temperature Calculation

TP3

Illumination

Direction

TP2

Off-state Light

Window Edge

(4 surfaces)

TP2

TP3

TP1

图7-1. DMD Thermal Test Points

Micromirror array temperature can be computed analytically from measurement points on the outside of the

package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat

load. The relationship between micromirror array temperature and the reference ceramic temperature is provided

by the following equations:

T_ARRAY= T_CERAMIC+ (Q_ARRAY× R_{ARRAY–TO–CERAMIC}

Q_ARRAY= Q_ELECTRICAL+ Q_ILLUMINATION

Q_ILLUMINATION= (C_L2W× SL)

)

(1)

(2)

(3)

• T_ARRAY= Computed DMD array temperature (°C)

• T_CERAMIC= Measured ceramic temperature (°C), TP1 location in 图7-1

• R_{ARRAY–TO–CERAMIC}= DMD package thermal resistance from array to outside ceramic (°C/W) specified in

Thermal Information

• Q_ARRAY= Total DMD power; electrical plus absorbed (calculated) (W)

• Q_ELECTRICAL= Nominal DMD electrical power dissipation (W)

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• C_L2W= Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below

• SL = Measured ANSI screen lumens (lm)

Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.1 W.

Absorbed optical power from the illumination source is variable and depends on the operating state of the

micromirrors and the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with

total projection efficiency through the projection lens from DMD to the screen of 87%.

The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral

efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and

16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00266

W/lm.

Sample Calculation for typical projection application:

1. T_CERAMIC= 55°C, assumed system measurement; see Recommended Operating Conditions for specification

limits.

2. SL = 300 lm

3. Q_ELECTRICAL= 0.100 W

4. CL2W = 0.00266 W/lm

5. Q_ARRAY= 0.100 + (0.00266 × 300) = 0.898 W

6. T_ARRAY= 55°C + (0.898 W × 5.4°C/W) = 59.84°C

7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the ON state versus the amount of time the same

micromirror is landed in the OFF state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the

time (and in the OFF state 0% of the time), whereas 0/100 would indicate that the pixel is in the OFF state 100%

of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)

always add to 100.

7.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric

landed duty cycle for a prolonged period of time can reduce the DMD’s usable life.

Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed

duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed

duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

7.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD temperature and landed duty cycle interact to affect the DMD’s usable life, and this

interaction can be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD’s

usable life. This is quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:

• All points along this curve represent the same usable life.

• All points above this curve represent lower usable life (and the further away from the curve, the lower the

usable life).

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• All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at

for a given long-term average landed duty cycle.

7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the landed duty cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel

will experience a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the pixel

will experience a 0/100 landed duty cycle.

Between the two extremes (ignoring for the moment color and any image processing that may be applied to an

incoming image), the landed duty cycle tracks one-to-one with the grayscale value, as shown in 表7-1.

表7-1. Grayscale Value

and Landed Duty Cycle

Grayscale

Value

Landed Duty

Cycle

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0/100

10/90

20/80

30/70

40/60

50/50

60/40

70/30

80/20

90/10

100/0

Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from

0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color

cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a

given primary must be displayed in order to achieve the desired white point.

During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:

Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% (4)

Blue_Scale_Value)

where

Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_% represent the percentage of the frame time that red, green,

and blue are displayed (respectively) to achieve the desired white point.

For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in

order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue

color intensities would be as shown in 表7-2.

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表7-2. Example Landed Duty Cycle for Full-Color

Pixels

Red Cycle

Percentage

Green Cycle

Percentage

Blue Cycle

Percentage

50%

20%

30%

Red Scale

Value

Green Scale

Blue Scale

Value

Landed Duty

Cycle

Value

100%

0/100

50/50

20/80

30/70

6/94

100%

12%

35%

7/93

60%

18/82

70/30

50/50

80/20

13/87

25/75

24/76

100/0

100%

12%

35%

60%

100%

12%

100%

The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the

DLP Controller DLPC3433/DLPC3438, the two functions which affect landed duty cycle are Gamma and

IntelliBright^™.

Gamma is a power function of the form Output_Level = A × Input_Level^Gamma, where A is a scaling factor that is

typically set to 1.

In the DLPC3430/DLPC3435 controller, gamma is applied to the incoming image data on a pixel-by-pixel basis.

A typical gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.

100

Gamma = 2.2

Input Level (%)

90 100

D002

图7-2. Example of Gamma = 2.2

From 图7-2, if the grayscale value of a given input pixel is 40% (before gamma is applied), then grayscale value

will be 13% after gamma is applied. Therefore, since gamma has a direct impact on displayed grayscale level of

a pixel, it also has a direct impact on the landed duty cycle of a pixel.

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The IntelliBright algorithms content adaptive illumination control (CAIC) and local area brightness boost (LABB)

also apply transform functions on the grayscale level of each pixel.

But while amount of gamma applied to every pixel (of every frame) is constant (the exponent, ^Gamma, is

constant), CAIC and LABB are both adaptive functions that can apply a different amounts of either boost or

compression to every pixel of every frame.

Consideration must also be given to any image processing which occurs before the DLPC3433 or DLPC3438

controller.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

CAUTION

The DLP3010 DMD has mandatory software requirements. Refer to Software Requirements for TI

DLP^®Pico^™TRP Digital Micromirror Devices application report for additional information.

The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two

directions, with the primary direction being into a projection or collection optic. Each application is derived

primarily from the optical architecture of the system and the format of the data coming into the DLPC3433/

DLPC3438 controller. The new high tilt pixel in the side illuminated DMD increases brightness performance and

enables a smaller system electronics footprint for thickness constrained applications. Applications of interest

include projection embedded in display devices like smartphones, tablets, cameras, and camcorders. Other

applications include wearable (near-eye) displays, battery powered mobile accessory, interactive display, low-

latency gaming display, and digital signage.

DMD power-up and power-down sequencing is strictly controlled by the DLPA200x/DLPA3000. Refer to Power

Supply Recommendations for power-up and power-down specifications. To ensure reliable operation, DLP3010

DMD must always be used with DLPC3433 or DLPC3438 display controller and DLPA200x/DLPA3000

PMIC/LED driver.

8.2 Typical Application

A common application when using the DLPC3433/DLPC3438 is for creating a pico-projector that can be used as

an accessory to a smartphone, tablet or a laptop. The DLPC3433/DLPC3438 in the pico-projector receives

images from a multimedia front end within the product as shown in the following figure.

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DC_IN

Charger

BAT

1.8V

...

2.3 V-5.5 V

Projector Module Electronics

DC Supplies

1.8 V VSPI

Other

Supplies

1.1 V

1.8 V

1.1 V

Reg

On/Off

VDD

SYSPWR

1.8 V

HDMI

Receiver

PROJ_ON

VLED

Curr

entS

ense

VGA

Keystone

Sensor

Triple

ADC

GPIO_8

(Normal Park)

PAD2005

FLASH

Front-End

Chip

SPI_0

SPI_1

RED

GREEN

BLUE

FLASH,

SDRAM

RESETZ

INTZ

- OSD

PARKZ

HOST_IRQ

BIAS, RST, OFS

- AutoLock

- Scaler

- uController

LED_SEL(2)

CMP_PWM

Illuminatio

nOptics

WPC

LABB

DPP3433/8

Keypad

Parallel I/F

CMP_OUT

DLP3010A

WVGA

720p DMD

DDR

Thermistor

I2C

SD Card

Reader, etc.

(optional)

Sub-LVDS DATA

CTRL

1.8 V

1.1 V

VIO

VCC_INTF

VCC_FLSH

Spare R/

W GPIO

VCORE

Included in DLP® Chip Set

Non-DLP components

图8-1. Typical Application Diagram

8.2.1 Design Requirements

A pico-projector is created by using a DLP chip set comprised of DLP3010 DMD, a DLPC3433/DLPC3438

controller and a DLPA200x/DLPA3000 PMIC/LED driver. The DLPC3433/DLPC3438 controller does the digital

image processing, the DLPA200x/DLPA3000 provides the needed analog functions for the projector, and

DLP3010 DMD is the display device for producing the projected image.

In addition to the three DLP chips in the chip set, other chips may be needed. At a minimum a Flash part is

needed to store the software and firmware to control the DLPC3433/DLPC3438 controller.

The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often

contained in three separate packages, but sometimes more than one color of LED die may be in the same

package to reduce the overall size of the pico-projector.

For connecting the DLPC3433/DLPC3438 controller to the multimedia front end for receiving images, parallel

interface is used. When the parallel interface is used, I2C should be connected to the multimedia front end for

sending commands to the DLPC3433/DLPC3438 controller and configuring the DLPC3433/DLPC3438 controller

for different features.

8.2.2 Detailed Design Procedure

For connecting together the DLPC3433/DLPC3438 controller, the DLPA200x/DLPA3000, and the DLP3010

DMD, see the reference design schematic. When a circuit board layout is created from this schematic a very

small circuit board is possible. An example small board layout is included in the reference design data base.

Layout guidelines should be followed to achieve a reliable projector.

The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical

OEM who specializes in designing optics for DLP projectors.

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8.2.3 Application Curve

As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the

brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white

screen lumens changes with LED currents is as shown in 图 8-2. For the LED currents shown, it’s assumed

that the same current amplitude is applied to the red, green, and blue LEDs.

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

500

1000

1500

Current (mA)

2000

2500

3000

D001

图8-2. Luminance vs Current

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and

VRESET. DMD power-up and power-down sequencing is strictly controlled by the DLPA200x devices.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to the prescribed power-up and power-down procedures may affect

device reliability.

VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-

up and power-down operations. Failure to meet any of the below requirements will result in a

significant reduction in the DMD’s reliability and lifetime. Refer to 图 9-2. VSS must also be

connected.

9.1 Power Supply Power-Up Procedure

• During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET

voltages are applied to the DMD.

• During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the

specified limit shown in Recommended Operating Conditions. Refer to 表9-1 and the Layout Example for

power-up delay requirements.

• During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have

settled at operating voltage.

• During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow

the requirements listed previously and in 图9-1.

9.2 Power Supply Power-Down Procedure

• Power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be

supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.

• During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement

that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended

Operating Conditions (refer to Note 2 for 图9-1).

• During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in

Recommended Operating Conditions.

• During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements listed previously and in 图9-1.

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9.3 Power Supply Sequencing Requirements

DLP Display Controller and

PMIC control start of DMD

operation

DRAWING NOT TO SCALE.

DLP Display Controller and PMIC

disable VBIAS, VOFFSET and

VRESET

Mirror Park

Sequence

DETAILS OMITTED FOR CLARITY.

Note 4

Power Off

VDD / VDDI

VSS

VBIAS

VDD ≤ VBIAS < 6 V

VBIAS < 4 V

VSS

VOFFSET

VDD ≤ VOFFSET < 6 V

VOFFSET < 4 V

VOFFSET

VSS

VRESET < 0.5 V

VSS

VRESET > - 4 V

VRESET

VDD

VRESET

VDD

DMD_DEN_ARSTZ

VSS

INITIALIZATION

VDD

LS_CLK

VSS

LS_WDATA

VID

D_P(0:7), D_N(0:7)

DCLK_P, DCLK_N

VSS

A. Refer to 表9-1 and 图9-2 for critical power-up sequence delay requirements.

B. To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified in 节6.4. OEMs may find that the

most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during

power-down. Refer to 表9-1 and 图9-2 for power-up delay requirements.

C. To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified limit shown in 节6.4.

D. When system power is interrupted, the DLPA200x initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after

the Micromirror Park Sequence.

E. Drawing is not to scale and details are omitted for clarity.

图9-1. Power Supply Sequencing Requirements (Power Up and Power Down)

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表9-1. Power-Up Sequence Delay Requirement

PARAMETER

MIN

MAX UNIT

t_DELAY

V_OFFSET

V_BIAS

Delay requirement from VOFFSET power up to VBIAS power up

Supply voltage level during power–up sequence delay (see 图9-2)

12 V

VOFFSET

8 V

VDD ≤ VOFFSET < 6 V

4 V

VSS

0 V

t_DELAY

20 V

16 V

12 V

8 V

VBIAS

VDD ≤ VBIAS < 6 V

4 V

VSS

0 V

A. Refer to 表9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.

图9-2. Power-Up Sequence Delay Requirement

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10 Layout

10.1 Layout Guidelines

There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board

connector to a flex cable. Flex cable provides the interface of data and CTRL signals between the DLPC343x

controller and the DLP3010 DMD. For detailed layout guidelines refer to the layout design files. Some layout

guideline for the flex cable interface with DMD are:

• Match lengths for the LS_WDATA and LS_CLK signals.

• Minimize vias, layer changes, and turns for the HS bus signals. Refer 图10-1.

• Minimum of two 100-nF decoupling capacitor close to VBIAS. Capacitor C6 and C7 in 图10-1.

• Minimum of two 100-nF decoupling capacitor close to VRST. Capacitor C9 and C8 in 图10-1.

• Minimum of two 220-nF decoupling capacitor close to VOFS. Capacitor C5 and C4 in 图10-1.

• Minimum of four 100-nF decoupling capacitor close to Vcci and Vcc. Capacitor C1, C2, C3 and C10 in 图

10-1.

10.2 Layout Example

图10-1. Power Supply Connections

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11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.1.2 Device Nomenclature

DLP3010A FQK

Package Type

Device Descriptor

图11-1. Part Number Description

11.1.3 Device Markings

The device marking includes the legible character string GHJJJJK DLP3010AFQK. GHJJJJK is the lot trace

code. DLP3010AFQK is the device part number.

Lot Trace Code

GHJJJJK

DLP3010AFQK

Part Marking

图11-2. DMD Marking

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

表11-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

DLP3010A

DLPC3433

DLPC3438

DLPA2005

DLPA3000

Click here

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

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11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

IntelliBright^™, Pico^™, and TI E2E^™are trademarks of Texas Instruments.

DLP^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

28-Sep-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DLP3010AFQK

ACTIVE

CLGA

FQK

120

RoHS & Green

NI/AU

N / A for Pkg Type

0 to 70

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

DWG NO.

2512014

REVISIONS

NOTES UNLESS OTHERWISE SPECIFIED:

REV

DESCRIPTION

DATE

6/6/2013

6/17/2013

4/8/2020

ECO 2133835: INITIAL RELEASE

ECO 2134093: CORRECT WINDOW THK TOL, ZONE B6

ECO 2186947: ADD APERTURE SLOTS PICTORIALLY

BMH

PPC

DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.

ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION

TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.

BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.

NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC,

AS SHOWN IN SECTION A-A.

ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEW C

(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.

ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.

DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING

TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).

WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED

FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,

TO SUPPORT MECHANICAL LOADS.

1.1760.05

4X (R0.2)

0.3

0.1

90° 1°

(ILLUMINATION

DIRECTION)

4X R0.40.1

2X 2.50.075

(2.5)

1.25

3.5

0.2

0.1

0.2

0.1

2.25

0.2

0.1

(1)

0.8

16.4 0.08

0.3

0.1

18.2

(OFF-STATE

DIRECTION)

5 6

2X ENCAPSULANT

1.1 0.05

1.403 0.077

(2.183)

3 SURFACES INDICATED

IN VIEW B (SHEET 2)

0.038A

0.02D

1 8



0.780.063

ACTIVE ARRAY

1.60.1

(1.6)

(2.5)

0.4 MIN

TYP.

(SHEET 3)

0 MIN TYP.

DATE

DRAWN

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN MILLIMETERS

TOLERANCES:

TEXAS

6/6/2013

6/7/2013

6/6/2013

6/10/2013

6/6/2013

B. HASKETT

ENGINEER

B. HASKETT

QA/CE

INSTRUMENTS

Dallas Texas

ANGLES 1

TITLE

SECTION A-A

NOTCH OFFSETS

ICD, MECHANICAL, DMD,

.3 720p SERIES 245

(FQK PACKAGE)

2 PLACE DECIMALS 0.25

1 PLACE DECIMALS 0.50

DIMENSIONAL LIMITS APPLY BEFORE PROCESSES

INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME

Y14.5M-1994

P. KONRAD

S. SUSI

THIRD ANGLE

PROJECTION

DWG NO

REV

SIZE

0314DA

USED ON

REMOVE ALL BURRS AND SHARP EDGES

PARENTHETICAL INFORMATION FOR REFERENCE ONLY

S. CROFF

APPROVED

R. LONG

2512014

NEXT ASSY

SCALE

SHEET

APPLICATION

20:1

INV11-2006a

DWG NO.

7.2

2512014

2X (1)

2X 1.176

2X (0.8)

2X 16.4

4X 1.5

1.25

2.5

4X (2)

(1.1)

VIEW B

DATUMS A, B, C, AND E

1.176

16.4

(FROM SHEET 1)

(2.5)

1.25

3.6

VIEW C

ENCAPSULANT MAXIMUM X/Y DIMENSIONS

(FROM SHEET 1)

2X 0 MIN

VIEW D

ENCAPSULANT MAXIMUM HEIGHT

DWG NO

REV

SIZE

DRAWN

DATE

TEXAS

6/6/2013

2512014

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

DWG NO.

2512014

(6.912)

ACTIVE ARRAY

6.4490.075

4X (0.108)

0.9710.05

0.193 0.0635

(6.15)

WINDOW

(3.888)

ACTIVE ARRAY

4.319 0.0635

(ILLUMINATION

DIRECTION)

(2.5)

(4.512)

APERTURE

5.1790.05

1.25

1.784 0.075

0.4240.0635

2.961 0.05

7.1390.0635

(7.563)

APERTURE



8.815 0.05

(11.776)

WINDOW

VIEW E

WINDOW AND ACTIVE ARRAY

(FROM SHEET 1)

57X LGA PADS

0.52±0.05 X 0.52±0.05

12X TEST PADS

(0.52 0.05)

0.2ABC



0.1A

BACK INDEX MARK

(42°)

TYP.

(42°)

TYP.

17 18

(0.15) TYP.

(0.075) TYP.

1.25

(2.5)

2 X 0.7424

= 1.4848

0.7424

2X (0.7424)

(0.068) TYP.

(42°) TYP.



(0.7424)

DETAIL G

2.874

18 X 0.7424 = 13.3632

DETAIL F

APERTURE LEFT EDGE

APERTURE RIGHT EDGE

SCALE 60 : 1

VIEW H-H

SCALE 60 : 1

BACK SIDE METALLIZATION

(FROM SHEET 1)

DWG NO

REV

SIZE

DRAWN

DATE

6/6/2013

TEXAS

2512014

B. HASKETT

INSTRUMENTS

Dallas Texas

SCALE

SHEET

INV11-2006a

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