DLP471NE [TI]
0.47-inch, 1080p, HSSI DLP® digital micromirror device (DMD);
| 型号： | DLP471NE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.47-inch, 1080p, HSSI DLP® digital micromirror device (DMD) |
| 文件： | 总48页 (文件大小：2193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLP471NE
ZHCSM84B –SEPTEMBER 2020 –REVISED MAY 2022
DLP471NE 0.47 全高清DMD
1 特性
3 说明
• 0.47 英寸对角线微镜阵列
DLP471NE 数字微镜器件 (DMD) 是一款数控微机电系
统 (MEMS) 空间照明调制器 (SLM)，可用于实现高亮
的全高清显示系统。TI DLP® 产品 0.47 英寸全高清
(1080p) 芯片组由 DMD、DLPC7540 显示控制器以及
DLPA100 电源和电机驱动器组成。芯片组的外形紧
凑，为体型小巧的全高清显示提供完整的系统解决方
案。
– 1080p (1920 × 1080) 显示分辨率
– 5.4µm 微镜间距
– ±17° 微镜倾斜度（相对于平坦表面）
– 底部照明
• 高速串行接口(HSSI) 输入数据总线
• 支持全高清（高达240Hz）
• 由DLPC7540 显示控制器、DLPA100 电源管理和
电机驱动器IC 支持激光荧光、LED、RGB 激光和
灯泡运行
DMD 生态系统还提供现成的资源，帮助用户加快设计
周期。这些资源包括 量产就绪型光学模块、光学模块
制造商和设计公司。
2 应用
访问 TI DLP 显示技术入门页，了解有关使用 DMD 开
始设计的更多信息。
• 智能投影仪
• 企业投影仪
器件信息
器件型号(1)
DLP471NE
封装尺寸（标称值）
封装
FYN (149)
32.2mm × 22.3mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
LS Interface
HSSI Macro A Data Pairs
DMD DCLKA
8
8
HSSI Macro B Data Pairs
DMD DCLKB
DLPC7540
DLP471NE
HSSI DMD
VOFFSET
DMD Power Enable
Display Controller
Power
Management
TPS65145
VBIAS
3.3 V
VRESET
VREG
12 V
1.8 V
VREG
DMD VDD Enable
I2C
Temperature
TMP411
2
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS190
DLP471NE
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ZHCSM84B –SEPTEMBER 2020 –REVISED MAY 2022
Table of Contents
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 26
8 Application and Implementation..................................29
8.1 Application Information............................................. 29
8.2 Typical Application.................................................... 29
8.3 Temperature Sensor Diode.......................................32
9 Power Supply Recommendations................................34
9.1 DMD Power Supply Power-Up Procedure................34
9.2 DMD Power Supply Power-Down Procedure........... 34
10 Layout...........................................................................36
10.1 Layout Guidelines................................................... 36
10.2 Impedance Requirements.......................................36
10.3 Layers..................................................................... 36
10.4 Trace Width, Spacing..............................................37
10.5 Power......................................................................37
10.6 Trace Length Matching Recommendations............ 38
11 Device and Documentation Support..........................39
11.1 第三方产品免责声明................................................39
11.2 Device Support........................................................39
11.3 Documentation Support.......................................... 40
11.4 Receiving Notification of Documentation Updates..40
11.5 支持资源..................................................................40
11.6 Trademarks............................................................. 40
11.7 Electrostatic Discharge Caution..............................40
11.8 术语表..................................................................... 40
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 Storage Conditions..................................................... 8
6.3 ESD Ratings............................................................... 8
6.4 Recommended Operating Conditions.........................8
6.5 Thermal Information..................................................10
6.6 Electrical Characteristics...........................................10
6.7 Switching Characteristics..........................................12
6.8 Timing Requirements................................................13
6.9 System Mounting Interface Loads............................ 17
6.10 Micromirror Array Physical Characteristics.............18
6.11 Micromirror Array Optical Characteristics............... 19
6.12 Window Characteristics.......................................... 21
6.13 Chipset Component Usage Specification............... 21
7 Detailed Description......................................................22
7.1 Overview...................................................................22
7.2 Functional Block Diagram.........................................22
7.3 Feature Description...................................................23
7.4 Device Functional Modes..........................................23
7.5 Optical Interface and System Image Quality
Considerations............................................................ 23
7.6 Micromirror Array Temperature Calculation.............. 24
Information.................................................................... 41
12.1 Package Option Addendum....................................42
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (September 2021) to Revision B (May 2022)
Page
• 根据最新的德州仪器(TI) 和行业数据表标准对本文档进行了更新.......................................................................1
• Updated the definition of tDELAY2 and fixed a typo in tDELAY3 units in 表9-1 .................................................... 34
• Updated 图9-1 ................................................................................................................................................ 34
Changes from Revision * (September 2020) to Revision A (June 2021)
Page
• Updated minimum value of VID | CLK 节6.4 ..................................................................................................... 8
• Updated ILLUV value and wavelength range in 节6.4 .......................................................................................8
• Updated table header with package information in 节6.5 ...............................................................................10
• Put in separate minimum eye opening parameters for data and clock 节6.6 ................................................. 10
• Split rise and fall time for HSSI clock and data signals into separate lines in 节6.8 .......................................13
• Corrected typo in 图6-8 ...................................................................................................................................13
• Updated table in 节6.12 ..................................................................................................................................21
• Corrected a typo in 节7.2 ................................................................................................................................22
• Corrected typo in 节7.7.4.................................................................................................................................26
• Added pin connection conditions for when the temp sensor is not used in 节8.3. ..........................................32
• Merged Table 9-1 and Table 9-2 into a new 表9-1 ..........................................................................................34
• Updated table references to reflect Table 9-2 was merged into Table 9-1 in 节9.1 ........................................ 34
• Updated table references to reflect Table 9-2 was merged into Table 9-1 and fixed typos in 节9.2 ...............34
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• Updated 图9-1 ................................................................................................................................................ 34
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5 Pin Configuration and Functions
1
3
5
7
9
11 13 15 17 19
12 14 16 18 20
2
4
6
8
10
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
图5-1. FYN Package 149-Pin PGA Bottom View
CAUTION
Properly manage the layout and the operation of signals identified in the Pin Functions table to make sure there is reliable,
long-term operation of the 0.47”Full HD S451 DMD. Refer to the PCB Design Requirements for TI DLP TRP Digital
Micromirror Devices application report for specific details and guidelines before designing the board.
表5-1. Pin Functions
PIN
TRACE
LENGTH (mm)
INPUT-OUTPUT(1)
DESCRIPTION
NAME
D_AP(0)
No.
J1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
16.24427
16.24426
16.39699
16.39691
15.58905
15.58908
14.98471
14.9844
High–speed differential data pair lane A0
High–speed differential data pair lane A0
High–speed differential data pair lane A1
High–speed differential data pair lane A1
High–speed differential data pair lane A2
High–speed differential data pair lane A2
High–speed differential data pair lane A3
High–speed differential data pair lane A3
High–speed differential data pair lane A4
High–speed differential data pair lane A4
High–speed differential data pair lane A5
High–speed differential data pair lane A5
High–speed differential data pair lane A6
High–speed differential data pair lane A6
High–speed differential data pair lane A7
D_AN(0)
D_AP(1)
D_AN(1)
D_AP(2)
D_AN(2)
D_AP(3)
D_AN(3)
D_AP(4)
D_AN(4)
D_AP(5)
D_AN(5)
D_AP(6)
D_AN(6)
D_AP(7)
H1
G1
F1
F2
E2
D2
C2
A3
A4
A5
A6
A7
A8
A9
12.89101
12.89101
10.57206
10.57242
8.48593
8.48702
6.63434
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表5-1. Pin Functions (continued)
PIN
TRACE
LENGTH (mm)
INPUT-OUTPUT(1)
DESCRIPTION
NAME
D_AN(7)
No.
A10
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
6.63441
15.53899
15.53868
4.52398
4.52368
6.4103
High–speed differential data pair lane A7
High–speed differential clock A
DCLK_AP
DCLK_AN
D_BP(0)
C1
D1
High–speed differential clock A
A11
A12
A13
A14
A15
A16
A18
A19
D19
C19
H20
J20
D20
E20
F20
G20
B17
B18
T10
R11
R9
High–speed differential data pair lane B0
High–speed differential data pair lane B0
High–speed differential data pair lane B1
High–speed differential data pair lane B1
High–speed differential data pair lane B2
High–speed differential data pair lane B2
High–speed differential data pair lane B3
High–speed differential data pair lane B3
High–speed differential data pair lane B4
High–speed differential data pair lane B4
High–speed differential data pair lane B5
High–speed differential data pair lane B5
High–speed differential data pair lane B6
High–speed differential data pair lane B6
High–speed differential data pair lane B7
High–speed differential data pair lane B7
High–speed differential clock B
D_BN(0)
D_BP(1)
D_BN(1)
6.40894
8.78102
8.78364
12.05827
12.06154
11.04817
11.0479
14.54976
14.54991
11.67363
11.67598
12.33442
12.33409
10.22973
10.22551
7.8047
D_BP(2)
D_BN(2)
D_BP(3)
D_BN(3)
D_BP(4)
D_BN(4)
D_BP(5)
D_BN(5)
D_BP(6)
D_BN(6)
D_BP(7)
D_BN(7)
DCLK_BP
DCLK_BN
LS_WDATA_P
LS_WDATA_N
LS_CLK_P
LS_CLK_N
High–speed differential clock B
LVDS data
LVDS data
0.64391
8.20952
7.35885
LVDS CLK
R10
LVDS CLK
LS_RDATA_A_B
ISTA
T13
O
LVCMOS output
2.01174
BIST_B
T12
B20
R14
O
O
O
LVCMOS output
Analog test mux
Digital test mux
2.20006
10.74435
2.25459
AMUX_OUT
DMUX_OUT
DMD_DEN_AR
STZ
T11
I
ARSTZ
2.00365
TEMP_N
TEMP_P
R8
R7
I
I
Temp diode N
Temp diode P
9.03231
11.38391
B13, B7, C18,
E3, H3, J2, K3,
L2, L19, M1, M2,
N3, N19, P2,
P18, R3, R5,
R12, R17, R19,
T2, T4, T6, T8,
T18
VDD
P
Digital core supply voltage
Plane
B11, B16, B4,
B9, C20, D3,
E18, G2, G19
VDDA
P
HSSI supply voltage
Plane
VRESET
VBIAS
B3, R1
E1, P1
P
P
Supply voltage for negative bias of micromirror reset signal
Supply voltage for positive bias of micromirror reset signal
Plane
Plane
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ZHCSM84B –SEPTEMBER 2020 –REVISED MAY 2022
表5-1. Pin Functions (continued)
PIN
TRACE
LENGTH (mm)
INPUT-OUTPUT(1)
DESCRIPTION
NAME
No.
A20, B2, T1,
T20
VOFFSET
P
Supply voltage for HVCMOS logic, stepped up logic level
Plane
A17, B10, B14,
B6, D18, F3,
F19, J3, K19,
K2, L1, L3, M3,
N2, N18, N20,
P3, P20, R2, R4,
R6, R13, R20,
T5, T7, T16,
VSS
G
G
Ground
Plane
T17, T19
B12, B15, B19,
B5, B8, C3, E19,
G3, H2, H19,
K1, N1, P19,
R18, T3, T9
VSSA
N/C
Ground
Plane
F18, G18, H18,
J18, J19, K18,
K20, L18, L20,
M18, M19, M20,
R15, R16, T14,
T15
No connect
(1) I=Input, O=output, P=Power, G=Ground, NC = No Connect
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6 Specifications
6.1 Absolute Maximum Ratings
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not
imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating
Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
MIN
MAX UNIT
SUPPLY VOLTAGE
Supply voltage for LVCMOS core logic and LVCMOS low speed interface
(LSIF)(1)
VDD
2.3
V
–0.5
VDDA
Supply voltage for high speed serial interface (HSSI) receivers(1)
Supply voltage for HVCMOS and micromirror electrode(1) (2)
Supply voltage for micromirror electrode(1)
2.2
11
V
V
V
V
V
V
V
–0.3
–0.5
–0.5
–15
VOFFSET
VBIAS
19
0.5
0.3
11
VRESET
Supply voltage for micromirror electrode(1)
Supply voltage delta (absolute value)(3)
| VDDA –VDD
|
Supply voltage delta (absolute value)(4)
| VBIAS –VOFFSET
|
Supply voltage delta (absolute value)(5)
34
| VBIAS –VRESET
|
INPUT VOLTAGE
Input voltage for other inputs –LSIF and LVCMOS(1)
Input voltage for other inputs –HSSI(1) (6)
–0.5
–0.2
2.45
V
V
VDDA
LOW SPEED INTERFACE (LSIF)
fCLOCK LSIF clock frequency (LS_CLK)
130 MHz
| VID
IID
|
LSIF differential input voltage magnitude(6)
810
10
mV
mA
LSIF differential input current
HIGH SPEED SERIAL INTERFACE (HSSI)
fCLOCK HSSI clock frequency (DCLK)
1.65 GHz
| VID
| VID
|
|
HSSI differential input voltage magnitude Data Lane(6)
HSSI differential input voltage magnitude Clock Lane(6)
700
700
mV
mV
ENVIRONMENTAL
Temperature, operating(7)
0
90
90
°C
°C
TWINDOW and TARRAY
Temperature, non-operating(7)
–40
Absolute temperature delta between any point on the window edge and the
ceramic test point TP1(8)
|TDELTA
TDP
|
30
81
°C
°C
Dew point temperature, operating and non–operating (noncondensing)
(1) All voltage values are with respect to the ground terminals (VSS). The following required power supplies must be connected for proper
DMD operation: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable absolute voltage difference between VDDA and VDD may result in excessive current draw.
(4) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS and HSSI
differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(7) The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the
window edge as defined in 图7-1. The locations of thermal test points TP2, TP3, TP4 and TP5 in 图7-1 are intended to measure the
highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,
that point should be used.
(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.
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6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
MIN
MAX
UNIT
°C
TDMD
DMD temperature
80
28
36
–40
TDP-AVG
TDP-ELR
CTELR
Average dew point temperature, non-condensing(1)
Elevated dew point temperature range, non-condensing(2)
Cumulative time in elevated dew point temperature range
°C
28
°C
24 months
(1) The average temperature over time (including storage and operating temperatures) that the device is not in the elevated dew point
temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
6.3 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the
device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended
Operating Conditions. No level of performance is implied when operating the device above or below the Recommended
Operating Conditions limits.
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGES(1) (2)
Supply voltage for LVCMOS core logic and low speed
interface (LSIF)
VDD
1.71
1.8
1.95
V
VDDA
Supply voltage for high speed serial interface (HSSI) receivers
Supply voltage for HVCMOS and micromirror electrode(3)
Supply voltage for micromirror electrode
Supply voltage for micromirror electrode
Supply voltage delta, absolute value(4)
1.71
9.5
1.8
10
1.95
10.5
V
V
V
V
V
VOFFSET
VBIAS
17.5
18
18.5
VRESET
–14.5
–14
–13.5
0.3
| VDDA –VDD
|
| VBIAS –VOFFSET
|
Supply voltage delta, absolute value(5)
Supply voltage delta, absolute value
|
10.5
33
V
V
| VBIAS –VRESET
LVCMOS INPUT
VIH
VIL
High level input voltage(6)
Low level input voltage(6)
0.7 × VDD
V
V
0.3 × VDD
LOW SPEED SERIAL INTERFACE (LSIF)
fCLOCK
DCDIN
LSIF clock frequency (LS_CLK)(7)
108
44%
150
575
700
90
120
350
130
56%
440
MHz
LSIF duty cycle distortion (LS_CLK)
LSIF differential input voltage magnitude(7)
LSIF voltage(7)
| VID
|
mV
mV
mV
Ω
VLVDS
VCM
ZLINE
ZIN
1520
1300
110
Common mode voltage(7)
900
100
100
Line differential impedance (PWB/trace)
Internal differential termination resistance
80
120
Ω
HIGH SPEED SERIAL INTERFACE (HSSI)
fCLOCK
HSSI clock frequency (DCLK)(8)
1.2
1.6
GHz
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6.4 Recommended Operating Conditions (continued)
Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the
device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended
Operating Conditions. No level of performance is implied when operating the device above or below the Recommended
Operating Conditions limits.
MIN
44%
100
295
200
200
TYP
MAX
56%
600
600
800
800
UNIT
DCDIN
HSSI duty cycle distortion (DCLK)
50%
| VID | Data
| VID | CLK
VCMDC Data
VCMDC CLK
HSSI differential input voltage magnitude data lane(8)
HSSI differential input voltage magnitude Clock lane(8)
Input common mode voltage (DC) data lane(8)
Input common mode voltage (DC) Clk lane(8)
mV
mV
mV
mV
600
600
AC peak to peak (ripple) on common mode voltage of data
lane and Clock lane(8)
VCMACp-p
100
mV
ZLINE
Line differential impedance (PWB/trace)
100
100
Ω
Ω
ZIN
Internal differential termination resistance (RXterm
)
80
120
ENVIRONMENTAL
Array temperature, long–term operational(9) (10) (11) (12) (13)
Array temperature, short-term operational, 500 hr max(10) (14)
Window temperature, operational(15)
10
0
40 to 70
10
°C
°C
°C
TARRAY
TWINDOW
85
Absolute temperature delta between any point on the window
edge and the ceramic test point TP1(16)
|TDELTA
|
14
°C
Average dew point temperature (non–condensing)(17)
Elevated dew point temperature range (non-condensing)(18)
Cumulative time in elevated dew point temperature range
Illumination marginal ray angle(19)
TDP-AVG
TDP-ELR
CTELR
ILLθ
28
36
°C
°C
28
24 months
55 degrees
LAMP ILLUMINATION
ILLUV
ILLVIS
ILLIR
Illumination wavelength < 395 nm(9)
0.68
2
mW/cm2
W/cm2
Illumination wavelengths between 395 nm and 800 nm(13)
36.8
Illumination wavelength > 800 nm
10 mW/cm2
SOLID STATE ILLUMINATION
ILLUV
ILLVIS
ILLIR
Illumination wavelength < 410 nm(9)
3
mW/cm2
Illumination wavelengths between 410 nm and 800 nm(13)
44.9 W/cm2
10 mW/cm2
Illumination wavelength > 800 nm
(1) All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
(2) All voltage values are with respect to the VSS ground pins.
(3) VOFFSET supply transients must fall within specified max voltages.
(4) To prevent excess current, the supply voltage delta | VDDA –VDD | must be less than specified limit.
(5) To prevent excess current, the supply voltage delta | VBIAS –VOFFSET | must be less than specified limit.
(6) LVCMOS input pin is DMD_DEN_ARSTZ.
(7) See the low speed interface (LSIF) timing requirements in Timing Requirements.
(8) See the high speed serial interface (HSSI) timing requirements in Timing Requirements.
(9) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination
reduces device lifetime.
(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point
(TP1) shown in 图7-1 and the package thermal resistance using the Micromirror Array Temperature Calculation.
(11) Per 图6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty
cycle.
(12) Long-term is defined as the usable life of the device.
(13) The maximum optical power that can be incident on the DMD is limited by the maximum opical power density and the micromirror
array temperature
(14) Short-term is the total cumulative time over the useful life of the device.
(15) The locations of thermal test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to measure the highest window edge
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temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular
application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in 图
7-1. The window test points TP2, TP3, TP4, and TP5 shown in 图7-1 are intended to result in the worst case delta temperature. If a
particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.
(17) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.
(18) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR
.
(19) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including pond of micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily
been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not
been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)
will contribute to thermal limitations described in this document, and may negatively affect lifetime.
80
70
60
50
40
30
0/100
100/0
5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
65/35
95/5
90/10
85/15
80/20
75/25
70/30
60/40
55/45
50/50
Micromirror Landed Duty Cycle
图6-1. Maximum Recommended Array Temperature—Derating Curve
6.5 Thermal Information
DLP471NE
FYP PACKAGE
149 PINS
THERMAL METRIC
Unit
Thermal Resistance, active area to test point 1 (TP1)(1)
0.8
°C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the DMD within the temperature range specified in 节6.4. The total heat load on the DMD is largely driven by the incident
light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical
power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear
aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER (1) (2)
CURRENT –TYPICAL
IDD Supply current VDD
TEST CONDITIONS (1)
MIN
TYP
MAX UNIT
(3)
800
1200 mA
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6.6 Electrical Characteristics (continued)
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER (1) (2)
TEST CONDITIONS (1)
MIN
TYP
1000
500
20
MAX UNIT
1200 mA
600 mA
25 mA
4.0 mA
mA
(3)
IDDA
Supply current VDDA
Supply current VDDA
(3)
IDDA
Single macro mode
(4) (5)
IOFFSET
IBIAS
Supply current VOFFSET
(4) (5)
Supply current VBIAS
Supply current VRESET
2.5
(5)
IRESET
-9.3
-6.9
POWER –TYPICAL
(3)
PDD
Supply power dissipation VDD
1440
1620
900
2437.5 mW
2340 mW
1170 mW
(3)
(3)
PDDA
Supply power dissipation VDDA
Supply power dissipation VDDA
PDDA
single macro mode
(4) (5)
POFFSET
Supply power dissipation VOFFSET
230
367.5 mW
70.3 mW
(4) (5)
PBIAS
Supply power dissipation VBIAS
Supply power dissipation VRESET
Supply power dissipation Total
43.2
107.8
3441
(5)
PRESET
152.25 mW
5367.55 mW
PTOTAL
LVCMOS INPUT
IIL
Low level input current (6)
High level input current (6)
VDD = 1.95 V, VI = 0 V
nA
–100
IIH
VDD = 1.95 V, VI = 1.95 V
135 µA
LVCMOS OUTPUT
VOH
VOL
DC output high voltage (7)
DC output low voltage (7)
IOH = -2 mA
IOL = 2 mA
0.8 x VDD
V
0.2 x VDD
V
RECEIVER EYE CHARACTERISTICS
Minimum data eye opening (8) (9)
100
295
600 mV
600 mV
600 mV
A1
Minimum clock eye opening (8) (9)
Maximum data signal swing (8) (9)
Maximum data eye closure (8)
Maximum data eye closure (8)
A2
X1
X2
0.275
UI
UI
0.4
20
Drift between Clock and Data between
Training Patterns
| tDRIFT
|
ps
CAPACITANCE
CIN
Input capacitance LVCMOS
f = 1 MHz
f = 1 MHz
10 pF
20 pF
Input capacitance LSIF (low speed
interface)
CIN
Input capacitance HSSI (high speed serial
interface)
CIN
f = 1 MHz
f = 1 MHz
20 pF
10 pF
COUT
Output capacitance
(1) All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta | VDDA –VDD | must be less than specified limit.
(4) To prevent excess current, the supply voltage delta | VBIAS –VOFFSET | must be less than specified limit.
(5) Supply power dissipation based on 3 global resets in 200 µs.
(6) LVCMOS input specifications are for pin DMD_DEN_ARSTZ.
(7) LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.
(8) Refer to 图6-11, Receiver Eye Mask (1e-12 BER).
(9) Defined in Recommended Operating Conditions.
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6.7 Switching Characteristics
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Output propagation, Clock to Q (C2Q), rising edge of
LS_CLK (differential clock signal) input to LS_RDATA
output.(1)
CL = 5 pF
11.1
11.3
ns
ns
tpd
CL = 10 pF
Slew rate, LS_RDATA
20%-80%, CL <10pF
0.5
V/ns
Output duty cycle distortion, LS_RDATA_A and
LS_RDATA_B
50-(C2Q rise - C2Q
fall )*130e6*100
40%
60%
(1) See Switching Characteristics.
LS_CLK_P
1
0
1
0
1
0
1
0
1
0
LS_CLK_N
1 period
LS_WDATA_P
LS_WDATA_N
Stop (1)
Start (0)
tPD
LS_RDATA_A
BIST_A
Acknowledge
图6-2. Switching Characteristics
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6.8 Timing Requirements
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LVCMOS
tr
tf
Rise time(1)
Fall time(1)
20% to 80% reference points
25
25
ns
ns
80% to 20% reference points
LOW SPEED INTERFACE (LSIF)
tr
Rise time(2)
20% to 80% reference points
450
450
ps
ps
ns
ns
tf
Fall time(2)
80% to 20% reference points
tW(H)
tW(L)
Pulse duration high(3)
Pulse duration low(3)
LS_CLK. 50% to 50% reference points
LS_CLK. 50% to 50% reference points
3.1
3.1
LS_WDATA valid before rising edge of LS_CLK
(differential)
tsu
th
Setup time(4)
Hold time(4)
1.5
1.5
ns
ns
LS_WDATA valid after rising edge of LS_CLK
(differential)
HIGH SPEED SERIAL INTERFACE (HSSI)
Rise time(5) —data
from –A1 to A1 minimum eye height specification
from –A1 to A1 minimum eye height specification
from A1 to –A1 minimum eye height specification
from A1 to –A1 minimum eye height specification
DCLK. 50% to 50% reference points
50
50
115
135
115
135
ps
ps
ps
ps
ns
ns
tr
Rise time(5) —clock
Fall time(5) - data
50
tf
Fall time(5) - clock
50
tW(H)
tW(L)
Pulse duration high(6)
Pulse duration low(6)
0.275
0.275
DCLK. 50% to 50% reference points
(1) See 图6-9 for rise time and fall time for LVCMOS.
(2) See 图6-5 for rise time and fall time for LSIF.
(3) See 图6-4 for pulse duration high and low time for LSIF.
(4) See 图6-4 for setup and hold time for LSIF.
(5) See 图6-10 for rise time and fall time for HSSI.
(6) See 图6-12 for pulse duration high and low for HSSI.
1.255 V
V
LVDS(max)
V
V
CM
ID
V
LVDS(min)
0.575 V
A. See 方程式1 and 方程式2
图6-3. LSIF Waveform Requirements
1
VLVDS max = V
:
; + , × V
,
;
ID max
;
:
CM max
:
2
(1)
(2)
1
VLVDS min = V
:
; F , × V
,
;
ID max
;
:
CM min
:
2
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t
t
W(H)|
W(L)|
LS_CLK_P
50%
LS_CLK_N
t
t
H|
SU|
LS_WDATA_P
50%
LS_WDATA_N
t
WINDOW|
图6-4. LSIF Timing Requirements
V
, V
, V
LS_CLK_P LS_CLK_N LS_WDATA_P LS_WDATA_N
, V
100
90
80
70
60
50
40
30
20
10
0
tr
tf
图6-5. LSIF Rise, Fall Time Slew
+
(VIP + VIN)
2
VCM
=
œ
LS_CLK_P,
LS_WDATA_P
VID
LS_CLK_N,
LS_WDATA_N
LVDS
Receiver
VCM
VIP
VIN
图6-6. LSIF Voltage Requirements
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LS_CLK_P
LS_WDATA_P
Internal
Termination
ESD
ESD
(ZIN)
LVDS
Receiver
LS_CLK_N
LS_WDATA_N
图6-7. LSIF Equivalent Input
V
IH
V
T+
DV
T
V
Tœ
V
IL
DMD_DEN_ARTZ
Time
图6-8. LVCMOS Input Hysteresis
DMD_DEN_ARSTZ
100
80
V
IL(AC)
20
t
F
t
R
Time
图6-9. LVCMOS Rise, Fall Time Slew Rate
t
f
V
HSSI(max)
V
V
ID
CM
V
HSSI(min)
t
r
A. See 方程式3 and 方程式4 .
图6-10. HSSI Waveform Requirements
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1
; + , × V
2
VHSSI max = V
:
,
: ;
ID max
;
:
CM max
(3)
1
VHSSI min = V
:
; F , × V
,
;
ID max
;
:
CM min
:
2
(4)
A2
A1
0V
-A1
-A2
X1
1-X1
X2 1-X2
0
1 UI
图6-11. HSSI Eye Characteristics
t
C|
t
t
W(H)|
W(L)|
DCLK_?P
50%
DCLK_?N
图6-12. HSSI CLK Characteristics
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6.9 System Mounting Interface Loads
PARAMETER
MIN
TYP
MAX
UNIT
When loads are applied to the electrical and thermal interface areas
Maximum load to be applied to the electrical interface area(1)
Maximum load to be applied to the thermal interface area(1)
When a load is applied to only the electrical interface area
Maximum load to be applied to the electrical interface area(1)
Maximum load to be applied to the thermal interface area(1)
111
111
N
N
222
0
N
N
(1) The load should be uniformly applied in the corresponding areas shown in 图6-13.
Electrical Interface Area
Thermal Interface Area
图6-13. System Mounting Interface Loads
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6.10 Micromirror Array Physical Characteristics
PARAMETER DESCRIPTION
VALUE
1920
1080
5.4
UNIT
Number of active columns(1)
Number of active rows(1)
M
micromirrors
micromirrors
μm
N
Micromirror (pixel) pitch (1)
Micromirror active array width(1)
Micromirror active array height(1)
Micromirror active border(2)
P
Micromirror pitch × number of active columns
Micromirror pitch × number of active rows
Pond of micromirror (POM)
10.368
5.832
20
mm
mm
micromirrors/side
(1) See 图6-14.
(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors referred to as the
Pond Of Micromirrors (POM). These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state
but still require an electrical bias to tilt toward the OFF state.
Off-State
Light Path
0
1
2
3
Active Micromirror Array
N x P
M x N Micromirrors
Nœ 4
Nœ 3
Nœ 2
Nœ 1
M x P
P
Incident
Illumination
Light Path
P
P
Pond Of Micromirrors (POM) omitted for clarity.
Details omitted for clarity.
Not to scale.
P
图6-14. Micromirror Array Physical Characteristics
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6.11 Micromirror Array Optical Characteristics
PARAMETER
Micromirror tilt angle (1) (2) (3) (4)
TEST CONDITIONS
MIN
TYP MAX
UNIT
Landed state
15.6
18.4
degrees
Micromirror crossover time (5)
Micromirror switching time (6)
Typical performance
Typical performance
Gray 10 Screen (9)
Gray 10 Screen (9)
White Screen
1
3
μs
6
Bright pixel(s) in active area (8)
0
1
4
0
0
Bright pixel(s) in the POM (10)
Dark pixel(s) in the active area (11)
Adjacent pixel(s) (12)
Image
micromirrors
performance(7)
Any Screen
Unstable pixel(s) in active area (13)
Any Screen
(1) Measured relative to the plane formed by the overall micromirror array.
(2) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(3) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations or system contrast variations.
(4) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State
direction. A binary value of 0 results in a micromirror landing in the OFF State direction. See 图6-15.
(5) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(6) The minimum time between successive transitions of a micromirror.
(7) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear.
Test set brightness and contrast shall be set to nominal.
The diagonal size of the projected image shall be a minimum of 60 inches.
The projections screen shall be 1X gain.
The projected image shall be inspected from a 8 foot minimum viewing distance.
The image shall be in focus during all image quality tests.
(8) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels.
(9) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(10) POM definition: Rectangular border of off-state mirrors surrounding the active area.
(11) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels.
(12) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster.
(13) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable
pixel appears to be flickering asynchronously with the image.
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Off-State
Light Direction
Incident
Light Direction
B
Tilted Rotation
Axis
Tilted Mirror
On-State
Mirror
Landed Edge
Landed Edge
Tilt Angle
Off-State
Mirror
B
View B-B
On-State Mirror - Tilted Position
Landed Edge
A
A
Tilt Angle
Tilted Mirror
Landed Edge
View A-A
Off-State Mirror - Tilted Position
图6-15. Micromirror Landed Orientation and Tilt
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6.12 Window Characteristics
DESCRIPTION(1)
MIN
TYP MAX
Corning Eagle XG
1.5119
Window material
Window refractive index
At wavelength 546.1 nm
Minimum within the wavelength range 420 nm to
680 nm. Applies to all angles 0° to 30° AOI (2)
97%
97%
Window transmittance, single-pass
through both surfaces and glass
Average over the wavelength range 420 nm to 680
nm. Applies to all angles 30° to 45° AOI (2)
(1) See 节7.5 for more information.
(2) Angle of incidence (AOI) is the angle between an incident ray and the normal to a reflecting or refracting surface.
6.13 Chipset Component Usage Specification
Reliable function and operation of the DLP471NE DMD requires that it be used in conjunction with the other
components of the applicable DLP chipset, including those components that contain or implement TI DMD
control technology. TI DMD control technology consists of the TI technology and devices used for operating or
controlling a DLP DMD.
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
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7 Detailed Description
7.1 Overview
The DMD is a 0.47-inch diagonal spatial light modulator which consists of an array of highly reflective aluminum
micromirrors. The DMD is an electrical input, optical output micro-optical-electrical-mechanical system
(MOEMS). The fast switching speed of the DMD micromirrors combined with advanced DLP image processing
algorithms enables frame rates of up to 240Hz to be displayed. The electrical interface is low voltage differential
signaling (LVDS). The DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is
organized in a grid of M memory cell columns by N memory cell rows. Refer to the 节 7.2. The positive or
negative deflection angle of the micromirrors can be individually controlled by changing the address voltage of
underlying CMOS addressing circuitry and micromirror reset signals (MBRST).
The DLP 0.47” 1080p chipset is comprised of the DLP471NE DMD, DLPC7540 display controller, and the
DLPA100 power management and motor driver. To ensure reliable operation, the DLP471NE DMD must always
be used with the DLP display controller and the power management and motor driver specified in the chipset.
7.2 Functional Block Diagram
Channel A Interface
Control
Control
Column Read/Write
Bit Lines
(0,0)
Word
Lines
Voltages
Voltage
Generators
Micromirror
Array
Row
(M-1,N-1)
Bit Lines
Control
Column Read/Write
Control
Channel B Interface
.
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7.3 Feature Description
7.3.1 Power Interface
The DMD requires 4 DC voltages: 1.8 V source, VOFFSET, VRESET, and VBIAS. In a typical configuration, 3.3 V is
created by the DLPA100 power management and motor driver and is used on the DMD board to create the 1.8
V. The TI voltage regulator TPS65145 takes in the 3.3 V and outputs VOFFSET, VRESET, VBIAS
.
7.3.2 Timing
The data sheet specifies timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be considered. Timing reference loads are not intended to be precise
representations of any particular system environment or depiction of the actual load presented by a production
test. TI recommends that system designers use IBIS or other simulation tools to correlate the timing reference
load to a system environment. Use the specified load capacitance value for characterization and measurement
of AC timing signals only. This load capacitance value does not indicate the maximum load the device is capable
of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC7540 display controller. See the DLPC7540 display controller
data sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
TI recommends that the light cone angle defined by the numerical aperture of the illumination optics is the same
as the light cone angle defined by the numerical aperture of the projection optics. This angle must not exceed
the nominal device micromirror tilt angle unless appropriate apertures are added in the illumination and/or
projection pupils to block out flat-state and stray light from the projection lens. The micromirror tilt angle defines
DMD capability to separate the "ON" optical path from any other light path, including undesirable flat-state
specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such
as prism or lens surfaces. If the numerical aperture exceeds the micromirror tilt angle, or if the projection
numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle (and
vice versa), contrast degradation and objectionable artifacts in the display border and/or active area could occur.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border and/or active area, which may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. Design the illumination optical
system to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the
average flux level in the active area. Depending on the particular system optical architecture, overfill light may
have to be further reduced below the suggested 10% level in order to be acceptable.
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7.6 Micromirror Array Temperature Calculation
Array
TP2
2X 11.75
TP5
TP4
2X 16.10
TP3
Window Aperture
Window Edge
(4 surfaces)
TP3 (TP2)
TP5
TP4
TP1
4.5
16.1
TP1
图7-1. DMD Thermal Test Points
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Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from
measurement points on the outside of the package, the package thermal resistance, the electrical power, and
the illumination heat load. The relationship between array temperature and the reference ceramic temperature
(thermal test TP1 in 图7-1) is provided by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC
)
(5)
(6)
QARRAY = QELECTRICAL + QILLUMINATION
where
• TARRAY = Computed array temperature (°C)
• TCERAMIC = Measured ceramic temperature (°C) (TP1 location)
• RARRAY-TO-CERAMIC = Thermal resistance of package specified in 节6.5 from array to ceramic TP1 (°C/Watt)
• QARRAY = Total DMD power on the array (W) (electrical + absorbed)
• QELECTRICAL = Nominal electrical power (W)
• QINCIDENT = Incident illumination optical power (W)
• QILLUMINATION = (DMD average thermal absorptivity × QINCIDENT) (W)
• DMD average thermal absorptivity = 0.40
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 2.5 W. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for a single chip or multichip DMD
system. It assumes an illumination distribution of 83.7% on the active array, and 16.3% on the array border.
The sample calculation for a typical projection application is as follows:
QINCIDENT = 25 W (measured)
TCERAMIC = 55.0°C (measured)
(7)
(8)
QELECTRICAL = 2.5 W
(9)
QARRAY = 2.5 W + (0.40 × 25 W) = 12.5 W
(10)
(11)
TARRAY = 55.0°C + (12.5 W × 0.8°C/W) = 65.0°C
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7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the percentage of time that an
individual micromirror is landed in the ON state versus the amount of time the same micromirror is landed in the
OFF state.
For example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the time
(and in the OFF state 0% of the time); whereas 0/100 would indicate that the pixel is in the OFF state 100% of
the time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD useful life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect DMD useful life, and this interaction can
be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD useful life. This is
quantified in the de-rating curve shown in 图6-1. The importance of this curve is that:
• All points along this curve represent the same useful life.
• All points above this curve represent lower useful life (and the further away from the curve, the lower the
useful life).
• All points below this curve represent higher useful life (and the further away from the curve, the higher the
useful life).
In practice, this curve specifies the maximum operating DMD temperature for a given long-term average landed
duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the
pixel operates under a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the gray scale value, as shown in 表7-1.
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表7-1. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0/100
10/90
20/80
30/70
40/60
50/50
60/40
70/30
80/20
90/10
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a
given primary must be displayed in order to achieve the desired white point.
Use 方程式12 to calculate the landed duty cycle of a given pixel during a given time period
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% (12)
×
Blue_Scale_Value)
where
• Red_Cycle_%, represents the percentage of the frame time that red is displayed to achieve the desired white
point
• Green_Cycle_% represents the percentage of the frame time that green is displayed to achieve the desired
white point
• Blue_Cycle_%, represents the percentage of the frame time that blue is displayed to achieve the desired
white point
For example, assume that the red, green, and blue color cycle times are 30%, 50%, and 20% respectively (in
order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue
color intensities would be as shown in 表7-2 and 表7-3.
表7-2. Example Landed Duty Cycle for Full-Color,
Color Percentage
CYCLE PERCENTAGE
RED
GREEN
BLUE
30%
50%
20%
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表7-3. Example Landed Duty Cycle for Full-Color
SCALE VALUE
GREEN
0%
LANDED DUTY
CYCLE
RED
0%
BLUE
0%
0/100
30/70
50/50
20/80
6/94
100%
0%
0%
0%
100%
0%
0%
0%
100%
0%
0%
12%
0%
0%
35%
0%
7/93
60%
0%
0%
18/82
70/30
50/50
80/20
13/87
25/75
24/76
100/0
100%
0%
100%
100%
0%
100%
100%
0%
100%
12%
35%
35%
0%
60%
60%
100%
0%
12%
100%
100%
The last factor to account for in estimating the landed duty cycle is any applied image processing. Within the
DLPC7540 controller, the gamma function affects the landed duty cycle.
Gamma is a power function of the form Output_Level = A × Input_LevelGamma, where A is a scaling factor that is
typically set to 1.
In the DLPC7540 controller, gamma is applied to the incoming image data on a pixel-by-pixel basis. A typical
gamma factor is 2.2, which transforms the incoming data as shown in 图7-2.
100
90
80
Gamma = 2.2
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
Input Level (%)
70
80
90 100
D002
图7-2. Example of Gamma = 2.2
From 图 7-2, if the gray scale value of a given input pixel is 40% (before gamma is applied), then gray scale
value is 13% after gamma is applied. Therefore, it can be seen that since gamma has a direct impact on the
displayed gray scale level of a pixel, it also has a direct impact on the landed duty cycle of a pixel.
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Consideration must also be given to any image processing which occurs before the DLPC7540 controllers.
8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two
directions, with the primary direction being into a projection or collection optic. Each application is derived
primarily from the optical architecture of the system and the format of the data coming into the DLPC7540
controller. The high tilt pixel in the bottom-illuminated DMD increases brightness performance and enables a
smaller system footprint for thickness constrained applications. Typical applications using the DLP471NE include
smart projectors and enterprise projectors.
DMD power-up and power-down sequencing is strictly controlled by the DLPC7540 through the TPS65145
PMIC. Refer to 节 9 for power-up and power-down specifications. To ensure reliable operation, the DLP471NE
DMD must always be used with DLPC7540 controller, a DLPA100 PMIC/Motor driver and aTPS65145 PMIC.
8.2 Typical Application
The DLP471NE DMD combined with DLPC7540 digital controller and a power management device provides full
HD (1920x1080) resolution for bright, colorful display applications. A typical display system using laser phosphor
illumination combines the DLP471NE DMD, DLPC7540 display controller, TPS65145 voltage regulator and
DLPA100 PMIC and motor driver. 图 8-1 shows a system block diagram for this configuration of the DLP 0.47”
Full HD chipset and additional system components needed. See 图 8-2, a block diagram showing the system
components needed along with the lamp configuration of the DLP 0.47” Full HD chipset. The components
include the DLP471NE DMD, DLPC7540 display controller and the DLPA100 PMIC and motor driver and a
TPS65145 PMIC.
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Laser
Driver
CTRL Signals
1.15V
12V
TPS56121
Core 1.15V
Voltage Reg.
DLPC7540
1.8V
1.21V
3.3V
12 V
DLPC7540
DLPA100
(Controller
Voltages)
3.3V
}
LMR33630C
3.3V
TPS65145
12V
5V
PW Motor Drive
Fans (3x)
Flash
CTRL
(SPI)
ADDR
DATA
CW Motor Drive
Fans (3x)
23
16
DLPA100
(Filter wheel)
12V
1.15V
1.21V
1.8V
CW_INDEX1
3.3V
Vref
CW_INDEX2
40 MHz
Vref
GND
2 Port HSSI
DMD LS-interface
36
GND
FE CTRL
(I2C)
HDMI
Front End
(VbyOneTM)
DLP471NE
.47" 1080p
S451 HSSI
DMD
VOFFSET
VbyOneTM
TPS65145
DMD
Voltages
3.3V
VRESET
VBIAS
30 Bit Data
18
DLPC7540
Controller
3D L/R
GPIO
1.8V
12V
3.3V
LMR33630C
1.8V
Temp
2
Tilt (& Roll)
Sensor
TMP411
I2C
(2x)
IR Rx
USB2.0 OTG
USB 2.0
GPIO
USB2.0
Mux
DB Drive Data
Dynamic Black
Actuators (2X)
USB
Camera
DLP Chipset Components
TI Components
3rd Party Components
图8-1. Typical Full HD Laser Phosphor Application Diagram
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CTRL Signals
Lamp
Ballast
1.15V
12V
TPS56121
Core 1.15V
Voltage Reg.
DLPC7540
1.8V
DLPC7540
1.21V
12 V
3.3V
LMR33630C
3.3V
TPS65145
12V
DLPA100
(Controller
Voltages)
3.3V
}
5V
Flash
PW Motor Drive
Fans (3x)
ADDR
DATA
23
16
1.15V
1.21V
1.8V
CTRL (SPI)
3.3V
CW_INDEX1
Vref
40 MHz
GND
GND
2 Port HSSI
DMD LS-interface
36
FE CTRL
(I2C)
VbyOneTM
HDMI
Front End
(VbyOneTM)
DLP471NE
.47" 1080p
S451 HSSI
DMD
VOFFSET
TPS65145
DMD
Voltages
3.3V
VRESET
VBIAS
30 Bit Data
18
DLPC7540
Controller
3D L/R
GPIO
1.8V
12V
3.3V
LMR33630C
1.8V
Temp
2
Tilt (& Roll)
Sensor
TMP411
I2C
(2x)
IR Rx
USB2.0 OTG
USB 2.0
GPIO
USB2.0
Mux
DB Drive Data
Dynamic Black
Actuators (2X)
USB
Camera
DLP Chipset Components
TI Components
3rd Party Components
图8-2. Typical Full HD Lamp Application Diagram
8.2.1 Design Requirements
Other core components of the display system include an illumination source, an optical engine for the
illumination and projection optics, other electrical and mechanical components, and software. The type of
illumination used and desired brightness has a major effect on the overall system design and size.
The display system uses the DLP471NE as the core imaging device and contains a 0.47-inch array of
micromirrors. The DLPC7540 controller is the digital interface between the DMD and the rest of the system,
taking digital input from front end receiver and driving the DMD over a high-speed interface. The DLPA100 PMIC
serves as a voltage regulator for the controller, and color filter wheel and phosphor wheel motor control. The
TPS65145 provide the DMD reset, offset and bias voltages. The LMR33630C provides the 1.8-V power to the
DLP471NE.
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8.2.2 Detailed Design Procedure
For a complete DLP system, an optical module or light engine is required that contains the DLP471NE DMD,
associated illumination sources, optical elements, and necessary mechanical components.
To ensure reliable operation, the DMD must always be used with DLPC7540 display controller and the
TPS65145 PMIC and DLPA100. Refer to PCB Design Requirements for TI DLP TRP Digital Micromirror Devices
for the DMD board design and manufacturing handling of the DMD sub assemblies.
8.2.3 Application Curves
In a typical projector application, the luminous flux on the screen from the DMD depends on the optical design of
the projector. The efficiency and total power of the illumination optical system and the projection optical system
determines the overall light output of the projector. The DMD is inherently a linear spatial light modulator, so its
efficiency just scales the light output. 图 8-3 describes the relationship of laser input optical power to light output
for a laser-phosphor illumination system, where the phosphor is not at its thermal quenching limit. .
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
Normalized Laser Power
0.75
0.8
0.85
0.9
0.95
1
norm
图8-3. Normalized Light Output vs. Normalized Laser Power for Laser Phosphor Illumination
8.3 Temperature Sensor Diode
The DMD features a built-in thermal diode that measures the temperature at one corner of the die outside the
micromirror array. The thermal diode can be interfaced with the TMP411 temperature sensor as shown in 图8-4.
The software application contains functions to configure the TMP411 to read the DLP471NE DMD temperature
sensor diode. This data can be leveraged by the customer to incorporate additional functionality in the overall
system design such as adjusting illumination, fan speeds, etc. All communication between the TMP411 and the
DLPC7540 controller happens over the I2C interface. The TMP411 connects to the DMD via pins outlined in 表
5-1.
If the temp sensor is not used, TEMP_N and TEMP_P pins should be left unconnected (NC).
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3.3V
R1
R2
TMP411
DLP471NE
SCL
VCC
D+
R3
R5
TEMP_P
SDA
ALERT
THERM
GND
C1
R4
R6
D-
TEMP_N
GND
A. Details omitted for clarity.
B. See the TMP411 datasheet for system board layout recommendation.
C. See the TMP411 datasheet and the TI reference design for suggested component values for R1, R2, R3, R4, and C1.
D. R5 = 0 Ω. R6 = 0 Ω. Place 0-Ωresistors close to the DMD package pins.
图8-4. TMP411 Sample Schematic
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD:
• VSS
• VBIAS
• VDD
• VOFFSET
• VRESET
DMD power-up and power-down sequencing is strictly controlled by the DLP display controller.
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to any of the prescribed power-up and power-down requirements may
affect device reliability. See the DMD power supply sequencing requirements in 图9-1.
VBIAS, VDD, VOFFSET, and VRESET power supplies must be coordinated during power-up and power-
down operations. Failure to meet any of the below requirements will result in a significant reduction
in the DMD reliability and lifetime. Common ground VSS must also be connected.
表9-1. Power Supply Sequence Requirements
SYMBOL
PARAMETER
Delay requirement
DESCRIPTION
MIN
TYP
MAX UNIT
tDELAY1
from VOFFSET power up to VBIAS power up
1
2
ms
from VBIAS and VRESET powered on and stable to
DMD_EN_ARSTZ going high
tDELAY2
tDELAY3
Delay requirement
Delay requirement
20
50
µs
µs
from VOFFSET, VBIAS, and VRESET power down to
when VDD and VDDA can power down
9.1 DMD Power Supply Power-Up Procedure
• During power-up, VDD must always start and settle before VOFFSET plus tDELAY1 specified in 图9-1, VBIAS, and
VRESET voltages are applied to the DMD.
• During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in 节6.4.
• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS
.
• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements specified in 节6.1, in 节6.4, and in 图9-1 .
• During power-up, LVCMOS input pins must not be driven high until after VDD has settled at operating voltage
listed in 节6.4.
9.2 DMD Power Supply Power-Down Procedure
• During power-down, VDD must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the
specified limit of ground. See 图9-1.
• During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in 节6.4.
• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS
.
• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements specified in 节6.1, in 节6.4, and in 图9-1.
• During power-down, LVCMOS input pins must be less than specified in 节6.4.
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Note A
Note J
...
VDD and VDDA
VSS
VSS
Note H
tDELAY3
...
...
Note B
V < Specification
VOFFSET
Note D
tDELAY1
VBIAS
VSS
VSS
Note C
V < Specification
VRESET
Note E
...
Note F
tDELAY2
Note G
...
DMD_EN_ARSTZ
VSS
Time
A. See 节5 for the Pin Functions Table.
B. To prevent excess current, the supply voltage difference |VBIAS –VOFFSET| must be less than the specified limit in 节6.4.
C. To prevent excess current, the supply difference |VBIAS –VRESET| must be less than the specified limit in the 节6.4.
D. VBIAS must power up after VOFFSET has powered up, per the Delay1 specification in 表9-1.
E. VRESET, VOFFSET and VBIAS ramps must start after VDD and VDDA are powered up and stable.
F. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates
DMD_EN_ARSTZ and disables VBIAS, VRESET and VOFFSET
.
G. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware
DMD_EN_ARSTZ goes low.
H. VDD must remain high until after VOFFSET, VBIAS, VRESET go low, per Delay2 specification in 表9-1.
I.
To prevent excess current, the supply voltage delta |VDDA –VDD| must be less than specified limit in 节6.4.
J. Not to scale. Details are omitted for clarity.
图9-1. DMD Power Supply Requirements
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10 Layout
10.1 Layout Guidelines
The DLP471NE DMD is part of a chipset that is controlled by the DLPC7540 display controller in conjunction
with theTPS65145 PMIC and the DLPA100 power and motor controller. These guidelines are targeted at
designing a PCB board with the DLP471NE DMD. The DMD board is a high-speed multi-layer PCB, with
primarily high-speed digital logic including double data rate 3.2 Gbps and 250 Mbps differential data buses run to
the DMD. TI recommends that full or mini power planes are used for VOFFSET, VRESET, and VBIAS. Solid planes
are required for ground (VSS). The target impedance for the PCB is 50 Ω±10% with exceptions listed in 表10-1.
TI recommends a 10 layer stack-up as described in 表 10-2. TI recommends manufacturing the PCB with a high
quality FR-4 material.
10.2 Impedance Requirements
TI recommends a target impedance for the PCB of 50 Ω ±10% for all signals. The exceptions are listed in 表
10-1.
表10-1. Special Impedance Requirements
Signal Type
Signal Name
Impedance (Ω)
DMD_HSSI0_N_(0…7),
DMD_HSSI0_P_(0…7),
DMD_HSSI1_N_(0…7),
DMD_HSSI1_P_(0…7),
DMD_HSSI0_CLK_N,
DMD_HSSI0_CLK_P,
DMD_HSSI1_CLK_N,
DMD_HSSI1_CLK_P
100-Ω differential (50-Ω single
DMD High Speed Data Signals
ended)
DMD_LS0_WDATA_N,
DMD_LS0_WDATA_P,
DMD_LS0_CLK_N,
DMD_LS0_CLK_P
DMD Low Speed Interface
Signals
100-Ω differential (50-Ω single
ended)
10.3 Layers
The layer stack-up and copper weight for each layer is shown in 表10-2.
表10-2. Layer Stack-Up
LAYER
NO.
LAYER NAME
COPPER WT. (oz.)
COMMENTS
DMD and escapes. Two data input connectors. Top components including
power generation and two data input connectors. Low frequency signals
routing. Should have a copper fill (GND) plated up to 1 oz.
Side A –DMD, primary
components, power mini-
planes
0.5 oz. (before
plating)
1
2
3
Ground
0.5
0.5
Solid ground plane (net GND) reference for signal layers #1, 3
High speed signal layer. High speed differential data buses from input
connector to DMD
Signal (high frequency)
4
5
6
7
Ground
Power
Power
Ground
0.5
0.5
0.5
0.5
Solid ground plane (net GND) reference for signal layers #3, #5
Primary split power planes for 1.8 V, 3.3 V, 10 V, –14 V, 18 V
Primary split power planes for 1.8 V, 3.3 V, 10 V, –14V, 18V.
Solid ground plane (net GND) reference for signal layer #8
High Speed Signal layer. High speed differential data buses from input
connector to DMD
8
9
Signal (high frequency)
Ground
0.5
0.5
Solid ground plane (net GND) reference for signal layers #8, 10
Side B –secondary
components, power mini-
planes
0.5 oz. (before
plating)
Discrete components if necessary. Low frequency signals routing. Should
have copper fill plated up to 1 oz.
10
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10.4 Trace Width, Spacing
Unless otherwise specified, TI recommends that all signals follow the 0.005”/0.015” (trace-width/spacing)
design rule. Use an analysis of impedance and stack-up requirements to determine and calculate actual trace
widths.
Maximized the width of all voltage signals as space permits. Follow the width and spacing requirements listed in
表10-3.
表10-3. Special Trace Widths, Spacing Requirements
MINIMUM TRACE
WIDTH (MIL)
SIGNAL NAME
MINIMUM TRACE SPACING (MIL)
LAYOUT REQUIREMENT
GND
MAXIMIZE
5
Maximize trace width to connecting pin as a minimum
Create mini planes on layers 1 and 10 as needed. Connect
to devices on layers 1 and 10 as necessary with multiple
vias.
VDD
40
40
15
15
Create mini planes on layers 1 and 10 as needed. Connect
to devices on layers 1 and 10 as necessary with multiple
vias.
VDDA
Create mini-planes on layers 1 and 10 as needed. Connect
to devices on layers 1 and 10 as necessary.
VOFFSET
VRESET
VBIAS
40
40
40
15
15
15
Create mini-planes on layers 1 and 10 as needed. Connect
to devices on layers 1 and 10 as necessary.
Create mini-planes on layers 1 and 10 as needed. Connect
to devices on layers 1 and 10 as necessary.
10.5 Power
TI strongly discourages signal routing on power planes or on planes adjacent to power planes. If signals must be
routed on layers adjacent to power planes, they must not cross splits in power planes to prevent EMI and
preserve signal integrity.
Connect all internal digital ground (GND) planes in as many places as possible. Connect all internal ground
planes with a minimum distance between connections of 0.5”. Extra vias may not required if there are sufficient
ground vias due to normal ground connections of devices.
Connect power and ground pins of each component to the power and ground planes with at least one via for
each pin. Minimize trace lengths for component power and ground pins. (ideally, less than 0.100”).
Ground plane slots are strongly discouraged.
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10.6 Trace Length Matching Recommendations
表 10-4 and 表 10-5 describe recommended signal trace length matching requirements. Follow these guidelines
to avoid routing long traces over large areas of the PCB:
• Match the trace lengths so that longer signals route in a serpentine pattern
• Minimize the number of turns.
• Ensure that the turn angles no sharper than 45 degrees.
图10-1 shows an example of the HSSI signal pair routing.
Signals listed in 表 10-4 are specified fro data rate operation at up to 3.2 Gbps. Minimize the layer changes for
these signals. Minimize the number of vias. Avoid sharp turns and layer switching while minimizing the lengths.
When layer changes are necessary, place GND vias around the signal vias to provide a signal return path. The
distance from one pair of differential signals to another must be at least 2 times the distance within the pair.
表10-4. HSSI High Speed DMD Data Signals
SIGNAL NAME
DMD_HSSI0_N(0...7),
REFERENCE SIGNAL
ROUTING SPECIFICATION
UNIT
DMD_HSSI0_CLK_N,
DMD_HSSI_CLK_P
±0.25
inch
DMD_HSSI0_P(0...7)
DMD_HSSI1_N(0...7),
DMD_HSSI1_P(0...7)
DMD_HSSI0_CLK_N,
DMD_HSSI_CLK_P
±0.25
inch
DMD_HSSI0_CLK_P
Intra-pair P
DMD_HSSI1_CLK_P
Intra-pair N
±0.05
±0.01
inch
inch
表10-5. Other Timing Critical Signals
SIGNAL NAME
Constraints
Routing Layers
LS_CLK_P, LS_CLK_N
LS_WDATA_P,
LS_WDATA_N
Intra-pair (P to N)
Matched to 0.01 inches
Signal-to-signal
Layers 3, 8
LS_RDATA_A
Matched to +/- 0.25 inches
图10-1. Example HSSI PCB Routing
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11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Device Support
11.2.1 Device Nomenclature
DLP471NE xc FYN
Package
TI Internal Numbering
Device Descriptor
图11-1. Part Number Description
11.2.2 Device Markings
The device marking includes both human-readable information and a 2-dimensional matrix code. The human-
readable information is described in 图 11-2. The 2-dimensional matrix code is an alpha-numeric string that
contains the DMD part number, Part 1 and Part 2 of the serial number.
Example:
TI Internal Numbering
DMD Part Number
Part 2 of Serial Number
(7 characters)
Part 1 of Serial Number
(7 characters)
2-Dimension Matrix Code
(Part Number and Serial Number)
图11-2. DMD Marking Locations
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11.3 Documentation Support
11.3.1 Related Documentation
The following documents contain additional information related to the chipset components used with the DMD.
• DLPC7540 Display Controller Data Sheet
• TPS65145 Data Sheet
• DLPA100 Power and Motor Driver Data Sheet
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.6 Trademarks
TI E2E™ is a trademark of Texas Instruments.
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Package Option Addendum
12.1.1 Packaging Information
Package
Type
Package
Drawing
MSL Peak Temp
Device Marking(5)
Orderable Device
Status (1)
Pins
Package Qty
Eco Plan (2)
Lead/Ball Finish(4)
Op Temp (°C)
(3)
(6)
see Device
Marking section
DLP471NEA0FYN
ACTIVE
CPGA
FYN
149
33
RoHS & Green
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(4) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain
information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION
www.ti.com
25-Mar-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DLP471NEA0FYN
FYN
CPGA
149
33
3 x 11
150
315 135.9 12190 27.5
20
27.45
Pack Materials-Page 1
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Copyright © 2022，德州仪器 (TI) 公司
相关型号：
DLP471TEA0FYN
0.47-inch, 4K UHD, HSSI DLP® digital micromirror device (DMD) | FYN | 149 | 0 to 70
TI
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