DLPA2000DYFFR [TI]
DLP® PMIC/LED driver for DLP2010 (0.2 WVGA) DMD | YFF | 56 | -10 to 85;
| 型号： | DLPA2000DYFFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DLP® PMIC/LED driver for DLP2010 (0.2 WVGA) DMD | YFF | 56 | -10 to 85 集成电源管理电路 |
| 文件： | 总58页 (文件大小：1911K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
DLPA2000 电源管理和 LED/灯驱动器 IC
1 特性
–
–
–
–
LED 电压，LED 电流
光传感器（用于白点修正）
内部基准电压
1
•
高效 RGB LED/灯驱动器，在小型芯片级封装中集
成了降压/升压直流/直流转换器、DMD 电源、DPP
内核电源、1.8V 负载开关以及测量系统
外部（热敏电阻）温度传感器
•
三个用于通道选择的低阻抗（27°C 时典型值为
30mΩ）金属氧化物半导体场效应晶体管
(MOSFET) 开关
•
•
监控和保护电路
–
–
–
–
–
热模警告和热关断
低电池电压警告
•
•
每个通道具有独立的 10 位电流控制
可编程的电池欠压闭锁 (UVLO)
负载开关 UVLO
针对 DLPA2000 嵌入式应用的最大 LED 电流为
750mA
过流和欠压保护
•
•
片上电机驱动器
DLPA2000 芯片级球栅阵列 (DSBGA) 封装
DMD 调节器
–
–
56 球 0.4mm 间距
–
–
–
–
–
仅需一个电感器
裸片尺寸：3.280mm × 3.484mm ± 0.03mm
VOFS：10V
VBIAS：18V
2 应用
VRST：–14V
DLP™显示投影仪
当禁用时对接地 (GND) 被动放电
DLP™移动传感
•
DPP 1.1V 内核电源
–
–
具有集成开关 FET 的同步降压转换器
支持高达 600mA 的输出电流
3 说明
DLPA2000 是一款专用于 DLP2010 和 DLP2010NIR
数字微镜器件 (DMD) 的 PMIC/RGB LED/灯驱动器，
与 DLPC3430、DLPC3435 或 DLPC150 数字控制器
搭配使用。为确保这些芯片组可靠运行，必须搭配
DLPA2000 使用。
•
•
VLED 降压/升压转换器
轻负载电流状态下的省电模式
低阻抗负载开关
–
–
–
–
VIN 范围：1.8V 至 3.6V
支持高达 200mA 的电流
器件信息(1)
当禁用时对接地 (GND) 被动放电
器件型号
DLPA2000
封装
封装尺寸（标称值）
•
•
•
DMD 复位信号生成和电源排序
33MHz 串行外设接口 (SPI)
用于测量模拟信号的多路复用器
3.28mm × 3.48mm ±
0.03mm
DSBGA (56)
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
–
电池电压
图 1. 简化电路原理图
DC_IN
Charger
BAT
2.3 to 5.5
V
Projector Module Electronics
DC Supplies
1.8
V
VSPI
1.1
1.8
V
V
1.1
Reg
V
Other
Supplies
1.8 V
On/Off
L3
SYSPWR
VDD
1.8
V
HDMI
VLED
HDMI
Receiver
PROJ_ON
PROJ_ON
Current
Sense
L1
L2
VGA
Triple
ADC
Keystone
Sensor
GPIO_8 (Normal Park)
SPI_0
DLPA2000
Cal data
(optional)
4
FLASH
4
Front-End
Chip
EEPROM
RED
GREEN
BLUE
SPI_1
RESETZ
INTZ
FLASH,
SDRAM
-
-
-
OSD
AutoLock
Scaler
I2C_1
HOST_IRQ
PARKZ
BIAS, RST, OFS
3
LED_SEL(2)
CMP_PWM
-MicroController
WPC
Illumination
Optics
DLPC3430/
DLPC3435
Keypad
Parallel I/F
28
LABB
CMP_OUT
eDRAM
DLP2010
DMD)
I2C
SD Card
Reader, and
so forth
(WVGA
Thermistor
Sub-LVDS DATA
CTRL
1.8
1.1
V
V
VIO
(optional)
VCC_INTF
VCC_FLSH
VCORE
18
Spare R/W
GPIO
BT.656
CVBS
TVP5151
Video
Decoder
Included in DLP® Chip Set
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: DLPS043
DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 27
7.5 Register Maps......................................................... 29
Application and Implementation ........................ 41
8.1 Application Information............................................ 41
8.2 Typical Projector Application .................................. 41
8.3 Typical Mobile Sensing Application ....................... 43
Power Supply Recommendations...................... 46
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 Storage Conditions.................................................... 5
6.3 ESD Ratings.............................................................. 5
6.4 Recommended Operating Conditions....................... 5
6.5 Thermal Information.................................................. 6
6.6 Electrical Characteristics........................................... 6
6.7 Motor Driver Timing Requirements......................... 11
6.8 Data Transmission Timing Requirements............... 12
6.9 Typical Characteristics............................................ 13
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 16
8
9
10 Layout................................................................... 47
10.1 Layout Guidelines ................................................. 47
10.2 Layout Example .................................................... 48
11 器件和文档支持 ..................................................... 49
11.1 器件支持 ............................................................... 49
11.2 相关链接................................................................ 49
11.3 社区资源................................................................ 49
11.4 商标....................................................................... 49
11.5 静电放电警告......................................................... 49
11.6 Glossary................................................................ 50
12 机械、封装和可订购信息....................................... 51
7
4 修订历史记录
Changes from Revision A (August 2015) to Revision B
Page
•
•
•
•
•
修正了器件信息中的封装尺寸的拼写错误，将 3.48mm2 更正为 3.48mm............................................................................... 1
已添加 在修订版本 A 中添加先前缺失的历史记录标记........................................................................................................... 1
Corrected package family to 'DSBGA' in Pin Functions Diagram, originally labeled as 'DSGBA' ......................................... 3
Added mechanical package designator YFF to Thermal Information .................................................................................... 6
Changed layout example to show correct image in Figure 46 ............................................................................................. 48
Changes from Original (June 2014) to Revision A
Page
•
•
•
•
已更改 将最大电流更改为 750mA........................................................................................................................................... 1
已添加 移动传感应用 .............................................................................................................................................................. 1
Added typical Mobile sensing application ............................................................................................................................ 43
Updated the Power Supply Recommendations to remove information that did not apply to the DLPA2000 ..................... 46
2
Copyright © 2014–2018, Texas Instruments Incorporated
DLPA2000
www.ti.com.cn
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
5 Pin Configuration and Functions
YFF PACKAGE
56-PIN DSBGA
BOTTOM VIEW
SW6
SW5
SW4
VLED
L2
RLIM
RLIM
V6V
AOUT2
AOUT1
VINM
VINC
SWC
H
G
F
RBOT_
K
PGND
CM
BOUT2
BOUT1
VCORE
LS_IN
DGND
AGND
RLIM_
K
LED_
SEL1
LED_
SEL0
LS_
OUT
PROJ_
ON
VLED
L2
SENS1
VSPI
SENS2
V2V5
VINA
E
D
C
B
A
CMP_
OUT
PWM_
IN
SPI_
CLK
SPI_
CSZ
SPI_
DIN
SPI_
DOUT
PGNDL
L1
PGNDL
L1
VOFS
VBIAS
SWP
RESET
Z
CNTR_
VRST
REF_
VRST
INTZ
VINR
VINL
VINL
AGND1
SWN
PGNDR
1
2
3
4
5
6
7
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NUMBER
A1
VINL
I
Power supply input for VLED BUCK-BOOST power stage. Connect to system power.
A2
AGND1
VINR
A3
GND
Analog ground. Connect to ground plane.
A4
I
I
Power supply input for DMD switch mode power supply (SMPS). Connect to system power.
Connection for the DMD SMPS-inductor (high-side switch).
Power ground for DMD SMPS. Connect to ground plane.
Connection for the DMD SMPS-inductor (low-side switch).
SWN
A5
PGNDR
SWP
A6
GND
O
A7
B1
L1
O
Connection for VLED BUCK-BOOST inductor.
B2
RESETZ
INTZ
B3
O
O
O
I
Reset output to the DLP system (active low). Pin is held low to reset DLP system.
Interrupt output signal (open drain). Connect to pull-up resistor or short to ground.
Connection to VRST for fast discharge function.
B4
CNTR_VRST
REF_VRST
VBIAS
B5
B6
Reference pin for the VRST regulator. Connect to VRST rail through 100-kΩ resistor.
VBIAS output rail. Connect to ceramic capacitor.
B7
O
C1
C2
C3
C4
C5
PGNDL
GND
Power ground for VLED BUCK-BOOST. Connect to ground plane.
SPI_CLK
SPI_CSZ
SPI_DIN
I
I
I
Clock input for SPI interface.
SPI chip select (active low).
SPI data input.
Copyright © 2014–2018, Texas Instruments Incorporated
3
DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
SPI_DOUT
VOFS
NUMBER
C6
O
O
SPI data output.
C7
VOFS output rail. Connect to ceramic capacitor.
D1
L2
I
Connection for VLED BUCK-BOOST inductor.
D2
VSPI
D3
I
O
Power supply input for SPI interface. Connect to system I/O voltage.
Analog-comparator output.
CMP_OUT
PWM_IN
AGND
D4
D5
I
Reference voltage input for analog comparator.
Analog ground. Connect to ground plane.
D6
GND
VINA
D7
POWER Power supply input for sensitive analog circuitry.
E1
VLED
O
VLED BUCK-BOOST converter output pin.
E2
SENS1
SENS2
PROJ_ON
DGND
V2V5
E3
I
Input signal from light sensor.
E4
I
I
Input signal from temperature sensor.
E5
Input signal to enable or disable the IC and DLP projector.
Digital ground. Connect to ground plane.
E6
GND
O
E7
Internal supply filter pin for digital logic; typical 2.5 V.
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
Kelvin sense connection to top side of LED current sense resistor.
SW4
F1
O
RLIM_K
F2
I
For best accuracy, route this trace directly to the top of the current sense resistor and
separate it from the normal trace from the current sense resistor to the RLIM pins.
LED_SEL1
LED_SEL0
BOUT1
F3
F4
F5
F6
F7
G1
I
I
Digital input to the RGB STROBE DECODER.
Digital input to the RGB STROBE DECODER.
Motor driver B phase output1.
O
I
LS_IN
Load switch.
LS_OUT
SW5
O
O
Load switch.
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
Connection to LED ‘current sense’ resistor.
Bottom side of sense resistor is connected to GND.
RLIM
G2
O
RBOT_K
AOUT1
BOUT2
VCORE
PGNDCM
SW6
G3
G4
G5
G6
G7
H1
I
O
Kelvin sense connection to ground side of LED current sense resistor.
Motor driver A phase output1.
O
Motor driver B phase output2.
I
VCORE BUCK converter feedback pin.
GND
O
Power ground for VCORE BUCK and motor driver.
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
Connection to LED current sense resistor.
Bottom side of sense resistor is connected to GND.
RLIM
H2
O
V6V
H3
H4
H5
H6
H7
O
O
I
Internal supply filter pin for gate driver circuitry. Typical 6.25 V.
Motor driver A phase output2.
AOUT2
VINM
VINC
SWC
Power supply input for motor driver power stage. Connect to system power.
Power supply input for VCORE BUCK power stage. Connect to system power.
Connection for 1.1-V BUCK inductor.
I
I/O
4
Copyright © 2014–2018, Texas Instruments Incorporated
DLPA2000
www.ti.com.cn
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–18.0
–0.3
–0.3
–0.3
–0.3
MAX
7
UNIT
V
Input voltage at VINL, VINA, VINR, VINC, VINM
Ground pins to system ground
Voltage at SWN
0.3
7
V
V
Voltage at SWP, VBIAS
20
12
7
V
Voltage at VOFS
V
Voltage at V6V, VLED, L1, L2, SWC, SW4, SW5, SW6, INTZ, PROJ_ON
Voltage at all pins, unless noted otherwise
Source current RESETZ, CMP_OUT
Source current SPI_DOUT
V
3.6
1
V
mA
mA
mA
mA
5.5
1
Sink current RESETZ, CMP_OUT
Sink current SPI_DOUT, INTZ
5.5
Peak output current
Internally limited
Internally limited by thermal
shutdown
Continuous total power dissipation
Operating junction temperature
TJ
–30
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Storage Conditions
applicable before the DMD is installed in the final product.
MIN
MAX
UNIT
ENVIRONMENTAL
Tstg
DMD Storage Temperature
–65
150
°C
6.3 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
Full functional and parametric performance
2.7
3.6
3.6
1.8
6
Input voltage range at VINL, VINA, VINR, VINC
VINM
,
V
6
Extended operating range, limited parametric
performance
2.3
Voltage range at VSPI
1.65
–10
–10
3.6
85
V
TA
TJ
Operational ambient temperature
Operational junction temperature
°C
°C
120
Copyright © 2014–2018, Texas Instruments Incorporated
5
DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
www.ti.com.cn
6.5 Thermal Information
DLPA2000
YFF (DSBGA)
56 PINS
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance(2)
45
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm × 114.3 mm, and
2-oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application.
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (see
(1)(2)
)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLIES
INPUT VOLTAGE
Input voltage range
2.7
2.3
3.6
3.6
3
6
V
6
VI
VINA, VINR, VINL, VINC
Extended input voltage range(1)
Low-battery warning threshold
Hysteresis
VINA falling
VINA rising
V
VLOW_BAT
100
mV
Undervoltage lockout threshold
Hysteresis
VINA falling (through 5-bit trim function)
VINA rising
2.3
2.5
4.5
V
mV
V
Vhys(UVLO)
VSTARTUP
100
Startup voltage
VBIAS, VOFS, VRST; loaded with 2 mA
INPUT CURRENT
IQ
ACTIVE mode
Motor current excluded
15
900
10
mA
µA
µA
ISTD
IIDLE
STANDBY mode
IDLE mode
INTERNAL SUPPLIES
VV6V
Internal supply, analog
6.25
100
2.5
V
nF
V
CLDO_V6V
VV2V5
Filter capacitor for V6V LDO
Internal supply, logic
CLDO_V2V5 Filter capacitor for V2V5 LDO
2.2
µF
DMD REGULATOR
Switch E (from VINR to SWN)
1000
320
RDS(ON)
MOSFET ON-resistance
Forward voltage drop
mΩ
Switch F (from SWP to PGNDR)
Switch G(2) (from SWP to VBIAS
VINR = 5 V, VSWP = 2 V, IF = 100 mA
)
1.3
1.3
VFW
V
Switch H (from SWP to VOFS
)
VINR = 5 V, VSWP = 2 V, IF = 100 mA
VIN = 2.9 V; COUT = 110 nF
Not tested in production
tDIS
tPG
ILIMIT
L
Rail discharge time
Power-good timeout
Switch current limit
Inductor value
40
µs
ms
mA
µH
6
312
10
VOFS REGULATOR
Output voltage
10
V
DC output voltage accuracy
DC load regulation
IOUT = 2 mA
–2%
2%
VOFS
VIN = 3.6 V, IOUT = 0 to 2 mA
–19
35
V/A
VINA, VINL, VINR, VINC 2.7 to 6.0 V, IOUT
2 mA
=
DC line regulation
mV/V
VRIPPLE
IOUT
Output ripple
VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF(3)
375
mVpp
mA
Output current
0
3
(1) Fully functional but limited parametric performance
(2) Including rectifying diode
(3) To reduce ripple the COUT can be increased. VRIPPLE is inversely proportional to COUT
.
6
Copyright © 2014–2018, Texas Instruments Incorporated
DLPA2000
www.ti.com.cn
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (see (1)(2)
)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Power-good threshold
(fraction of nominal output
voltage)
VOFS rising
VOFS falling
86%
PG
66%
100
RDIS
Output discharge resistor
Active when rail is disabled
Ω
Recommended value (output capacitors for
VOFS/VBIAS must be equal)
110
100
220
nF
COUT
Output capacitor
tDISCHARGE < 40 µs at 2.9 V
110
nF
Copyright © 2014–2018, Texas Instruments Incorporated
7
DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
www.ti.com.cn
MAX UNIT
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (see (1)(2)
)
PARAMETER
VBIAS REGULATOR
TEST CONDITIONS
MIN
TYP
Output voltage
18
V
DC output voltage accuracy
DC load regulation
IOUT = 2 mA
–2%
2%
VBIAS
VIN = 3.6 V, IOUT = 0 to 2 mA
–14
18
V/A
VINA, VINL, VINR, VINC 2.7 to 6 V,
IOUT = 2 mA
DC line regulation
mV/V
mVpp
VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF
VRIPPLE
IOUT
Output ripple
375
(3)
(see
)
Output current
0
4
mA
Power-good threshold
(fraction of nominal output
voltage)
VBIAS rising
86%
66%
100
PG
VBIAS falling
RDIS
Output discharge resistor
Active when rail is disabled
Ω
Recommended value (output capacitors for
VOFS / VBIAS must be equal)
110
100
220
COUT
Output capacitor
nF
tDISCHARGE < 40 µs at 2.9 V
110
3%
VRST REGULATOR
Output voltage
–14
V
DC output voltage accuracy
DC load regulation
IOUT = 2 mA
–3%
VRST
VIN = 3.6 V, IOUT = 0 to 2 mA
13
V/A
VINA, VINL, VINR, VINC 2.7 to 6 V,
IOUT = 2 mA
DC line regulation
Output ripple
–21
mV/V
VIN = 3.6 V, IOUT = 2 mA, COUT = 440 nF
VRIPPLE
375
500
mVpp
(3)
(see
)
VREF_VRST Reference voltage
mV
mA
IOUT
Output current
0
4
VRST rising
90%
90%
±150
220
Power-good threshold (fraction of
nominal output voltage)
PG
VRST falling
RDIS
COUT
Output discharge resistor
Output capacitor
Active when rail is disabled
Ω
110
100
nF
tDISCHARGE < 70 µs at VBAT ≥ 2.7 V
110
LED DRIVER
VLED BUCK-BOOST
Output voltage range
1.2
5.5
3.5
5.5
7
VLED
V
Default output voltage
Output overvoltage protection
Fault detection threshold
Switch current limit
SW4, SW5, SW6 in OPEN position
Clamps buck-boost output
3.5
VOVP
V
V
A
VLED_OVP
ISW
Triggers VLED_OVP interrupt
5.4
4.0
4.5
Switch A (from VINL to L1)
Switch B (from L1 to PGNDL)
Switch C (from L2 to PGNDL)
Switch D (from L2 to VLED)
50
50
RDS(ON)
MOSFET ON-resistance
mΩ
50
50
ƒSW
Switching frequency
Output capacitance
2.25
2 × 22
MHz
µF
COUT
RGB STROBE CONTROLLER SWITCHES
RDS(ON)
ILEAK
Drain-source ON-resistance
OFF-state leakage current
SW4, SW5, SW6
VDS = 5.0 V
30
75
1
mΩ
µA
8
Copyright © 2014–2018, Texas Instruments Incorporated
DLPA2000
www.ti.com.cn
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (see (1)(2)
)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LED CURRENT CONTROL
Vf
LED forward voltage
4.8
V
VIN ≥ 2.3 V, VLED ≤ 4.8 V
RLIM = 100 mΩ, 0.1%, TA = 25°C (see
register settings)
25
Current at minimum code 0x00Ch for SWx
IDAC[9:0].
DLPA2000 LED currents
mA
VIN ≥ 2.3 V, VLED ≤ 4.8 V
RLIM = 100 mΩ, 0.1%, TA = 25°C (see
register settings)
ILED
750
Current at maximum code 0x307h for
SWx_IDAC[9:0].
DC current accuracy, SW4, 5, 6
Transient LED current limit range
RLIM = 100 mΩ
25
130
mA
mA
ILIM[3:0] = 0000 at RLIM = 100 mΩ
ILIM[3:0] = 1111 at RLIM = 100 mΩ
1500
ILED from 5% to 95%, ILED = 300 mA,
Transient current limit disabled
Not tested in production
trise
Current rise time
50
µs
1.1-V REGULATOR
VCORE (BUCK)
VIN
Input voltage
2.3
6
V
V
Nominal fixed output voltage
1.1
VOUT
0 mA ≤ IOUT ≤ 600 mA at VIN > 2.5 V
VOUT = 1.1 V
DC output voltage accuracy
–1.5%
1.5%
d
Maximum duty cycle
100%
380
Low-side MOSFET on-resistance
High-side MOSFET on-resistance
Output current
185
240
300
1
mΩ
mΩ
mA
A
RDS(ON)
VIN = 3.6 V, TJ = 27ºC
VIN > 2.3 V
480
IOUT
600
ILIMIT
Switch current limit
Time to ramp from 10% to 90% of VOUT
VIN = 3.6 V
,
TSS
Soft-start time
250
µs
COUT
L
Output capacitance
Nominal Inductance
10
µF
µH
2.2
LOAD SWITCH
VIN
Input voltage range
LS_IN
1.8
3.6
V
P-channel MOSFET on-
resistance
RDS(ON)
VIN = 1.8 V, over full temperature range
385
505
mΩ
Output capacitor
Ceramic
Ceramic
4.7
5
10
20
12
µF
COUT
ESR of output capacitor
500
mΩ
MEASUREMENT SYSTEM (AFE)
AFE_GAIN[1:0] = 01
AFE_GAIN[1:0] = 10
AFE_GAIN[1:0] = 11
1.0
9.5
18
G
Amplifier gain (PGA)
V/V
mV
PGA, AFE_CAL_DIS = 1
Not tested in production
–1
1
1.5
15
VOFS
Input referred offset voltage
Comparator
Not tested in production
–1.5
To 1% of final value
(not tested in production)
tsettle
Settling time
µs
To 0.1% of final value
(not tested in production)
52
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MAX UNIT
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (see (1)(2)
)
PARAMETER
TEST CONDITIONS
Not tested in production
MIN
TYP
ƒsample
Sampling rate
19
kHz
LOGIC LEVELS AND TIMING CHARACTERISTICS
IO = 0.5-mA sink current
(RESETZ, CMP_OUT)
0
0
0.3
0.3 × VSPI
2.5
VOL
Output low-level
V
IO = 5-mA sink current
(SPI_DOUT, INTZ)
IO = 0.5-mA source current
(RESETZ, CMP_OUT)
1.3
VOH
Output high-level
Input low-level
V
IO = 5-mA source current
(SPI_DOUT)
0.7 × VSPI
VSPI
PROJ_ON, LED_SEL0, LED_SEL1
SPI_CSZ, SPI_CLK, SPI_DIN
PROJ_ON, LED_SEL0, LED_SEL1
SPI_CSZ, SPI_CLK, SPI_DIN
VIO = 3.3 V, any input pin
0
0
0.4
VIL
V
V
0.3 × VSPI
1.2
VIH
Input high-level
0.7 × VSPI
VSPI
0.5
IBIAS
Input bias current
µA
ms
PROJ_ON,
(not tested in production)
1
tDEGLITCH
Deglitch time
LED_SEL0, LED_SEL1 pins
(not tested in production)
300
ns
INTERNAL OSCILLATOR
Oscillator frequency
Frequency accuracy
THERMAL SHUTDOWN
9
MHz
ƒOSC
TA = –30 to 85°C
–10%
10%
Thermal warning (HOT threshold)
120
10
TWARN
°C
°C
Hysteresis
Thermal shutdown (TSD
threshold)
150
15
TSHTDWN
Hysteresis
MOTOR DRIVER
POWER SUPPLY
VINM
IM
H-BRIDGE FETS
Operating motor supply voltage
2
6
V
Operating motor current
500(4)
mA
VV2V5 = 2.5 V, VM = 3 V, IO = 200 mA,
TJ = 25°C
RDS(ON)
HS + LS FET on resistance
1.9
2.1
Ω
IOFF
Off-state leakage current
±200
nA
MOTOR DRIVER PROTECTION CIRCUITS
Overcurrent protection trip level
per A-out or B-out pin
IOCP
0.53
150
1.16
180
A
tTSD
Thermal shutdown temperature
Die temperature
160
°C
(4) Power dissipation and thermal limits must be observed
10
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6.7 Motor Driver Timing Requirements
The table lists the timing numbers to drive the motor voltages correctly, while Figure 2 shows the timing sequences.
NUMBER
MIN
MAX
300
200
200
300
200
300
300
300
160
160
188
188
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
tR
tF
Delay time, xPHASE high to xOUT1 low
Delay time, xPHASE high to xOUT2 high
Delay time, xPHASE low to xOUT1 high
Delay time, xPHASE low to xOUT1 low
Delay time, xENBL high to xOUTx high
Delay time, xENBL high to xOUTx low
Output enable time
3
4
5
6
7
8
Output disable time
9
Delay time, xINx high to xOUTx high
Delay time, xINx low to xOUTx low
Output rise time
10
11
12
30
30
Output fall time
x
x
x
x
Figure 2. Bridge Control
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6.8 Data Transmission Timing Requirements
VBAT = 3.6 ± 5%, TA = 25 ºC, CL = 10 pF (unless otherwise noted)
MIN
0
NOM
MAX
UNIT
MHz
ns
ƒCLK
tCLKL
tCLKH
tt
Serial clock frequency
36
Pulse width low, SPI_CLK, 50% level
Pulse width high, SPI_CLK, 50% level
Transition time, 20% to 80% level, all signals
SPI_CSZ falling to SPI_CLK rising, 50% level
SPI_CLK falling to SPI_CSZ rising, 50% level
SPI_DIN data setup time, 50% level
SPI_DIN data hold time, 50% level
SPI_DOUT data setup time(1), 50% level
SPI_DOUT data hold time(1), 50% level
SPI_CLK falling to SPI_DOUT data valid, 50% level
SPI_CSZ rising to SPI_DOUT HiZ
10
10
0.2
8
ns
4
1
ns
tCSCR
tCFCS
tCDS
tCDH
tiS
ns
ns
7
6
ns
ns
10
0
ns
tiH
ns
tCFDO
tCSZ
13
6
ns
ns
(1) The DPPxxxx processors send and receive data on the falling edge of the clock.
SPI_CSZ
(SS)
tCSCR
tCLKL
tCLKH
tCFCS
SPI_CLK
(SCLK)
tCDS
tCDH
SPI_DIN
(MOSI)
tCFDO
tiH
tCSZ
tiS
SPI_DOUT
(MISO)
HiZ
HiZ
Figure 3. SPI Timing Diagram
12
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6.9 Typical Characteristics
The maximum output current of the buck-boost is a function of input voltage (VIN) and output voltage (VLED). The relationship
between VIN, VLED, and MAX ILED is shown in Figure 4. Note that VLED is the output of the buck-boost regulator, which includes
the voltage drop across the sense resistor RLIM (100 mΩ typical), internal strobe control switch
(75 mΩ max), and the forward voltage of the LED.
Gamma Curves
0.8
0.6
0.4
0.2
0
2
3
4
5
6
VIN(V)
D001
2.3 V < VLED < 4.8 V
Figure 4. Maximum LED Output Current as a Function of
Input Voltage (VIN) and Buck-Boost Output Voltage (VLED
)
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7 Detailed Description
7.1 Overview
The DLPA2000 is a power management and LED driver IC optimized for DLP video and data display systems
and meant for use in either embedded or accessory projector applications. DLPA2000 is part of the chipset
comprising of either DLP2010 (0.2 WVGA) DMD and DLPC3430/DLPC3435 controller or the DLP2010NIR (0.2
WVGA NIR) DMD and DLPC150 controller. The DLPA2000 contains a complete LED driver including high
efficiency power convertors. The DLPA2000 can supply up to 750 mA per LED. Integrated high-current switches
are included for sequentially selecting R, G, and B LEDs. The DLPA2000 also contains three regulated DC
supplies for the DMD reset circuitry: VBIAS, VRST and VOFS, as well as a regulated DC supply of 1.1 V and a load
switch for the 1.8 V to support the DLPC3430 or DLPC3435 controller. The DLPA2000 also contains a motor
driver which can be used to drive the focus lens motor. The DLPA2000 has a SPI used for setting the
configuration. Using SPI, currents can be set independently for each LED with 10-bit resolution. Other features
included are the generation of the system reset, power sequencing, input signals for sequentially selecting the
active LED, IC self-protections, and an analog MUX for routing analog information to an external ADC.
14
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7.2 Functional Block Diagram
VINA
V2V5
REFERENCE
SYSTEM
VREF
VLED
From system power
LDO_V2V5
LDO_V6V
2.2µ
1µ
UVLO
V6V
VREF
VLED_OVP
100n
LOW_BAT
VREF
VINL
From system power
AGND
A
AGND1
SET_LOW_BAT_USB
L1
1µ
B
PGNDL
2.2µ
VLED
AFE_GAIN [1:0]
AFE_SEL[3:0]
BUCK-BOOST
C
VINA/3
VLED/3
SW4
AFE
L2
PWM_IN
From host
SW5
SW6
RLIM_K
VREF
D
CMP_OUT
VLED
22µ
To host
MUX
22µ
SW4
SENS1
From light sensor
SW5
SW6
SENS2
RGB
STROBE
DECODER
From temperature sensor
RLIM
VINR
RLIM
From system power
RLIM_K
RBOT_K
E
10µ
SWN
REF_VRST
SWP
VRST
MOTOR DRIVER
Full H-Bridge
VINM
From system power
100k
220n
Aout1
Aout2
10µ
H
CNTR_VRST
G
F
DMD
RESET
REGULATORS
Bout1
Bout2
220n
220n
PGNDR
VBIAS
VOFS
Full H-Bridge
VBIAS
VOFS
VINC
From system power
2.2uH
SWC
Vout DCDC1 (0.9-1.2V @ 450mA)
VCORE
BUCK
10µF
PGNDC/PGNDM
VCORE
LS_IN
from any 1.8V-3.3V supply
LS_OUT
to system load
Load Switch
10mF
V2V5
PROJ_ON
LED_SEL0
LED_SEL1
RESETZ
From host
From host
From host
To system
0.1u
DIGITAL
CORE
VSPI
SPI_CSZ
SPI_CLK
SPI_DIN
VIO (depends on DPP requirements)
5k
From host
From host
INTZ
To DPP (optional)
From host
From host
SPI
DGND
SPI_DOUT
To host
A. Pin names refer to DLPA2000 pinout
B. Pins connected to ‘system power’ can be locally decoupled with the capacity as indicated in the block diagram. At
least adequate decoupling capacity (50 μF or more) should be connected at the location the supply is entering the
board.
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7.3 Feature Description
7.3.1 DMD Regulators
DLPA2000 contains three switch-mode power supplies that power the DMD. These rails are VOFS, VBIAS, and
VRST. After pulling the PROJ_ON pin high, the DMD is first initialized followed by a power-up of the VOFS line
after a small delay of less than 10 ms followed by VBIAS and VRST with an additional delay of 145 ms. The LED
driver and STROBE DECODER circuit can only be enabled after all three rails are enabled. There are two
power-down sequences, the normal power-down timing initiated after pulling the PROJ_ON pin low, and a fast
power-down mode where if any one of the rails encounters a fault such as an output short, all three rails are
discharged simultaneously. The detailed power-up and power-down diagrams are shown in Figure 5 and
Figure 6.
5 ms (min)
System Power
(VINx)
10 ms
25 ms
PROJ_ON
DMD_EN
in register 0x01h
V2V5
Stop Regulating
VBIAS
VBIAS
Pad DMD_EN
by DPP through
VOFS
SPI write
VRST
Stop Regulating
VRST
10 ms
DMD
initialization
by DPP
≤ 10 ms
145 ms
≥10 ms
VCORE
LS_OUT (1.8 V)
VLED
INTZ
Startup DPP
RESETZ
ACTIVE1
OFF
STANDBY
ACTIVE2
OFF
STATE
Figure 5. Power Sequence Normal Shutdown Mode
NOTE
All values are typical (unless otherwise noted).
16
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Feature Description (continued)
Fault Condition
5 ms (min)
System Power
(VINx)
PROJ_ON
DMD_EN
in register 0x01h
V2V5
Stop Regulating
VBIAS
VBIAS Delay
VBIAS
Pad DMD_EN
by DPP through
VOFS
VOFS
Delay
SPI write
VRST
VRST Delay
10 ms
DMD
initialization
by DPP
≤ 10 ms
145 ms
Stop Regulating
VRST
≥ 10 ms
VCORE
LS_OUT (1.8V)
VLED
INTZ
Startup DPP
RESETZ
RESETZ Delay
STANDBY
ACTIVE1
OFF
STANDBY
ACTIVE2
STATE
A. If the FAULT condition happens and its associated interrupt is masked in the interrupt mask register (0Dh), the INTZ
does not go low, but all other timing shown in the diagram is unaffected.
Figure 6. Power Sequence Fault Shutdown Mode
NOTE
All values are typical (unless otherwise noted).
7.3.2 RGB Strobe Decoder
DLPA2000 contains RGB color-sequential circuitry that is composed of three NMOS switches, the LED driver,
the strobe decoder, and the LED current control. The NMOS switches are connected to the terminals of the
external LED package and turn the currents through the LEDs on and off. Package connections are shown in
Figure 7 and Figure 10 and the corresponding switch map is in Table 1.
The LED_SEL[1:0] signals typically receive a rotating code switching from RED to GREEN to BLUE and then
back to RED. When the LED_SEL[1:0] input signals select a specific color, the NMOSFETs are controlled based
on the color selected, and a 10-bit current control DAC for this color is selected that provides a control current to
the RGB LEDs' feedback control network.
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Feature Description (continued)
VLED
SW4
SW5
SW6
R
G
B
SW4
SW5
SW6
RLIM
RLIM_K
RLIM
RBOT_K
Figure 7. Switch Connection for a Common-Anode LED Assembly
Table 1. Switch Positions for Common Anode RGB LEDs (MAP = 0)
Common Anode
LED_SEL[1:0]
0x00h
SW6
Open
Open
Open
Closed
SW5
Open
Open
Closed
Open
SW4
Open
Closed
Open
Open
IDAC INPUT
N/A
0x01h
SW4_IDAC[9:0]
SW5_IDAC[9:0]
SW6_IDAC[9:0]
0x02h
0x03h
The switching of the three NMOS switches is controlled such that switches are returned to the open position first
before the closed connections are made (break before make). The dead time between opening and closing
switches is controlled through the BBM register. Switches that already are in the closed position (and are to
remain in the closed state according to the SWCNTRL register) are not opened during the BBM delay time.
BBM dead time
SW6
SW4
SW5
SW6
SW4
TIME
Figure 8. BBM Timing (See Register 0Bh in Figure 27)
7.3.3 LED Current Control
DLPA2000 provides time-sequential circuitry to drive three LEDs with independent current control. A system
based on a common anode LED configuration is shown in Figure 10 and consists of a buck-boost converter,
which provides the voltage to drive the LEDs, three switches connected to the cathodes of the LEDs, an RLIM
resistor used to sense the LED current, and a current DAC to control the LED current. The voltage measured at
the pin V(RLIM_K) is used by the regulator loop.
The STROBE DECODER controls the switch positions as described in the previous section (RGB Strobe
Decoder). With all switches in the open position, the buck-boost output assumes an output voltage of 3.5 V.
18
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For a common-anode RGB LED configuration, the buck-boost output voltage (VLED) assumes a value such that
the voltage drop across the sense resistor equals:
(SW4_IDAC[9:0]Ivalue + ILED) × RLIM
(1)
The exact value of VLED depends on the current setting and the voltage drop across the LED but is limited to
5.4 V. When the STROBE decoder switches from SW4 to SW5, the buck-boost assumes a new output voltage
such that the sense voltage equals:
(SW5_IDAC[9:0]Ivalue + ILED) × RLIM
(SW6_IDAC[9:0]Ivalue + ILED) × RLIM
(2)
(3)
The relationship between VIN, VLED, and MAX ILED is shown in Figure 4.
7.3.4 Calculating Inductor Peak Current
To properly configure the DLPA2000 device, a 2.2-µH inductor must be connected between pin L1 and pin L2.
The peak current for the inductor in steady state operation can be calculated.
Equation 4 shows how to calculate the peak current I1 in step down mode operation, and Equation 5 shows how
to calculate the peak current I2 in boost mode operation. VIN1 is the maximum input voltage, VIN2 is the minimum
input voltage, f is the switching frequency (2.25 MHz), and L the inductor value (2.2 µH).
VOUT
VIN1 - VOUT
IOUT
0.8
(
)
I1 =
+
2ì VIN1 ì f ìL
(4)
V
V
- V
VOUT ìIOUT
(
)
IN2
OUT IN2
I2 =
+
0.8ì V
2ì VOUT ì f ìL
IN2
(5)
The critical current value for selecting the right inductor is the higher value of I1 and I2. Also consider that load
transients and error conditions may cause higher inductor currents. This needs to be accounted for when
selecting an appropriate inductor. Internally the switching current is limited to a maximum of 4 A.
7.3.5 LED Current Accuracy
The LED drive current is controlled by a current digital-to-analog converter (DAC) and can be set independently
for switch SW4, SW5, and SW6. The DAC is trimmed at a current of 750 mA for the DLPA2000 at code: 0x307h.
The DLPA2000 current step size is 0.95 mA.
First order gain-error of the DAC can be neglected, but an offset current error must be taken into account. This
offset error differs depending on the used RLIM and will be ±25 mA for the DLPA2000 for a 100-mΩ current sense
resistor.
The max current of the DLPA2000 (SWx_IDAC[9:0] = 0x307h) is regulated to 750 mA. At the lowest setting
(SWx_IDAC[9:0] = 0x001h) the current is regulated to 14 mA for the DLPA2000. For this current setting
(0x001h), the absolute current error results into a large relative error; however, this is not a typical operating
point.
Be aware that the LED current setting not only depends on the accuracy of the RLIM resistor, but also strongly
depends on the added resistance of PCB traces and soldering quality. Due to the low value of the current sense
resistor RLIM, any extra introduced resistance (for example several mΩ) will result in a noticeable different LED
current.
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7.3.6 Transient Current Limiting
Typically the forward voltages of the green and blue diodes are close to each other (about 3 V to 4 V). However,
the forward voltage of the red diode is significantly lower (1.8 V to 2.5 V). This can lead to a current spike in the
red diode when the strobe controller switches from green or blue to red because VLED is initially at a higher
voltage than required to drive the RED diode. DLPA2000 provides transient current limiting for each switch to
limit the current in the LEDs during the transition. The transient current limit value is controlled through the
ILIM[3:0] bits in the IREG register. The same register also contains three bits to select which switch employs the
transient current limiting feature. In a typical application, the transient current limit will only apply to the RED
diode, and the ILIM[3:0] value will typically be set approximately 10% higher than the DC regulation current. The
effect that the transient current limit has on the LED current is shown in Figure 9.
1500
1200
900
600
300
0
1500
1200
900
600
300
0
Current overshoot due to
initially too high buck-boost
output voltage
Transient current
limit active
TIME
LED current with transient current limit.
Red LED current without transient current limit. The
current overshoots because the buck-boost voltage
starts at the (higher) level of the green or blue LED.
Figure 9. RED LED Current With and Without Transient Current Limit
20
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VLED
BUCK-BOOST
VLED
FB
SW4LIM_EN
SW4
I-LED
0
ILIM [3:0]
VDAC
E/A
1
SW5LIM_EN
SW5
I-LED
0
E/A
1
SW6LIM_EN
SW6
I-LED
0
LED_SEL [1:0]
MAP
STROBE
DECODER
RLIM
E/A
1
SW4_IDAQ [9:0]
RLIM_K
SW5_IDAQ [9:0]
SW6_IDAQ [9:0]
IDAC
I-DAC
200
RLIM
RBOT_K
Figure 10. LED Driver Block Diagram
7.3.7 1.1-V Regulator (Buck Converter)
The buck converter creates a voltage of 1.1 V, and due to its switching nature, an output ripple with a frequency
of approximately 2.25 MHz occurs on its output. This ripple is strongly dependent on the decoupling capacitor at
the output in combination with the inductor. The magnitude of the ripple can be calculated with Equation 6.
VCORE
1 -
≈
∆
«
’
÷
◊
V
1
INC
DVCORE = VCORE
ì
ì
+ ESR
L ì f
8 ì COUT ì f
(6)
21
The best way to minimize this ripple is to select a capacitor with a very-low ESR.
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7.3.8 Motor Driver
Two control modes are available in the DLPA2000: IN/IN mode and PHASE/ENABLE mode. IN/IN mode is
selected if the MODE pin is driven low or left unconnected; PHASE/ENABLE mode is selected if the MODE pin is
driven to logic high. Table 2 and Table 3 show the logic for these modes.
The main difference between both modes is that to change the rotation direction for IN/IN mode, both xIN1 and
xIN2 signals must change polarity, while for PHASE/ENABLE mode, the PHASE signal must be held high while
the PHASE signal is used to change rotation direction for a DC motor. In case a stepper motor is used, the
sequence of OUT1 and OUT2 determines the rotation direction.
The motor position is changed by using the internal, register-generated, control signals AIN1 and AIN2 (register
0F[123:122] in combination with BIN1 and BIN2 (register 0F[121:120].
Table 2. IN/IN Mode (See Figure 31)
MD_MODE
BIT 124 REG 0Fh
FUNCTION
(DC MOTOR)
xIN1
xIN2
xOUT1
xOUT2
0
0
0
0
0
0
1
1
0
1
0
1
Z
L
Z
H
L
Coast
Reverse
Forward
Brake
H
L
L
Table 3. PHASE/ENABLE Mode (See Figure 31)
MD_MODE
BIT 124 REG 0Fh
xIN1
(ENABLE)
xIN2
(PHASE)
FUNCTION
(DC MOTOR)
xOUT1
xOUT2
1
1
1
0
1
1
X
1
0
L
L
L
H
L
Brake
Reverse
Forward
H
7.3.8.1 Motor Driver Overcurrent Protection
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for a longer period of time than the overcurrent deglitch time, all FETs in the H-
bridge will be disabled. After approximately 1 ms, the bridge will be re-enabled automatically.
7.3.9 Measurement System
The measurement system is composed of a 10:1 analog multiplexer (MUX), a programmable-gain amplifier, and
a comparator. It works together with the DPP processor to provide:
•
White-point correction (WPC) by independently adjusting the RGB LED currents after measuring the
brightness of each color with an external light sensor
•
A measurement of the:
–
–
–
–
Battery voltage
LED forward voltage
Exact LED current
Temperature as derived by measuring the voltage across an external thermistor
Figure 11 shows a block diagram of the measurement system.
22
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AFE_GAIN [1:0]
AFE_SEL[3:0]
From host
VINA/3
VLED/3
SW4
AFE
PWM_IN
SW5
CMP_OUT
MUX
To host
From light sensor
SENS1
SENS2
From temperature sensor
Figure 11. Block Diagram of the Measurement System
Table 4. Recommended Configuration of the AFE for Different Input Selections
RECOMMENDED GAIN SETTING
AFE-GAIN[1:0]
RECOMMENDED SETTING OF
AFE_CAL_DIS BIT
AFE_SEL[3:0]
SELECTED INPUT
0x00h
0x01h
0x02h
0x03h
SENS2
VLED
0x01h (1x)
0x01h (1x)
0x01h (1x)
0x01h (1x)
Setting has no effect on measurement.
Setting has no effect on measurement.
Setting has no effect on measurement.
Setting has no effect on measurement.
VINA
SENS1
Set to 1 if sense voltage is >100 mV.
Otherwise set to 0 (default).
0x04h
0x05h
0x06h
0x07h
RLIM_K
SW4
0x03h (18x)
0x02h (9.5x)
0x02h (9.5x)
0x02h (9.5x)
Set to 1 if sense voltage is >200 mV.
Otherwise set to 0 (default).
Set to 1 if sense voltage is >200 mV.
Otherwise set to 0 (default).
SW5
Set to 1 if sense voltage is >200 mV.
Otherwise set to 0 (default).
SW6
0x08h
0x09h
No connect
VREF
N/A
N/A.
0x01h (1x)
Setting has no effect on measurement.
7.3.10 Protection Circuits
DLPA2000 has several protection circuits to protect the IC and system from damage due to excessive power
consumption, die temperature, or over-voltages. These circuits are described in the following sections.
7.3.10.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)
DLPA2000 continuously monitors the junction temperature and issues a HOT interrupt if temperature exceeds
the HOT threshold. If the temperature continues to increase above the thermal shutdown threshold, all rails are
disabled and the TSD bit in the INT register is set. After the temperature drops below its threshold, the system
recovers and waits for the DPP to resend the DMD_EN bit.
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Thermal Shutdown
Threshold
Hysteresis
Hysteresis
Thermal warning
Threshold
Temperature
HOT
(Internal Signal)
TSD
(Internal Signal)
Available Time for Controlled
Shutdown of System
Figure 12. Definition of the Thermal Shutdown and Hot-Die Temperature Warning
7.3.10.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)
If the battery voltage drops below the BAT_LOW threshold (typically 3.0 V) the BAT_LOW interrupt is issued, but
normal operation continues. After the battery drops below the undervoltage threshold which has a default
hardcoded value of 2.3 V (this UVLO voltage can be changed through register 09h from 2.3 V to 4.5 V), the
UVLO interrupt is issued, all rails are powered down in sequence, the DMD_EN bit is reset, and the part enters
STANDBY mode. The power rails cannot be re-enabled before the input voltage recovers to >2.4 V. To re-enable
the rails, the PROJ_ON pin must be toggled. The undervoltage threshold is programmable from 2.3 V to 4.5 V in
31 steps.
The UVLO shutdown process will protect the DMD by allowing time for the mirrors to park, then doing a fast
discharge of VOFS, VRST, and VBIAS. This protection occurs even in the case of sudden battery removal from the
projector, as long as the bulk capacitance on the battery voltage (VINx) keeps this voltage above 2.3 V for as long
as needed for VOFS, VRST, and VBIAS to discharge to the required safe levels as shown in the DMD data sheet.
VOFS, VRST, and VBIAS discharge times depend on the load capacitance on each regulator. When for instance
every supply is decoupled using a capacitor of 0.5 µF, VINx should stay above 2.3 V for at least 100 µs after the
battery is suddenly removed. During this time, the mirrors can be placed in a safe position and VOFS, VRST, and
VBIAS can be discharged.
NOTE
As required by the DMD data sheet, LS_OUT must stay above 1.65 V until VOFS, VRST
,
and VBIAS have discharged to their required safe levels.
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VINA
Hysteresis
BAT_LOW Threshold
Hysteresis
UVLO Threshold
ACTIVE
BAT LOW
(Internal Signal)
INACTIVE
ACTIVE
200-µs
deglitch
UVLO
INACTIVE
(Internal Signal)
Programmable Deglitch Time1
A. This time is programmable from 0 to 100 µs.
Figure 13. UVLO is Asserted When the Input Supply Drops Below the UVLO Threshold
7.3.10.3 DMD Regulator Fault (DMD_FLT)
The DMD regulator is continuously monitored to check if the output rails are in regulation and if the inductor
current increases as expected during a switching cycle. If either one of the output rails drops out of regulation (for
example, due to a shorted output) or the inductor current does not increase as expected during a switching cycle
(due to a disconnected inductor), the DMD_FLT interrupt bit is set in the INT register, the DMD_EN bit is reset,
and the DMD regulator is shut down. Resetting the DMD_EN bit also causes the LED driver to power down. To
restart the system, the PROJ_ON pin must be toggled. In case the interrupt is masked, it is sufficient to set the
DMD_EN bit to restart the system.
7.3.10.4 V6V Power-Good (V6V_PGF) Fault
The LED driver regulation loop requires the V6V rail for proper operation. The rail is continuously monitored and
should the output drop below the power-good threshold, the V6V_PGF bit is set. The VLED buck-boost is then
disabled and attempts to restart automatically.
7.3.10.5 VLED Overvoltage (VLED_OVP) Fault
If the buck-boost output voltage rises above 5.4 V, the VLED_OVP interrupt is set but the buck-boost regulator is
not turned off. A typical condition to cause this fault is an open LED.
7.3.10.6 VLED Power Save Mode
In normal PWM operation, the efficiency of the VLED buck-boost converter dramatically reduces for LED currents
below 100 mA. In this case, the power save mode allows high converting efficiency at low output currents by
skipping pulses in the switcher’s gate driver control.
7.3.10.7 V1V8 PG Failure
If for any reason the voltage on the LS_OUT drops below approximately 1.3 V, then VOFS, VBIAS, and VRST
immediately go into fast shut down. Holding off power down to do mirror parking is not included since 1.3 V is too
low to wait for this. Reactivating can only be done by toggling the PROJ_ON off and on again.
7.3.10.8 Interrupt Pin (INTZ)
The interrupt pin is used to signal events and fault conditions to the host processor. Whenever a fault or event
occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output is pulled low.
The INTZ pin is released (returns to HiZ state) and fault bits are cleared when the INT register is read by the
host.
However, if a failure persists, the corresponding INT bit remains set and the INTZ pin is pulled low again after a
maximum of 32 µs.
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Interrupt events include fault conditions such as power-good faults, over-voltage, over-temperature shutdown,
and UVLO. For all interrupt conditions see the interrupt register on Figure 28.
The MASK register is used to mask events from generating interrupts, that is, from pulling the INTZ pin low. The
MASK settings affect the INTZ pin only and have no impact on protection and monitor circuits themselves. When
an interrupt is masked, the event causing the interrupt still sets the corresponding bit in the INT register.
However, it does not pull the INTZ pin low.
7.3.10.9 SPI
DLPA2000 provides a 4-wire SPI port that supports high-speed serial data transfers up to 33.3 MHz. Support
includes register and data buffer write and read operations. The SPI_CSZ input serves as the active low chip
select for the SPI port. The SPI_CSZ input must be forced low in order to write or read registers and data
buffers. When SPI_CSZ is forced high, the data at the SPI_DIN input is ignored, and the SPI_DOUT output is
forced to a high-impedance state. The SPI_DIN input serves as the serial data input for the port; the SPI_DOUT
output serves as the serial data output. The SPI_CLK input serves as the serial data clock for both the input and
output data. Data is latched at the SPI_DIN input on the rising edge of SPI_CLK, while data is clocked out of the
SPI_DOUT output on the falling edge of SPI_CLK. Figure 14 shows the SPI port protocol. Byte 0 is referred to as
the command byte, where the most significant bit is the write/not read bit. For the W/nR bit, a 1 indicates a write
operation, while a 0 indicates a read operation. The remaining seven bits of the command byte are the register
address targeted by the write or read operation. The SPI port supports write and read operations for multiple
sequential register addresses through the implementation of an auto-increment mode. As shown in Figure 14,
the auto-increment mode is invoked by simply holding the SPI_CSZ input low for multiple data bytes. The
register address is automatically incremented after each data byte transferred, starting with the address specified
by the command byte. After reaching address 0x7Fh the address pointer jumps back to 0x00h.
Set SPI_CSZ = 1 here to write/read one register location
Hold SPI_CSZ = 0 to enable auto-increment mode
SPI_CSZ
SPI_DIN
Header
Register Data (write)
Byte0
Byte1
Byte2
Byte3
ByteN
Register Data (read)
Data for A[6:0]
Data for A[6:0] + 1
SPI_DOUT
SPI_CLK
Data for A[6:0] + (N – 2)
Byte 0
Byte 1
W/nR
W/nR
SPI_DIN
A6 A5 A4 A3 A2 A1 A0 N7 N6 N5 N4 N3 N2 N1 N0
Set high for write, low for read
Register Address
SPI_CLK
Figure 14. SPI Protocol
7.3.11 Password Protected Registers
Register addresses 0x11h through 0x27h can be read-accessed the same way as any other register, but are
protected against accidental write operations through the PASSWORD register (address 0x10h). To write to a
protected register, follow these steps:
1. Write data 0xBAh to register address 0x10h.
2. Write data 0xBEh to register address 0x10h.
Both writes must be consecutive, that is, there must be no other read or write operation in between sending the
two bytes. After the password has been successfully written, registers 0x11h through 0x27h are unlocked and
can be write accessed using the regular SPI protocol. They remain unlocked until any byte other than 0xBAh is
written to the PASSWORD register or the part is power cycled.
To check if the registers are unlocked, read back the PASSWORD register. If the data returned is 0x00h, the
registers are locked. If the PASSWORD register returns 0x01h, the registers are unlocked.
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7.4 Device Functional Modes
Table 5. Modes of Operation
MODE
DESCRIPTION
This is the lowest-power mode of operation. All power functions are turned off, registers are reset to their default values, and
the IC does not respond to SPI commands. RESETZ pin is pulled low. The IC will enter OFF mode whenever the PROJ_ON
pin is low.
OFF
The DMD regulators and LED power (VLED) are turned off, but the IC does respond to the SPI. The device enters STANDBY
mode whenever PROJ_ON is set high or DMD_EN(1) bit is set to 0 using the SPI interface after PROJ_ON is already high.
The device also enters STANDBY mode when a fault condition is detected(2). (See Protection Circuits).
STANDBY
The DMD supplies are enabled but LED power (VLED) is disabled. PROJ_ON pin must be high, DMD_EN bit must be set to 1,
and VLED_EN(3) bit is set to 0.
ACTIVE1
ACTIVE2
DMD supplies and LED power are enabled. PROJ_ON pin must be high and DMD_EN and VLED_EN bits must both be set to
1.
(1) Settings can be done through Reg01h [9] and Reg2E [119].
(2) Power-good faults, over-voltage, overtemperature shutdown, and undervoltage lockout.
(3) Settings can be done through Reg47h [60], bit is named VLED_EN_SET
.
Table 6. Device State as a Function of Control-Pin
Status
PROJ_ON PIN
STATE
LOW
OFF
STANDBY
ACTIVE1
ACTIVE2
HIGH
(Device state depends on DMD_EN and VLED_EN
bits and whether there are any fault conditions.)
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POWERDOWN
Valid power source connected
VRST = OFF
VBIAS = OFF
VOFS = OFF
VLED = OFF
PROJ_ON = low
OFF
SPI interface disabled
PWR_EN = low
RESETZ = low
All registers set to default values
PROJ_ON = low
PROJ_ON = high
VRST = OFF
VBIAS = OFF
VOFS = OFF
DMD_EN = 0
||
VLED = OFF
FAULT = 1
STANDBY
SPI interface enabled
PWR_EN = high
RESETZ = high (but is low if entered
state due to UVLO detection)
DMD_EN = 1
FAULT = 0
&
VRST = ON
VBIAS = ON
VOFS = ON
ACTIVE 1
VLED = OFF
SPI interface enabled
PWR_EN = high
RESETZ = high
VLED_EN = 1
VLED_EN = 0
VRST = ON
VBIAS = ON
VOFS = ON
VLED = ON
ACTIVE 2
SPI interface enabled
PWR_EN = high
RESETZ = high
A. || = OR, & = AND.
B. FAULT = Undervoltage on any supply (except LS_OUT), thermal shutdown, or UVLO detection.
C. UVLO detection, per the diagram, causes the DLPA2000 to go into the standby state. This is not the lowest power
state. If lower power is desired, PROJ_ON should be set low.
D. DMD_EN register bit can be reset or set by SPI writes. DMD_EN defaults to 0 when PROJ_ON goes from low to high
and then the DPP ASIC software automatically sets it to 1. Also, FAULT = 1 causes the DMD_EN register bit to be
reset.
E. PWR_EN is a signal internal to the PAD200x. This signal turns on the VCORE regulator and the load switch that
drives pin LS_OUT.
Figure 15. State Diagram
28
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7.5 Register Maps
Table 7. Register Description
ADDRESS
REGISTER
DEFAULT
NAME
TABLE
DESCRIPTION
(HEX)
USER CONFIGURATION DEFINITIONS
R
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
CHIP ID
CHIPENABLE
IREG
Figure 16
Chip revision register; DLPA2000
B3
0F
30
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Figure 17
Enable register
Figure 18
Transient-current limit settings
Regulation current MSB, SW4
Regulation current LSB, SW4
Regulation current MSB, SW5
Regulation current LSB, SW5
Regulation current MSB, SW6
Regulation current LSB, SW6
Switch ON/OFF control (direct mode)
AFE (MUX) control
SW4MSB
SW4LSB
SW5MSB
SW5LSB
SW6MSB
SW6LSB
SWCNTRL
AFE
Figure 19
Table 12, Table 13
Figure 21
0
0
Figure 22, Table 16
Figure 23
0
0
Figure 24, Table 19
Figure 25
0
0
Figure 26
0
BBM
Figure 27, Table 22
Figure 28, Table 23
Figure 29, Table 24
Break before make timing
Interrupt register
0
INT
0
R/W
INT MASK
Interrupt mask register
DFh
Timing register VOFS, VBIAS, VRST, and
RESETZ
R/W
R/W
0x0E
0x0F
TIMING
Figure 30, Table 26
Figure 31, Table 27
7
0
MOTOR CTRL
Motor control register
USER PROTECTED DEFINITION
R/W
R/W
0x10
0x11
PASSWORD
SYSTEM
Figure 32
Figure 33
Password register
0
0
System configuration register
USER EEPROM SCRATCH PAD DEFINITION
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
User EEPROM, Byte0
User EEPROM, Byte1
User EEPROM, Byte2
User EEPROM, Byte3
User EEPROM, Byte4
User EEPROM, Byte5
User EEPROM, Byte6
User EEPROM, Byte7
0
0
0
0
0
0
0
0
7.5.1 Chip Revision Register
Figure 16. Chip Revision Register, Address = 00h, HEX = B3
7
6
5
4
3
2
1
0
CHIP ID [7:0]
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 8. Chip Revision Register Field Descriptions
BIT
7:4
3:0
FIELD
TYPE
RESET
1011
0011
DESCRIPTION
R
R
CHIPID<3:0>
REVID<3:0>
CHIP ID
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7.5.2 Enable Register
Figure 17. Enable Register, Address = 01h, HEX = 0F
7
6
5
4
3
2
1
0
CHIPENABLE [15:8]
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Enable Register Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
0000
DESCRIPTION
15:12
USER_GPO<3:0>
VLED_POWER_SAVE_MODE_DIS
Power save mode is used to improve efficiency at light load.
11
R/W
1
FAST_SHUTDOWN_EN
Applicable only during a fault condition.
Shutdown timing is defined by register 0Eh (see Figure 7).
CHIPENABLE
10
R/W
1
9
8
R/W
R/W
1
1
DMD_EN
VLED_EN
7.5.3 Transient-Current Limit Settings
Figure 18. Transient-Current Limit Settings, Address = 02h, HEX = 30
7
6
5
4
3
2
1
0
IREG [23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 10. Transient-Current Limit Settings Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
23
RSVD
0
Not used
IREG_ILIM<3:0>
0000
RLIM = 100 mΩ
130 mA
150 mA
172 mA
192 mA
220 mA
275 mA
330 mA
440 mA
550 mA
660 mA
770 mA
880 mA
990 mA
1160 mA
1330 mA
1500 mA
0001
0010
0011
0100
0101
0110
22:19 IREG
R/W
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SW6LIM_EN
Transient current-limit enable for SW6
0 – Transient current-limit is disabled
1 – Transient current-limit is enabled
18
SW6LIM_EN
R/W
0
30
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ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
Table 10. Transient-Current Limit Settings Field Descriptions (continued)
FIELD
TYPE
RESET
DESCRIPTION
SW5LIM_EN
Transient current-limit enable for SW5
0 – Transient current-limit is disabled
1 – Transient current-limit is enabled
17
16
SW5LIM_EN
R/W
0
0
SW4LIM_EN
Transient current-limit enable for SW4
0 – Transient current-limit is disabled
1 – Transient current-limit is enabled
SW4LIM_EN
R/W
7.5.4 Regulation Current MSB, SW4
Figure 19. Regulation Current MSB, SW4, Address = 03h, HEX = 00
7
6
5
4
3
2
1
0
SW4MSB [31:24]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 11. Regulation Current MSB, SW4 Field Descriptions(1)
BIT
FIELD
TYPE
R/W
R/W
RESET
0000
0000
DESCRIPTION
31:26
25:24
TBD
SW4MSB
SW4_IDAC<9:8>
(1) The DLPA2000 can use up to code 0x0FFh for SW4_IDAC[9:0].
7.5.5 Regulation Current LSB, SW4
Figure 20. Regulation Current LSB, SW4, Address = 04h, HEX = 00
7
6
5
4
3
2
1
0
SW4LSB [39:32]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 12. Regulation Current LSB, SW4 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
39:32
SW4LSB
R/W
00000000 SW4_IDAC<7:0>
Table 13. Regulation Current LSB, SW4 Bit Definitions
DLPA2000(1)(2)
SW4_IDAC[9:0]
0x000h
LED CURRENT
0 mA
SW4_IDAC[9:0]
0x100h
LED CURRENT
257 mA
SW4_IDAC[9:0]
0x200h
LED CURRENT
500 mA
0x00Ch
25 mA
26 mA
...
0x101h
0x102h
...
258 mA
259 mA
...
0x201h
0x202h
...
501 mA
502 mA
...
0x00Dh
...
0x0FEh
255 mA
256 mA
0x1FEh
0x1FFh
498 mA
499 mA
0x306h
0x307h
749 mA
750 mA
0x0FFh
(1) Values shown are for a typical DLPA2000 unit at T = 25°C. Typical step size is 0.95 mA for RLIM = 100 mΩ.
(2) The DLPA2000 can use up to code 0x307h for SW4_IDAC[9:0].
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7.5.6 Regulation Current MSB, SW5
Figure 21. Regulation Current MSB, SW5, Address = 05h, HEX = 00
7
6
5
4
3
2
1
0
SW5MSB [47:40]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 14. Regulation Current MSB, SW5 Field Descriptions(1)
BIT
FIELD
TYPE
R/W
R/W
RESET
0000
0000
DESCRIPTION
47:42
41:40
TBD
SW5MSB
SW5_IDAC<9:8>
(1) The DLPA2000 can use up to code 0x0FFh for SW5_IDAC[9:0].
7.5.7 Regulation Current LSB, SW5
Figure 22. Regulation Current LSB, SW5, Address = 06h, HEX = 00
7
6
5
4
3
2
1
0
SW5LSB [55:48]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 15. Regulation Current LSB, SW5 Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
55:48
SW5LSB
00000000 SW5_IDAC<7:0>
Table 16. Regulation Current LSB, SW5 Bit Definitions
DLPA2000(1)(2)
SW5_IDAC[9:0]
0x000h
LED CURRENT
0 mA
SW5_IDAC[9:0]
0x100h
LED CURRENT
257 mA
SW5_IDAC[9:0]
0x200h
LED CURRENT
500 mA
0x00Ch
25 mA
26 mA
...
0x101h
0x102h
...
258 mA
259 mA
...
0x201h
0x202h
...
501 mA
502 mA
...
0x00Dh
...
0x0FEh
255 mA
256 mA
0x1FEh
0x1FFh
498 mA
499 mA
0x306h
0x307h
749 mA
750 mA
0x0FFh
(1) Values shown are for a typical DLPA2000 unit at T = 25°C. Typical step size is 0.95 mA for RLIM = 100 mΩ.
(2) The DLPA2000 can use up to code 0x307h for SW5_IDAC[9:0].
32
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7.5.8 Regulation Current MSB, SW6
Figure 23. Regulation Current MSB, SW6, Address = 07h, HEX = 00
7
6
5
4
3
2
1
0
SW6MSB [63:56]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 17. Regulation Current MSB, SW6 Field Descriptions(1)
BIT
FIELD
Type
R/W
R/W
Reset
0000
0000
Description
63:58
57:56
TBD
SW6MSB
SW6_IDAC<9:8>
(1) The DLPA2000 can use up to code 0x0FFh for SW6_IDAC[9:0].
7.5.9 Regulation Current LSB, SW6
Figure 24. Regulation Current LSB, SW6, Address = 08h, HEX = 00
7
6
5
4
3
2
1
0
SW6LSB [71:64]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 18. Regulation Current LSB, SW6 Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
71:64
SW6LSB
00000000 SW6_IDAC<7:0>
Table 19. Regulation Current LSB, SW6 Bit Definitions
DLPA2000(1)(2)
SW6_IDAC[9:0]
0x000h
LED CURRENT
0 mA
SW6_IDAC[9:0]
0x100h
LED CURRENT
257 mA
SW6_IDAC[9:0]
0x200h
LED CURRENT
500 mA
0x00Ch
25 mA
26 mA
...
0x101h
0x102h
...
258 mA
259 mA
...
0x201h
0x202h
...
501 mA
502 mA
...
0x00Dh
...
0x0FEh
255 mA
256 mA
0x1FEh
0x1FFh
498 mA
499 mA
0x306h
0x307h
749 mA
750 mA
0x0FFh
(1) Values shown are for a typical DLPA2000 unit at T = 25°C. Typical step size is 0.95 mA for RLIM = 100 mΩ.
(2) The DLPA2000 can use up to code 0x307h for SW6_IDAC[9:0].
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7.5.10 Switch On/Off Control (Direct Mode)
Figure 25. Switch On/Off Control (Direct Mode), Address = 09h, HEX = 00
7
6
5
4
3
2
1
0
SWCNTRL [79:72]
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 20. Switch On/Off Control (Direct Mode) Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
SW6 (controls switch 6 if direct mode
(see reg 11h) is enabled)
79
R/W
0
0
0
00000
00001
.....
11110
11111
2.3 V (minimum value – default value)
2.37 V
Step approximately 70 mV
4.43 V
SW5 (controls switch 5 if direct mode
(see reg 11h) is enabled)
78
R/W
SWCNTRL
SW4 (controls switch 4 if direct mode
(see reg 11h) is enabled)
77
R/W
R/W
4.5 V (maximum value)
76:72
00000
UVLO_TRIM<4:0>
7.5.11 AFE (MUX) Control
Figure 26. AFE (MUX) Control, Address = 0Ah, HEX = 00
7
6
5
4
3
2
1
0
AFE [87:80]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 21. AFE (MUX) Control Field Descriptions
BIT
87
FIELD
TYPE
R/W
RESET
00
DESCRIPTION
AFE_EN
86
R/W
R/W
R/W
00
00
00
AFE_CAL_DIS
AFE_GAIN<1:0>
AFE_SEL<3:0>
AFE
85:84
83:80
7.5.12 Break Before Make (BBM) Timing
Figure 27. BBM Timing, Address = 0Bh, HEX = 00
7
6
5
4
3
2
1
0
BBM [95:88]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 22. BBM Timing Field Descriptions(1)
BIT
FIELD
TYPE
R/W
RESET
00000000
DESCRIPTION
95:88 BBM
BBM_DELAY<7:0>
0x00 – 0 ns
0x40 – 7326 ns
0x41 – 7437 ns
0x42 – 7548 ns
...
0x80 – 14430 ns 0xC0 – 21534 ns
0x81 – 14541 ns 0xC1 – 21645 ns
0x82 – 14652 ns 0xC2 – 21756 ns
0x01 – 333 ns
0x02 – 444 ns
...
...
...
0x3E – 7104 ns
0x3F – 7215 ns
0x7E – 14208 ns 0xBE – 21312 ns 0xFE – 28416 ns
0x7F – 14319 ns 0xBF – 21423 ns 0xFF – 28527 ns
(1) It takes 333 to 444 ns to turn off the switches from the time a change occurs on LED_SEL[1:0].
34
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7.5.13 Interrupt Register
Figure 28. Interrupt Register, Address = 0Ch, HEX = 00
7
6
5
4
3
2
1
0
INT [103:96]
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 23. Interrupt Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
103
VLED_OVP
VLED buck_boost overvoltage fault interrupt (normal operation
R
R
R
0
0
0
resumes)
0 – No fault
1 – Buck_boost output is above OVP threshold
102
101
IREG_PG_FAULT
V6V power-good fault interrupt (normal operation resumes)
0 – No fault
1 – V6V is not in regulation
PROJ_ON_INT
Proj_On interrupt (part enters OFF mode)
0 – Pin is pulled high, normal mode
1 – Pin is pulled low, alerts the DPP that the DMD regulator is
about to shut down.
100
DMD_FAULT
DMD regulator fault (part enters STANDBY mode and DMD_EN
bit is cleared)
0 – No fault
R
0
1 – The inductor current is not increasing at the correct rate,
likely to be caused by an open inductor.
Or, one of the regulator outputs has dropped below the power-
good threshold, likely to be caused by a short.
INT
99
98
UVLO
UVLO interrupt (sensed at VINA pin), DMD bit is cleared.
0 – Battery voltage is above the UVLO threshold.
1 – Battery voltage has dropped below the UVLO threshold.
R
R
0
0
BAT_LOW_WARN
Low battery warning interrupt (sensed at VINA pin, normal
operation resumes)
0 – Battery voltage is above the low-battery threshold
1 – Battery voltage has dropped below the low-battery threshold
97
96
TS_WARN
Thermal warning interrupt (normal operation resumes)
0 – Die temperature is in normal operating range
1 – Die temperature is above the HOT threshold
Or, part has not cooled down enough to recover from HOT.
R
R
0
0
TS_WARN
Thermal Warning Interrupt (normal operation resumes)
0 – Die temperature is in normal operating range
1 – Die temperature is above the HOT threshold
Or, part has not cooled down enough to recover from HOT.
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7.5.14 Interrupt Mask Register
Figure 29. Interrupt Mask Register, Address = 0Dh, HEX = DF
7
6
5
4
3
2
1
0
INT MASK [111:104]
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 24. Interrupt Mask Register Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
111
1
VLED BUCK_BOOST
Overvoltage fault interrupt mask
0 – Interrupt is not masked
1 – Interrupt is masked
110
109
108
107
106
105
104
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
1
1
1
IREG_PG_FAULT_MASK
0 – Interrupt is not masked
1 – Interrupt is masked
PROJ_ON interrupt mask
0 – Interrupt is not masked
1 – Interrupt is masked
DMD_REGULATOR fault mask
0 – Interrupt is not masked
1 – Interrupt is masked
INT MASK
UVLO_MASK
0 – Interrupt is not masked
1 – Interrupt is masked
Low battery warning mask (sensed at VINA pin)
0 – Interrupt is not masked
1 – Interrupt is masked
Thermal shutdown interrupt mask
0 – Interrupt is not masked
1 – Interrupt is masked
Thermal warning interrupt mask
0 – Interrupt is not masked
1 – Interrupt is masked
36
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ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
7.5.15 Timing Register VOFS, VBIAS, VRST, and RESETZ
Figure 30. Timing Register VOFS, VBIAS, VRST, and RESETZ, Address = 0Eh, HEX = 07
7
6
5
4
3
2
1
0
TIMING [119:112]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 25. Timing Register VOFS, VBIAS, VRST, and RESETZ Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
0000
DESCRIPTION
119:116
VOFS/RESETZ_DELAY<3:0> (for values see minimum and
maximum delay)
TIMING
115:112
R/W
0111
VBIAS/VRST_DELAY<3:0> (for values see minimum and
maximum delay)
Table 26. Timing Register VOFS, VBIAS, VRST, and RESETZ Bit Definitions
FIELD NAME
BIT
BIT DEFINITION
Minimum Delay (μs)
Maximum Delay (μs)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4.0
8.0
4.4
8.9
16.0
32.0
64.0
128.0
256.0
512.0
6.2
17.8
35.5
71.1
142.2
284.4
569.0
7.1
TIMING
[119:112]
12.4
24.9
49.8
99.5
199.1
398.3
1024.2
14.2
28.4
56.9
113.8
227.6
455.2
1138.0
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7.5.16 Motor Control Register
Figure 31. Motor Control Register, Address = 0Fh, HEX = 00(1)
7
6
5
4
3
2
1
0
MOTOR CTRL [127:120]
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
(1) VINM can be left floating if the motor controller is not used.
Table 27. Motor Control Register Field Descriptions
BIT
127
126
125
124
123
122
121
120
FIELD
TYPE
R/W
RESET
DESCRIPTION
0
0
0
0
0
0
0
0
TBD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TBD
MD_EN
MD_MODE
MD_AIN1
MD_AIN2
MD_BIN1
MD_BIN2
MOTOR CTRL
7.5.17 Password Register
Figure 32. Password Register, Address = 10h, HEX = 00
7
6
5
4
3
2
1
0
PASSWORD [135:128]
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. Password Register Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
135:128 PASSWORD
00000000 USER PASSWORD (0xBAh + 0xBEh) disable (0x00h).
Once set, register 11h can be written.
7.5.18 System Configuration Register
Figure 33. System Configuration Register, Address = 11h, HEX = 00
7
6
5
4
3
2
1
0
SYSTEM [143:136]
R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 29. System Configuration Register Field Descriptions
BIT
143:139
138
FIELD
TYPE
R/W
RESET
00000
DESCRIPTION
TBD
R/W
0
EEPROM_PROGRAM
Program scratch pad values to EEPROM
SYSTEM
137
136
R/W
0
DIRECT_MODE
Allows direct control of switches through SW CONTROL
REGISTER
R/W
0
TBD
38
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7.5.19 User EEPROM, BYTE0
Figure 34. User EEPROM, BYTE0, Address = 20h, HEX = 00
7
6
5
4
3
2
1
0
BYTE0 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 30. User EEPROM, BYTE0 Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
7:0
BYTE0
00000000 USER BYTE 0
7.5.20 User EEPROM, BYTE1
Figure 35. User EEPROM, BYTE1, Address = 21h, HEX = 00
7
6
5
4
3
2
1
0
BYTE1 [15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 31. User EEPROM, BYTE1 Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
15:8
BYTE1
00000000 USER BYTE 1
7.5.21 User EEPROM, BYTE2
Figure 36. User EEPROM, BYTE2, Address = 22h, HEX = 00
7
6
5
4
3
2
1
0
BYTE2 [23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 32. User EEPROM, BYTE2 Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
23:16
BYTE2
00000000 USER BYTE 2
7.5.22 User EEPROM, BYTE3
Figure 37. User EEPROM, BYTE3, Address = 23h, HEX = 00
7
6
5
4
3
2
1
0
BYTE3 [31:24]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 33. User EEPROM, BYTE3 Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
31:24
BYTE3
00000000 USER BYTE 3
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7.5.23 User EEPROM, BYTE4
Figure 38. User EEPROM, BYTE4, Address = 24h, HEX = 00
7
6
5
4
3
2
1
0
BYTE4 [39:32]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 34. User EEPROM, BYTE4 Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
39:32
BYTE4
00000000 USER BYTE 4
7.5.24 User EEPROM, BYTE5
Figure 39. User EEPROM, BYTE5, Address = 25h, HEX = 00
7
6
5
4
3
2
1
0
BYTE5 [47:40]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 35. User EEPROM, BYTE5 Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
47:40
BYTE5
00000000 USER BYTE 5
7.5.25 User EEPROM, BYTE6
Figure 40. User EEPROM, BYTE6, Address = 26h, HEX = 00
7
6
5
4
3
2
1
0
BYTE6 [55:48]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 36. User EEPROM, BYTE6 Field Descriptions
BIT
FIELD
TYPE
R/W
RESET
DESCRIPTION
55:48
BYTE6
00000000 USER BYTE 6
7.5.26 User EEPROM, BYTE7
Figure 41. User EEPROM, BYTE7, Address = 27h, HEX = 00
7
6
5
4
3
2
1
0
BYTE7 [63:56]
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.
Table 37. User EEPROM, BYTE7 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
63:56
BYTE7
R
00000000 USER BYTE 7
40
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ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A DLPC343x controller can be used with a DLP2010 (0.2 WVGA) DMD or DLP3010 (0.3 720p) DMD to provide a
compact, reliable, high-efficiency display solution for many different video display applications. The DMDs are
spatial light modulators which reflect incoming light from an illumination source to one of two directions with the
primary direction being into collection optics within a projection lens. The projection lens sends the light to the
destination needed for the application. Each application is derived primarily from the optical architecture of the
system and the format of the pixel data being input into the DLPC343x.
In display applications using the DLP2010 DMD or DLP3010 DMD, the DLPA2000 provides all needed analog
functions including the analog power supplies and the RGB LED driver to provide a robust and efficient display
solution. Display applications of interest include pico-projectors embedded in display devices like smart phones,
tablets, cameras, and camcorders. Other applications include wearable (near-eye) displays, battery-powered
mobile accessories, interactive displays, low latency gaming displays, and digital signage.
Alternately, a DLPC150 controller can be used with a DLP2010 or DLP2010NIR DMD. Applications of interest
when using the DLPC150 controller include machine vision systems, spectrometers, skin analysis, medical
systems, material identification, chemical sensing, infrared projection, and compressive sensing. In a
spectroscopy application the DLPC150 controller and DLP2010NIR DMD are often combined with a single
element detector to replace expensive InGaAs array-based detector designs. In this application the DMD acts as
a wavelength selector reflecting specific wavelengths of light into the single point detector.
8.2 Typical Projector Application
A common application when using DLPA2000 with DLP2010 DMD and DLPC3430 controller is for creating a
pico-projector embedded in a handheld product. For example, a pico-projector may be embedded in a smart
phone, a tablet, a camera, or camcorder. The DLPC3430 in the pico-projector embedded module typically
receives images from a host processor within the product as shown in Figure 42. DLPA2000 provides power
supply sequencing and controls the LED currents as required by the application.
DC_IN
Charger
BAT
2.3 to 5.5 V
Projector Module Electronics
DC Supplies
1.8 V
VSPI
1.1 V
1.8 V
1.1 V
Reg
1.8 V
Other
Supplies
On/Off
L3
SYSPWR
1.8 V
VDD
HDMI
VLED
HDMI
Receiver
PROJ_ON
PROJ_ON
Current
Sense
L1
L2
VGA
GPIO_8 (Normal Park)
Triple
ADC
Keystone
Sensor
DLPA2000
Cal data
(optional)
4
SPI_0
SPI_1
FLASH
4
Front-End
Chip
- OSD
- AutoLock
- Scaler
EEPROM
RED
GREEN
BLUE
RESETZ
INTZ
FLASH,
SDRAM
I2C_1
HOST_IRQ
PARKZ
BIAS, RST, OFS
3
LED_SEL(2)
CMP_PWM
-MicroController
WPC
Illumination
Optics
DLPC3430/
Keypad
DLPC3435
Parallel I/F
28
LABB
CMP_OUT
eDRAM
DLP2010
DMD)
I2C
SD Card
Reader, and
so forth
(WVGA
Thermistor
Sub-LVDS DATA
CTRL
1.8 V
1.1 V
VIO
(optional)
VCC_INTF
VCC_FLSH
VCORE
18
Spare R/W
GPIO
BT.656
CVBS
TVP5151
Video
Decoder
Included in DLP® Chip Set
GND
Figure 42. Typical Embedded Setup Using DLPA2000
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Typical Projector Application (continued)
8.2.1 Design Requirements
A pico-projector is created by using a DLP chipset comprised of DLP2010 (0.2 WVGA) DMD, DLPC3430, or
DLPC3435 controller and DLPA2000 PMIC/LED driver. The DLPC3430 or DLPC3435 does the digital image
processing, the DLPA2000 provides the needed analog functions for the projector, and DMD is the display
device for producing the projected image.
In addition to the three DLP chips in the chipset, other chips may be needed. At a minimum, a flash part is
needed to store the software and firmware to control the DLPC3430 or DLPC3435.
The illumination light that is applied to the DMD is typically from red, green, and blue LEDs. These are often
contained in three separate packages, but sometimes more than one color of LED die may be in the same
package to reduce the overall size of the pico-projector.
When connecting the DLPC3430 or DLPC3435 to the host processing to receive images, a parallel interface is
used. While using the parallel interface, I2C should be connected to the host processor for sending commands to
the DLPC3430 or DLPC3435.
The only power supplies needed external to the projector are the battery (SYSPWR) and a regulated 1.8-V
supply. The entire pico-projector can be turned on and off by using a single signal called PROJ_ON. When
PROJ_ON is high, the projector turns on and begins displaying images. When PROJ_ON is set low, the projector
turns off and draws just microamps of current on SYSPWR. When PROJ_ON is set low, the 1.8-V supply can
continue to be left at 1.8 V and used by other non-projector sections of the product. If PROJ_ON is low, the
DLPA2000 will not draw current on the 1.8-V supply.
8.2.2 Detailed Design Procedure
For connecting together the DLP2010, DLPC3430 or DLPC3435, and DLPA2000, see the reference design
schematic. When a circuit board layout is created from this schematic, a very small circuit board is possible. An
example small board layout is included in the reference design database. Layout guidelines should be followed to
achieve a reliable projector.
The optical engine that has the LED packages and the DMD mounted to it is typically supplied by an optical
OEM who specializes in designing optics for DLP projectors.
A miniature stepper motor can optionally be added to the optical engine for creating a motorized focus. Direct
control and driving of the motor can be done by the DLPA2000, and software commands sent over I2C to the
DLPC3430 or DLPC3435 are available to move the motor to the desired position.
42
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www.ti.com.cn
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
Typical Projector Application (continued)
8.2.3 Application Curve
As the LED currents that are driven time-sequentially through the red, green, and blue LEDs are increased, the
brightness of the projector increases. This increase is somewhat non-linear, and the curve for typical white
screen lumens changes with LED currents is as shown in Figure 43. For the LED currents shown, it is assumed
that the same current amplitude is applied to the red, green, and blue LEDs.
SPACE
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
100
200
300
400
500
600
700
Current (mA)
D001
Figure 43. Luminance vs Current
8.3 Typical Mobile Sensing Application
A typical embedded system application using the DLPC150 controller and the DLPC2010NIR is shown in
Figure 44. In this configuration, the DLPC150 controller supports a 24-bit parallel RGB input, typical of LCD
interfaces, from an external source or processor. The DLPC150 controller processes the digital input image and
converts the data into the format needed by the DLP2010NIR. The DLP2010NIR steers light by setting specific
micromirrors to the on position, directing light to the detector, while unwanted micromirrors are set to the off
position, directing light away from the detector. The microprocessor sends binary images to the DLP2010NIR to
steer specific wavelengths of light into the detector. The microprocessor uses an analog-to-digital converter to
sample the signal received by the detector into a digital value. By sequentially selecting different wavelengths of
light and capturing the values at the detector, the microprocessor can then plot a spectral response to the light.
Copyright © 2014–2018, Texas Instruments Incorporated
43
DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
www.ti.com.cn
Typical Mobile Sensing Application (continued)
0/F5:
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9GSGMKRKSX
'$,&B
'$'&B
;XNKV
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B5:
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<>;6F;:
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'$,&B
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8?F5:
B810
<>;6F;:
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&')$"
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<>;6F;:
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5QQYROSGXOTS&
;UXOIW
.5-?"&>?@"&;2?
)
810F?18ꢁ(
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7K[UGJ
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'$,?&B
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B5;
.QYKXTTXN
B//F5:@2
B//F28?4
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;UXOIW
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0KXKIXTV
$&%ꢀ3ꢀ$.0-,ꢁ+1
08<\&/NOU&?KX
Figure 44. Typical Application Diagram
8.3.1 Design Requirements
All applications using the DLP 0.2-inch WVGA chipset require the:
•
•
•
DLPC150 controller, and
DLPA2000 PMIC, and
DLP2010 or DLP2010NIR DMD
components for operation. The system also requires an external parallel flash memory device loaded with the
DLPC150 configuration and support firmware. DLPC150 does the digital image processing and formats the data
for the DMD. DLPA2000 PMIC provides the needed analog functions for the DLPC150 and DLP2010 or
DLP2010NIR. The chipset has several system interfaces and requires some support circuitry. The following
interfaces and support circuitry are required:
•
DLPC150 system interfaces:
–
–
–
–
Control interface
Trigger interface
Input data interface
Illumination interface
•
•
DLPC150 support circuitry and interfaces:
–
–
–
Reference clock
PLL
Program memory flash interface
DMD interfaces:
–
–
–
DLPC150 to DMD digital data
DLPC150 to DMD control interface
DLPC150 to DMD micromirror reset control interface
44
Copyright © 2014–2018, Texas Instruments Incorporated
DLPA2000
www.ti.com.cn
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
Typical Mobile Sensing Application (continued)
8.3.2 Detailed Design Procedure
8.3.2.1 Dlpc150 System Interfaces
The 0.2-inch WVGA chipset supports a 16-bit or 24-bit parallel RGB interface for image data transfers from
another device. There are two primary output interfaces: Illumination driver control interface and sync outputs.
8.3.2.1.1 Control Interface
The 0.2-inch WVGA chipset supports I2C commands through the control interface. The control interface allows
another master processor to send commands to the DLPC150 controller to query system status or perform
realtime operations, such as LED driver current settings.
8.3.3 Application Curve
In a reflective spectroscopy application, a broadband light source illuminates a sample and the reflected light
spectrum is dispersed onto the DLP2010NIR. A microprocessor in conjunction with the DLPC150 controls
individual DLP2010NIR micromirrors to reflect specific wavelengths of light to a single point detector. The
microprocessor uses an analog-to-digital converter to sample the signal received by the detector into a digital
value. By sequentially selecting different wavelengths of light and capturing the values at the detector, the
microprocessor can then plot a spectral response to the light. This systems allows the measurement of the
collected light and derive the wavelengths absorbed by the sample. This process leads to the absorption
spectrum shown in Figure 45.
Figure 45. Sample DLPC150 Based Spectrometer Output
Copyright © 2014–2018, Texas Instruments Incorporated
45
DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
www.ti.com.cn
9 Power Supply Recommendations
The DLPA2000 is designed to operate from a 2.3-V to 6-V input voltage supply or battery. To avoid insufficient
supply current due to line drop, ringing due to trace inductance at the VIN terminal, or supply peak current
limitations, additional bulk capacitance may be required. In the case ringing that is caused by the interaction with
the ceramic input capacitors, an electrolytic or tantalum type capacitor may be needed for damping. The amount
of bulk capacitance required should be evaluated such that the input voltage can remain in specification long
enough for a proper fast shutdown to occur for the VOFS, VRST, and VBIAS supplies. The shutdown begins when
the input voltage drops below the programmable UVLO threshold such as when the external power supply or
battery supply is suddenly removed from the system.
46
Copyright © 2014–2018, Texas Instruments Incorporated
DLPA2000
www.ti.com.cn
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
10 Layout
10.1 Layout Guidelines
As for all chips with switching power supplies, the layout is an important step in the design, especially in the case
of high peak currents and high switching frequencies. If the layout is not carefully done, the regulators could
show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current paths
and for the power ground tracks. Input capacitors, output capacitors, and inductors should be placed as close as
possible to the IC.
Figure 46 shows an example layout that has critical parts placed as close as possible to the pins they are
connected to. Here are recommendations for the following components:
R1
is RLIM and is connected via a wide trace and as short as possible to the DLPA2000 and the ground.
is the big inductor for the VLED that is connected via two wide traces to the pins.
L1
C3/C4
are the decoupling capacitors for the VLED and they are as close as possible placed to the part and
directly connected to ground.
L3/C20 are components used for the VCORE BUCK. L3 is placed close to the pin and connected with a wide
trace to the part. C20 is placed directly beside the inductor and connected to the PGND pin.
L2
This inductor is part of the DMD reset regulators and is also placed as close as possible to the
DLPA2000 using wide PCB traces.
版权 © 2014–2018, Texas Instruments Incorporated
47
DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
www.ti.com.cn
10.2 Layout Example
Figure 46. Example Layout of DLPA2000
48
版权 © 2014–2018, Texas Instruments Incorporated
DLPA2000
www.ti.com.cn
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
TI = TI LETTERS
YM = YEAR / MONTH DATE CODE
LLLL= LOT TRACE CODE
S
= ASSEMBLY SITE CODE
=pin 1 Marking
图 47. DLPA2000 封装标记（俯视图）
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件以及申请样片或购买产品的快速访问
链接。
表 38. 相关链接
器件
产品文件夹
单击此处
样片与购买
单击此处
技术文档
单击此处
工具和软件
单击此处
支持和社区
单击此处
DLPA2000
DLPC3430
DLPC3435
DLP2010
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
DLP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
版权 © 2014–2018, Texas Instruments Incorporated
49
DLPA2000
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
www.ti.com.cn
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
50
版权 © 2014–2018, Texas Instruments Incorporated
DLPA2000
www.ti.com.cn
ZHCSCO5B –JUNE 2014–REVISED FEBRUARY 2018
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
•
•
•
器件插入方向 – 定位器件时，符号朝上，引脚朝下。
盖带 – 盖带不覆盖导孔并且不会从载带移出。
带结构 - 载带由塑料制成，其结构如上文的电路原理图所示。器件置于载带的压纹区域，并由塑料制成的盖带
覆盖。
•
•
•
抗静电放电 (ESD) 塑料 - 载带和盖带使用的材料均为抗静电型。
材料 - 聚碳酸酯、聚苯乙烯或/和经认证的等效材料（静电消散型/抗静电型）。
包装方法 - 用胶带将导引带末端固定，然后用防潮袋来包装卷带并热封固定。方形扁平无引脚 (QFN) 器件的包
装中含有干燥剂和湿度指示剂。
•
带盒 - 每个防潮袋均包装到带盒内。
•
•
带盒材料 - 瓦楞纸板
装运箱 - 如果装运箱内存在间隙，则需要填充缓冲垫之类的填充物。装运箱的尺寸可根据带盒的包装数量进行
更改。
版权 © 2014–2018, Texas Instruments Incorporated
51
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DLPA2000DYFFR
ACTIVE
DSBGA
YFF
56
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-10 to 85
PAD2000
A3
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DLPA2000DYFFR
DSBGA
YFF
56
3000
330.0
12.4
3.4
3.75
0.82
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YFF 56
SPQ
Length (mm) Width (mm) Height (mm)
335.0 335.0 25.0
DLPA2000DYFFR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0056
DSBGA - 0.625 mm max height
S
C
A
L
E
4
.
2
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
2.4 TYP
SYMM
H
G
D: Max = 3.514 mm, Min =3.454 mm
E: Max = 3.31 mm, Min = 3.25 mm
F
E
D
C
SYMM
2.8
TYP
0.3
0.2
56X
B
A
0.015
C A
B
0.4 TYP
1
2
3
4
5
6
7
0.4 TYP
4219481/A 10/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0056
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
56X ( 0.23)
(0.4) TYP
2
4
5
6
7
1
A
B
C
D
E
F
SYMM
G
H
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
(
0.23)
(
0.23)
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219481/A 10/2014
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0056
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
56X ( 0.25)
(R0.05) TYP
1
2
3
4
5
6
7
A
(0.4)
TYP
B
METAL
TYP
C
D
E
F
SYMM
G
H
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219481/A 10/2014
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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Copyright © 2022，德州仪器 (TI) 公司
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